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Commit | Line | Data |
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d4e8164f FB |
1 | /* |
2 | * internal execution defines for qemu | |
5fafdf24 | 3 | * |
d4e8164f FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
d4e8164f FB |
18 | */ |
19 | ||
875cdcf6 AL |
20 | #ifndef _EXEC_ALL_H_ |
21 | #define _EXEC_ALL_H_ | |
7d99a001 BS |
22 | |
23 | #include "qemu-common.h" | |
24 | ||
b346ff46 | 25 | /* allow to see translation results - the slowdown should be negligible, so we leave it */ |
de9a95f0 | 26 | #define DEBUG_DISAS |
b346ff46 | 27 | |
41c1b1c9 PB |
28 | /* Page tracking code uses ram addresses in system mode, and virtual |
29 | addresses in userspace mode. Define tb_page_addr_t to be an appropriate | |
30 | type. */ | |
31 | #if defined(CONFIG_USER_ONLY) | |
b480d9b7 | 32 | typedef abi_ulong tb_page_addr_t; |
41c1b1c9 PB |
33 | #else |
34 | typedef ram_addr_t tb_page_addr_t; | |
35 | #endif | |
36 | ||
b346ff46 FB |
37 | /* is_jmp field values */ |
38 | #define DISAS_NEXT 0 /* next instruction can be analyzed */ | |
39 | #define DISAS_JUMP 1 /* only pc was modified dynamically */ | |
40 | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ | |
41 | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ | |
42 | ||
2e70f6ef | 43 | typedef struct TranslationBlock TranslationBlock; |
b346ff46 FB |
44 | |
45 | /* XXX: make safe guess about sizes */ | |
b689c622 | 46 | #define MAX_OP_PER_INSTR 96 |
0115be31 PB |
47 | /* A Call op needs up to 6 + 2N parameters (N = number of arguments). */ |
48 | #define MAX_OPC_PARAM 10 | |
6db73509 | 49 | #define OPC_BUF_SIZE 640 |
b346ff46 FB |
50 | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) |
51 | ||
a208e54a | 52 | /* Maximum size a TCG op can expand to. This is complicated because a |
0cbfcd2b AJ |
53 | single op may require several host instructions and register reloads. |
54 | For now take a wild guess at 192 bytes, which should allow at least | |
a208e54a | 55 | a couple of fixup instructions per argument. */ |
0cbfcd2b | 56 | #define TCG_MAX_OP_SIZE 192 |
a208e54a | 57 | |
0115be31 | 58 | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM) |
b346ff46 | 59 | |
c27004ec FB |
60 | extern target_ulong gen_opc_pc[OPC_BUF_SIZE]; |
61 | extern target_ulong gen_opc_npc[OPC_BUF_SIZE]; | |
66e85a21 | 62 | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; |
b346ff46 | 63 | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE]; |
2e70f6ef | 64 | extern uint16_t gen_opc_icount[OPC_BUF_SIZE]; |
c3278b7b | 65 | extern target_ulong gen_opc_jump_pc[2]; |
30d6cb84 | 66 | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE]; |
b346ff46 | 67 | |
79383c9c | 68 | #include "qemu-log.h" |
b346ff46 | 69 | |
2cfc5f17 TS |
70 | void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
71 | void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); | |
d2856f1a AJ |
72 | void gen_pc_load(CPUState *env, struct TranslationBlock *tb, |
73 | unsigned long searched_pc, int pc_pos, void *puc); | |
74 | ||
d07bde88 | 75 | unsigned long code_gen_max_block_size(void); |
57fec1fe | 76 | void cpu_gen_init(void); |
4c3a88a2 | 77 | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
d07bde88 | 78 | int *gen_code_size_ptr); |
5fafdf24 | 79 | int cpu_restore_state(struct TranslationBlock *tb, |
58fe2f10 FB |
80 | CPUState *env, unsigned long searched_pc, |
81 | void *puc); | |
5fafdf24 | 82 | int cpu_restore_state_copy(struct TranslationBlock *tb, |
58fe2f10 FB |
83 | CPUState *env, unsigned long searched_pc, |
84 | void *puc); | |
2e12669a | 85 | void cpu_resume_from_signal(CPUState *env1, void *puc); |
2e70f6ef PB |
86 | void cpu_io_recompile(CPUState *env, void *retaddr); |
87 | TranslationBlock *tb_gen_code(CPUState *env, | |
88 | target_ulong pc, target_ulong cs_base, int flags, | |
89 | int cflags); | |
6a00d601 | 90 | void cpu_exec_init(CPUState *env); |
a5e50b26 | 91 | void QEMU_NORETURN cpu_loop_exit(void); |
53a5960a | 92 | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
41c1b1c9 | 93 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, |
2e12669a | 94 | int is_cpu_write_access); |
4390df51 | 95 | void tb_invalidate_page_range(target_ulong start, target_ulong end); |
2e12669a | 96 | void tlb_flush_page(CPUState *env, target_ulong addr); |
ee8b7021 | 97 | void tlb_flush(CPUState *env, int flush_global); |
c527ee8f | 98 | #if !defined(CONFIG_USER_ONLY) |
5fafdf24 | 99 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
c227f099 | 100 | target_phys_addr_t paddr, int prot, |
6ebbf390 | 101 | int mmu_idx, int is_softmmu); |
4d7a0880 | 102 | static inline int tlb_set_page(CPUState *env1, target_ulong vaddr, |
c227f099 | 103 | target_phys_addr_t paddr, int prot, |
6ebbf390 | 104 | int mmu_idx, int is_softmmu) |
84b7b8e7 FB |
105 | { |
106 | if (prot & PAGE_READ) | |
107 | prot |= PAGE_EXEC; | |
4d7a0880 | 108 | return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu); |
84b7b8e7 | 109 | } |
c527ee8f | 110 | #endif |
d4e8164f | 111 | |
d4e8164f FB |
112 | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
113 | ||
4390df51 FB |
114 | #define CODE_GEN_PHYS_HASH_BITS 15 |
115 | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) | |
116 | ||
26a5f13b | 117 | #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024) |
d4e8164f | 118 | |
4390df51 FB |
119 | /* estimated block size for TB allocation */ |
120 | /* XXX: use a per code average code fragment size and modulate it | |
121 | according to the host CPU */ | |
122 | #if defined(CONFIG_SOFTMMU) | |
123 | #define CODE_GEN_AVG_BLOCK_SIZE 128 | |
124 | #else | |
125 | #define CODE_GEN_AVG_BLOCK_SIZE 64 | |
126 | #endif | |
127 | ||
a8cd70fc | 128 | #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__) |
d4e8164f FB |
129 | #define USE_DIRECT_JUMP |
130 | #endif | |
131 | ||
2e70f6ef | 132 | struct TranslationBlock { |
2e12669a FB |
133 | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ |
134 | target_ulong cs_base; /* CS base for this block */ | |
c068688b | 135 | uint64_t flags; /* flags defining in which context the code was generated */ |
d4e8164f FB |
136 | uint16_t size; /* size of target code for this block (1 <= |
137 | size <= TARGET_PAGE_SIZE) */ | |
58fe2f10 | 138 | uint16_t cflags; /* compile flags */ |
2e70f6ef PB |
139 | #define CF_COUNT_MASK 0x7fff |
140 | #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ | |
58fe2f10 | 141 | |
d4e8164f | 142 | uint8_t *tc_ptr; /* pointer to the translated code */ |
4390df51 | 143 | /* next matching tb for physical address. */ |
5fafdf24 | 144 | struct TranslationBlock *phys_hash_next; |
4390df51 FB |
145 | /* first and second physical page containing code. The lower bit |
146 | of the pointer tells the index in page_next[] */ | |
5fafdf24 | 147 | struct TranslationBlock *page_next[2]; |
41c1b1c9 | 148 | tb_page_addr_t page_addr[2]; |
4390df51 | 149 | |
d4e8164f FB |
150 | /* the following data are used to directly call another TB from |
151 | the code of this one. */ | |
152 | uint16_t tb_next_offset[2]; /* offset of original jump target */ | |
153 | #ifdef USE_DIRECT_JUMP | |
4cbb86e1 | 154 | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
d4e8164f | 155 | #else |
57fec1fe | 156 | unsigned long tb_next[2]; /* address of jump generated code */ |
d4e8164f FB |
157 | #endif |
158 | /* list of TBs jumping to this one. This is a circular list using | |
159 | the two least significant bits of the pointers to tell what is | |
160 | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 = | |
161 | jmp_first */ | |
5fafdf24 | 162 | struct TranslationBlock *jmp_next[2]; |
d4e8164f | 163 | struct TranslationBlock *jmp_first; |
2e70f6ef PB |
164 | uint32_t icount; |
165 | }; | |
d4e8164f | 166 | |
b362e5e0 PB |
167 | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
168 | { | |
169 | target_ulong tmp; | |
170 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); | |
b5e19d4c | 171 | return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK; |
b362e5e0 PB |
172 | } |
173 | ||
8a40a180 | 174 | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
d4e8164f | 175 | { |
b362e5e0 PB |
176 | target_ulong tmp; |
177 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); | |
b5e19d4c EI |
178 | return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK) |
179 | | (tmp & TB_JMP_ADDR_MASK)); | |
d4e8164f FB |
180 | } |
181 | ||
41c1b1c9 | 182 | static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc) |
4390df51 FB |
183 | { |
184 | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); | |
185 | } | |
186 | ||
c27004ec | 187 | TranslationBlock *tb_alloc(target_ulong pc); |
2e70f6ef | 188 | void tb_free(TranslationBlock *tb); |
0124311e | 189 | void tb_flush(CPUState *env); |
41c1b1c9 PB |
190 | void tb_link_page(TranslationBlock *tb, |
191 | tb_page_addr_t phys_pc, tb_page_addr_t phys_page2); | |
192 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); | |
d4e8164f | 193 | |
4390df51 | 194 | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
d4e8164f | 195 | extern uint8_t *code_gen_ptr; |
26a5f13b | 196 | extern int code_gen_max_blocks; |
d4e8164f | 197 | |
4390df51 FB |
198 | #if defined(USE_DIRECT_JUMP) |
199 | ||
e58ffeb3 | 200 | #if defined(_ARCH_PPC) |
810260a8 | 201 | extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr); |
202 | #define tb_set_jmp_target1 ppc_tb_set_jmp_target | |
57fec1fe | 203 | #elif defined(__i386__) || defined(__x86_64__) |
4390df51 FB |
204 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
205 | { | |
206 | /* patch the branch destination */ | |
207 | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4); | |
1235fc06 | 208 | /* no need to flush icache explicitly */ |
4390df51 | 209 | } |
811d4cf4 AZ |
210 | #elif defined(__arm__) |
211 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) | |
212 | { | |
3233f0d4 AZ |
213 | #if QEMU_GNUC_PREREQ(4, 1) |
214 | void __clear_cache(char *beg, char *end); | |
215 | #else | |
811d4cf4 AZ |
216 | register unsigned long _beg __asm ("a1"); |
217 | register unsigned long _end __asm ("a2"); | |
218 | register unsigned long _flg __asm ("a3"); | |
3233f0d4 | 219 | #endif |
811d4cf4 AZ |
220 | |
221 | /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */ | |
87b78ad1 LD |
222 | *(uint32_t *)jmp_addr = |
223 | (*(uint32_t *)jmp_addr & ~0xffffff) | |
224 | | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff); | |
811d4cf4 | 225 | |
3233f0d4 AZ |
226 | #if QEMU_GNUC_PREREQ(4, 1) |
227 | __clear_cache((char *) jmp_addr, (char *) jmp_addr + 4); | |
228 | #else | |
811d4cf4 AZ |
229 | /* flush icache */ |
230 | _beg = jmp_addr; | |
231 | _end = jmp_addr + 4; | |
232 | _flg = 0; | |
233 | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); | |
3233f0d4 | 234 | #endif |
811d4cf4 | 235 | } |
4390df51 | 236 | #endif |
d4e8164f | 237 | |
5fafdf24 | 238 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
4cbb86e1 FB |
239 | int n, unsigned long addr) |
240 | { | |
241 | unsigned long offset; | |
242 | ||
243 | offset = tb->tb_jmp_offset[n]; | |
244 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); | |
245 | offset = tb->tb_jmp_offset[n + 2]; | |
246 | if (offset != 0xffff) | |
247 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); | |
248 | } | |
249 | ||
d4e8164f FB |
250 | #else |
251 | ||
252 | /* set the jump target */ | |
5fafdf24 | 253 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
d4e8164f FB |
254 | int n, unsigned long addr) |
255 | { | |
95f7652d | 256 | tb->tb_next[n] = addr; |
d4e8164f FB |
257 | } |
258 | ||
259 | #endif | |
260 | ||
5fafdf24 | 261 | static inline void tb_add_jump(TranslationBlock *tb, int n, |
d4e8164f FB |
262 | TranslationBlock *tb_next) |
263 | { | |
cf25629d FB |
264 | /* NOTE: this test is only needed for thread safety */ |
265 | if (!tb->jmp_next[n]) { | |
266 | /* patch the native jump address */ | |
267 | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); | |
3b46e624 | 268 | |
cf25629d FB |
269 | /* add in TB jmp circular list */ |
270 | tb->jmp_next[n] = tb_next->jmp_first; | |
271 | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n)); | |
272 | } | |
d4e8164f FB |
273 | } |
274 | ||
a513fe19 FB |
275 | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
276 | ||
d5975363 | 277 | #include "qemu-lock.h" |
d4e8164f | 278 | |
c227f099 | 279 | extern spinlock_t tb_lock; |
d4e8164f | 280 | |
36bdbe54 | 281 | extern int tb_invalidated_flag; |
6e59c1db | 282 | |
e95c8d51 | 283 | #if !defined(CONFIG_USER_ONLY) |
6e59c1db | 284 | |
b3755a91 PB |
285 | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
286 | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; | |
287 | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; | |
288 | ||
6ebbf390 | 289 | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
6e59c1db FB |
290 | void *retaddr); |
291 | ||
79383c9c BS |
292 | #include "softmmu_defs.h" |
293 | ||
6ebbf390 | 294 | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
6e59c1db FB |
295 | #define MEMSUFFIX _code |
296 | #define env cpu_single_env | |
297 | ||
298 | #define DATA_SIZE 1 | |
299 | #include "softmmu_header.h" | |
300 | ||
301 | #define DATA_SIZE 2 | |
302 | #include "softmmu_header.h" | |
303 | ||
304 | #define DATA_SIZE 4 | |
305 | #include "softmmu_header.h" | |
306 | ||
c27004ec FB |
307 | #define DATA_SIZE 8 |
308 | #include "softmmu_header.h" | |
309 | ||
6e59c1db FB |
310 | #undef ACCESS_TYPE |
311 | #undef MEMSUFFIX | |
312 | #undef env | |
313 | ||
314 | #endif | |
4390df51 FB |
315 | |
316 | #if defined(CONFIG_USER_ONLY) | |
41c1b1c9 | 317 | static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr) |
4390df51 FB |
318 | { |
319 | return addr; | |
320 | } | |
321 | #else | |
322 | /* NOTE: this function can trigger an exception */ | |
1ccde1cb FB |
323 | /* NOTE2: the returned address is not exactly the physical address: it |
324 | is the offset relative to phys_ram_base */ | |
41c1b1c9 | 325 | static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr) |
4390df51 | 326 | { |
4d7a0880 | 327 | int mmu_idx, page_index, pd; |
5579c7f3 | 328 | void *p; |
4390df51 | 329 | |
4d7a0880 BS |
330 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
331 | mmu_idx = cpu_mmu_index(env1); | |
551bd27f TS |
332 | if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code != |
333 | (addr & TARGET_PAGE_MASK))) { | |
c27004ec FB |
334 | ldub_code(addr); |
335 | } | |
4d7a0880 | 336 | pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; |
2a4188a3 | 337 | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { |
647de6ca | 338 | #if defined(TARGET_SPARC) || defined(TARGET_MIPS) |
e18231a3 | 339 | do_unassigned_access(addr, 0, 1, 0, 4); |
6c36d3fa | 340 | #else |
4d7a0880 | 341 | cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
6c36d3fa | 342 | #endif |
4390df51 | 343 | } |
5579c7f3 PB |
344 | p = (void *)(unsigned long)addr |
345 | + env1->tlb_table[mmu_idx][page_index].addend; | |
346 | return qemu_ram_addr_from_host(p); | |
4390df51 | 347 | } |
2e70f6ef | 348 | |
bf20dc07 | 349 | /* Deterministic execution requires that IO only be performed on the last |
2e70f6ef PB |
350 | instruction of a TB so that interrupts take effect immediately. */ |
351 | static inline int can_do_io(CPUState *env) | |
352 | { | |
353 | if (!use_icount) | |
354 | return 1; | |
355 | ||
356 | /* If not executing code then assume we are ok. */ | |
357 | if (!env->current_tb) | |
358 | return 1; | |
359 | ||
360 | return env->can_do_io != 0; | |
361 | } | |
4390df51 | 362 | #endif |
9df217a3 | 363 | |
dde2367e AL |
364 | typedef void (CPUDebugExcpHandler)(CPUState *env); |
365 | ||
366 | CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler); | |
1b530a6d AJ |
367 | |
368 | /* vl.c */ | |
369 | extern int singlestep; | |
370 | ||
875cdcf6 | 371 | #endif |