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Commit | Line | Data |
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54936004 | 1 | /* |
fd6ce8f6 | 2 | * virtual page mapping and translated block handling |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
54936004 | 18 | */ |
67b915a5 | 19 | #include "config.h" |
d5a8f07c FB |
20 | #ifdef _WIN32 |
21 | #include <windows.h> | |
22 | #else | |
a98d49b1 | 23 | #include <sys/types.h> |
d5a8f07c FB |
24 | #include <sys/mman.h> |
25 | #endif | |
54936004 | 26 | |
055403b2 | 27 | #include "qemu-common.h" |
6180a181 FB |
28 | #include "cpu.h" |
29 | #include "exec-all.h" | |
b67d9a52 | 30 | #include "tcg.h" |
b3c7724c | 31 | #include "hw/hw.h" |
cc9e98cb | 32 | #include "hw/qdev.h" |
74576198 | 33 | #include "osdep.h" |
7ba1e619 | 34 | #include "kvm.h" |
432d268c | 35 | #include "hw/xen.h" |
29e922b6 | 36 | #include "qemu-timer.h" |
53a5960a PB |
37 | #if defined(CONFIG_USER_ONLY) |
38 | #include <qemu.h> | |
f01576f1 JL |
39 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) |
40 | #include <sys/param.h> | |
41 | #if __FreeBSD_version >= 700104 | |
42 | #define HAVE_KINFO_GETVMMAP | |
43 | #define sigqueue sigqueue_freebsd /* avoid redefinition */ | |
44 | #include <sys/time.h> | |
45 | #include <sys/proc.h> | |
46 | #include <machine/profile.h> | |
47 | #define _KERNEL | |
48 | #include <sys/user.h> | |
49 | #undef _KERNEL | |
50 | #undef sigqueue | |
51 | #include <libutil.h> | |
52 | #endif | |
53 | #endif | |
432d268c JN |
54 | #else /* !CONFIG_USER_ONLY */ |
55 | #include "xen-mapcache.h" | |
6506e4f9 | 56 | #include "trace.h" |
53a5960a | 57 | #endif |
54936004 | 58 | |
fd6ce8f6 | 59 | //#define DEBUG_TB_INVALIDATE |
66e85a21 | 60 | //#define DEBUG_FLUSH |
9fa3e853 | 61 | //#define DEBUG_TLB |
67d3b957 | 62 | //#define DEBUG_UNASSIGNED |
fd6ce8f6 FB |
63 | |
64 | /* make various TB consistency checks */ | |
5fafdf24 TS |
65 | //#define DEBUG_TB_CHECK |
66 | //#define DEBUG_TLB_CHECK | |
fd6ce8f6 | 67 | |
1196be37 | 68 | //#define DEBUG_IOPORT |
db7b5426 | 69 | //#define DEBUG_SUBPAGE |
1196be37 | 70 | |
99773bd4 PB |
71 | #if !defined(CONFIG_USER_ONLY) |
72 | /* TB consistency checks only implemented for usermode emulation. */ | |
73 | #undef DEBUG_TB_CHECK | |
74 | #endif | |
75 | ||
9fa3e853 FB |
76 | #define SMC_BITMAP_USE_THRESHOLD 10 |
77 | ||
bdaf78e0 | 78 | static TranslationBlock *tbs; |
24ab68ac | 79 | static int code_gen_max_blocks; |
9fa3e853 | 80 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
bdaf78e0 | 81 | static int nb_tbs; |
eb51d102 | 82 | /* any access to the tbs or the page table must use this lock */ |
c227f099 | 83 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; |
fd6ce8f6 | 84 | |
141ac468 BS |
85 | #if defined(__arm__) || defined(__sparc_v9__) |
86 | /* The prologue must be reachable with a direct jump. ARM and Sparc64 | |
87 | have limited branch ranges (possibly also PPC) so place it in a | |
d03d860b BS |
88 | section close to code segment. */ |
89 | #define code_gen_section \ | |
90 | __attribute__((__section__(".gen_code"))) \ | |
91 | __attribute__((aligned (32))) | |
f8e2af11 SW |
92 | #elif defined(_WIN32) |
93 | /* Maximum alignment for Win32 is 16. */ | |
94 | #define code_gen_section \ | |
95 | __attribute__((aligned (16))) | |
d03d860b BS |
96 | #else |
97 | #define code_gen_section \ | |
98 | __attribute__((aligned (32))) | |
99 | #endif | |
100 | ||
101 | uint8_t code_gen_prologue[1024] code_gen_section; | |
bdaf78e0 BS |
102 | static uint8_t *code_gen_buffer; |
103 | static unsigned long code_gen_buffer_size; | |
26a5f13b | 104 | /* threshold to flush the translated code buffer */ |
bdaf78e0 | 105 | static unsigned long code_gen_buffer_max_size; |
24ab68ac | 106 | static uint8_t *code_gen_ptr; |
fd6ce8f6 | 107 | |
e2eef170 | 108 | #if !defined(CONFIG_USER_ONLY) |
9fa3e853 | 109 | int phys_ram_fd; |
74576198 | 110 | static int in_migration; |
94a6b54f | 111 | |
f471a17e | 112 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list) }; |
e2eef170 | 113 | #endif |
9fa3e853 | 114 | |
6a00d601 FB |
115 | CPUState *first_cpu; |
116 | /* current CPU in the current thread. It is only valid inside | |
117 | cpu_exec() */ | |
5fafdf24 | 118 | CPUState *cpu_single_env; |
2e70f6ef | 119 | /* 0 = Do not count executed instructions. |
bf20dc07 | 120 | 1 = Precise instruction counting. |
2e70f6ef PB |
121 | 2 = Adaptive rate instruction counting. */ |
122 | int use_icount = 0; | |
123 | /* Current instruction counter. While executing translated code this may | |
124 | include some instructions that have not yet been executed. */ | |
125 | int64_t qemu_icount; | |
6a00d601 | 126 | |
54936004 | 127 | typedef struct PageDesc { |
92e873b9 | 128 | /* list of TBs intersecting this ram page */ |
fd6ce8f6 | 129 | TranslationBlock *first_tb; |
9fa3e853 FB |
130 | /* in order to optimize self modifying code, we count the number |
131 | of lookups we do to a given page to use a bitmap */ | |
132 | unsigned int code_write_count; | |
133 | uint8_t *code_bitmap; | |
134 | #if defined(CONFIG_USER_ONLY) | |
135 | unsigned long flags; | |
136 | #endif | |
54936004 FB |
137 | } PageDesc; |
138 | ||
41c1b1c9 | 139 | /* In system mode we want L1_MAP to be based on ram offsets, |
5cd2c5b6 RH |
140 | while in user mode we want it to be based on virtual addresses. */ |
141 | #if !defined(CONFIG_USER_ONLY) | |
41c1b1c9 PB |
142 | #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS |
143 | # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS | |
144 | #else | |
5cd2c5b6 | 145 | # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS |
41c1b1c9 | 146 | #endif |
bedb69ea | 147 | #else |
5cd2c5b6 | 148 | # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS |
bedb69ea | 149 | #endif |
54936004 | 150 | |
5cd2c5b6 RH |
151 | /* Size of the L2 (and L3, etc) page tables. */ |
152 | #define L2_BITS 10 | |
54936004 FB |
153 | #define L2_SIZE (1 << L2_BITS) |
154 | ||
5cd2c5b6 RH |
155 | /* The bits remaining after N lower levels of page tables. */ |
156 | #define P_L1_BITS_REM \ | |
157 | ((TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) | |
158 | #define V_L1_BITS_REM \ | |
159 | ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) | |
160 | ||
161 | /* Size of the L1 page table. Avoid silly small sizes. */ | |
162 | #if P_L1_BITS_REM < 4 | |
163 | #define P_L1_BITS (P_L1_BITS_REM + L2_BITS) | |
164 | #else | |
165 | #define P_L1_BITS P_L1_BITS_REM | |
166 | #endif | |
167 | ||
168 | #if V_L1_BITS_REM < 4 | |
169 | #define V_L1_BITS (V_L1_BITS_REM + L2_BITS) | |
170 | #else | |
171 | #define V_L1_BITS V_L1_BITS_REM | |
172 | #endif | |
173 | ||
174 | #define P_L1_SIZE ((target_phys_addr_t)1 << P_L1_BITS) | |
175 | #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS) | |
176 | ||
177 | #define P_L1_SHIFT (TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS - P_L1_BITS) | |
178 | #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS) | |
179 | ||
83fb7adf FB |
180 | unsigned long qemu_real_host_page_size; |
181 | unsigned long qemu_host_page_bits; | |
182 | unsigned long qemu_host_page_size; | |
183 | unsigned long qemu_host_page_mask; | |
54936004 | 184 | |
5cd2c5b6 RH |
185 | /* This is a multi-level map on the virtual address space. |
186 | The bottom level has pointers to PageDesc. */ | |
187 | static void *l1_map[V_L1_SIZE]; | |
54936004 | 188 | |
e2eef170 | 189 | #if !defined(CONFIG_USER_ONLY) |
41c1b1c9 PB |
190 | typedef struct PhysPageDesc { |
191 | /* offset in host memory of the page + io_index in the low bits */ | |
192 | ram_addr_t phys_offset; | |
193 | ram_addr_t region_offset; | |
194 | } PhysPageDesc; | |
195 | ||
5cd2c5b6 RH |
196 | /* This is a multi-level map on the physical address space. |
197 | The bottom level has pointers to PhysPageDesc. */ | |
198 | static void *l1_phys_map[P_L1_SIZE]; | |
6d9a1304 | 199 | |
e2eef170 PB |
200 | static void io_mem_init(void); |
201 | ||
33417e70 | 202 | /* io memory support */ |
33417e70 FB |
203 | CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
204 | CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; | |
a4193c8a | 205 | void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
511d2b14 | 206 | static char io_mem_used[IO_MEM_NB_ENTRIES]; |
6658ffb8 PB |
207 | static int io_mem_watch; |
208 | #endif | |
33417e70 | 209 | |
34865134 | 210 | /* log support */ |
1e8b27ca JR |
211 | #ifdef WIN32 |
212 | static const char *logfilename = "qemu.log"; | |
213 | #else | |
d9b630fd | 214 | static const char *logfilename = "/tmp/qemu.log"; |
1e8b27ca | 215 | #endif |
34865134 FB |
216 | FILE *logfile; |
217 | int loglevel; | |
e735b91c | 218 | static int log_append = 0; |
34865134 | 219 | |
e3db7226 | 220 | /* statistics */ |
b3755a91 | 221 | #if !defined(CONFIG_USER_ONLY) |
e3db7226 | 222 | static int tlb_flush_count; |
b3755a91 | 223 | #endif |
e3db7226 FB |
224 | static int tb_flush_count; |
225 | static int tb_phys_invalidate_count; | |
226 | ||
7cb69cae FB |
227 | #ifdef _WIN32 |
228 | static void map_exec(void *addr, long size) | |
229 | { | |
230 | DWORD old_protect; | |
231 | VirtualProtect(addr, size, | |
232 | PAGE_EXECUTE_READWRITE, &old_protect); | |
233 | ||
234 | } | |
235 | #else | |
236 | static void map_exec(void *addr, long size) | |
237 | { | |
4369415f | 238 | unsigned long start, end, page_size; |
7cb69cae | 239 | |
4369415f | 240 | page_size = getpagesize(); |
7cb69cae | 241 | start = (unsigned long)addr; |
4369415f | 242 | start &= ~(page_size - 1); |
7cb69cae FB |
243 | |
244 | end = (unsigned long)addr + size; | |
4369415f FB |
245 | end += page_size - 1; |
246 | end &= ~(page_size - 1); | |
7cb69cae FB |
247 | |
248 | mprotect((void *)start, end - start, | |
249 | PROT_READ | PROT_WRITE | PROT_EXEC); | |
250 | } | |
251 | #endif | |
252 | ||
b346ff46 | 253 | static void page_init(void) |
54936004 | 254 | { |
83fb7adf | 255 | /* NOTE: we can always suppose that qemu_host_page_size >= |
54936004 | 256 | TARGET_PAGE_SIZE */ |
c2b48b69 AL |
257 | #ifdef _WIN32 |
258 | { | |
259 | SYSTEM_INFO system_info; | |
260 | ||
261 | GetSystemInfo(&system_info); | |
262 | qemu_real_host_page_size = system_info.dwPageSize; | |
263 | } | |
264 | #else | |
265 | qemu_real_host_page_size = getpagesize(); | |
266 | #endif | |
83fb7adf FB |
267 | if (qemu_host_page_size == 0) |
268 | qemu_host_page_size = qemu_real_host_page_size; | |
269 | if (qemu_host_page_size < TARGET_PAGE_SIZE) | |
270 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
271 | qemu_host_page_bits = 0; | |
272 | while ((1 << qemu_host_page_bits) < qemu_host_page_size) | |
273 | qemu_host_page_bits++; | |
274 | qemu_host_page_mask = ~(qemu_host_page_size - 1); | |
50a9569b | 275 | |
2e9a5713 | 276 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
50a9569b | 277 | { |
f01576f1 JL |
278 | #ifdef HAVE_KINFO_GETVMMAP |
279 | struct kinfo_vmentry *freep; | |
280 | int i, cnt; | |
281 | ||
282 | freep = kinfo_getvmmap(getpid(), &cnt); | |
283 | if (freep) { | |
284 | mmap_lock(); | |
285 | for (i = 0; i < cnt; i++) { | |
286 | unsigned long startaddr, endaddr; | |
287 | ||
288 | startaddr = freep[i].kve_start; | |
289 | endaddr = freep[i].kve_end; | |
290 | if (h2g_valid(startaddr)) { | |
291 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
292 | ||
293 | if (h2g_valid(endaddr)) { | |
294 | endaddr = h2g(endaddr); | |
fd436907 | 295 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
f01576f1 JL |
296 | } else { |
297 | #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS | |
298 | endaddr = ~0ul; | |
fd436907 | 299 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
f01576f1 JL |
300 | #endif |
301 | } | |
302 | } | |
303 | } | |
304 | free(freep); | |
305 | mmap_unlock(); | |
306 | } | |
307 | #else | |
50a9569b | 308 | FILE *f; |
50a9569b | 309 | |
0776590d | 310 | last_brk = (unsigned long)sbrk(0); |
5cd2c5b6 | 311 | |
fd436907 | 312 | f = fopen("/compat/linux/proc/self/maps", "r"); |
50a9569b | 313 | if (f) { |
5cd2c5b6 RH |
314 | mmap_lock(); |
315 | ||
50a9569b | 316 | do { |
5cd2c5b6 RH |
317 | unsigned long startaddr, endaddr; |
318 | int n; | |
319 | ||
320 | n = fscanf (f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr); | |
321 | ||
322 | if (n == 2 && h2g_valid(startaddr)) { | |
323 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
324 | ||
325 | if (h2g_valid(endaddr)) { | |
326 | endaddr = h2g(endaddr); | |
327 | } else { | |
328 | endaddr = ~0ul; | |
329 | } | |
330 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
50a9569b AZ |
331 | } |
332 | } while (!feof(f)); | |
5cd2c5b6 | 333 | |
50a9569b | 334 | fclose(f); |
5cd2c5b6 | 335 | mmap_unlock(); |
50a9569b | 336 | } |
f01576f1 | 337 | #endif |
50a9569b AZ |
338 | } |
339 | #endif | |
54936004 FB |
340 | } |
341 | ||
41c1b1c9 | 342 | static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) |
54936004 | 343 | { |
41c1b1c9 PB |
344 | PageDesc *pd; |
345 | void **lp; | |
346 | int i; | |
347 | ||
5cd2c5b6 | 348 | #if defined(CONFIG_USER_ONLY) |
2e9a5713 | 349 | /* We can't use qemu_malloc because it may recurse into a locked mutex. */ |
5cd2c5b6 RH |
350 | # define ALLOC(P, SIZE) \ |
351 | do { \ | |
352 | P = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, \ | |
353 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); \ | |
5cd2c5b6 RH |
354 | } while (0) |
355 | #else | |
356 | # define ALLOC(P, SIZE) \ | |
357 | do { P = qemu_mallocz(SIZE); } while (0) | |
17e2377a | 358 | #endif |
434929bf | 359 | |
5cd2c5b6 RH |
360 | /* Level 1. Always allocated. */ |
361 | lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1)); | |
362 | ||
363 | /* Level 2..N-1. */ | |
364 | for (i = V_L1_SHIFT / L2_BITS - 1; i > 0; i--) { | |
365 | void **p = *lp; | |
366 | ||
367 | if (p == NULL) { | |
368 | if (!alloc) { | |
369 | return NULL; | |
370 | } | |
371 | ALLOC(p, sizeof(void *) * L2_SIZE); | |
372 | *lp = p; | |
17e2377a | 373 | } |
5cd2c5b6 RH |
374 | |
375 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); | |
376 | } | |
377 | ||
378 | pd = *lp; | |
379 | if (pd == NULL) { | |
380 | if (!alloc) { | |
381 | return NULL; | |
382 | } | |
383 | ALLOC(pd, sizeof(PageDesc) * L2_SIZE); | |
384 | *lp = pd; | |
54936004 | 385 | } |
5cd2c5b6 RH |
386 | |
387 | #undef ALLOC | |
5cd2c5b6 RH |
388 | |
389 | return pd + (index & (L2_SIZE - 1)); | |
54936004 FB |
390 | } |
391 | ||
41c1b1c9 | 392 | static inline PageDesc *page_find(tb_page_addr_t index) |
54936004 | 393 | { |
5cd2c5b6 | 394 | return page_find_alloc(index, 0); |
fd6ce8f6 FB |
395 | } |
396 | ||
6d9a1304 | 397 | #if !defined(CONFIG_USER_ONLY) |
c227f099 | 398 | static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc) |
92e873b9 | 399 | { |
e3f4e2a4 | 400 | PhysPageDesc *pd; |
5cd2c5b6 RH |
401 | void **lp; |
402 | int i; | |
92e873b9 | 403 | |
5cd2c5b6 RH |
404 | /* Level 1. Always allocated. */ |
405 | lp = l1_phys_map + ((index >> P_L1_SHIFT) & (P_L1_SIZE - 1)); | |
108c49b8 | 406 | |
5cd2c5b6 RH |
407 | /* Level 2..N-1. */ |
408 | for (i = P_L1_SHIFT / L2_BITS - 1; i > 0; i--) { | |
409 | void **p = *lp; | |
410 | if (p == NULL) { | |
411 | if (!alloc) { | |
412 | return NULL; | |
413 | } | |
414 | *lp = p = qemu_mallocz(sizeof(void *) * L2_SIZE); | |
415 | } | |
416 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); | |
108c49b8 | 417 | } |
5cd2c5b6 | 418 | |
e3f4e2a4 | 419 | pd = *lp; |
5cd2c5b6 | 420 | if (pd == NULL) { |
e3f4e2a4 | 421 | int i; |
5cd2c5b6 RH |
422 | |
423 | if (!alloc) { | |
108c49b8 | 424 | return NULL; |
5cd2c5b6 RH |
425 | } |
426 | ||
427 | *lp = pd = qemu_malloc(sizeof(PhysPageDesc) * L2_SIZE); | |
428 | ||
67c4d23c | 429 | for (i = 0; i < L2_SIZE; i++) { |
5cd2c5b6 RH |
430 | pd[i].phys_offset = IO_MEM_UNASSIGNED; |
431 | pd[i].region_offset = (index + i) << TARGET_PAGE_BITS; | |
67c4d23c | 432 | } |
92e873b9 | 433 | } |
5cd2c5b6 RH |
434 | |
435 | return pd + (index & (L2_SIZE - 1)); | |
92e873b9 FB |
436 | } |
437 | ||
c227f099 | 438 | static inline PhysPageDesc *phys_page_find(target_phys_addr_t index) |
92e873b9 | 439 | { |
108c49b8 | 440 | return phys_page_find_alloc(index, 0); |
92e873b9 FB |
441 | } |
442 | ||
c227f099 AL |
443 | static void tlb_protect_code(ram_addr_t ram_addr); |
444 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, | |
3a7d929e | 445 | target_ulong vaddr); |
c8a706fe PB |
446 | #define mmap_lock() do { } while(0) |
447 | #define mmap_unlock() do { } while(0) | |
9fa3e853 | 448 | #endif |
fd6ce8f6 | 449 | |
4369415f FB |
450 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024) |
451 | ||
452 | #if defined(CONFIG_USER_ONLY) | |
ccbb4d44 | 453 | /* Currently it is not recommended to allocate big chunks of data in |
4369415f FB |
454 | user mode. It will change when a dedicated libc will be used */ |
455 | #define USE_STATIC_CODE_GEN_BUFFER | |
456 | #endif | |
457 | ||
458 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
ebf50fb3 AJ |
459 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] |
460 | __attribute__((aligned (CODE_GEN_ALIGN))); | |
4369415f FB |
461 | #endif |
462 | ||
8fcd3692 | 463 | static void code_gen_alloc(unsigned long tb_size) |
26a5f13b | 464 | { |
4369415f FB |
465 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
466 | code_gen_buffer = static_code_gen_buffer; | |
467 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
468 | map_exec(code_gen_buffer, code_gen_buffer_size); | |
469 | #else | |
26a5f13b FB |
470 | code_gen_buffer_size = tb_size; |
471 | if (code_gen_buffer_size == 0) { | |
4369415f FB |
472 | #if defined(CONFIG_USER_ONLY) |
473 | /* in user mode, phys_ram_size is not meaningful */ | |
474 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
475 | #else | |
ccbb4d44 | 476 | /* XXX: needs adjustments */ |
94a6b54f | 477 | code_gen_buffer_size = (unsigned long)(ram_size / 4); |
4369415f | 478 | #endif |
26a5f13b FB |
479 | } |
480 | if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE) | |
481 | code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE; | |
482 | /* The code gen buffer location may have constraints depending on | |
483 | the host cpu and OS */ | |
484 | #if defined(__linux__) | |
485 | { | |
486 | int flags; | |
141ac468 BS |
487 | void *start = NULL; |
488 | ||
26a5f13b FB |
489 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
490 | #if defined(__x86_64__) | |
491 | flags |= MAP_32BIT; | |
492 | /* Cannot map more than that */ | |
493 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
494 | code_gen_buffer_size = (800 * 1024 * 1024); | |
141ac468 BS |
495 | #elif defined(__sparc_v9__) |
496 | // Map the buffer below 2G, so we can use direct calls and branches | |
497 | flags |= MAP_FIXED; | |
498 | start = (void *) 0x60000000UL; | |
499 | if (code_gen_buffer_size > (512 * 1024 * 1024)) | |
500 | code_gen_buffer_size = (512 * 1024 * 1024); | |
1cb0661e | 501 | #elif defined(__arm__) |
63d41246 | 502 | /* Map the buffer below 32M, so we can use direct calls and branches */ |
1cb0661e AZ |
503 | flags |= MAP_FIXED; |
504 | start = (void *) 0x01000000UL; | |
505 | if (code_gen_buffer_size > 16 * 1024 * 1024) | |
506 | code_gen_buffer_size = 16 * 1024 * 1024; | |
eba0b893 RH |
507 | #elif defined(__s390x__) |
508 | /* Map the buffer so that we can use direct calls and branches. */ | |
509 | /* We have a +- 4GB range on the branches; leave some slop. */ | |
510 | if (code_gen_buffer_size > (3ul * 1024 * 1024 * 1024)) { | |
511 | code_gen_buffer_size = 3ul * 1024 * 1024 * 1024; | |
512 | } | |
513 | start = (void *)0x90000000UL; | |
26a5f13b | 514 | #endif |
141ac468 BS |
515 | code_gen_buffer = mmap(start, code_gen_buffer_size, |
516 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
26a5f13b FB |
517 | flags, -1, 0); |
518 | if (code_gen_buffer == MAP_FAILED) { | |
519 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
520 | exit(1); | |
521 | } | |
522 | } | |
cbb608a5 B |
523 | #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \ |
524 | || defined(__DragonFly__) || defined(__OpenBSD__) | |
06e67a82 AL |
525 | { |
526 | int flags; | |
527 | void *addr = NULL; | |
528 | flags = MAP_PRIVATE | MAP_ANONYMOUS; | |
529 | #if defined(__x86_64__) | |
530 | /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume | |
531 | * 0x40000000 is free */ | |
532 | flags |= MAP_FIXED; | |
533 | addr = (void *)0x40000000; | |
534 | /* Cannot map more than that */ | |
535 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
536 | code_gen_buffer_size = (800 * 1024 * 1024); | |
4cd31ad2 BS |
537 | #elif defined(__sparc_v9__) |
538 | // Map the buffer below 2G, so we can use direct calls and branches | |
539 | flags |= MAP_FIXED; | |
540 | addr = (void *) 0x60000000UL; | |
541 | if (code_gen_buffer_size > (512 * 1024 * 1024)) { | |
542 | code_gen_buffer_size = (512 * 1024 * 1024); | |
543 | } | |
06e67a82 AL |
544 | #endif |
545 | code_gen_buffer = mmap(addr, code_gen_buffer_size, | |
546 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
547 | flags, -1, 0); | |
548 | if (code_gen_buffer == MAP_FAILED) { | |
549 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
550 | exit(1); | |
551 | } | |
552 | } | |
26a5f13b FB |
553 | #else |
554 | code_gen_buffer = qemu_malloc(code_gen_buffer_size); | |
26a5f13b FB |
555 | map_exec(code_gen_buffer, code_gen_buffer_size); |
556 | #endif | |
4369415f | 557 | #endif /* !USE_STATIC_CODE_GEN_BUFFER */ |
26a5f13b FB |
558 | map_exec(code_gen_prologue, sizeof(code_gen_prologue)); |
559 | code_gen_buffer_max_size = code_gen_buffer_size - | |
239fda31 | 560 | (TCG_MAX_OP_SIZE * OPC_MAX_SIZE); |
26a5f13b FB |
561 | code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE; |
562 | tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock)); | |
563 | } | |
564 | ||
565 | /* Must be called before using the QEMU cpus. 'tb_size' is the size | |
566 | (in bytes) allocated to the translation buffer. Zero means default | |
567 | size. */ | |
568 | void cpu_exec_init_all(unsigned long tb_size) | |
569 | { | |
26a5f13b FB |
570 | cpu_gen_init(); |
571 | code_gen_alloc(tb_size); | |
572 | code_gen_ptr = code_gen_buffer; | |
4369415f | 573 | page_init(); |
e2eef170 | 574 | #if !defined(CONFIG_USER_ONLY) |
26a5f13b | 575 | io_mem_init(); |
e2eef170 | 576 | #endif |
9002ec79 RH |
577 | #if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE) |
578 | /* There's no guest base to take into account, so go ahead and | |
579 | initialize the prologue now. */ | |
580 | tcg_prologue_init(&tcg_ctx); | |
581 | #endif | |
26a5f13b FB |
582 | } |
583 | ||
9656f324 PB |
584 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
585 | ||
e59fb374 | 586 | static int cpu_common_post_load(void *opaque, int version_id) |
e7f4eff7 JQ |
587 | { |
588 | CPUState *env = opaque; | |
9656f324 | 589 | |
3098dba0 AJ |
590 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
591 | version_id is increased. */ | |
592 | env->interrupt_request &= ~0x01; | |
9656f324 PB |
593 | tlb_flush(env, 1); |
594 | ||
595 | return 0; | |
596 | } | |
e7f4eff7 JQ |
597 | |
598 | static const VMStateDescription vmstate_cpu_common = { | |
599 | .name = "cpu_common", | |
600 | .version_id = 1, | |
601 | .minimum_version_id = 1, | |
602 | .minimum_version_id_old = 1, | |
e7f4eff7 JQ |
603 | .post_load = cpu_common_post_load, |
604 | .fields = (VMStateField []) { | |
605 | VMSTATE_UINT32(halted, CPUState), | |
606 | VMSTATE_UINT32(interrupt_request, CPUState), | |
607 | VMSTATE_END_OF_LIST() | |
608 | } | |
609 | }; | |
9656f324 PB |
610 | #endif |
611 | ||
950f1472 GC |
612 | CPUState *qemu_get_cpu(int cpu) |
613 | { | |
614 | CPUState *env = first_cpu; | |
615 | ||
616 | while (env) { | |
617 | if (env->cpu_index == cpu) | |
618 | break; | |
619 | env = env->next_cpu; | |
620 | } | |
621 | ||
622 | return env; | |
623 | } | |
624 | ||
6a00d601 | 625 | void cpu_exec_init(CPUState *env) |
fd6ce8f6 | 626 | { |
6a00d601 FB |
627 | CPUState **penv; |
628 | int cpu_index; | |
629 | ||
c2764719 PB |
630 | #if defined(CONFIG_USER_ONLY) |
631 | cpu_list_lock(); | |
632 | #endif | |
6a00d601 FB |
633 | env->next_cpu = NULL; |
634 | penv = &first_cpu; | |
635 | cpu_index = 0; | |
636 | while (*penv != NULL) { | |
1e9fa730 | 637 | penv = &(*penv)->next_cpu; |
6a00d601 FB |
638 | cpu_index++; |
639 | } | |
640 | env->cpu_index = cpu_index; | |
268a362c | 641 | env->numa_node = 0; |
72cf2d4f BS |
642 | QTAILQ_INIT(&env->breakpoints); |
643 | QTAILQ_INIT(&env->watchpoints); | |
dc7a09cf JK |
644 | #ifndef CONFIG_USER_ONLY |
645 | env->thread_id = qemu_get_thread_id(); | |
646 | #endif | |
6a00d601 | 647 | *penv = env; |
c2764719 PB |
648 | #if defined(CONFIG_USER_ONLY) |
649 | cpu_list_unlock(); | |
650 | #endif | |
b3c7724c | 651 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
0be71e32 AW |
652 | vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env); |
653 | register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION, | |
b3c7724c PB |
654 | cpu_save, cpu_load, env); |
655 | #endif | |
fd6ce8f6 FB |
656 | } |
657 | ||
d1a1eb74 TG |
658 | /* Allocate a new translation block. Flush the translation buffer if |
659 | too many translation blocks or too much generated code. */ | |
660 | static TranslationBlock *tb_alloc(target_ulong pc) | |
661 | { | |
662 | TranslationBlock *tb; | |
663 | ||
664 | if (nb_tbs >= code_gen_max_blocks || | |
665 | (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size) | |
666 | return NULL; | |
667 | tb = &tbs[nb_tbs++]; | |
668 | tb->pc = pc; | |
669 | tb->cflags = 0; | |
670 | return tb; | |
671 | } | |
672 | ||
673 | void tb_free(TranslationBlock *tb) | |
674 | { | |
675 | /* In practice this is mostly used for single use temporary TB | |
676 | Ignore the hard cases and just back up if this TB happens to | |
677 | be the last one generated. */ | |
678 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) { | |
679 | code_gen_ptr = tb->tc_ptr; | |
680 | nb_tbs--; | |
681 | } | |
682 | } | |
683 | ||
9fa3e853 FB |
684 | static inline void invalidate_page_bitmap(PageDesc *p) |
685 | { | |
686 | if (p->code_bitmap) { | |
59817ccb | 687 | qemu_free(p->code_bitmap); |
9fa3e853 FB |
688 | p->code_bitmap = NULL; |
689 | } | |
690 | p->code_write_count = 0; | |
691 | } | |
692 | ||
5cd2c5b6 RH |
693 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */ |
694 | ||
695 | static void page_flush_tb_1 (int level, void **lp) | |
fd6ce8f6 | 696 | { |
5cd2c5b6 | 697 | int i; |
fd6ce8f6 | 698 | |
5cd2c5b6 RH |
699 | if (*lp == NULL) { |
700 | return; | |
701 | } | |
702 | if (level == 0) { | |
703 | PageDesc *pd = *lp; | |
7296abac | 704 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 RH |
705 | pd[i].first_tb = NULL; |
706 | invalidate_page_bitmap(pd + i); | |
fd6ce8f6 | 707 | } |
5cd2c5b6 RH |
708 | } else { |
709 | void **pp = *lp; | |
7296abac | 710 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 RH |
711 | page_flush_tb_1 (level - 1, pp + i); |
712 | } | |
713 | } | |
714 | } | |
715 | ||
716 | static void page_flush_tb(void) | |
717 | { | |
718 | int i; | |
719 | for (i = 0; i < V_L1_SIZE; i++) { | |
720 | page_flush_tb_1(V_L1_SHIFT / L2_BITS - 1, l1_map + i); | |
fd6ce8f6 FB |
721 | } |
722 | } | |
723 | ||
724 | /* flush all the translation blocks */ | |
d4e8164f | 725 | /* XXX: tb_flush is currently not thread safe */ |
6a00d601 | 726 | void tb_flush(CPUState *env1) |
fd6ce8f6 | 727 | { |
6a00d601 | 728 | CPUState *env; |
0124311e | 729 | #if defined(DEBUG_FLUSH) |
ab3d1727 BS |
730 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", |
731 | (unsigned long)(code_gen_ptr - code_gen_buffer), | |
732 | nb_tbs, nb_tbs > 0 ? | |
733 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0); | |
fd6ce8f6 | 734 | #endif |
26a5f13b | 735 | if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size) |
a208e54a PB |
736 | cpu_abort(env1, "Internal error: code buffer overflow\n"); |
737 | ||
fd6ce8f6 | 738 | nb_tbs = 0; |
3b46e624 | 739 | |
6a00d601 FB |
740 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
741 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); | |
742 | } | |
9fa3e853 | 743 | |
8a8a608f | 744 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *)); |
fd6ce8f6 | 745 | page_flush_tb(); |
9fa3e853 | 746 | |
fd6ce8f6 | 747 | code_gen_ptr = code_gen_buffer; |
d4e8164f FB |
748 | /* XXX: flush processor icache at this point if cache flush is |
749 | expensive */ | |
e3db7226 | 750 | tb_flush_count++; |
fd6ce8f6 FB |
751 | } |
752 | ||
753 | #ifdef DEBUG_TB_CHECK | |
754 | ||
bc98a7ef | 755 | static void tb_invalidate_check(target_ulong address) |
fd6ce8f6 FB |
756 | { |
757 | TranslationBlock *tb; | |
758 | int i; | |
759 | address &= TARGET_PAGE_MASK; | |
99773bd4 PB |
760 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
761 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
762 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
763 | address >= tb->pc + tb->size)) { | |
0bf9e31a BS |
764 | printf("ERROR invalidate: address=" TARGET_FMT_lx |
765 | " PC=%08lx size=%04x\n", | |
99773bd4 | 766 | address, (long)tb->pc, tb->size); |
fd6ce8f6 FB |
767 | } |
768 | } | |
769 | } | |
770 | } | |
771 | ||
772 | /* verify that all the pages have correct rights for code */ | |
773 | static void tb_page_check(void) | |
774 | { | |
775 | TranslationBlock *tb; | |
776 | int i, flags1, flags2; | |
3b46e624 | 777 | |
99773bd4 PB |
778 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
779 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
780 | flags1 = page_get_flags(tb->pc); |
781 | flags2 = page_get_flags(tb->pc + tb->size - 1); | |
782 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | |
783 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | |
99773bd4 | 784 | (long)tb->pc, tb->size, flags1, flags2); |
fd6ce8f6 FB |
785 | } |
786 | } | |
787 | } | |
788 | } | |
789 | ||
790 | #endif | |
791 | ||
792 | /* invalidate one TB */ | |
793 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb, | |
794 | int next_offset) | |
795 | { | |
796 | TranslationBlock *tb1; | |
797 | for(;;) { | |
798 | tb1 = *ptb; | |
799 | if (tb1 == tb) { | |
800 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset); | |
801 | break; | |
802 | } | |
803 | ptb = (TranslationBlock **)((char *)tb1 + next_offset); | |
804 | } | |
805 | } | |
806 | ||
9fa3e853 FB |
807 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) |
808 | { | |
809 | TranslationBlock *tb1; | |
810 | unsigned int n1; | |
811 | ||
812 | for(;;) { | |
813 | tb1 = *ptb; | |
814 | n1 = (long)tb1 & 3; | |
815 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
816 | if (tb1 == tb) { | |
817 | *ptb = tb1->page_next[n1]; | |
818 | break; | |
819 | } | |
820 | ptb = &tb1->page_next[n1]; | |
821 | } | |
822 | } | |
823 | ||
d4e8164f FB |
824 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) |
825 | { | |
826 | TranslationBlock *tb1, **ptb; | |
827 | unsigned int n1; | |
828 | ||
829 | ptb = &tb->jmp_next[n]; | |
830 | tb1 = *ptb; | |
831 | if (tb1) { | |
832 | /* find tb(n) in circular list */ | |
833 | for(;;) { | |
834 | tb1 = *ptb; | |
835 | n1 = (long)tb1 & 3; | |
836 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
837 | if (n1 == n && tb1 == tb) | |
838 | break; | |
839 | if (n1 == 2) { | |
840 | ptb = &tb1->jmp_first; | |
841 | } else { | |
842 | ptb = &tb1->jmp_next[n1]; | |
843 | } | |
844 | } | |
845 | /* now we can suppress tb(n) from the list */ | |
846 | *ptb = tb->jmp_next[n]; | |
847 | ||
848 | tb->jmp_next[n] = NULL; | |
849 | } | |
850 | } | |
851 | ||
852 | /* reset the jump entry 'n' of a TB so that it is not chained to | |
853 | another TB */ | |
854 | static inline void tb_reset_jump(TranslationBlock *tb, int n) | |
855 | { | |
856 | tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n])); | |
857 | } | |
858 | ||
41c1b1c9 | 859 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) |
fd6ce8f6 | 860 | { |
6a00d601 | 861 | CPUState *env; |
8a40a180 | 862 | PageDesc *p; |
d4e8164f | 863 | unsigned int h, n1; |
41c1b1c9 | 864 | tb_page_addr_t phys_pc; |
8a40a180 | 865 | TranslationBlock *tb1, *tb2; |
3b46e624 | 866 | |
8a40a180 FB |
867 | /* remove the TB from the hash list */ |
868 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
869 | h = tb_phys_hash_func(phys_pc); | |
5fafdf24 | 870 | tb_remove(&tb_phys_hash[h], tb, |
8a40a180 FB |
871 | offsetof(TranslationBlock, phys_hash_next)); |
872 | ||
873 | /* remove the TB from the page list */ | |
874 | if (tb->page_addr[0] != page_addr) { | |
875 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | |
876 | tb_page_remove(&p->first_tb, tb); | |
877 | invalidate_page_bitmap(p); | |
878 | } | |
879 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { | |
880 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | |
881 | tb_page_remove(&p->first_tb, tb); | |
882 | invalidate_page_bitmap(p); | |
883 | } | |
884 | ||
36bdbe54 | 885 | tb_invalidated_flag = 1; |
59817ccb | 886 | |
fd6ce8f6 | 887 | /* remove the TB from the hash list */ |
8a40a180 | 888 | h = tb_jmp_cache_hash_func(tb->pc); |
6a00d601 FB |
889 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
890 | if (env->tb_jmp_cache[h] == tb) | |
891 | env->tb_jmp_cache[h] = NULL; | |
892 | } | |
d4e8164f FB |
893 | |
894 | /* suppress this TB from the two jump lists */ | |
895 | tb_jmp_remove(tb, 0); | |
896 | tb_jmp_remove(tb, 1); | |
897 | ||
898 | /* suppress any remaining jumps to this TB */ | |
899 | tb1 = tb->jmp_first; | |
900 | for(;;) { | |
901 | n1 = (long)tb1 & 3; | |
902 | if (n1 == 2) | |
903 | break; | |
904 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
905 | tb2 = tb1->jmp_next[n1]; | |
906 | tb_reset_jump(tb1, n1); | |
907 | tb1->jmp_next[n1] = NULL; | |
908 | tb1 = tb2; | |
909 | } | |
910 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */ | |
9fa3e853 | 911 | |
e3db7226 | 912 | tb_phys_invalidate_count++; |
9fa3e853 FB |
913 | } |
914 | ||
915 | static inline void set_bits(uint8_t *tab, int start, int len) | |
916 | { | |
917 | int end, mask, end1; | |
918 | ||
919 | end = start + len; | |
920 | tab += start >> 3; | |
921 | mask = 0xff << (start & 7); | |
922 | if ((start & ~7) == (end & ~7)) { | |
923 | if (start < end) { | |
924 | mask &= ~(0xff << (end & 7)); | |
925 | *tab |= mask; | |
926 | } | |
927 | } else { | |
928 | *tab++ |= mask; | |
929 | start = (start + 8) & ~7; | |
930 | end1 = end & ~7; | |
931 | while (start < end1) { | |
932 | *tab++ = 0xff; | |
933 | start += 8; | |
934 | } | |
935 | if (start < end) { | |
936 | mask = ~(0xff << (end & 7)); | |
937 | *tab |= mask; | |
938 | } | |
939 | } | |
940 | } | |
941 | ||
942 | static void build_page_bitmap(PageDesc *p) | |
943 | { | |
944 | int n, tb_start, tb_end; | |
945 | TranslationBlock *tb; | |
3b46e624 | 946 | |
b2a7081a | 947 | p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8); |
9fa3e853 FB |
948 | |
949 | tb = p->first_tb; | |
950 | while (tb != NULL) { | |
951 | n = (long)tb & 3; | |
952 | tb = (TranslationBlock *)((long)tb & ~3); | |
953 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
954 | if (n == 0) { | |
955 | /* NOTE: tb_end may be after the end of the page, but | |
956 | it is not a problem */ | |
957 | tb_start = tb->pc & ~TARGET_PAGE_MASK; | |
958 | tb_end = tb_start + tb->size; | |
959 | if (tb_end > TARGET_PAGE_SIZE) | |
960 | tb_end = TARGET_PAGE_SIZE; | |
961 | } else { | |
962 | tb_start = 0; | |
963 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
964 | } | |
965 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); | |
966 | tb = tb->page_next[n]; | |
967 | } | |
968 | } | |
969 | ||
2e70f6ef PB |
970 | TranslationBlock *tb_gen_code(CPUState *env, |
971 | target_ulong pc, target_ulong cs_base, | |
972 | int flags, int cflags) | |
d720b93d FB |
973 | { |
974 | TranslationBlock *tb; | |
975 | uint8_t *tc_ptr; | |
41c1b1c9 PB |
976 | tb_page_addr_t phys_pc, phys_page2; |
977 | target_ulong virt_page2; | |
d720b93d FB |
978 | int code_gen_size; |
979 | ||
41c1b1c9 | 980 | phys_pc = get_page_addr_code(env, pc); |
c27004ec | 981 | tb = tb_alloc(pc); |
d720b93d FB |
982 | if (!tb) { |
983 | /* flush must be done */ | |
984 | tb_flush(env); | |
985 | /* cannot fail at this point */ | |
c27004ec | 986 | tb = tb_alloc(pc); |
2e70f6ef PB |
987 | /* Don't forget to invalidate previous TB info. */ |
988 | tb_invalidated_flag = 1; | |
d720b93d FB |
989 | } |
990 | tc_ptr = code_gen_ptr; | |
991 | tb->tc_ptr = tc_ptr; | |
992 | tb->cs_base = cs_base; | |
993 | tb->flags = flags; | |
994 | tb->cflags = cflags; | |
d07bde88 | 995 | cpu_gen_code(env, tb, &code_gen_size); |
d720b93d | 996 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
3b46e624 | 997 | |
d720b93d | 998 | /* check next page if needed */ |
c27004ec | 999 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
d720b93d | 1000 | phys_page2 = -1; |
c27004ec | 1001 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
41c1b1c9 | 1002 | phys_page2 = get_page_addr_code(env, virt_page2); |
d720b93d | 1003 | } |
41c1b1c9 | 1004 | tb_link_page(tb, phys_pc, phys_page2); |
2e70f6ef | 1005 | return tb; |
d720b93d | 1006 | } |
3b46e624 | 1007 | |
9fa3e853 FB |
1008 | /* invalidate all TBs which intersect with the target physical page |
1009 | starting in range [start;end[. NOTE: start and end must refer to | |
d720b93d FB |
1010 | the same physical page. 'is_cpu_write_access' should be true if called |
1011 | from a real cpu write access: the virtual CPU will exit the current | |
1012 | TB if code is modified inside this TB. */ | |
41c1b1c9 | 1013 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, |
d720b93d FB |
1014 | int is_cpu_write_access) |
1015 | { | |
6b917547 | 1016 | TranslationBlock *tb, *tb_next, *saved_tb; |
d720b93d | 1017 | CPUState *env = cpu_single_env; |
41c1b1c9 | 1018 | tb_page_addr_t tb_start, tb_end; |
6b917547 AL |
1019 | PageDesc *p; |
1020 | int n; | |
1021 | #ifdef TARGET_HAS_PRECISE_SMC | |
1022 | int current_tb_not_found = is_cpu_write_access; | |
1023 | TranslationBlock *current_tb = NULL; | |
1024 | int current_tb_modified = 0; | |
1025 | target_ulong current_pc = 0; | |
1026 | target_ulong current_cs_base = 0; | |
1027 | int current_flags = 0; | |
1028 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
1029 | |
1030 | p = page_find(start >> TARGET_PAGE_BITS); | |
5fafdf24 | 1031 | if (!p) |
9fa3e853 | 1032 | return; |
5fafdf24 | 1033 | if (!p->code_bitmap && |
d720b93d FB |
1034 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && |
1035 | is_cpu_write_access) { | |
9fa3e853 FB |
1036 | /* build code bitmap */ |
1037 | build_page_bitmap(p); | |
1038 | } | |
1039 | ||
1040 | /* we remove all the TBs in the range [start, end[ */ | |
1041 | /* XXX: see if in some cases it could be faster to invalidate all the code */ | |
1042 | tb = p->first_tb; | |
1043 | while (tb != NULL) { | |
1044 | n = (long)tb & 3; | |
1045 | tb = (TranslationBlock *)((long)tb & ~3); | |
1046 | tb_next = tb->page_next[n]; | |
1047 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
1048 | if (n == 0) { | |
1049 | /* NOTE: tb_end may be after the end of the page, but | |
1050 | it is not a problem */ | |
1051 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
1052 | tb_end = tb_start + tb->size; | |
1053 | } else { | |
1054 | tb_start = tb->page_addr[1]; | |
1055 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
1056 | } | |
1057 | if (!(tb_end <= start || tb_start >= end)) { | |
d720b93d FB |
1058 | #ifdef TARGET_HAS_PRECISE_SMC |
1059 | if (current_tb_not_found) { | |
1060 | current_tb_not_found = 0; | |
1061 | current_tb = NULL; | |
2e70f6ef | 1062 | if (env->mem_io_pc) { |
d720b93d | 1063 | /* now we have a real cpu fault */ |
2e70f6ef | 1064 | current_tb = tb_find_pc(env->mem_io_pc); |
d720b93d FB |
1065 | } |
1066 | } | |
1067 | if (current_tb == tb && | |
2e70f6ef | 1068 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
1069 | /* If we are modifying the current TB, we must stop |
1070 | its execution. We could be more precise by checking | |
1071 | that the modification is after the current PC, but it | |
1072 | would require a specialized function to partially | |
1073 | restore the CPU state */ | |
3b46e624 | 1074 | |
d720b93d | 1075 | current_tb_modified = 1; |
618ba8e6 | 1076 | cpu_restore_state(current_tb, env, env->mem_io_pc); |
6b917547 AL |
1077 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1078 | ¤t_flags); | |
d720b93d FB |
1079 | } |
1080 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
6f5a9f7e FB |
1081 | /* we need to do that to handle the case where a signal |
1082 | occurs while doing tb_phys_invalidate() */ | |
1083 | saved_tb = NULL; | |
1084 | if (env) { | |
1085 | saved_tb = env->current_tb; | |
1086 | env->current_tb = NULL; | |
1087 | } | |
9fa3e853 | 1088 | tb_phys_invalidate(tb, -1); |
6f5a9f7e FB |
1089 | if (env) { |
1090 | env->current_tb = saved_tb; | |
1091 | if (env->interrupt_request && env->current_tb) | |
1092 | cpu_interrupt(env, env->interrupt_request); | |
1093 | } | |
9fa3e853 FB |
1094 | } |
1095 | tb = tb_next; | |
1096 | } | |
1097 | #if !defined(CONFIG_USER_ONLY) | |
1098 | /* if no code remaining, no need to continue to use slow writes */ | |
1099 | if (!p->first_tb) { | |
1100 | invalidate_page_bitmap(p); | |
d720b93d | 1101 | if (is_cpu_write_access) { |
2e70f6ef | 1102 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); |
d720b93d FB |
1103 | } |
1104 | } | |
1105 | #endif | |
1106 | #ifdef TARGET_HAS_PRECISE_SMC | |
1107 | if (current_tb_modified) { | |
1108 | /* we generate a block containing just the instruction | |
1109 | modifying the memory. It will ensure that it cannot modify | |
1110 | itself */ | |
ea1c1802 | 1111 | env->current_tb = NULL; |
2e70f6ef | 1112 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d | 1113 | cpu_resume_from_signal(env, NULL); |
9fa3e853 | 1114 | } |
fd6ce8f6 | 1115 | #endif |
9fa3e853 | 1116 | } |
fd6ce8f6 | 1117 | |
9fa3e853 | 1118 | /* len must be <= 8 and start must be a multiple of len */ |
41c1b1c9 | 1119 | static inline void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len) |
9fa3e853 FB |
1120 | { |
1121 | PageDesc *p; | |
1122 | int offset, b; | |
59817ccb | 1123 | #if 0 |
a4193c8a | 1124 | if (1) { |
93fcfe39 AL |
1125 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", |
1126 | cpu_single_env->mem_io_vaddr, len, | |
1127 | cpu_single_env->eip, | |
1128 | cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base); | |
59817ccb FB |
1129 | } |
1130 | #endif | |
9fa3e853 | 1131 | p = page_find(start >> TARGET_PAGE_BITS); |
5fafdf24 | 1132 | if (!p) |
9fa3e853 FB |
1133 | return; |
1134 | if (p->code_bitmap) { | |
1135 | offset = start & ~TARGET_PAGE_MASK; | |
1136 | b = p->code_bitmap[offset >> 3] >> (offset & 7); | |
1137 | if (b & ((1 << len) - 1)) | |
1138 | goto do_invalidate; | |
1139 | } else { | |
1140 | do_invalidate: | |
d720b93d | 1141 | tb_invalidate_phys_page_range(start, start + len, 1); |
9fa3e853 FB |
1142 | } |
1143 | } | |
1144 | ||
9fa3e853 | 1145 | #if !defined(CONFIG_SOFTMMU) |
41c1b1c9 | 1146 | static void tb_invalidate_phys_page(tb_page_addr_t addr, |
d720b93d | 1147 | unsigned long pc, void *puc) |
9fa3e853 | 1148 | { |
6b917547 | 1149 | TranslationBlock *tb; |
9fa3e853 | 1150 | PageDesc *p; |
6b917547 | 1151 | int n; |
d720b93d | 1152 | #ifdef TARGET_HAS_PRECISE_SMC |
6b917547 | 1153 | TranslationBlock *current_tb = NULL; |
d720b93d | 1154 | CPUState *env = cpu_single_env; |
6b917547 AL |
1155 | int current_tb_modified = 0; |
1156 | target_ulong current_pc = 0; | |
1157 | target_ulong current_cs_base = 0; | |
1158 | int current_flags = 0; | |
d720b93d | 1159 | #endif |
9fa3e853 FB |
1160 | |
1161 | addr &= TARGET_PAGE_MASK; | |
1162 | p = page_find(addr >> TARGET_PAGE_BITS); | |
5fafdf24 | 1163 | if (!p) |
9fa3e853 FB |
1164 | return; |
1165 | tb = p->first_tb; | |
d720b93d FB |
1166 | #ifdef TARGET_HAS_PRECISE_SMC |
1167 | if (tb && pc != 0) { | |
1168 | current_tb = tb_find_pc(pc); | |
1169 | } | |
1170 | #endif | |
9fa3e853 FB |
1171 | while (tb != NULL) { |
1172 | n = (long)tb & 3; | |
1173 | tb = (TranslationBlock *)((long)tb & ~3); | |
d720b93d FB |
1174 | #ifdef TARGET_HAS_PRECISE_SMC |
1175 | if (current_tb == tb && | |
2e70f6ef | 1176 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
1177 | /* If we are modifying the current TB, we must stop |
1178 | its execution. We could be more precise by checking | |
1179 | that the modification is after the current PC, but it | |
1180 | would require a specialized function to partially | |
1181 | restore the CPU state */ | |
3b46e624 | 1182 | |
d720b93d | 1183 | current_tb_modified = 1; |
618ba8e6 | 1184 | cpu_restore_state(current_tb, env, pc); |
6b917547 AL |
1185 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1186 | ¤t_flags); | |
d720b93d FB |
1187 | } |
1188 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
1189 | tb_phys_invalidate(tb, addr); |
1190 | tb = tb->page_next[n]; | |
1191 | } | |
fd6ce8f6 | 1192 | p->first_tb = NULL; |
d720b93d FB |
1193 | #ifdef TARGET_HAS_PRECISE_SMC |
1194 | if (current_tb_modified) { | |
1195 | /* we generate a block containing just the instruction | |
1196 | modifying the memory. It will ensure that it cannot modify | |
1197 | itself */ | |
ea1c1802 | 1198 | env->current_tb = NULL; |
2e70f6ef | 1199 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d FB |
1200 | cpu_resume_from_signal(env, puc); |
1201 | } | |
1202 | #endif | |
fd6ce8f6 | 1203 | } |
9fa3e853 | 1204 | #endif |
fd6ce8f6 FB |
1205 | |
1206 | /* add the tb in the target page and protect it if necessary */ | |
5fafdf24 | 1207 | static inline void tb_alloc_page(TranslationBlock *tb, |
41c1b1c9 | 1208 | unsigned int n, tb_page_addr_t page_addr) |
fd6ce8f6 FB |
1209 | { |
1210 | PageDesc *p; | |
9fa3e853 FB |
1211 | TranslationBlock *last_first_tb; |
1212 | ||
1213 | tb->page_addr[n] = page_addr; | |
5cd2c5b6 | 1214 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1); |
9fa3e853 FB |
1215 | tb->page_next[n] = p->first_tb; |
1216 | last_first_tb = p->first_tb; | |
1217 | p->first_tb = (TranslationBlock *)((long)tb | n); | |
1218 | invalidate_page_bitmap(p); | |
fd6ce8f6 | 1219 | |
107db443 | 1220 | #if defined(TARGET_HAS_SMC) || 1 |
d720b93d | 1221 | |
9fa3e853 | 1222 | #if defined(CONFIG_USER_ONLY) |
fd6ce8f6 | 1223 | if (p->flags & PAGE_WRITE) { |
53a5960a PB |
1224 | target_ulong addr; |
1225 | PageDesc *p2; | |
9fa3e853 FB |
1226 | int prot; |
1227 | ||
fd6ce8f6 FB |
1228 | /* force the host page as non writable (writes will have a |
1229 | page fault + mprotect overhead) */ | |
53a5960a | 1230 | page_addr &= qemu_host_page_mask; |
fd6ce8f6 | 1231 | prot = 0; |
53a5960a PB |
1232 | for(addr = page_addr; addr < page_addr + qemu_host_page_size; |
1233 | addr += TARGET_PAGE_SIZE) { | |
1234 | ||
1235 | p2 = page_find (addr >> TARGET_PAGE_BITS); | |
1236 | if (!p2) | |
1237 | continue; | |
1238 | prot |= p2->flags; | |
1239 | p2->flags &= ~PAGE_WRITE; | |
53a5960a | 1240 | } |
5fafdf24 | 1241 | mprotect(g2h(page_addr), qemu_host_page_size, |
fd6ce8f6 FB |
1242 | (prot & PAGE_BITS) & ~PAGE_WRITE); |
1243 | #ifdef DEBUG_TB_INVALIDATE | |
ab3d1727 | 1244 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", |
53a5960a | 1245 | page_addr); |
fd6ce8f6 | 1246 | #endif |
fd6ce8f6 | 1247 | } |
9fa3e853 FB |
1248 | #else |
1249 | /* if some code is already present, then the pages are already | |
1250 | protected. So we handle the case where only the first TB is | |
1251 | allocated in a physical page */ | |
1252 | if (!last_first_tb) { | |
6a00d601 | 1253 | tlb_protect_code(page_addr); |
9fa3e853 FB |
1254 | } |
1255 | #endif | |
d720b93d FB |
1256 | |
1257 | #endif /* TARGET_HAS_SMC */ | |
fd6ce8f6 FB |
1258 | } |
1259 | ||
9fa3e853 FB |
1260 | /* add a new TB and link it to the physical page tables. phys_page2 is |
1261 | (-1) to indicate that only one page contains the TB. */ | |
41c1b1c9 PB |
1262 | void tb_link_page(TranslationBlock *tb, |
1263 | tb_page_addr_t phys_pc, tb_page_addr_t phys_page2) | |
d4e8164f | 1264 | { |
9fa3e853 FB |
1265 | unsigned int h; |
1266 | TranslationBlock **ptb; | |
1267 | ||
c8a706fe PB |
1268 | /* Grab the mmap lock to stop another thread invalidating this TB |
1269 | before we are done. */ | |
1270 | mmap_lock(); | |
9fa3e853 FB |
1271 | /* add in the physical hash table */ |
1272 | h = tb_phys_hash_func(phys_pc); | |
1273 | ptb = &tb_phys_hash[h]; | |
1274 | tb->phys_hash_next = *ptb; | |
1275 | *ptb = tb; | |
fd6ce8f6 FB |
1276 | |
1277 | /* add in the page list */ | |
9fa3e853 FB |
1278 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); |
1279 | if (phys_page2 != -1) | |
1280 | tb_alloc_page(tb, 1, phys_page2); | |
1281 | else | |
1282 | tb->page_addr[1] = -1; | |
9fa3e853 | 1283 | |
d4e8164f FB |
1284 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); |
1285 | tb->jmp_next[0] = NULL; | |
1286 | tb->jmp_next[1] = NULL; | |
1287 | ||
1288 | /* init original jump addresses */ | |
1289 | if (tb->tb_next_offset[0] != 0xffff) | |
1290 | tb_reset_jump(tb, 0); | |
1291 | if (tb->tb_next_offset[1] != 0xffff) | |
1292 | tb_reset_jump(tb, 1); | |
8a40a180 FB |
1293 | |
1294 | #ifdef DEBUG_TB_CHECK | |
1295 | tb_page_check(); | |
1296 | #endif | |
c8a706fe | 1297 | mmap_unlock(); |
fd6ce8f6 FB |
1298 | } |
1299 | ||
9fa3e853 FB |
1300 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
1301 | tb[1].tc_ptr. Return NULL if not found */ | |
1302 | TranslationBlock *tb_find_pc(unsigned long tc_ptr) | |
fd6ce8f6 | 1303 | { |
9fa3e853 FB |
1304 | int m_min, m_max, m; |
1305 | unsigned long v; | |
1306 | TranslationBlock *tb; | |
a513fe19 FB |
1307 | |
1308 | if (nb_tbs <= 0) | |
1309 | return NULL; | |
1310 | if (tc_ptr < (unsigned long)code_gen_buffer || | |
1311 | tc_ptr >= (unsigned long)code_gen_ptr) | |
1312 | return NULL; | |
1313 | /* binary search (cf Knuth) */ | |
1314 | m_min = 0; | |
1315 | m_max = nb_tbs - 1; | |
1316 | while (m_min <= m_max) { | |
1317 | m = (m_min + m_max) >> 1; | |
1318 | tb = &tbs[m]; | |
1319 | v = (unsigned long)tb->tc_ptr; | |
1320 | if (v == tc_ptr) | |
1321 | return tb; | |
1322 | else if (tc_ptr < v) { | |
1323 | m_max = m - 1; | |
1324 | } else { | |
1325 | m_min = m + 1; | |
1326 | } | |
5fafdf24 | 1327 | } |
a513fe19 FB |
1328 | return &tbs[m_max]; |
1329 | } | |
7501267e | 1330 | |
ea041c0e FB |
1331 | static void tb_reset_jump_recursive(TranslationBlock *tb); |
1332 | ||
1333 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) | |
1334 | { | |
1335 | TranslationBlock *tb1, *tb_next, **ptb; | |
1336 | unsigned int n1; | |
1337 | ||
1338 | tb1 = tb->jmp_next[n]; | |
1339 | if (tb1 != NULL) { | |
1340 | /* find head of list */ | |
1341 | for(;;) { | |
1342 | n1 = (long)tb1 & 3; | |
1343 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1344 | if (n1 == 2) | |
1345 | break; | |
1346 | tb1 = tb1->jmp_next[n1]; | |
1347 | } | |
1348 | /* we are now sure now that tb jumps to tb1 */ | |
1349 | tb_next = tb1; | |
1350 | ||
1351 | /* remove tb from the jmp_first list */ | |
1352 | ptb = &tb_next->jmp_first; | |
1353 | for(;;) { | |
1354 | tb1 = *ptb; | |
1355 | n1 = (long)tb1 & 3; | |
1356 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1357 | if (n1 == n && tb1 == tb) | |
1358 | break; | |
1359 | ptb = &tb1->jmp_next[n1]; | |
1360 | } | |
1361 | *ptb = tb->jmp_next[n]; | |
1362 | tb->jmp_next[n] = NULL; | |
3b46e624 | 1363 | |
ea041c0e FB |
1364 | /* suppress the jump to next tb in generated code */ |
1365 | tb_reset_jump(tb, n); | |
1366 | ||
0124311e | 1367 | /* suppress jumps in the tb on which we could have jumped */ |
ea041c0e FB |
1368 | tb_reset_jump_recursive(tb_next); |
1369 | } | |
1370 | } | |
1371 | ||
1372 | static void tb_reset_jump_recursive(TranslationBlock *tb) | |
1373 | { | |
1374 | tb_reset_jump_recursive2(tb, 0); | |
1375 | tb_reset_jump_recursive2(tb, 1); | |
1376 | } | |
1377 | ||
1fddef4b | 1378 | #if defined(TARGET_HAS_ICE) |
94df27fd PB |
1379 | #if defined(CONFIG_USER_ONLY) |
1380 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) | |
1381 | { | |
1382 | tb_invalidate_phys_page_range(pc, pc + 1, 0); | |
1383 | } | |
1384 | #else | |
d720b93d FB |
1385 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
1386 | { | |
c227f099 | 1387 | target_phys_addr_t addr; |
9b3c35e0 | 1388 | target_ulong pd; |
c227f099 | 1389 | ram_addr_t ram_addr; |
c2f07f81 | 1390 | PhysPageDesc *p; |
d720b93d | 1391 | |
c2f07f81 PB |
1392 | addr = cpu_get_phys_page_debug(env, pc); |
1393 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
1394 | if (!p) { | |
1395 | pd = IO_MEM_UNASSIGNED; | |
1396 | } else { | |
1397 | pd = p->phys_offset; | |
1398 | } | |
1399 | ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK); | |
706cd4b5 | 1400 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
d720b93d | 1401 | } |
c27004ec | 1402 | #endif |
94df27fd | 1403 | #endif /* TARGET_HAS_ICE */ |
d720b93d | 1404 | |
c527ee8f PB |
1405 | #if defined(CONFIG_USER_ONLY) |
1406 | void cpu_watchpoint_remove_all(CPUState *env, int mask) | |
1407 | ||
1408 | { | |
1409 | } | |
1410 | ||
1411 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, | |
1412 | int flags, CPUWatchpoint **watchpoint) | |
1413 | { | |
1414 | return -ENOSYS; | |
1415 | } | |
1416 | #else | |
6658ffb8 | 1417 | /* Add a watchpoint. */ |
a1d1bb31 AL |
1418 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
1419 | int flags, CPUWatchpoint **watchpoint) | |
6658ffb8 | 1420 | { |
b4051334 | 1421 | target_ulong len_mask = ~(len - 1); |
c0ce998e | 1422 | CPUWatchpoint *wp; |
6658ffb8 | 1423 | |
b4051334 AL |
1424 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ |
1425 | if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) { | |
1426 | fprintf(stderr, "qemu: tried to set invalid watchpoint at " | |
1427 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); | |
1428 | return -EINVAL; | |
1429 | } | |
a1d1bb31 | 1430 | wp = qemu_malloc(sizeof(*wp)); |
a1d1bb31 AL |
1431 | |
1432 | wp->vaddr = addr; | |
b4051334 | 1433 | wp->len_mask = len_mask; |
a1d1bb31 AL |
1434 | wp->flags = flags; |
1435 | ||
2dc9f411 | 1436 | /* keep all GDB-injected watchpoints in front */ |
c0ce998e | 1437 | if (flags & BP_GDB) |
72cf2d4f | 1438 | QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); |
c0ce998e | 1439 | else |
72cf2d4f | 1440 | QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); |
6658ffb8 | 1441 | |
6658ffb8 | 1442 | tlb_flush_page(env, addr); |
a1d1bb31 AL |
1443 | |
1444 | if (watchpoint) | |
1445 | *watchpoint = wp; | |
1446 | return 0; | |
6658ffb8 PB |
1447 | } |
1448 | ||
a1d1bb31 AL |
1449 | /* Remove a specific watchpoint. */ |
1450 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len, | |
1451 | int flags) | |
6658ffb8 | 1452 | { |
b4051334 | 1453 | target_ulong len_mask = ~(len - 1); |
a1d1bb31 | 1454 | CPUWatchpoint *wp; |
6658ffb8 | 1455 | |
72cf2d4f | 1456 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 | 1457 | if (addr == wp->vaddr && len_mask == wp->len_mask |
6e140f28 | 1458 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
a1d1bb31 | 1459 | cpu_watchpoint_remove_by_ref(env, wp); |
6658ffb8 PB |
1460 | return 0; |
1461 | } | |
1462 | } | |
a1d1bb31 | 1463 | return -ENOENT; |
6658ffb8 PB |
1464 | } |
1465 | ||
a1d1bb31 AL |
1466 | /* Remove a specific watchpoint by reference. */ |
1467 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint) | |
1468 | { | |
72cf2d4f | 1469 | QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); |
7d03f82f | 1470 | |
a1d1bb31 AL |
1471 | tlb_flush_page(env, watchpoint->vaddr); |
1472 | ||
1473 | qemu_free(watchpoint); | |
1474 | } | |
1475 | ||
1476 | /* Remove all matching watchpoints. */ | |
1477 | void cpu_watchpoint_remove_all(CPUState *env, int mask) | |
1478 | { | |
c0ce998e | 1479 | CPUWatchpoint *wp, *next; |
a1d1bb31 | 1480 | |
72cf2d4f | 1481 | QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { |
a1d1bb31 AL |
1482 | if (wp->flags & mask) |
1483 | cpu_watchpoint_remove_by_ref(env, wp); | |
c0ce998e | 1484 | } |
7d03f82f | 1485 | } |
c527ee8f | 1486 | #endif |
7d03f82f | 1487 | |
a1d1bb31 AL |
1488 | /* Add a breakpoint. */ |
1489 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, | |
1490 | CPUBreakpoint **breakpoint) | |
4c3a88a2 | 1491 | { |
1fddef4b | 1492 | #if defined(TARGET_HAS_ICE) |
c0ce998e | 1493 | CPUBreakpoint *bp; |
3b46e624 | 1494 | |
a1d1bb31 | 1495 | bp = qemu_malloc(sizeof(*bp)); |
4c3a88a2 | 1496 | |
a1d1bb31 AL |
1497 | bp->pc = pc; |
1498 | bp->flags = flags; | |
1499 | ||
2dc9f411 | 1500 | /* keep all GDB-injected breakpoints in front */ |
c0ce998e | 1501 | if (flags & BP_GDB) |
72cf2d4f | 1502 | QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); |
c0ce998e | 1503 | else |
72cf2d4f | 1504 | QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); |
3b46e624 | 1505 | |
d720b93d | 1506 | breakpoint_invalidate(env, pc); |
a1d1bb31 AL |
1507 | |
1508 | if (breakpoint) | |
1509 | *breakpoint = bp; | |
4c3a88a2 FB |
1510 | return 0; |
1511 | #else | |
a1d1bb31 | 1512 | return -ENOSYS; |
4c3a88a2 FB |
1513 | #endif |
1514 | } | |
1515 | ||
a1d1bb31 AL |
1516 | /* Remove a specific breakpoint. */ |
1517 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags) | |
1518 | { | |
7d03f82f | 1519 | #if defined(TARGET_HAS_ICE) |
a1d1bb31 AL |
1520 | CPUBreakpoint *bp; |
1521 | ||
72cf2d4f | 1522 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
a1d1bb31 AL |
1523 | if (bp->pc == pc && bp->flags == flags) { |
1524 | cpu_breakpoint_remove_by_ref(env, bp); | |
1525 | return 0; | |
1526 | } | |
7d03f82f | 1527 | } |
a1d1bb31 AL |
1528 | return -ENOENT; |
1529 | #else | |
1530 | return -ENOSYS; | |
7d03f82f EI |
1531 | #endif |
1532 | } | |
1533 | ||
a1d1bb31 AL |
1534 | /* Remove a specific breakpoint by reference. */ |
1535 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint) | |
4c3a88a2 | 1536 | { |
1fddef4b | 1537 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 1538 | QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); |
d720b93d | 1539 | |
a1d1bb31 AL |
1540 | breakpoint_invalidate(env, breakpoint->pc); |
1541 | ||
1542 | qemu_free(breakpoint); | |
1543 | #endif | |
1544 | } | |
1545 | ||
1546 | /* Remove all matching breakpoints. */ | |
1547 | void cpu_breakpoint_remove_all(CPUState *env, int mask) | |
1548 | { | |
1549 | #if defined(TARGET_HAS_ICE) | |
c0ce998e | 1550 | CPUBreakpoint *bp, *next; |
a1d1bb31 | 1551 | |
72cf2d4f | 1552 | QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { |
a1d1bb31 AL |
1553 | if (bp->flags & mask) |
1554 | cpu_breakpoint_remove_by_ref(env, bp); | |
c0ce998e | 1555 | } |
4c3a88a2 FB |
1556 | #endif |
1557 | } | |
1558 | ||
c33a346e FB |
1559 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
1560 | CPU loop after each instruction */ | |
1561 | void cpu_single_step(CPUState *env, int enabled) | |
1562 | { | |
1fddef4b | 1563 | #if defined(TARGET_HAS_ICE) |
c33a346e FB |
1564 | if (env->singlestep_enabled != enabled) { |
1565 | env->singlestep_enabled = enabled; | |
e22a25c9 AL |
1566 | if (kvm_enabled()) |
1567 | kvm_update_guest_debug(env, 0); | |
1568 | else { | |
ccbb4d44 | 1569 | /* must flush all the translated code to avoid inconsistencies */ |
e22a25c9 AL |
1570 | /* XXX: only flush what is necessary */ |
1571 | tb_flush(env); | |
1572 | } | |
c33a346e FB |
1573 | } |
1574 | #endif | |
1575 | } | |
1576 | ||
34865134 FB |
1577 | /* enable or disable low levels log */ |
1578 | void cpu_set_log(int log_flags) | |
1579 | { | |
1580 | loglevel = log_flags; | |
1581 | if (loglevel && !logfile) { | |
11fcfab4 | 1582 | logfile = fopen(logfilename, log_append ? "a" : "w"); |
34865134 FB |
1583 | if (!logfile) { |
1584 | perror(logfilename); | |
1585 | _exit(1); | |
1586 | } | |
9fa3e853 FB |
1587 | #if !defined(CONFIG_SOFTMMU) |
1588 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ | |
1589 | { | |
b55266b5 | 1590 | static char logfile_buf[4096]; |
9fa3e853 FB |
1591 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); |
1592 | } | |
bf65f53f FN |
1593 | #elif !defined(_WIN32) |
1594 | /* Win32 doesn't support line-buffering and requires size >= 2 */ | |
34865134 | 1595 | setvbuf(logfile, NULL, _IOLBF, 0); |
9fa3e853 | 1596 | #endif |
e735b91c PB |
1597 | log_append = 1; |
1598 | } | |
1599 | if (!loglevel && logfile) { | |
1600 | fclose(logfile); | |
1601 | logfile = NULL; | |
34865134 FB |
1602 | } |
1603 | } | |
1604 | ||
1605 | void cpu_set_log_filename(const char *filename) | |
1606 | { | |
1607 | logfilename = strdup(filename); | |
e735b91c PB |
1608 | if (logfile) { |
1609 | fclose(logfile); | |
1610 | logfile = NULL; | |
1611 | } | |
1612 | cpu_set_log(loglevel); | |
34865134 | 1613 | } |
c33a346e | 1614 | |
3098dba0 | 1615 | static void cpu_unlink_tb(CPUState *env) |
ea041c0e | 1616 | { |
3098dba0 AJ |
1617 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the |
1618 | problem and hope the cpu will stop of its own accord. For userspace | |
1619 | emulation this often isn't actually as bad as it sounds. Often | |
1620 | signals are used primarily to interrupt blocking syscalls. */ | |
ea041c0e | 1621 | TranslationBlock *tb; |
c227f099 | 1622 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; |
59817ccb | 1623 | |
cab1b4bd | 1624 | spin_lock(&interrupt_lock); |
3098dba0 AJ |
1625 | tb = env->current_tb; |
1626 | /* if the cpu is currently executing code, we must unlink it and | |
1627 | all the potentially executing TB */ | |
f76cfe56 | 1628 | if (tb) { |
3098dba0 AJ |
1629 | env->current_tb = NULL; |
1630 | tb_reset_jump_recursive(tb); | |
be214e6c | 1631 | } |
cab1b4bd | 1632 | spin_unlock(&interrupt_lock); |
3098dba0 AJ |
1633 | } |
1634 | ||
97ffbd8d | 1635 | #ifndef CONFIG_USER_ONLY |
3098dba0 | 1636 | /* mask must never be zero, except for A20 change call */ |
ec6959d0 | 1637 | static void tcg_handle_interrupt(CPUState *env, int mask) |
3098dba0 AJ |
1638 | { |
1639 | int old_mask; | |
be214e6c | 1640 | |
2e70f6ef | 1641 | old_mask = env->interrupt_request; |
68a79315 | 1642 | env->interrupt_request |= mask; |
3098dba0 | 1643 | |
8edac960 AL |
1644 | /* |
1645 | * If called from iothread context, wake the target cpu in | |
1646 | * case its halted. | |
1647 | */ | |
b7680cb6 | 1648 | if (!qemu_cpu_is_self(env)) { |
8edac960 AL |
1649 | qemu_cpu_kick(env); |
1650 | return; | |
1651 | } | |
8edac960 | 1652 | |
2e70f6ef | 1653 | if (use_icount) { |
266910c4 | 1654 | env->icount_decr.u16.high = 0xffff; |
2e70f6ef | 1655 | if (!can_do_io(env) |
be214e6c | 1656 | && (mask & ~old_mask) != 0) { |
2e70f6ef PB |
1657 | cpu_abort(env, "Raised interrupt while not in I/O function"); |
1658 | } | |
2e70f6ef | 1659 | } else { |
3098dba0 | 1660 | cpu_unlink_tb(env); |
ea041c0e FB |
1661 | } |
1662 | } | |
1663 | ||
ec6959d0 JK |
1664 | CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt; |
1665 | ||
97ffbd8d JK |
1666 | #else /* CONFIG_USER_ONLY */ |
1667 | ||
1668 | void cpu_interrupt(CPUState *env, int mask) | |
1669 | { | |
1670 | env->interrupt_request |= mask; | |
1671 | cpu_unlink_tb(env); | |
1672 | } | |
1673 | #endif /* CONFIG_USER_ONLY */ | |
1674 | ||
b54ad049 FB |
1675 | void cpu_reset_interrupt(CPUState *env, int mask) |
1676 | { | |
1677 | env->interrupt_request &= ~mask; | |
1678 | } | |
1679 | ||
3098dba0 AJ |
1680 | void cpu_exit(CPUState *env) |
1681 | { | |
1682 | env->exit_request = 1; | |
1683 | cpu_unlink_tb(env); | |
1684 | } | |
1685 | ||
c7cd6a37 | 1686 | const CPULogItem cpu_log_items[] = { |
5fafdf24 | 1687 | { CPU_LOG_TB_OUT_ASM, "out_asm", |
f193c797 FB |
1688 | "show generated host assembly code for each compiled TB" }, |
1689 | { CPU_LOG_TB_IN_ASM, "in_asm", | |
1690 | "show target assembly code for each compiled TB" }, | |
5fafdf24 | 1691 | { CPU_LOG_TB_OP, "op", |
57fec1fe | 1692 | "show micro ops for each compiled TB" }, |
f193c797 | 1693 | { CPU_LOG_TB_OP_OPT, "op_opt", |
e01a1157 BS |
1694 | "show micro ops " |
1695 | #ifdef TARGET_I386 | |
1696 | "before eflags optimization and " | |
f193c797 | 1697 | #endif |
e01a1157 | 1698 | "after liveness analysis" }, |
f193c797 FB |
1699 | { CPU_LOG_INT, "int", |
1700 | "show interrupts/exceptions in short format" }, | |
1701 | { CPU_LOG_EXEC, "exec", | |
1702 | "show trace before each executed TB (lots of logs)" }, | |
9fddaa0c | 1703 | { CPU_LOG_TB_CPU, "cpu", |
e91c8a77 | 1704 | "show CPU state before block translation" }, |
f193c797 FB |
1705 | #ifdef TARGET_I386 |
1706 | { CPU_LOG_PCALL, "pcall", | |
1707 | "show protected mode far calls/returns/exceptions" }, | |
eca1bdf4 AL |
1708 | { CPU_LOG_RESET, "cpu_reset", |
1709 | "show CPU state before CPU resets" }, | |
f193c797 | 1710 | #endif |
8e3a9fd2 | 1711 | #ifdef DEBUG_IOPORT |
fd872598 FB |
1712 | { CPU_LOG_IOPORT, "ioport", |
1713 | "show all i/o ports accesses" }, | |
8e3a9fd2 | 1714 | #endif |
f193c797 FB |
1715 | { 0, NULL, NULL }, |
1716 | }; | |
1717 | ||
f6f3fbca MT |
1718 | #ifndef CONFIG_USER_ONLY |
1719 | static QLIST_HEAD(memory_client_list, CPUPhysMemoryClient) memory_client_list | |
1720 | = QLIST_HEAD_INITIALIZER(memory_client_list); | |
1721 | ||
1722 | static void cpu_notify_set_memory(target_phys_addr_t start_addr, | |
9742bf26 | 1723 | ram_addr_t size, |
0fd542fb MT |
1724 | ram_addr_t phys_offset, |
1725 | bool log_dirty) | |
f6f3fbca MT |
1726 | { |
1727 | CPUPhysMemoryClient *client; | |
1728 | QLIST_FOREACH(client, &memory_client_list, list) { | |
0fd542fb | 1729 | client->set_memory(client, start_addr, size, phys_offset, log_dirty); |
f6f3fbca MT |
1730 | } |
1731 | } | |
1732 | ||
1733 | static int cpu_notify_sync_dirty_bitmap(target_phys_addr_t start, | |
9742bf26 | 1734 | target_phys_addr_t end) |
f6f3fbca MT |
1735 | { |
1736 | CPUPhysMemoryClient *client; | |
1737 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1738 | int r = client->sync_dirty_bitmap(client, start, end); | |
1739 | if (r < 0) | |
1740 | return r; | |
1741 | } | |
1742 | return 0; | |
1743 | } | |
1744 | ||
1745 | static int cpu_notify_migration_log(int enable) | |
1746 | { | |
1747 | CPUPhysMemoryClient *client; | |
1748 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1749 | int r = client->migration_log(client, enable); | |
1750 | if (r < 0) | |
1751 | return r; | |
1752 | } | |
1753 | return 0; | |
1754 | } | |
1755 | ||
2173a75f AW |
1756 | struct last_map { |
1757 | target_phys_addr_t start_addr; | |
1758 | ram_addr_t size; | |
1759 | ram_addr_t phys_offset; | |
1760 | }; | |
1761 | ||
8d4c78e7 AW |
1762 | /* The l1_phys_map provides the upper P_L1_BITs of the guest physical |
1763 | * address. Each intermediate table provides the next L2_BITs of guest | |
1764 | * physical address space. The number of levels vary based on host and | |
1765 | * guest configuration, making it efficient to build the final guest | |
1766 | * physical address by seeding the L1 offset and shifting and adding in | |
1767 | * each L2 offset as we recurse through them. */ | |
2173a75f AW |
1768 | static void phys_page_for_each_1(CPUPhysMemoryClient *client, int level, |
1769 | void **lp, target_phys_addr_t addr, | |
1770 | struct last_map *map) | |
f6f3fbca | 1771 | { |
5cd2c5b6 | 1772 | int i; |
f6f3fbca | 1773 | |
5cd2c5b6 RH |
1774 | if (*lp == NULL) { |
1775 | return; | |
1776 | } | |
1777 | if (level == 0) { | |
1778 | PhysPageDesc *pd = *lp; | |
8d4c78e7 | 1779 | addr <<= L2_BITS + TARGET_PAGE_BITS; |
7296abac | 1780 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 | 1781 | if (pd[i].phys_offset != IO_MEM_UNASSIGNED) { |
2173a75f AW |
1782 | target_phys_addr_t start_addr = addr | i << TARGET_PAGE_BITS; |
1783 | ||
1784 | if (map->size && | |
1785 | start_addr == map->start_addr + map->size && | |
1786 | pd[i].phys_offset == map->phys_offset + map->size) { | |
1787 | ||
1788 | map->size += TARGET_PAGE_SIZE; | |
1789 | continue; | |
1790 | } else if (map->size) { | |
1791 | client->set_memory(client, map->start_addr, | |
1792 | map->size, map->phys_offset, false); | |
1793 | } | |
1794 | ||
1795 | map->start_addr = start_addr; | |
1796 | map->size = TARGET_PAGE_SIZE; | |
1797 | map->phys_offset = pd[i].phys_offset; | |
f6f3fbca | 1798 | } |
5cd2c5b6 RH |
1799 | } |
1800 | } else { | |
1801 | void **pp = *lp; | |
7296abac | 1802 | for (i = 0; i < L2_SIZE; ++i) { |
8d4c78e7 | 1803 | phys_page_for_each_1(client, level - 1, pp + i, |
2173a75f | 1804 | (addr << L2_BITS) | i, map); |
f6f3fbca MT |
1805 | } |
1806 | } | |
1807 | } | |
1808 | ||
1809 | static void phys_page_for_each(CPUPhysMemoryClient *client) | |
1810 | { | |
5cd2c5b6 | 1811 | int i; |
2173a75f AW |
1812 | struct last_map map = { }; |
1813 | ||
5cd2c5b6 RH |
1814 | for (i = 0; i < P_L1_SIZE; ++i) { |
1815 | phys_page_for_each_1(client, P_L1_SHIFT / L2_BITS - 1, | |
2173a75f AW |
1816 | l1_phys_map + i, i, &map); |
1817 | } | |
1818 | if (map.size) { | |
1819 | client->set_memory(client, map.start_addr, map.size, map.phys_offset, | |
1820 | false); | |
f6f3fbca | 1821 | } |
f6f3fbca MT |
1822 | } |
1823 | ||
1824 | void cpu_register_phys_memory_client(CPUPhysMemoryClient *client) | |
1825 | { | |
1826 | QLIST_INSERT_HEAD(&memory_client_list, client, list); | |
1827 | phys_page_for_each(client); | |
1828 | } | |
1829 | ||
1830 | void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *client) | |
1831 | { | |
1832 | QLIST_REMOVE(client, list); | |
1833 | } | |
1834 | #endif | |
1835 | ||
f193c797 FB |
1836 | static int cmp1(const char *s1, int n, const char *s2) |
1837 | { | |
1838 | if (strlen(s2) != n) | |
1839 | return 0; | |
1840 | return memcmp(s1, s2, n) == 0; | |
1841 | } | |
3b46e624 | 1842 | |
f193c797 FB |
1843 | /* takes a comma separated list of log masks. Return 0 if error. */ |
1844 | int cpu_str_to_log_mask(const char *str) | |
1845 | { | |
c7cd6a37 | 1846 | const CPULogItem *item; |
f193c797 FB |
1847 | int mask; |
1848 | const char *p, *p1; | |
1849 | ||
1850 | p = str; | |
1851 | mask = 0; | |
1852 | for(;;) { | |
1853 | p1 = strchr(p, ','); | |
1854 | if (!p1) | |
1855 | p1 = p + strlen(p); | |
9742bf26 YT |
1856 | if(cmp1(p,p1-p,"all")) { |
1857 | for(item = cpu_log_items; item->mask != 0; item++) { | |
1858 | mask |= item->mask; | |
1859 | } | |
1860 | } else { | |
1861 | for(item = cpu_log_items; item->mask != 0; item++) { | |
1862 | if (cmp1(p, p1 - p, item->name)) | |
1863 | goto found; | |
1864 | } | |
1865 | return 0; | |
f193c797 | 1866 | } |
f193c797 FB |
1867 | found: |
1868 | mask |= item->mask; | |
1869 | if (*p1 != ',') | |
1870 | break; | |
1871 | p = p1 + 1; | |
1872 | } | |
1873 | return mask; | |
1874 | } | |
ea041c0e | 1875 | |
7501267e FB |
1876 | void cpu_abort(CPUState *env, const char *fmt, ...) |
1877 | { | |
1878 | va_list ap; | |
493ae1f0 | 1879 | va_list ap2; |
7501267e FB |
1880 | |
1881 | va_start(ap, fmt); | |
493ae1f0 | 1882 | va_copy(ap2, ap); |
7501267e FB |
1883 | fprintf(stderr, "qemu: fatal: "); |
1884 | vfprintf(stderr, fmt, ap); | |
1885 | fprintf(stderr, "\n"); | |
1886 | #ifdef TARGET_I386 | |
7fe48483 FB |
1887 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); |
1888 | #else | |
1889 | cpu_dump_state(env, stderr, fprintf, 0); | |
7501267e | 1890 | #endif |
93fcfe39 AL |
1891 | if (qemu_log_enabled()) { |
1892 | qemu_log("qemu: fatal: "); | |
1893 | qemu_log_vprintf(fmt, ap2); | |
1894 | qemu_log("\n"); | |
f9373291 | 1895 | #ifdef TARGET_I386 |
93fcfe39 | 1896 | log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP); |
f9373291 | 1897 | #else |
93fcfe39 | 1898 | log_cpu_state(env, 0); |
f9373291 | 1899 | #endif |
31b1a7b4 | 1900 | qemu_log_flush(); |
93fcfe39 | 1901 | qemu_log_close(); |
924edcae | 1902 | } |
493ae1f0 | 1903 | va_end(ap2); |
f9373291 | 1904 | va_end(ap); |
fd052bf6 RV |
1905 | #if defined(CONFIG_USER_ONLY) |
1906 | { | |
1907 | struct sigaction act; | |
1908 | sigfillset(&act.sa_mask); | |
1909 | act.sa_handler = SIG_DFL; | |
1910 | sigaction(SIGABRT, &act, NULL); | |
1911 | } | |
1912 | #endif | |
7501267e FB |
1913 | abort(); |
1914 | } | |
1915 | ||
c5be9f08 TS |
1916 | CPUState *cpu_copy(CPUState *env) |
1917 | { | |
01ba9816 | 1918 | CPUState *new_env = cpu_init(env->cpu_model_str); |
c5be9f08 TS |
1919 | CPUState *next_cpu = new_env->next_cpu; |
1920 | int cpu_index = new_env->cpu_index; | |
5a38f081 AL |
1921 | #if defined(TARGET_HAS_ICE) |
1922 | CPUBreakpoint *bp; | |
1923 | CPUWatchpoint *wp; | |
1924 | #endif | |
1925 | ||
c5be9f08 | 1926 | memcpy(new_env, env, sizeof(CPUState)); |
5a38f081 AL |
1927 | |
1928 | /* Preserve chaining and index. */ | |
c5be9f08 TS |
1929 | new_env->next_cpu = next_cpu; |
1930 | new_env->cpu_index = cpu_index; | |
5a38f081 AL |
1931 | |
1932 | /* Clone all break/watchpoints. | |
1933 | Note: Once we support ptrace with hw-debug register access, make sure | |
1934 | BP_CPU break/watchpoints are handled correctly on clone. */ | |
72cf2d4f BS |
1935 | QTAILQ_INIT(&env->breakpoints); |
1936 | QTAILQ_INIT(&env->watchpoints); | |
5a38f081 | 1937 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 1938 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
5a38f081 AL |
1939 | cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); |
1940 | } | |
72cf2d4f | 1941 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
5a38f081 AL |
1942 | cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, |
1943 | wp->flags, NULL); | |
1944 | } | |
1945 | #endif | |
1946 | ||
c5be9f08 TS |
1947 | return new_env; |
1948 | } | |
1949 | ||
0124311e FB |
1950 | #if !defined(CONFIG_USER_ONLY) |
1951 | ||
5c751e99 EI |
1952 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr) |
1953 | { | |
1954 | unsigned int i; | |
1955 | ||
1956 | /* Discard jump cache entries for any tb which might potentially | |
1957 | overlap the flushed page. */ | |
1958 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); | |
1959 | memset (&env->tb_jmp_cache[i], 0, | |
9742bf26 | 1960 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
5c751e99 EI |
1961 | |
1962 | i = tb_jmp_cache_hash_page(addr); | |
1963 | memset (&env->tb_jmp_cache[i], 0, | |
9742bf26 | 1964 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
5c751e99 EI |
1965 | } |
1966 | ||
08738984 IK |
1967 | static CPUTLBEntry s_cputlb_empty_entry = { |
1968 | .addr_read = -1, | |
1969 | .addr_write = -1, | |
1970 | .addr_code = -1, | |
1971 | .addend = -1, | |
1972 | }; | |
1973 | ||
ee8b7021 FB |
1974 | /* NOTE: if flush_global is true, also flush global entries (not |
1975 | implemented yet) */ | |
1976 | void tlb_flush(CPUState *env, int flush_global) | |
33417e70 | 1977 | { |
33417e70 | 1978 | int i; |
0124311e | 1979 | |
9fa3e853 FB |
1980 | #if defined(DEBUG_TLB) |
1981 | printf("tlb_flush:\n"); | |
1982 | #endif | |
0124311e FB |
1983 | /* must reset current TB so that interrupts cannot modify the |
1984 | links while we are modifying them */ | |
1985 | env->current_tb = NULL; | |
1986 | ||
33417e70 | 1987 | for(i = 0; i < CPU_TLB_SIZE; i++) { |
cfde4bd9 IY |
1988 | int mmu_idx; |
1989 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
08738984 | 1990 | env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry; |
cfde4bd9 | 1991 | } |
33417e70 | 1992 | } |
9fa3e853 | 1993 | |
8a40a180 | 1994 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
9fa3e853 | 1995 | |
d4c430a8 PB |
1996 | env->tlb_flush_addr = -1; |
1997 | env->tlb_flush_mask = 0; | |
e3db7226 | 1998 | tlb_flush_count++; |
33417e70 FB |
1999 | } |
2000 | ||
274da6b2 | 2001 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
61382a50 | 2002 | { |
5fafdf24 | 2003 | if (addr == (tlb_entry->addr_read & |
84b7b8e7 | 2004 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 2005 | addr == (tlb_entry->addr_write & |
84b7b8e7 | 2006 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 2007 | addr == (tlb_entry->addr_code & |
84b7b8e7 | 2008 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
08738984 | 2009 | *tlb_entry = s_cputlb_empty_entry; |
84b7b8e7 | 2010 | } |
61382a50 FB |
2011 | } |
2012 | ||
2e12669a | 2013 | void tlb_flush_page(CPUState *env, target_ulong addr) |
33417e70 | 2014 | { |
8a40a180 | 2015 | int i; |
cfde4bd9 | 2016 | int mmu_idx; |
0124311e | 2017 | |
9fa3e853 | 2018 | #if defined(DEBUG_TLB) |
108c49b8 | 2019 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
9fa3e853 | 2020 | #endif |
d4c430a8 PB |
2021 | /* Check if we need to flush due to large pages. */ |
2022 | if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) { | |
2023 | #if defined(DEBUG_TLB) | |
2024 | printf("tlb_flush_page: forced full flush (" | |
2025 | TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", | |
2026 | env->tlb_flush_addr, env->tlb_flush_mask); | |
2027 | #endif | |
2028 | tlb_flush(env, 1); | |
2029 | return; | |
2030 | } | |
0124311e FB |
2031 | /* must reset current TB so that interrupts cannot modify the |
2032 | links while we are modifying them */ | |
2033 | env->current_tb = NULL; | |
61382a50 FB |
2034 | |
2035 | addr &= TARGET_PAGE_MASK; | |
2036 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
cfde4bd9 IY |
2037 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
2038 | tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); | |
0124311e | 2039 | |
5c751e99 | 2040 | tlb_flush_jmp_cache(env, addr); |
9fa3e853 FB |
2041 | } |
2042 | ||
9fa3e853 FB |
2043 | /* update the TLBs so that writes to code in the virtual page 'addr' |
2044 | can be detected */ | |
c227f099 | 2045 | static void tlb_protect_code(ram_addr_t ram_addr) |
9fa3e853 | 2046 | { |
5fafdf24 | 2047 | cpu_physical_memory_reset_dirty(ram_addr, |
6a00d601 FB |
2048 | ram_addr + TARGET_PAGE_SIZE, |
2049 | CODE_DIRTY_FLAG); | |
9fa3e853 FB |
2050 | } |
2051 | ||
9fa3e853 | 2052 | /* update the TLB so that writes in physical page 'phys_addr' are no longer |
3a7d929e | 2053 | tested for self modifying code */ |
c227f099 | 2054 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
3a7d929e | 2055 | target_ulong vaddr) |
9fa3e853 | 2056 | { |
f7c11b53 | 2057 | cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG); |
1ccde1cb FB |
2058 | } |
2059 | ||
5fafdf24 | 2060 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, |
1ccde1cb FB |
2061 | unsigned long start, unsigned long length) |
2062 | { | |
2063 | unsigned long addr; | |
84b7b8e7 FB |
2064 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
2065 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; | |
1ccde1cb | 2066 | if ((addr - start) < length) { |
0f459d16 | 2067 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY; |
1ccde1cb FB |
2068 | } |
2069 | } | |
2070 | } | |
2071 | ||
5579c7f3 | 2072 | /* Note: start and end must be within the same ram block. */ |
c227f099 | 2073 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
0a962c02 | 2074 | int dirty_flags) |
1ccde1cb FB |
2075 | { |
2076 | CPUState *env; | |
4f2ac237 | 2077 | unsigned long length, start1; |
f7c11b53 | 2078 | int i; |
1ccde1cb FB |
2079 | |
2080 | start &= TARGET_PAGE_MASK; | |
2081 | end = TARGET_PAGE_ALIGN(end); | |
2082 | ||
2083 | length = end - start; | |
2084 | if (length == 0) | |
2085 | return; | |
f7c11b53 | 2086 | cpu_physical_memory_mask_dirty_range(start, length, dirty_flags); |
f23db169 | 2087 | |
1ccde1cb FB |
2088 | /* we modify the TLB cache so that the dirty bit will be set again |
2089 | when accessing the range */ | |
b2e0a138 | 2090 | start1 = (unsigned long)qemu_safe_ram_ptr(start); |
a57d23e4 | 2091 | /* Check that we don't span multiple blocks - this breaks the |
5579c7f3 | 2092 | address comparisons below. */ |
b2e0a138 | 2093 | if ((unsigned long)qemu_safe_ram_ptr(end - 1) - start1 |
5579c7f3 PB |
2094 | != (end - 1) - start) { |
2095 | abort(); | |
2096 | } | |
2097 | ||
6a00d601 | 2098 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
cfde4bd9 IY |
2099 | int mmu_idx; |
2100 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
2101 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
2102 | tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], | |
2103 | start1, length); | |
2104 | } | |
6a00d601 | 2105 | } |
1ccde1cb FB |
2106 | } |
2107 | ||
74576198 AL |
2108 | int cpu_physical_memory_set_dirty_tracking(int enable) |
2109 | { | |
f6f3fbca | 2110 | int ret = 0; |
74576198 | 2111 | in_migration = enable; |
f6f3fbca MT |
2112 | ret = cpu_notify_migration_log(!!enable); |
2113 | return ret; | |
74576198 AL |
2114 | } |
2115 | ||
2116 | int cpu_physical_memory_get_dirty_tracking(void) | |
2117 | { | |
2118 | return in_migration; | |
2119 | } | |
2120 | ||
c227f099 AL |
2121 | int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, |
2122 | target_phys_addr_t end_addr) | |
2bec46dc | 2123 | { |
7b8f3b78 | 2124 | int ret; |
151f7749 | 2125 | |
f6f3fbca | 2126 | ret = cpu_notify_sync_dirty_bitmap(start_addr, end_addr); |
151f7749 | 2127 | return ret; |
2bec46dc AL |
2128 | } |
2129 | ||
e5896b12 AP |
2130 | int cpu_physical_log_start(target_phys_addr_t start_addr, |
2131 | ram_addr_t size) | |
2132 | { | |
2133 | CPUPhysMemoryClient *client; | |
2134 | QLIST_FOREACH(client, &memory_client_list, list) { | |
2135 | if (client->log_start) { | |
2136 | int r = client->log_start(client, start_addr, size); | |
2137 | if (r < 0) { | |
2138 | return r; | |
2139 | } | |
2140 | } | |
2141 | } | |
2142 | return 0; | |
2143 | } | |
2144 | ||
2145 | int cpu_physical_log_stop(target_phys_addr_t start_addr, | |
2146 | ram_addr_t size) | |
2147 | { | |
2148 | CPUPhysMemoryClient *client; | |
2149 | QLIST_FOREACH(client, &memory_client_list, list) { | |
2150 | if (client->log_stop) { | |
2151 | int r = client->log_stop(client, start_addr, size); | |
2152 | if (r < 0) { | |
2153 | return r; | |
2154 | } | |
2155 | } | |
2156 | } | |
2157 | return 0; | |
2158 | } | |
2159 | ||
3a7d929e FB |
2160 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
2161 | { | |
c227f099 | 2162 | ram_addr_t ram_addr; |
5579c7f3 | 2163 | void *p; |
3a7d929e | 2164 | |
84b7b8e7 | 2165 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
5579c7f3 PB |
2166 | p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK) |
2167 | + tlb_entry->addend); | |
e890261f | 2168 | ram_addr = qemu_ram_addr_from_host_nofail(p); |
3a7d929e | 2169 | if (!cpu_physical_memory_is_dirty(ram_addr)) { |
0f459d16 | 2170 | tlb_entry->addr_write |= TLB_NOTDIRTY; |
3a7d929e FB |
2171 | } |
2172 | } | |
2173 | } | |
2174 | ||
2175 | /* update the TLB according to the current state of the dirty bits */ | |
2176 | void cpu_tlb_update_dirty(CPUState *env) | |
2177 | { | |
2178 | int i; | |
cfde4bd9 IY |
2179 | int mmu_idx; |
2180 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
2181 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
2182 | tlb_update_dirty(&env->tlb_table[mmu_idx][i]); | |
2183 | } | |
3a7d929e FB |
2184 | } |
2185 | ||
0f459d16 | 2186 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) |
1ccde1cb | 2187 | { |
0f459d16 PB |
2188 | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) |
2189 | tlb_entry->addr_write = vaddr; | |
1ccde1cb FB |
2190 | } |
2191 | ||
0f459d16 PB |
2192 | /* update the TLB corresponding to virtual page vaddr |
2193 | so that it is no longer dirty */ | |
2194 | static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) | |
1ccde1cb | 2195 | { |
1ccde1cb | 2196 | int i; |
cfde4bd9 | 2197 | int mmu_idx; |
1ccde1cb | 2198 | |
0f459d16 | 2199 | vaddr &= TARGET_PAGE_MASK; |
1ccde1cb | 2200 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
cfde4bd9 IY |
2201 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
2202 | tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr); | |
9fa3e853 FB |
2203 | } |
2204 | ||
d4c430a8 PB |
2205 | /* Our TLB does not support large pages, so remember the area covered by |
2206 | large pages and trigger a full TLB flush if these are invalidated. */ | |
2207 | static void tlb_add_large_page(CPUState *env, target_ulong vaddr, | |
2208 | target_ulong size) | |
2209 | { | |
2210 | target_ulong mask = ~(size - 1); | |
2211 | ||
2212 | if (env->tlb_flush_addr == (target_ulong)-1) { | |
2213 | env->tlb_flush_addr = vaddr & mask; | |
2214 | env->tlb_flush_mask = mask; | |
2215 | return; | |
2216 | } | |
2217 | /* Extend the existing region to include the new page. | |
2218 | This is a compromise between unnecessary flushes and the cost | |
2219 | of maintaining a full variable size TLB. */ | |
2220 | mask &= env->tlb_flush_mask; | |
2221 | while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) { | |
2222 | mask <<= 1; | |
2223 | } | |
2224 | env->tlb_flush_addr &= mask; | |
2225 | env->tlb_flush_mask = mask; | |
2226 | } | |
2227 | ||
2228 | /* Add a new TLB entry. At most one entry for a given virtual address | |
2229 | is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the | |
2230 | supplied size is only used by tlb_flush_page. */ | |
2231 | void tlb_set_page(CPUState *env, target_ulong vaddr, | |
2232 | target_phys_addr_t paddr, int prot, | |
2233 | int mmu_idx, target_ulong size) | |
9fa3e853 | 2234 | { |
92e873b9 | 2235 | PhysPageDesc *p; |
4f2ac237 | 2236 | unsigned long pd; |
9fa3e853 | 2237 | unsigned int index; |
4f2ac237 | 2238 | target_ulong address; |
0f459d16 | 2239 | target_ulong code_address; |
355b1943 | 2240 | unsigned long addend; |
84b7b8e7 | 2241 | CPUTLBEntry *te; |
a1d1bb31 | 2242 | CPUWatchpoint *wp; |
c227f099 | 2243 | target_phys_addr_t iotlb; |
9fa3e853 | 2244 | |
d4c430a8 PB |
2245 | assert(size >= TARGET_PAGE_SIZE); |
2246 | if (size != TARGET_PAGE_SIZE) { | |
2247 | tlb_add_large_page(env, vaddr, size); | |
2248 | } | |
92e873b9 | 2249 | p = phys_page_find(paddr >> TARGET_PAGE_BITS); |
9fa3e853 FB |
2250 | if (!p) { |
2251 | pd = IO_MEM_UNASSIGNED; | |
9fa3e853 FB |
2252 | } else { |
2253 | pd = p->phys_offset; | |
9fa3e853 FB |
2254 | } |
2255 | #if defined(DEBUG_TLB) | |
7fd3f494 SW |
2256 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx |
2257 | " prot=%x idx=%d pd=0x%08lx\n", | |
2258 | vaddr, paddr, prot, mmu_idx, pd); | |
9fa3e853 FB |
2259 | #endif |
2260 | ||
0f459d16 PB |
2261 | address = vaddr; |
2262 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { | |
2263 | /* IO memory case (romd handled later) */ | |
2264 | address |= TLB_MMIO; | |
2265 | } | |
5579c7f3 | 2266 | addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK); |
0f459d16 PB |
2267 | if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { |
2268 | /* Normal RAM. */ | |
2269 | iotlb = pd & TARGET_PAGE_MASK; | |
2270 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM) | |
2271 | iotlb |= IO_MEM_NOTDIRTY; | |
2272 | else | |
2273 | iotlb |= IO_MEM_ROM; | |
2274 | } else { | |
ccbb4d44 | 2275 | /* IO handlers are currently passed a physical address. |
0f459d16 PB |
2276 | It would be nice to pass an offset from the base address |
2277 | of that region. This would avoid having to special case RAM, | |
2278 | and avoid full address decoding in every device. | |
2279 | We can't use the high bits of pd for this because | |
2280 | IO_MEM_ROMD uses these as a ram address. */ | |
8da3ff18 PB |
2281 | iotlb = (pd & ~TARGET_PAGE_MASK); |
2282 | if (p) { | |
8da3ff18 PB |
2283 | iotlb += p->region_offset; |
2284 | } else { | |
2285 | iotlb += paddr; | |
2286 | } | |
0f459d16 PB |
2287 | } |
2288 | ||
2289 | code_address = address; | |
2290 | /* Make accesses to pages with watchpoints go via the | |
2291 | watchpoint trap routines. */ | |
72cf2d4f | 2292 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
a1d1bb31 | 2293 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { |
bf298f83 JK |
2294 | /* Avoid trapping reads of pages with a write breakpoint. */ |
2295 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { | |
2296 | iotlb = io_mem_watch + paddr; | |
2297 | address |= TLB_MMIO; | |
2298 | break; | |
2299 | } | |
6658ffb8 | 2300 | } |
0f459d16 | 2301 | } |
d79acba4 | 2302 | |
0f459d16 PB |
2303 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
2304 | env->iotlb[mmu_idx][index] = iotlb - vaddr; | |
2305 | te = &env->tlb_table[mmu_idx][index]; | |
2306 | te->addend = addend - vaddr; | |
2307 | if (prot & PAGE_READ) { | |
2308 | te->addr_read = address; | |
2309 | } else { | |
2310 | te->addr_read = -1; | |
2311 | } | |
5c751e99 | 2312 | |
0f459d16 PB |
2313 | if (prot & PAGE_EXEC) { |
2314 | te->addr_code = code_address; | |
2315 | } else { | |
2316 | te->addr_code = -1; | |
2317 | } | |
2318 | if (prot & PAGE_WRITE) { | |
2319 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM || | |
2320 | (pd & IO_MEM_ROMD)) { | |
2321 | /* Write access calls the I/O callback. */ | |
2322 | te->addr_write = address | TLB_MMIO; | |
2323 | } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM && | |
2324 | !cpu_physical_memory_is_dirty(pd)) { | |
2325 | te->addr_write = address | TLB_NOTDIRTY; | |
9fa3e853 | 2326 | } else { |
0f459d16 | 2327 | te->addr_write = address; |
9fa3e853 | 2328 | } |
0f459d16 PB |
2329 | } else { |
2330 | te->addr_write = -1; | |
9fa3e853 | 2331 | } |
9fa3e853 FB |
2332 | } |
2333 | ||
0124311e FB |
2334 | #else |
2335 | ||
ee8b7021 | 2336 | void tlb_flush(CPUState *env, int flush_global) |
0124311e FB |
2337 | { |
2338 | } | |
2339 | ||
2e12669a | 2340 | void tlb_flush_page(CPUState *env, target_ulong addr) |
0124311e FB |
2341 | { |
2342 | } | |
2343 | ||
edf8e2af MW |
2344 | /* |
2345 | * Walks guest process memory "regions" one by one | |
2346 | * and calls callback function 'fn' for each region. | |
2347 | */ | |
5cd2c5b6 RH |
2348 | |
2349 | struct walk_memory_regions_data | |
2350 | { | |
2351 | walk_memory_regions_fn fn; | |
2352 | void *priv; | |
2353 | unsigned long start; | |
2354 | int prot; | |
2355 | }; | |
2356 | ||
2357 | static int walk_memory_regions_end(struct walk_memory_regions_data *data, | |
b480d9b7 | 2358 | abi_ulong end, int new_prot) |
5cd2c5b6 RH |
2359 | { |
2360 | if (data->start != -1ul) { | |
2361 | int rc = data->fn(data->priv, data->start, end, data->prot); | |
2362 | if (rc != 0) { | |
2363 | return rc; | |
2364 | } | |
2365 | } | |
2366 | ||
2367 | data->start = (new_prot ? end : -1ul); | |
2368 | data->prot = new_prot; | |
2369 | ||
2370 | return 0; | |
2371 | } | |
2372 | ||
2373 | static int walk_memory_regions_1(struct walk_memory_regions_data *data, | |
b480d9b7 | 2374 | abi_ulong base, int level, void **lp) |
5cd2c5b6 | 2375 | { |
b480d9b7 | 2376 | abi_ulong pa; |
5cd2c5b6 RH |
2377 | int i, rc; |
2378 | ||
2379 | if (*lp == NULL) { | |
2380 | return walk_memory_regions_end(data, base, 0); | |
2381 | } | |
2382 | ||
2383 | if (level == 0) { | |
2384 | PageDesc *pd = *lp; | |
7296abac | 2385 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 RH |
2386 | int prot = pd[i].flags; |
2387 | ||
2388 | pa = base | (i << TARGET_PAGE_BITS); | |
2389 | if (prot != data->prot) { | |
2390 | rc = walk_memory_regions_end(data, pa, prot); | |
2391 | if (rc != 0) { | |
2392 | return rc; | |
9fa3e853 | 2393 | } |
9fa3e853 | 2394 | } |
5cd2c5b6 RH |
2395 | } |
2396 | } else { | |
2397 | void **pp = *lp; | |
7296abac | 2398 | for (i = 0; i < L2_SIZE; ++i) { |
b480d9b7 PB |
2399 | pa = base | ((abi_ulong)i << |
2400 | (TARGET_PAGE_BITS + L2_BITS * level)); | |
5cd2c5b6 RH |
2401 | rc = walk_memory_regions_1(data, pa, level - 1, pp + i); |
2402 | if (rc != 0) { | |
2403 | return rc; | |
2404 | } | |
2405 | } | |
2406 | } | |
2407 | ||
2408 | return 0; | |
2409 | } | |
2410 | ||
2411 | int walk_memory_regions(void *priv, walk_memory_regions_fn fn) | |
2412 | { | |
2413 | struct walk_memory_regions_data data; | |
2414 | unsigned long i; | |
2415 | ||
2416 | data.fn = fn; | |
2417 | data.priv = priv; | |
2418 | data.start = -1ul; | |
2419 | data.prot = 0; | |
2420 | ||
2421 | for (i = 0; i < V_L1_SIZE; i++) { | |
b480d9b7 | 2422 | int rc = walk_memory_regions_1(&data, (abi_ulong)i << V_L1_SHIFT, |
5cd2c5b6 RH |
2423 | V_L1_SHIFT / L2_BITS - 1, l1_map + i); |
2424 | if (rc != 0) { | |
2425 | return rc; | |
9fa3e853 | 2426 | } |
33417e70 | 2427 | } |
5cd2c5b6 RH |
2428 | |
2429 | return walk_memory_regions_end(&data, 0, 0); | |
edf8e2af MW |
2430 | } |
2431 | ||
b480d9b7 PB |
2432 | static int dump_region(void *priv, abi_ulong start, |
2433 | abi_ulong end, unsigned long prot) | |
edf8e2af MW |
2434 | { |
2435 | FILE *f = (FILE *)priv; | |
2436 | ||
b480d9b7 PB |
2437 | (void) fprintf(f, TARGET_ABI_FMT_lx"-"TARGET_ABI_FMT_lx |
2438 | " "TARGET_ABI_FMT_lx" %c%c%c\n", | |
edf8e2af MW |
2439 | start, end, end - start, |
2440 | ((prot & PAGE_READ) ? 'r' : '-'), | |
2441 | ((prot & PAGE_WRITE) ? 'w' : '-'), | |
2442 | ((prot & PAGE_EXEC) ? 'x' : '-')); | |
2443 | ||
2444 | return (0); | |
2445 | } | |
2446 | ||
2447 | /* dump memory mappings */ | |
2448 | void page_dump(FILE *f) | |
2449 | { | |
2450 | (void) fprintf(f, "%-8s %-8s %-8s %s\n", | |
2451 | "start", "end", "size", "prot"); | |
2452 | walk_memory_regions(f, dump_region); | |
33417e70 FB |
2453 | } |
2454 | ||
53a5960a | 2455 | int page_get_flags(target_ulong address) |
33417e70 | 2456 | { |
9fa3e853 FB |
2457 | PageDesc *p; |
2458 | ||
2459 | p = page_find(address >> TARGET_PAGE_BITS); | |
33417e70 | 2460 | if (!p) |
9fa3e853 FB |
2461 | return 0; |
2462 | return p->flags; | |
2463 | } | |
2464 | ||
376a7909 RH |
2465 | /* Modify the flags of a page and invalidate the code if necessary. |
2466 | The flag PAGE_WRITE_ORG is positioned automatically depending | |
2467 | on PAGE_WRITE. The mmap_lock should already be held. */ | |
53a5960a | 2468 | void page_set_flags(target_ulong start, target_ulong end, int flags) |
9fa3e853 | 2469 | { |
376a7909 RH |
2470 | target_ulong addr, len; |
2471 | ||
2472 | /* This function should never be called with addresses outside the | |
2473 | guest address space. If this assert fires, it probably indicates | |
2474 | a missing call to h2g_valid. */ | |
b480d9b7 PB |
2475 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
2476 | assert(end < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); | |
376a7909 RH |
2477 | #endif |
2478 | assert(start < end); | |
9fa3e853 FB |
2479 | |
2480 | start = start & TARGET_PAGE_MASK; | |
2481 | end = TARGET_PAGE_ALIGN(end); | |
376a7909 RH |
2482 | |
2483 | if (flags & PAGE_WRITE) { | |
9fa3e853 | 2484 | flags |= PAGE_WRITE_ORG; |
376a7909 RH |
2485 | } |
2486 | ||
2487 | for (addr = start, len = end - start; | |
2488 | len != 0; | |
2489 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
2490 | PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2491 | ||
2492 | /* If the write protection bit is set, then we invalidate | |
2493 | the code inside. */ | |
5fafdf24 | 2494 | if (!(p->flags & PAGE_WRITE) && |
9fa3e853 FB |
2495 | (flags & PAGE_WRITE) && |
2496 | p->first_tb) { | |
d720b93d | 2497 | tb_invalidate_phys_page(addr, 0, NULL); |
9fa3e853 FB |
2498 | } |
2499 | p->flags = flags; | |
2500 | } | |
33417e70 FB |
2501 | } |
2502 | ||
3d97b40b TS |
2503 | int page_check_range(target_ulong start, target_ulong len, int flags) |
2504 | { | |
2505 | PageDesc *p; | |
2506 | target_ulong end; | |
2507 | target_ulong addr; | |
2508 | ||
376a7909 RH |
2509 | /* This function should never be called with addresses outside the |
2510 | guest address space. If this assert fires, it probably indicates | |
2511 | a missing call to h2g_valid. */ | |
338e9e6c BS |
2512 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
2513 | assert(start < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); | |
376a7909 RH |
2514 | #endif |
2515 | ||
3e0650a9 RH |
2516 | if (len == 0) { |
2517 | return 0; | |
2518 | } | |
376a7909 RH |
2519 | if (start + len - 1 < start) { |
2520 | /* We've wrapped around. */ | |
55f280c9 | 2521 | return -1; |
376a7909 | 2522 | } |
55f280c9 | 2523 | |
3d97b40b TS |
2524 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */ |
2525 | start = start & TARGET_PAGE_MASK; | |
2526 | ||
376a7909 RH |
2527 | for (addr = start, len = end - start; |
2528 | len != 0; | |
2529 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
3d97b40b TS |
2530 | p = page_find(addr >> TARGET_PAGE_BITS); |
2531 | if( !p ) | |
2532 | return -1; | |
2533 | if( !(p->flags & PAGE_VALID) ) | |
2534 | return -1; | |
2535 | ||
dae3270c | 2536 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) |
3d97b40b | 2537 | return -1; |
dae3270c FB |
2538 | if (flags & PAGE_WRITE) { |
2539 | if (!(p->flags & PAGE_WRITE_ORG)) | |
2540 | return -1; | |
2541 | /* unprotect the page if it was put read-only because it | |
2542 | contains translated code */ | |
2543 | if (!(p->flags & PAGE_WRITE)) { | |
2544 | if (!page_unprotect(addr, 0, NULL)) | |
2545 | return -1; | |
2546 | } | |
2547 | return 0; | |
2548 | } | |
3d97b40b TS |
2549 | } |
2550 | return 0; | |
2551 | } | |
2552 | ||
9fa3e853 | 2553 | /* called from signal handler: invalidate the code and unprotect the |
ccbb4d44 | 2554 | page. Return TRUE if the fault was successfully handled. */ |
53a5960a | 2555 | int page_unprotect(target_ulong address, unsigned long pc, void *puc) |
9fa3e853 | 2556 | { |
45d679d6 AJ |
2557 | unsigned int prot; |
2558 | PageDesc *p; | |
53a5960a | 2559 | target_ulong host_start, host_end, addr; |
9fa3e853 | 2560 | |
c8a706fe PB |
2561 | /* Technically this isn't safe inside a signal handler. However we |
2562 | know this only ever happens in a synchronous SEGV handler, so in | |
2563 | practice it seems to be ok. */ | |
2564 | mmap_lock(); | |
2565 | ||
45d679d6 AJ |
2566 | p = page_find(address >> TARGET_PAGE_BITS); |
2567 | if (!p) { | |
c8a706fe | 2568 | mmap_unlock(); |
9fa3e853 | 2569 | return 0; |
c8a706fe | 2570 | } |
45d679d6 | 2571 | |
9fa3e853 FB |
2572 | /* if the page was really writable, then we change its |
2573 | protection back to writable */ | |
45d679d6 AJ |
2574 | if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) { |
2575 | host_start = address & qemu_host_page_mask; | |
2576 | host_end = host_start + qemu_host_page_size; | |
2577 | ||
2578 | prot = 0; | |
2579 | for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) { | |
2580 | p = page_find(addr >> TARGET_PAGE_BITS); | |
2581 | p->flags |= PAGE_WRITE; | |
2582 | prot |= p->flags; | |
2583 | ||
9fa3e853 FB |
2584 | /* and since the content will be modified, we must invalidate |
2585 | the corresponding translated code. */ | |
45d679d6 | 2586 | tb_invalidate_phys_page(addr, pc, puc); |
9fa3e853 | 2587 | #ifdef DEBUG_TB_CHECK |
45d679d6 | 2588 | tb_invalidate_check(addr); |
9fa3e853 | 2589 | #endif |
9fa3e853 | 2590 | } |
45d679d6 AJ |
2591 | mprotect((void *)g2h(host_start), qemu_host_page_size, |
2592 | prot & PAGE_BITS); | |
2593 | ||
2594 | mmap_unlock(); | |
2595 | return 1; | |
9fa3e853 | 2596 | } |
c8a706fe | 2597 | mmap_unlock(); |
9fa3e853 FB |
2598 | return 0; |
2599 | } | |
2600 | ||
6a00d601 FB |
2601 | static inline void tlb_set_dirty(CPUState *env, |
2602 | unsigned long addr, target_ulong vaddr) | |
1ccde1cb FB |
2603 | { |
2604 | } | |
9fa3e853 FB |
2605 | #endif /* defined(CONFIG_USER_ONLY) */ |
2606 | ||
e2eef170 | 2607 | #if !defined(CONFIG_USER_ONLY) |
8da3ff18 | 2608 | |
c04b2b78 PB |
2609 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
2610 | typedef struct subpage_t { | |
2611 | target_phys_addr_t base; | |
f6405247 RH |
2612 | ram_addr_t sub_io_index[TARGET_PAGE_SIZE]; |
2613 | ram_addr_t region_offset[TARGET_PAGE_SIZE]; | |
c04b2b78 PB |
2614 | } subpage_t; |
2615 | ||
c227f099 AL |
2616 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
2617 | ram_addr_t memory, ram_addr_t region_offset); | |
f6405247 RH |
2618 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
2619 | ram_addr_t orig_memory, | |
2620 | ram_addr_t region_offset); | |
db7b5426 BS |
2621 | #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ |
2622 | need_subpage) \ | |
2623 | do { \ | |
2624 | if (addr > start_addr) \ | |
2625 | start_addr2 = 0; \ | |
2626 | else { \ | |
2627 | start_addr2 = start_addr & ~TARGET_PAGE_MASK; \ | |
2628 | if (start_addr2 > 0) \ | |
2629 | need_subpage = 1; \ | |
2630 | } \ | |
2631 | \ | |
49e9fba2 | 2632 | if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \ |
db7b5426 BS |
2633 | end_addr2 = TARGET_PAGE_SIZE - 1; \ |
2634 | else { \ | |
2635 | end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \ | |
2636 | if (end_addr2 < TARGET_PAGE_SIZE - 1) \ | |
2637 | need_subpage = 1; \ | |
2638 | } \ | |
2639 | } while (0) | |
2640 | ||
8f2498f9 MT |
2641 | /* register physical memory. |
2642 | For RAM, 'size' must be a multiple of the target page size. | |
2643 | If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an | |
8da3ff18 PB |
2644 | io memory page. The address used when calling the IO function is |
2645 | the offset from the start of the region, plus region_offset. Both | |
ccbb4d44 | 2646 | start_addr and region_offset are rounded down to a page boundary |
8da3ff18 PB |
2647 | before calculating this offset. This should not be a problem unless |
2648 | the low bits of start_addr and region_offset differ. */ | |
0fd542fb | 2649 | void cpu_register_physical_memory_log(target_phys_addr_t start_addr, |
c227f099 AL |
2650 | ram_addr_t size, |
2651 | ram_addr_t phys_offset, | |
0fd542fb MT |
2652 | ram_addr_t region_offset, |
2653 | bool log_dirty) | |
33417e70 | 2654 | { |
c227f099 | 2655 | target_phys_addr_t addr, end_addr; |
92e873b9 | 2656 | PhysPageDesc *p; |
9d42037b | 2657 | CPUState *env; |
c227f099 | 2658 | ram_addr_t orig_size = size; |
f6405247 | 2659 | subpage_t *subpage; |
33417e70 | 2660 | |
3b8e6a2d | 2661 | assert(size); |
0fd542fb | 2662 | cpu_notify_set_memory(start_addr, size, phys_offset, log_dirty); |
f6f3fbca | 2663 | |
67c4d23c PB |
2664 | if (phys_offset == IO_MEM_UNASSIGNED) { |
2665 | region_offset = start_addr; | |
2666 | } | |
8da3ff18 | 2667 | region_offset &= TARGET_PAGE_MASK; |
5fd386f6 | 2668 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
c227f099 | 2669 | end_addr = start_addr + (target_phys_addr_t)size; |
3b8e6a2d EI |
2670 | |
2671 | addr = start_addr; | |
2672 | do { | |
db7b5426 BS |
2673 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
2674 | if (p && p->phys_offset != IO_MEM_UNASSIGNED) { | |
c227f099 AL |
2675 | ram_addr_t orig_memory = p->phys_offset; |
2676 | target_phys_addr_t start_addr2, end_addr2; | |
db7b5426 BS |
2677 | int need_subpage = 0; |
2678 | ||
2679 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, | |
2680 | need_subpage); | |
f6405247 | 2681 | if (need_subpage) { |
db7b5426 BS |
2682 | if (!(orig_memory & IO_MEM_SUBPAGE)) { |
2683 | subpage = subpage_init((addr & TARGET_PAGE_MASK), | |
8da3ff18 PB |
2684 | &p->phys_offset, orig_memory, |
2685 | p->region_offset); | |
db7b5426 BS |
2686 | } else { |
2687 | subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK) | |
2688 | >> IO_MEM_SHIFT]; | |
2689 | } | |
8da3ff18 PB |
2690 | subpage_register(subpage, start_addr2, end_addr2, phys_offset, |
2691 | region_offset); | |
2692 | p->region_offset = 0; | |
db7b5426 BS |
2693 | } else { |
2694 | p->phys_offset = phys_offset; | |
2695 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || | |
2696 | (phys_offset & IO_MEM_ROMD)) | |
2697 | phys_offset += TARGET_PAGE_SIZE; | |
2698 | } | |
2699 | } else { | |
2700 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2701 | p->phys_offset = phys_offset; | |
8da3ff18 | 2702 | p->region_offset = region_offset; |
db7b5426 | 2703 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
8da3ff18 | 2704 | (phys_offset & IO_MEM_ROMD)) { |
db7b5426 | 2705 | phys_offset += TARGET_PAGE_SIZE; |
0e8f0967 | 2706 | } else { |
c227f099 | 2707 | target_phys_addr_t start_addr2, end_addr2; |
db7b5426 BS |
2708 | int need_subpage = 0; |
2709 | ||
2710 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, | |
2711 | end_addr2, need_subpage); | |
2712 | ||
f6405247 | 2713 | if (need_subpage) { |
db7b5426 | 2714 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
8da3ff18 | 2715 | &p->phys_offset, IO_MEM_UNASSIGNED, |
67c4d23c | 2716 | addr & TARGET_PAGE_MASK); |
db7b5426 | 2717 | subpage_register(subpage, start_addr2, end_addr2, |
8da3ff18 PB |
2718 | phys_offset, region_offset); |
2719 | p->region_offset = 0; | |
db7b5426 BS |
2720 | } |
2721 | } | |
2722 | } | |
8da3ff18 | 2723 | region_offset += TARGET_PAGE_SIZE; |
3b8e6a2d EI |
2724 | addr += TARGET_PAGE_SIZE; |
2725 | } while (addr != end_addr); | |
3b46e624 | 2726 | |
9d42037b FB |
2727 | /* since each CPU stores ram addresses in its TLB cache, we must |
2728 | reset the modified entries */ | |
2729 | /* XXX: slow ! */ | |
2730 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
2731 | tlb_flush(env, 1); | |
2732 | } | |
33417e70 FB |
2733 | } |
2734 | ||
ba863458 | 2735 | /* XXX: temporary until new memory mapping API */ |
c227f099 | 2736 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr) |
ba863458 FB |
2737 | { |
2738 | PhysPageDesc *p; | |
2739 | ||
2740 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2741 | if (!p) | |
2742 | return IO_MEM_UNASSIGNED; | |
2743 | return p->phys_offset; | |
2744 | } | |
2745 | ||
c227f099 | 2746 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
f65ed4c1 AL |
2747 | { |
2748 | if (kvm_enabled()) | |
2749 | kvm_coalesce_mmio_region(addr, size); | |
2750 | } | |
2751 | ||
c227f099 | 2752 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
f65ed4c1 AL |
2753 | { |
2754 | if (kvm_enabled()) | |
2755 | kvm_uncoalesce_mmio_region(addr, size); | |
2756 | } | |
2757 | ||
62a2744c SY |
2758 | void qemu_flush_coalesced_mmio_buffer(void) |
2759 | { | |
2760 | if (kvm_enabled()) | |
2761 | kvm_flush_coalesced_mmio_buffer(); | |
2762 | } | |
2763 | ||
c902760f MT |
2764 | #if defined(__linux__) && !defined(TARGET_S390X) |
2765 | ||
2766 | #include <sys/vfs.h> | |
2767 | ||
2768 | #define HUGETLBFS_MAGIC 0x958458f6 | |
2769 | ||
2770 | static long gethugepagesize(const char *path) | |
2771 | { | |
2772 | struct statfs fs; | |
2773 | int ret; | |
2774 | ||
2775 | do { | |
9742bf26 | 2776 | ret = statfs(path, &fs); |
c902760f MT |
2777 | } while (ret != 0 && errno == EINTR); |
2778 | ||
2779 | if (ret != 0) { | |
9742bf26 YT |
2780 | perror(path); |
2781 | return 0; | |
c902760f MT |
2782 | } |
2783 | ||
2784 | if (fs.f_type != HUGETLBFS_MAGIC) | |
9742bf26 | 2785 | fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path); |
c902760f MT |
2786 | |
2787 | return fs.f_bsize; | |
2788 | } | |
2789 | ||
04b16653 AW |
2790 | static void *file_ram_alloc(RAMBlock *block, |
2791 | ram_addr_t memory, | |
2792 | const char *path) | |
c902760f MT |
2793 | { |
2794 | char *filename; | |
2795 | void *area; | |
2796 | int fd; | |
2797 | #ifdef MAP_POPULATE | |
2798 | int flags; | |
2799 | #endif | |
2800 | unsigned long hpagesize; | |
2801 | ||
2802 | hpagesize = gethugepagesize(path); | |
2803 | if (!hpagesize) { | |
9742bf26 | 2804 | return NULL; |
c902760f MT |
2805 | } |
2806 | ||
2807 | if (memory < hpagesize) { | |
2808 | return NULL; | |
2809 | } | |
2810 | ||
2811 | if (kvm_enabled() && !kvm_has_sync_mmu()) { | |
2812 | fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n"); | |
2813 | return NULL; | |
2814 | } | |
2815 | ||
2816 | if (asprintf(&filename, "%s/qemu_back_mem.XXXXXX", path) == -1) { | |
9742bf26 | 2817 | return NULL; |
c902760f MT |
2818 | } |
2819 | ||
2820 | fd = mkstemp(filename); | |
2821 | if (fd < 0) { | |
9742bf26 YT |
2822 | perror("unable to create backing store for hugepages"); |
2823 | free(filename); | |
2824 | return NULL; | |
c902760f MT |
2825 | } |
2826 | unlink(filename); | |
2827 | free(filename); | |
2828 | ||
2829 | memory = (memory+hpagesize-1) & ~(hpagesize-1); | |
2830 | ||
2831 | /* | |
2832 | * ftruncate is not supported by hugetlbfs in older | |
2833 | * hosts, so don't bother bailing out on errors. | |
2834 | * If anything goes wrong with it under other filesystems, | |
2835 | * mmap will fail. | |
2836 | */ | |
2837 | if (ftruncate(fd, memory)) | |
9742bf26 | 2838 | perror("ftruncate"); |
c902760f MT |
2839 | |
2840 | #ifdef MAP_POPULATE | |
2841 | /* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case | |
2842 | * MAP_PRIVATE is requested. For mem_prealloc we mmap as MAP_SHARED | |
2843 | * to sidestep this quirk. | |
2844 | */ | |
2845 | flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE; | |
2846 | area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0); | |
2847 | #else | |
2848 | area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); | |
2849 | #endif | |
2850 | if (area == MAP_FAILED) { | |
9742bf26 YT |
2851 | perror("file_ram_alloc: can't mmap RAM pages"); |
2852 | close(fd); | |
2853 | return (NULL); | |
c902760f | 2854 | } |
04b16653 | 2855 | block->fd = fd; |
c902760f MT |
2856 | return area; |
2857 | } | |
2858 | #endif | |
2859 | ||
d17b5288 | 2860 | static ram_addr_t find_ram_offset(ram_addr_t size) |
04b16653 AW |
2861 | { |
2862 | RAMBlock *block, *next_block; | |
09d7ae90 | 2863 | ram_addr_t offset = 0, mingap = ULONG_MAX; |
04b16653 AW |
2864 | |
2865 | if (QLIST_EMPTY(&ram_list.blocks)) | |
2866 | return 0; | |
2867 | ||
2868 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
2869 | ram_addr_t end, next = ULONG_MAX; | |
2870 | ||
2871 | end = block->offset + block->length; | |
2872 | ||
2873 | QLIST_FOREACH(next_block, &ram_list.blocks, next) { | |
2874 | if (next_block->offset >= end) { | |
2875 | next = MIN(next, next_block->offset); | |
2876 | } | |
2877 | } | |
2878 | if (next - end >= size && next - end < mingap) { | |
2879 | offset = end; | |
2880 | mingap = next - end; | |
2881 | } | |
2882 | } | |
2883 | return offset; | |
2884 | } | |
2885 | ||
2886 | static ram_addr_t last_ram_offset(void) | |
d17b5288 AW |
2887 | { |
2888 | RAMBlock *block; | |
2889 | ram_addr_t last = 0; | |
2890 | ||
2891 | QLIST_FOREACH(block, &ram_list.blocks, next) | |
2892 | last = MAX(last, block->offset + block->length); | |
2893 | ||
2894 | return last; | |
2895 | } | |
2896 | ||
84b89d78 | 2897 | ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name, |
6977dfe6 | 2898 | ram_addr_t size, void *host) |
84b89d78 CM |
2899 | { |
2900 | RAMBlock *new_block, *block; | |
2901 | ||
2902 | size = TARGET_PAGE_ALIGN(size); | |
2903 | new_block = qemu_mallocz(sizeof(*new_block)); | |
2904 | ||
2905 | if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) { | |
2906 | char *id = dev->parent_bus->info->get_dev_path(dev); | |
2907 | if (id) { | |
2908 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); | |
2909 | qemu_free(id); | |
2910 | } | |
2911 | } | |
2912 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); | |
2913 | ||
2914 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
2915 | if (!strcmp(block->idstr, new_block->idstr)) { | |
2916 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", | |
2917 | new_block->idstr); | |
2918 | abort(); | |
2919 | } | |
2920 | } | |
2921 | ||
432d268c | 2922 | new_block->offset = find_ram_offset(size); |
6977dfe6 YT |
2923 | if (host) { |
2924 | new_block->host = host; | |
cd19cfa2 | 2925 | new_block->flags |= RAM_PREALLOC_MASK; |
6977dfe6 YT |
2926 | } else { |
2927 | if (mem_path) { | |
c902760f | 2928 | #if defined (__linux__) && !defined(TARGET_S390X) |
6977dfe6 YT |
2929 | new_block->host = file_ram_alloc(new_block, size, mem_path); |
2930 | if (!new_block->host) { | |
2931 | new_block->host = qemu_vmalloc(size); | |
e78815a5 | 2932 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); |
6977dfe6 | 2933 | } |
c902760f | 2934 | #else |
6977dfe6 YT |
2935 | fprintf(stderr, "-mem-path option unsupported\n"); |
2936 | exit(1); | |
c902760f | 2937 | #endif |
6977dfe6 | 2938 | } else { |
6b02494d | 2939 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
ff83678a CB |
2940 | /* S390 KVM requires the topmost vma of the RAM to be smaller than |
2941 | an system defined value, which is at least 256GB. Larger systems | |
2942 | have larger values. We put the guest between the end of data | |
2943 | segment (system break) and this value. We use 32GB as a base to | |
2944 | have enough room for the system break to grow. */ | |
2945 | new_block->host = mmap((void*)0x800000000, size, | |
6977dfe6 | 2946 | PROT_EXEC|PROT_READ|PROT_WRITE, |
ff83678a | 2947 | MAP_SHARED | MAP_ANONYMOUS | MAP_FIXED, -1, 0); |
fb8b2735 AG |
2948 | if (new_block->host == MAP_FAILED) { |
2949 | fprintf(stderr, "Allocating RAM failed\n"); | |
2950 | abort(); | |
2951 | } | |
6b02494d | 2952 | #else |
432d268c JN |
2953 | if (xen_mapcache_enabled()) { |
2954 | xen_ram_alloc(new_block->offset, size); | |
2955 | } else { | |
2956 | new_block->host = qemu_vmalloc(size); | |
2957 | } | |
6b02494d | 2958 | #endif |
e78815a5 | 2959 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); |
6977dfe6 | 2960 | } |
c902760f | 2961 | } |
94a6b54f PB |
2962 | new_block->length = size; |
2963 | ||
f471a17e | 2964 | QLIST_INSERT_HEAD(&ram_list.blocks, new_block, next); |
94a6b54f | 2965 | |
f471a17e | 2966 | ram_list.phys_dirty = qemu_realloc(ram_list.phys_dirty, |
04b16653 | 2967 | last_ram_offset() >> TARGET_PAGE_BITS); |
d17b5288 | 2968 | memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS), |
94a6b54f PB |
2969 | 0xff, size >> TARGET_PAGE_BITS); |
2970 | ||
6f0437e8 JK |
2971 | if (kvm_enabled()) |
2972 | kvm_setup_guest_memory(new_block->host, size); | |
2973 | ||
94a6b54f PB |
2974 | return new_block->offset; |
2975 | } | |
e9a1ab19 | 2976 | |
6977dfe6 YT |
2977 | ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size) |
2978 | { | |
2979 | return qemu_ram_alloc_from_ptr(dev, name, size, NULL); | |
2980 | } | |
2981 | ||
1f2e98b6 AW |
2982 | void qemu_ram_free_from_ptr(ram_addr_t addr) |
2983 | { | |
2984 | RAMBlock *block; | |
2985 | ||
2986 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
2987 | if (addr == block->offset) { | |
2988 | QLIST_REMOVE(block, next); | |
2989 | qemu_free(block); | |
2990 | return; | |
2991 | } | |
2992 | } | |
2993 | } | |
2994 | ||
c227f099 | 2995 | void qemu_ram_free(ram_addr_t addr) |
e9a1ab19 | 2996 | { |
04b16653 AW |
2997 | RAMBlock *block; |
2998 | ||
2999 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
3000 | if (addr == block->offset) { | |
3001 | QLIST_REMOVE(block, next); | |
cd19cfa2 HY |
3002 | if (block->flags & RAM_PREALLOC_MASK) { |
3003 | ; | |
3004 | } else if (mem_path) { | |
04b16653 AW |
3005 | #if defined (__linux__) && !defined(TARGET_S390X) |
3006 | if (block->fd) { | |
3007 | munmap(block->host, block->length); | |
3008 | close(block->fd); | |
3009 | } else { | |
3010 | qemu_vfree(block->host); | |
3011 | } | |
fd28aa13 JK |
3012 | #else |
3013 | abort(); | |
04b16653 AW |
3014 | #endif |
3015 | } else { | |
3016 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) | |
3017 | munmap(block->host, block->length); | |
3018 | #else | |
432d268c JN |
3019 | if (xen_mapcache_enabled()) { |
3020 | qemu_invalidate_entry(block->host); | |
3021 | } else { | |
3022 | qemu_vfree(block->host); | |
3023 | } | |
04b16653 AW |
3024 | #endif |
3025 | } | |
3026 | qemu_free(block); | |
3027 | return; | |
3028 | } | |
3029 | } | |
3030 | ||
e9a1ab19 FB |
3031 | } |
3032 | ||
cd19cfa2 HY |
3033 | #ifndef _WIN32 |
3034 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) | |
3035 | { | |
3036 | RAMBlock *block; | |
3037 | ram_addr_t offset; | |
3038 | int flags; | |
3039 | void *area, *vaddr; | |
3040 | ||
3041 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
3042 | offset = addr - block->offset; | |
3043 | if (offset < block->length) { | |
3044 | vaddr = block->host + offset; | |
3045 | if (block->flags & RAM_PREALLOC_MASK) { | |
3046 | ; | |
3047 | } else { | |
3048 | flags = MAP_FIXED; | |
3049 | munmap(vaddr, length); | |
3050 | if (mem_path) { | |
3051 | #if defined(__linux__) && !defined(TARGET_S390X) | |
3052 | if (block->fd) { | |
3053 | #ifdef MAP_POPULATE | |
3054 | flags |= mem_prealloc ? MAP_POPULATE | MAP_SHARED : | |
3055 | MAP_PRIVATE; | |
3056 | #else | |
3057 | flags |= MAP_PRIVATE; | |
3058 | #endif | |
3059 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
3060 | flags, block->fd, offset); | |
3061 | } else { | |
3062 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; | |
3063 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
3064 | flags, -1, 0); | |
3065 | } | |
fd28aa13 JK |
3066 | #else |
3067 | abort(); | |
cd19cfa2 HY |
3068 | #endif |
3069 | } else { | |
3070 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) | |
3071 | flags |= MAP_SHARED | MAP_ANONYMOUS; | |
3072 | area = mmap(vaddr, length, PROT_EXEC|PROT_READ|PROT_WRITE, | |
3073 | flags, -1, 0); | |
3074 | #else | |
3075 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; | |
3076 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
3077 | flags, -1, 0); | |
3078 | #endif | |
3079 | } | |
3080 | if (area != vaddr) { | |
3081 | fprintf(stderr, "Could not remap addr: %lx@%lx\n", | |
3082 | length, addr); | |
3083 | exit(1); | |
3084 | } | |
3085 | qemu_madvise(vaddr, length, QEMU_MADV_MERGEABLE); | |
3086 | } | |
3087 | return; | |
3088 | } | |
3089 | } | |
3090 | } | |
3091 | #endif /* !_WIN32 */ | |
3092 | ||
dc828ca1 | 3093 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
5579c7f3 PB |
3094 | With the exception of the softmmu code in this file, this should |
3095 | only be used for local memory (e.g. video ram) that the device owns, | |
3096 | and knows it isn't going to access beyond the end of the block. | |
3097 | ||
3098 | It should not be used for general purpose DMA. | |
3099 | Use cpu_physical_memory_map/cpu_physical_memory_rw instead. | |
3100 | */ | |
c227f099 | 3101 | void *qemu_get_ram_ptr(ram_addr_t addr) |
dc828ca1 | 3102 | { |
94a6b54f PB |
3103 | RAMBlock *block; |
3104 | ||
f471a17e AW |
3105 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
3106 | if (addr - block->offset < block->length) { | |
7d82af38 VP |
3107 | /* Move this entry to to start of the list. */ |
3108 | if (block != QLIST_FIRST(&ram_list.blocks)) { | |
3109 | QLIST_REMOVE(block, next); | |
3110 | QLIST_INSERT_HEAD(&ram_list.blocks, block, next); | |
3111 | } | |
432d268c JN |
3112 | if (xen_mapcache_enabled()) { |
3113 | /* We need to check if the requested address is in the RAM | |
3114 | * because we don't want to map the entire memory in QEMU. | |
712c2b41 | 3115 | * In that case just map until the end of the page. |
432d268c JN |
3116 | */ |
3117 | if (block->offset == 0) { | |
712c2b41 | 3118 | return qemu_map_cache(addr, 0, 0); |
432d268c | 3119 | } else if (block->host == NULL) { |
6506e4f9 | 3120 | block->host = qemu_map_cache(block->offset, block->length, 1); |
432d268c JN |
3121 | } |
3122 | } | |
f471a17e AW |
3123 | return block->host + (addr - block->offset); |
3124 | } | |
94a6b54f | 3125 | } |
f471a17e AW |
3126 | |
3127 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
3128 | abort(); | |
3129 | ||
3130 | return NULL; | |
dc828ca1 PB |
3131 | } |
3132 | ||
b2e0a138 MT |
3133 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
3134 | * Same as qemu_get_ram_ptr but avoid reordering ramblocks. | |
3135 | */ | |
3136 | void *qemu_safe_ram_ptr(ram_addr_t addr) | |
3137 | { | |
3138 | RAMBlock *block; | |
3139 | ||
3140 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
3141 | if (addr - block->offset < block->length) { | |
432d268c JN |
3142 | if (xen_mapcache_enabled()) { |
3143 | /* We need to check if the requested address is in the RAM | |
3144 | * because we don't want to map the entire memory in QEMU. | |
712c2b41 | 3145 | * In that case just map until the end of the page. |
432d268c JN |
3146 | */ |
3147 | if (block->offset == 0) { | |
712c2b41 | 3148 | return qemu_map_cache(addr, 0, 0); |
432d268c | 3149 | } else if (block->host == NULL) { |
6506e4f9 | 3150 | block->host = qemu_map_cache(block->offset, block->length, 1); |
432d268c JN |
3151 | } |
3152 | } | |
b2e0a138 MT |
3153 | return block->host + (addr - block->offset); |
3154 | } | |
3155 | } | |
3156 | ||
3157 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
3158 | abort(); | |
3159 | ||
3160 | return NULL; | |
3161 | } | |
3162 | ||
38bee5dc SS |
3163 | /* Return a host pointer to guest's ram. Similar to qemu_get_ram_ptr |
3164 | * but takes a size argument */ | |
3165 | void *qemu_ram_ptr_length(target_phys_addr_t addr, target_phys_addr_t *size) | |
3166 | { | |
3167 | if (xen_mapcache_enabled()) | |
3168 | return qemu_map_cache(addr, *size, 1); | |
3169 | else { | |
3170 | RAMBlock *block; | |
3171 | ||
3172 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
3173 | if (addr - block->offset < block->length) { | |
3174 | if (addr - block->offset + *size > block->length) | |
3175 | *size = block->length - addr + block->offset; | |
3176 | return block->host + (addr - block->offset); | |
3177 | } | |
3178 | } | |
3179 | ||
3180 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
3181 | abort(); | |
3182 | ||
3183 | *size = 0; | |
3184 | return NULL; | |
3185 | } | |
3186 | } | |
3187 | ||
050a0ddf AP |
3188 | void qemu_put_ram_ptr(void *addr) |
3189 | { | |
3190 | trace_qemu_put_ram_ptr(addr); | |
050a0ddf AP |
3191 | } |
3192 | ||
e890261f | 3193 | int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr) |
5579c7f3 | 3194 | { |
94a6b54f PB |
3195 | RAMBlock *block; |
3196 | uint8_t *host = ptr; | |
3197 | ||
712c2b41 SS |
3198 | if (xen_mapcache_enabled()) { |
3199 | *ram_addr = qemu_ram_addr_from_mapcache(ptr); | |
3200 | return 0; | |
3201 | } | |
3202 | ||
f471a17e | 3203 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
432d268c JN |
3204 | /* This case append when the block is not mapped. */ |
3205 | if (block->host == NULL) { | |
3206 | continue; | |
3207 | } | |
f471a17e | 3208 | if (host - block->host < block->length) { |
e890261f MT |
3209 | *ram_addr = block->offset + (host - block->host); |
3210 | return 0; | |
f471a17e | 3211 | } |
94a6b54f | 3212 | } |
432d268c | 3213 | |
e890261f MT |
3214 | return -1; |
3215 | } | |
f471a17e | 3216 | |
e890261f MT |
3217 | /* Some of the softmmu routines need to translate from a host pointer |
3218 | (typically a TLB entry) back to a ram offset. */ | |
3219 | ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) | |
3220 | { | |
3221 | ram_addr_t ram_addr; | |
f471a17e | 3222 | |
e890261f MT |
3223 | if (qemu_ram_addr_from_host(ptr, &ram_addr)) { |
3224 | fprintf(stderr, "Bad ram pointer %p\n", ptr); | |
3225 | abort(); | |
3226 | } | |
3227 | return ram_addr; | |
5579c7f3 PB |
3228 | } |
3229 | ||
c227f099 | 3230 | static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) |
33417e70 | 3231 | { |
67d3b957 | 3232 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 3233 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
b4f0a316 | 3234 | #endif |
5b450407 | 3235 | #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
3236 | do_unassigned_access(addr, 0, 0, 0, 1); |
3237 | #endif | |
3238 | return 0; | |
3239 | } | |
3240 | ||
c227f099 | 3241 | static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) |
e18231a3 BS |
3242 | { |
3243 | #ifdef DEBUG_UNASSIGNED | |
3244 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
3245 | #endif | |
5b450407 | 3246 | #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
3247 | do_unassigned_access(addr, 0, 0, 0, 2); |
3248 | #endif | |
3249 | return 0; | |
3250 | } | |
3251 | ||
c227f099 | 3252 | static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) |
e18231a3 BS |
3253 | { |
3254 | #ifdef DEBUG_UNASSIGNED | |
3255 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
3256 | #endif | |
5b450407 | 3257 | #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 | 3258 | do_unassigned_access(addr, 0, 0, 0, 4); |
67d3b957 | 3259 | #endif |
33417e70 FB |
3260 | return 0; |
3261 | } | |
3262 | ||
c227f099 | 3263 | static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
33417e70 | 3264 | { |
67d3b957 | 3265 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 3266 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
67d3b957 | 3267 | #endif |
5b450407 | 3268 | #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
3269 | do_unassigned_access(addr, 1, 0, 0, 1); |
3270 | #endif | |
3271 | } | |
3272 | ||
c227f099 | 3273 | static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
e18231a3 BS |
3274 | { |
3275 | #ifdef DEBUG_UNASSIGNED | |
3276 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
3277 | #endif | |
5b450407 | 3278 | #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
3279 | do_unassigned_access(addr, 1, 0, 0, 2); |
3280 | #endif | |
3281 | } | |
3282 | ||
c227f099 | 3283 | static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
e18231a3 BS |
3284 | { |
3285 | #ifdef DEBUG_UNASSIGNED | |
3286 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
3287 | #endif | |
5b450407 | 3288 | #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 | 3289 | do_unassigned_access(addr, 1, 0, 0, 4); |
b4f0a316 | 3290 | #endif |
33417e70 FB |
3291 | } |
3292 | ||
d60efc6b | 3293 | static CPUReadMemoryFunc * const unassigned_mem_read[3] = { |
33417e70 | 3294 | unassigned_mem_readb, |
e18231a3 BS |
3295 | unassigned_mem_readw, |
3296 | unassigned_mem_readl, | |
33417e70 FB |
3297 | }; |
3298 | ||
d60efc6b | 3299 | static CPUWriteMemoryFunc * const unassigned_mem_write[3] = { |
33417e70 | 3300 | unassigned_mem_writeb, |
e18231a3 BS |
3301 | unassigned_mem_writew, |
3302 | unassigned_mem_writel, | |
33417e70 FB |
3303 | }; |
3304 | ||
c227f099 | 3305 | static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 3306 | uint32_t val) |
9fa3e853 | 3307 | { |
3a7d929e | 3308 | int dirty_flags; |
f7c11b53 | 3309 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
3a7d929e | 3310 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
9fa3e853 | 3311 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e | 3312 | tb_invalidate_phys_page_fast(ram_addr, 1); |
f7c11b53 | 3313 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
9fa3e853 | 3314 | #endif |
3a7d929e | 3315 | } |
5579c7f3 | 3316 | stb_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 | 3317 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
f7c11b53 | 3318 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
f23db169 FB |
3319 | /* we remove the notdirty callback only if the code has been |
3320 | flushed */ | |
3321 | if (dirty_flags == 0xff) | |
2e70f6ef | 3322 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
3323 | } |
3324 | ||
c227f099 | 3325 | static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 3326 | uint32_t val) |
9fa3e853 | 3327 | { |
3a7d929e | 3328 | int dirty_flags; |
f7c11b53 | 3329 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
3a7d929e | 3330 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
9fa3e853 | 3331 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e | 3332 | tb_invalidate_phys_page_fast(ram_addr, 2); |
f7c11b53 | 3333 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
9fa3e853 | 3334 | #endif |
3a7d929e | 3335 | } |
5579c7f3 | 3336 | stw_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 | 3337 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
f7c11b53 | 3338 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
f23db169 FB |
3339 | /* we remove the notdirty callback only if the code has been |
3340 | flushed */ | |
3341 | if (dirty_flags == 0xff) | |
2e70f6ef | 3342 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
3343 | } |
3344 | ||
c227f099 | 3345 | static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 3346 | uint32_t val) |
9fa3e853 | 3347 | { |
3a7d929e | 3348 | int dirty_flags; |
f7c11b53 | 3349 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
3a7d929e | 3350 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
9fa3e853 | 3351 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e | 3352 | tb_invalidate_phys_page_fast(ram_addr, 4); |
f7c11b53 | 3353 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
9fa3e853 | 3354 | #endif |
3a7d929e | 3355 | } |
5579c7f3 | 3356 | stl_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 | 3357 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
f7c11b53 | 3358 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
f23db169 FB |
3359 | /* we remove the notdirty callback only if the code has been |
3360 | flushed */ | |
3361 | if (dirty_flags == 0xff) | |
2e70f6ef | 3362 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
3363 | } |
3364 | ||
d60efc6b | 3365 | static CPUReadMemoryFunc * const error_mem_read[3] = { |
9fa3e853 FB |
3366 | NULL, /* never used */ |
3367 | NULL, /* never used */ | |
3368 | NULL, /* never used */ | |
3369 | }; | |
3370 | ||
d60efc6b | 3371 | static CPUWriteMemoryFunc * const notdirty_mem_write[3] = { |
1ccde1cb FB |
3372 | notdirty_mem_writeb, |
3373 | notdirty_mem_writew, | |
3374 | notdirty_mem_writel, | |
3375 | }; | |
3376 | ||
0f459d16 | 3377 | /* Generate a debug exception if a watchpoint has been hit. */ |
b4051334 | 3378 | static void check_watchpoint(int offset, int len_mask, int flags) |
0f459d16 PB |
3379 | { |
3380 | CPUState *env = cpu_single_env; | |
06d55cc1 AL |
3381 | target_ulong pc, cs_base; |
3382 | TranslationBlock *tb; | |
0f459d16 | 3383 | target_ulong vaddr; |
a1d1bb31 | 3384 | CPUWatchpoint *wp; |
06d55cc1 | 3385 | int cpu_flags; |
0f459d16 | 3386 | |
06d55cc1 AL |
3387 | if (env->watchpoint_hit) { |
3388 | /* We re-entered the check after replacing the TB. Now raise | |
3389 | * the debug interrupt so that is will trigger after the | |
3390 | * current instruction. */ | |
3391 | cpu_interrupt(env, CPU_INTERRUPT_DEBUG); | |
3392 | return; | |
3393 | } | |
2e70f6ef | 3394 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
72cf2d4f | 3395 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 AL |
3396 | if ((vaddr == (wp->vaddr & len_mask) || |
3397 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { | |
6e140f28 AL |
3398 | wp->flags |= BP_WATCHPOINT_HIT; |
3399 | if (!env->watchpoint_hit) { | |
3400 | env->watchpoint_hit = wp; | |
3401 | tb = tb_find_pc(env->mem_io_pc); | |
3402 | if (!tb) { | |
3403 | cpu_abort(env, "check_watchpoint: could not find TB for " | |
3404 | "pc=%p", (void *)env->mem_io_pc); | |
3405 | } | |
618ba8e6 | 3406 | cpu_restore_state(tb, env, env->mem_io_pc); |
6e140f28 AL |
3407 | tb_phys_invalidate(tb, -1); |
3408 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { | |
3409 | env->exception_index = EXCP_DEBUG; | |
3410 | } else { | |
3411 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); | |
3412 | tb_gen_code(env, pc, cs_base, cpu_flags, 1); | |
3413 | } | |
3414 | cpu_resume_from_signal(env, NULL); | |
06d55cc1 | 3415 | } |
6e140f28 AL |
3416 | } else { |
3417 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
0f459d16 PB |
3418 | } |
3419 | } | |
3420 | } | |
3421 | ||
6658ffb8 PB |
3422 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
3423 | so these check for a hit then pass through to the normal out-of-line | |
3424 | phys routines. */ | |
c227f099 | 3425 | static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 3426 | { |
b4051334 | 3427 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ); |
6658ffb8 PB |
3428 | return ldub_phys(addr); |
3429 | } | |
3430 | ||
c227f099 | 3431 | static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 3432 | { |
b4051334 | 3433 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ); |
6658ffb8 PB |
3434 | return lduw_phys(addr); |
3435 | } | |
3436 | ||
c227f099 | 3437 | static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 3438 | { |
b4051334 | 3439 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ); |
6658ffb8 PB |
3440 | return ldl_phys(addr); |
3441 | } | |
3442 | ||
c227f099 | 3443 | static void watch_mem_writeb(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
3444 | uint32_t val) |
3445 | { | |
b4051334 | 3446 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE); |
6658ffb8 PB |
3447 | stb_phys(addr, val); |
3448 | } | |
3449 | ||
c227f099 | 3450 | static void watch_mem_writew(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
3451 | uint32_t val) |
3452 | { | |
b4051334 | 3453 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE); |
6658ffb8 PB |
3454 | stw_phys(addr, val); |
3455 | } | |
3456 | ||
c227f099 | 3457 | static void watch_mem_writel(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
3458 | uint32_t val) |
3459 | { | |
b4051334 | 3460 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE); |
6658ffb8 PB |
3461 | stl_phys(addr, val); |
3462 | } | |
3463 | ||
d60efc6b | 3464 | static CPUReadMemoryFunc * const watch_mem_read[3] = { |
6658ffb8 PB |
3465 | watch_mem_readb, |
3466 | watch_mem_readw, | |
3467 | watch_mem_readl, | |
3468 | }; | |
3469 | ||
d60efc6b | 3470 | static CPUWriteMemoryFunc * const watch_mem_write[3] = { |
6658ffb8 PB |
3471 | watch_mem_writeb, |
3472 | watch_mem_writew, | |
3473 | watch_mem_writel, | |
3474 | }; | |
6658ffb8 | 3475 | |
f6405247 RH |
3476 | static inline uint32_t subpage_readlen (subpage_t *mmio, |
3477 | target_phys_addr_t addr, | |
3478 | unsigned int len) | |
db7b5426 | 3479 | { |
f6405247 | 3480 | unsigned int idx = SUBPAGE_IDX(addr); |
db7b5426 BS |
3481 | #if defined(DEBUG_SUBPAGE) |
3482 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__, | |
3483 | mmio, len, addr, idx); | |
3484 | #endif | |
db7b5426 | 3485 | |
f6405247 RH |
3486 | addr += mmio->region_offset[idx]; |
3487 | idx = mmio->sub_io_index[idx]; | |
3488 | return io_mem_read[idx][len](io_mem_opaque[idx], addr); | |
db7b5426 BS |
3489 | } |
3490 | ||
c227f099 | 3491 | static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr, |
f6405247 | 3492 | uint32_t value, unsigned int len) |
db7b5426 | 3493 | { |
f6405247 | 3494 | unsigned int idx = SUBPAGE_IDX(addr); |
db7b5426 | 3495 | #if defined(DEBUG_SUBPAGE) |
f6405247 RH |
3496 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", |
3497 | __func__, mmio, len, addr, idx, value); | |
db7b5426 | 3498 | #endif |
f6405247 RH |
3499 | |
3500 | addr += mmio->region_offset[idx]; | |
3501 | idx = mmio->sub_io_index[idx]; | |
3502 | io_mem_write[idx][len](io_mem_opaque[idx], addr, value); | |
db7b5426 BS |
3503 | } |
3504 | ||
c227f099 | 3505 | static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) |
db7b5426 | 3506 | { |
db7b5426 BS |
3507 | return subpage_readlen(opaque, addr, 0); |
3508 | } | |
3509 | ||
c227f099 | 3510 | static void subpage_writeb (void *opaque, target_phys_addr_t addr, |
db7b5426 BS |
3511 | uint32_t value) |
3512 | { | |
db7b5426 BS |
3513 | subpage_writelen(opaque, addr, value, 0); |
3514 | } | |
3515 | ||
c227f099 | 3516 | static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr) |
db7b5426 | 3517 | { |
db7b5426 BS |
3518 | return subpage_readlen(opaque, addr, 1); |
3519 | } | |
3520 | ||
c227f099 | 3521 | static void subpage_writew (void *opaque, target_phys_addr_t addr, |
db7b5426 BS |
3522 | uint32_t value) |
3523 | { | |
db7b5426 BS |
3524 | subpage_writelen(opaque, addr, value, 1); |
3525 | } | |
3526 | ||
c227f099 | 3527 | static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr) |
db7b5426 | 3528 | { |
db7b5426 BS |
3529 | return subpage_readlen(opaque, addr, 2); |
3530 | } | |
3531 | ||
f6405247 RH |
3532 | static void subpage_writel (void *opaque, target_phys_addr_t addr, |
3533 | uint32_t value) | |
db7b5426 | 3534 | { |
db7b5426 BS |
3535 | subpage_writelen(opaque, addr, value, 2); |
3536 | } | |
3537 | ||
d60efc6b | 3538 | static CPUReadMemoryFunc * const subpage_read[] = { |
db7b5426 BS |
3539 | &subpage_readb, |
3540 | &subpage_readw, | |
3541 | &subpage_readl, | |
3542 | }; | |
3543 | ||
d60efc6b | 3544 | static CPUWriteMemoryFunc * const subpage_write[] = { |
db7b5426 BS |
3545 | &subpage_writeb, |
3546 | &subpage_writew, | |
3547 | &subpage_writel, | |
3548 | }; | |
3549 | ||
c227f099 AL |
3550 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
3551 | ram_addr_t memory, ram_addr_t region_offset) | |
db7b5426 BS |
3552 | { |
3553 | int idx, eidx; | |
3554 | ||
3555 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
3556 | return -1; | |
3557 | idx = SUBPAGE_IDX(start); | |
3558 | eidx = SUBPAGE_IDX(end); | |
3559 | #if defined(DEBUG_SUBPAGE) | |
0bf9e31a | 3560 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__, |
db7b5426 BS |
3561 | mmio, start, end, idx, eidx, memory); |
3562 | #endif | |
95c318f5 GN |
3563 | if ((memory & ~TARGET_PAGE_MASK) == IO_MEM_RAM) |
3564 | memory = IO_MEM_UNASSIGNED; | |
f6405247 | 3565 | memory = (memory >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
db7b5426 | 3566 | for (; idx <= eidx; idx++) { |
f6405247 RH |
3567 | mmio->sub_io_index[idx] = memory; |
3568 | mmio->region_offset[idx] = region_offset; | |
db7b5426 BS |
3569 | } |
3570 | ||
3571 | return 0; | |
3572 | } | |
3573 | ||
f6405247 RH |
3574 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
3575 | ram_addr_t orig_memory, | |
3576 | ram_addr_t region_offset) | |
db7b5426 | 3577 | { |
c227f099 | 3578 | subpage_t *mmio; |
db7b5426 BS |
3579 | int subpage_memory; |
3580 | ||
c227f099 | 3581 | mmio = qemu_mallocz(sizeof(subpage_t)); |
1eec614b AL |
3582 | |
3583 | mmio->base = base; | |
2507c12a AG |
3584 | subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio, |
3585 | DEVICE_NATIVE_ENDIAN); | |
db7b5426 | 3586 | #if defined(DEBUG_SUBPAGE) |
1eec614b AL |
3587 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, |
3588 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); | |
db7b5426 | 3589 | #endif |
1eec614b | 3590 | *phys = subpage_memory | IO_MEM_SUBPAGE; |
f6405247 | 3591 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, orig_memory, region_offset); |
db7b5426 BS |
3592 | |
3593 | return mmio; | |
3594 | } | |
3595 | ||
88715657 AL |
3596 | static int get_free_io_mem_idx(void) |
3597 | { | |
3598 | int i; | |
3599 | ||
3600 | for (i = 0; i<IO_MEM_NB_ENTRIES; i++) | |
3601 | if (!io_mem_used[i]) { | |
3602 | io_mem_used[i] = 1; | |
3603 | return i; | |
3604 | } | |
c6703b47 | 3605 | fprintf(stderr, "RAN out out io_mem_idx, max %d !\n", IO_MEM_NB_ENTRIES); |
88715657 AL |
3606 | return -1; |
3607 | } | |
3608 | ||
dd310534 AG |
3609 | /* |
3610 | * Usually, devices operate in little endian mode. There are devices out | |
3611 | * there that operate in big endian too. Each device gets byte swapped | |
3612 | * mmio if plugged onto a CPU that does the other endianness. | |
3613 | * | |
3614 | * CPU Device swap? | |
3615 | * | |
3616 | * little little no | |
3617 | * little big yes | |
3618 | * big little yes | |
3619 | * big big no | |
3620 | */ | |
3621 | ||
3622 | typedef struct SwapEndianContainer { | |
3623 | CPUReadMemoryFunc *read[3]; | |
3624 | CPUWriteMemoryFunc *write[3]; | |
3625 | void *opaque; | |
3626 | } SwapEndianContainer; | |
3627 | ||
3628 | static uint32_t swapendian_mem_readb (void *opaque, target_phys_addr_t addr) | |
3629 | { | |
3630 | uint32_t val; | |
3631 | SwapEndianContainer *c = opaque; | |
3632 | val = c->read[0](c->opaque, addr); | |
3633 | return val; | |
3634 | } | |
3635 | ||
3636 | static uint32_t swapendian_mem_readw(void *opaque, target_phys_addr_t addr) | |
3637 | { | |
3638 | uint32_t val; | |
3639 | SwapEndianContainer *c = opaque; | |
3640 | val = bswap16(c->read[1](c->opaque, addr)); | |
3641 | return val; | |
3642 | } | |
3643 | ||
3644 | static uint32_t swapendian_mem_readl(void *opaque, target_phys_addr_t addr) | |
3645 | { | |
3646 | uint32_t val; | |
3647 | SwapEndianContainer *c = opaque; | |
3648 | val = bswap32(c->read[2](c->opaque, addr)); | |
3649 | return val; | |
3650 | } | |
3651 | ||
3652 | static CPUReadMemoryFunc * const swapendian_readfn[3]={ | |
3653 | swapendian_mem_readb, | |
3654 | swapendian_mem_readw, | |
3655 | swapendian_mem_readl | |
3656 | }; | |
3657 | ||
3658 | static void swapendian_mem_writeb(void *opaque, target_phys_addr_t addr, | |
3659 | uint32_t val) | |
3660 | { | |
3661 | SwapEndianContainer *c = opaque; | |
3662 | c->write[0](c->opaque, addr, val); | |
3663 | } | |
3664 | ||
3665 | static void swapendian_mem_writew(void *opaque, target_phys_addr_t addr, | |
3666 | uint32_t val) | |
3667 | { | |
3668 | SwapEndianContainer *c = opaque; | |
3669 | c->write[1](c->opaque, addr, bswap16(val)); | |
3670 | } | |
3671 | ||
3672 | static void swapendian_mem_writel(void *opaque, target_phys_addr_t addr, | |
3673 | uint32_t val) | |
3674 | { | |
3675 | SwapEndianContainer *c = opaque; | |
3676 | c->write[2](c->opaque, addr, bswap32(val)); | |
3677 | } | |
3678 | ||
3679 | static CPUWriteMemoryFunc * const swapendian_writefn[3]={ | |
3680 | swapendian_mem_writeb, | |
3681 | swapendian_mem_writew, | |
3682 | swapendian_mem_writel | |
3683 | }; | |
3684 | ||
3685 | static void swapendian_init(int io_index) | |
3686 | { | |
3687 | SwapEndianContainer *c = qemu_malloc(sizeof(SwapEndianContainer)); | |
3688 | int i; | |
3689 | ||
3690 | /* Swap mmio for big endian targets */ | |
3691 | c->opaque = io_mem_opaque[io_index]; | |
3692 | for (i = 0; i < 3; i++) { | |
3693 | c->read[i] = io_mem_read[io_index][i]; | |
3694 | c->write[i] = io_mem_write[io_index][i]; | |
3695 | ||
3696 | io_mem_read[io_index][i] = swapendian_readfn[i]; | |
3697 | io_mem_write[io_index][i] = swapendian_writefn[i]; | |
3698 | } | |
3699 | io_mem_opaque[io_index] = c; | |
3700 | } | |
3701 | ||
3702 | static void swapendian_del(int io_index) | |
3703 | { | |
3704 | if (io_mem_read[io_index][0] == swapendian_readfn[0]) { | |
3705 | qemu_free(io_mem_opaque[io_index]); | |
3706 | } | |
3707 | } | |
3708 | ||
33417e70 FB |
3709 | /* mem_read and mem_write are arrays of functions containing the |
3710 | function to access byte (index 0), word (index 1) and dword (index | |
0b4e6e3e | 3711 | 2). Functions can be omitted with a NULL function pointer. |
3ee89922 | 3712 | If io_index is non zero, the corresponding io zone is |
4254fab8 BS |
3713 | modified. If it is zero, a new io zone is allocated. The return |
3714 | value can be used with cpu_register_physical_memory(). (-1) is | |
3715 | returned if error. */ | |
1eed09cb | 3716 | static int cpu_register_io_memory_fixed(int io_index, |
d60efc6b BS |
3717 | CPUReadMemoryFunc * const *mem_read, |
3718 | CPUWriteMemoryFunc * const *mem_write, | |
dd310534 | 3719 | void *opaque, enum device_endian endian) |
33417e70 | 3720 | { |
3cab721d RH |
3721 | int i; |
3722 | ||
33417e70 | 3723 | if (io_index <= 0) { |
88715657 AL |
3724 | io_index = get_free_io_mem_idx(); |
3725 | if (io_index == -1) | |
3726 | return io_index; | |
33417e70 | 3727 | } else { |
1eed09cb | 3728 | io_index >>= IO_MEM_SHIFT; |
33417e70 FB |
3729 | if (io_index >= IO_MEM_NB_ENTRIES) |
3730 | return -1; | |
3731 | } | |
b5ff1b31 | 3732 | |
3cab721d RH |
3733 | for (i = 0; i < 3; ++i) { |
3734 | io_mem_read[io_index][i] | |
3735 | = (mem_read[i] ? mem_read[i] : unassigned_mem_read[i]); | |
3736 | } | |
3737 | for (i = 0; i < 3; ++i) { | |
3738 | io_mem_write[io_index][i] | |
3739 | = (mem_write[i] ? mem_write[i] : unassigned_mem_write[i]); | |
3740 | } | |
a4193c8a | 3741 | io_mem_opaque[io_index] = opaque; |
f6405247 | 3742 | |
dd310534 AG |
3743 | switch (endian) { |
3744 | case DEVICE_BIG_ENDIAN: | |
3745 | #ifndef TARGET_WORDS_BIGENDIAN | |
3746 | swapendian_init(io_index); | |
3747 | #endif | |
3748 | break; | |
3749 | case DEVICE_LITTLE_ENDIAN: | |
3750 | #ifdef TARGET_WORDS_BIGENDIAN | |
3751 | swapendian_init(io_index); | |
3752 | #endif | |
3753 | break; | |
3754 | case DEVICE_NATIVE_ENDIAN: | |
3755 | default: | |
3756 | break; | |
3757 | } | |
3758 | ||
f6405247 | 3759 | return (io_index << IO_MEM_SHIFT); |
33417e70 | 3760 | } |
61382a50 | 3761 | |
d60efc6b BS |
3762 | int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
3763 | CPUWriteMemoryFunc * const *mem_write, | |
dd310534 | 3764 | void *opaque, enum device_endian endian) |
1eed09cb | 3765 | { |
2507c12a | 3766 | return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque, endian); |
1eed09cb AK |
3767 | } |
3768 | ||
88715657 AL |
3769 | void cpu_unregister_io_memory(int io_table_address) |
3770 | { | |
3771 | int i; | |
3772 | int io_index = io_table_address >> IO_MEM_SHIFT; | |
3773 | ||
dd310534 AG |
3774 | swapendian_del(io_index); |
3775 | ||
88715657 AL |
3776 | for (i=0;i < 3; i++) { |
3777 | io_mem_read[io_index][i] = unassigned_mem_read[i]; | |
3778 | io_mem_write[io_index][i] = unassigned_mem_write[i]; | |
3779 | } | |
3780 | io_mem_opaque[io_index] = NULL; | |
3781 | io_mem_used[io_index] = 0; | |
3782 | } | |
3783 | ||
e9179ce1 AK |
3784 | static void io_mem_init(void) |
3785 | { | |
3786 | int i; | |
3787 | ||
2507c12a AG |
3788 | cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, |
3789 | unassigned_mem_write, NULL, | |
3790 | DEVICE_NATIVE_ENDIAN); | |
3791 | cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, | |
3792 | unassigned_mem_write, NULL, | |
3793 | DEVICE_NATIVE_ENDIAN); | |
3794 | cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, | |
3795 | notdirty_mem_write, NULL, | |
3796 | DEVICE_NATIVE_ENDIAN); | |
e9179ce1 AK |
3797 | for (i=0; i<5; i++) |
3798 | io_mem_used[i] = 1; | |
3799 | ||
3800 | io_mem_watch = cpu_register_io_memory(watch_mem_read, | |
2507c12a AG |
3801 | watch_mem_write, NULL, |
3802 | DEVICE_NATIVE_ENDIAN); | |
e9179ce1 AK |
3803 | } |
3804 | ||
e2eef170 PB |
3805 | #endif /* !defined(CONFIG_USER_ONLY) */ |
3806 | ||
13eb76e0 FB |
3807 | /* physical memory access (slow version, mainly for debug) */ |
3808 | #if defined(CONFIG_USER_ONLY) | |
a68fe89c PB |
3809 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
3810 | uint8_t *buf, int len, int is_write) | |
13eb76e0 FB |
3811 | { |
3812 | int l, flags; | |
3813 | target_ulong page; | |
53a5960a | 3814 | void * p; |
13eb76e0 FB |
3815 | |
3816 | while (len > 0) { | |
3817 | page = addr & TARGET_PAGE_MASK; | |
3818 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3819 | if (l > len) | |
3820 | l = len; | |
3821 | flags = page_get_flags(page); | |
3822 | if (!(flags & PAGE_VALID)) | |
a68fe89c | 3823 | return -1; |
13eb76e0 FB |
3824 | if (is_write) { |
3825 | if (!(flags & PAGE_WRITE)) | |
a68fe89c | 3826 | return -1; |
579a97f7 | 3827 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3828 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
a68fe89c | 3829 | return -1; |
72fb7daa AJ |
3830 | memcpy(p, buf, l); |
3831 | unlock_user(p, addr, l); | |
13eb76e0 FB |
3832 | } else { |
3833 | if (!(flags & PAGE_READ)) | |
a68fe89c | 3834 | return -1; |
579a97f7 | 3835 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3836 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
a68fe89c | 3837 | return -1; |
72fb7daa | 3838 | memcpy(buf, p, l); |
5b257578 | 3839 | unlock_user(p, addr, 0); |
13eb76e0 FB |
3840 | } |
3841 | len -= l; | |
3842 | buf += l; | |
3843 | addr += l; | |
3844 | } | |
a68fe89c | 3845 | return 0; |
13eb76e0 | 3846 | } |
8df1cd07 | 3847 | |
13eb76e0 | 3848 | #else |
c227f099 | 3849 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
13eb76e0 FB |
3850 | int len, int is_write) |
3851 | { | |
3852 | int l, io_index; | |
3853 | uint8_t *ptr; | |
3854 | uint32_t val; | |
c227f099 | 3855 | target_phys_addr_t page; |
2e12669a | 3856 | unsigned long pd; |
92e873b9 | 3857 | PhysPageDesc *p; |
3b46e624 | 3858 | |
13eb76e0 FB |
3859 | while (len > 0) { |
3860 | page = addr & TARGET_PAGE_MASK; | |
3861 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3862 | if (l > len) | |
3863 | l = len; | |
92e873b9 | 3864 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
13eb76e0 FB |
3865 | if (!p) { |
3866 | pd = IO_MEM_UNASSIGNED; | |
3867 | } else { | |
3868 | pd = p->phys_offset; | |
3869 | } | |
3b46e624 | 3870 | |
13eb76e0 | 3871 | if (is_write) { |
3a7d929e | 3872 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
c227f099 | 3873 | target_phys_addr_t addr1 = addr; |
13eb76e0 | 3874 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 | 3875 | if (p) |
6c2934db | 3876 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
6a00d601 FB |
3877 | /* XXX: could force cpu_single_env to NULL to avoid |
3878 | potential bugs */ | |
6c2934db | 3879 | if (l >= 4 && ((addr1 & 3) == 0)) { |
1c213d19 | 3880 | /* 32 bit write access */ |
c27004ec | 3881 | val = ldl_p(buf); |
6c2934db | 3882 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val); |
13eb76e0 | 3883 | l = 4; |
6c2934db | 3884 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
1c213d19 | 3885 | /* 16 bit write access */ |
c27004ec | 3886 | val = lduw_p(buf); |
6c2934db | 3887 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val); |
13eb76e0 FB |
3888 | l = 2; |
3889 | } else { | |
1c213d19 | 3890 | /* 8 bit write access */ |
c27004ec | 3891 | val = ldub_p(buf); |
6c2934db | 3892 | io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val); |
13eb76e0 FB |
3893 | l = 1; |
3894 | } | |
3895 | } else { | |
b448f2f3 FB |
3896 | unsigned long addr1; |
3897 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
13eb76e0 | 3898 | /* RAM case */ |
5579c7f3 | 3899 | ptr = qemu_get_ram_ptr(addr1); |
13eb76e0 | 3900 | memcpy(ptr, buf, l); |
3a7d929e FB |
3901 | if (!cpu_physical_memory_is_dirty(addr1)) { |
3902 | /* invalidate code */ | |
3903 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
3904 | /* set dirty bit */ | |
f7c11b53 YT |
3905 | cpu_physical_memory_set_dirty_flags( |
3906 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
3a7d929e | 3907 | } |
050a0ddf | 3908 | qemu_put_ram_ptr(ptr); |
13eb76e0 FB |
3909 | } |
3910 | } else { | |
5fafdf24 | 3911 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 3912 | !(pd & IO_MEM_ROMD)) { |
c227f099 | 3913 | target_phys_addr_t addr1 = addr; |
13eb76e0 FB |
3914 | /* I/O case */ |
3915 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 | 3916 | if (p) |
6c2934db AJ |
3917 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
3918 | if (l >= 4 && ((addr1 & 3) == 0)) { | |
13eb76e0 | 3919 | /* 32 bit read access */ |
6c2934db | 3920 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1); |
c27004ec | 3921 | stl_p(buf, val); |
13eb76e0 | 3922 | l = 4; |
6c2934db | 3923 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
13eb76e0 | 3924 | /* 16 bit read access */ |
6c2934db | 3925 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1); |
c27004ec | 3926 | stw_p(buf, val); |
13eb76e0 FB |
3927 | l = 2; |
3928 | } else { | |
1c213d19 | 3929 | /* 8 bit read access */ |
6c2934db | 3930 | val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1); |
c27004ec | 3931 | stb_p(buf, val); |
13eb76e0 FB |
3932 | l = 1; |
3933 | } | |
3934 | } else { | |
3935 | /* RAM case */ | |
050a0ddf AP |
3936 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK); |
3937 | memcpy(buf, ptr + (addr & ~TARGET_PAGE_MASK), l); | |
3938 | qemu_put_ram_ptr(ptr); | |
13eb76e0 FB |
3939 | } |
3940 | } | |
3941 | len -= l; | |
3942 | buf += l; | |
3943 | addr += l; | |
3944 | } | |
3945 | } | |
8df1cd07 | 3946 | |
d0ecd2aa | 3947 | /* used for ROM loading : can write in RAM and ROM */ |
c227f099 | 3948 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, |
d0ecd2aa FB |
3949 | const uint8_t *buf, int len) |
3950 | { | |
3951 | int l; | |
3952 | uint8_t *ptr; | |
c227f099 | 3953 | target_phys_addr_t page; |
d0ecd2aa FB |
3954 | unsigned long pd; |
3955 | PhysPageDesc *p; | |
3b46e624 | 3956 | |
d0ecd2aa FB |
3957 | while (len > 0) { |
3958 | page = addr & TARGET_PAGE_MASK; | |
3959 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3960 | if (l > len) | |
3961 | l = len; | |
3962 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3963 | if (!p) { | |
3964 | pd = IO_MEM_UNASSIGNED; | |
3965 | } else { | |
3966 | pd = p->phys_offset; | |
3967 | } | |
3b46e624 | 3968 | |
d0ecd2aa | 3969 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM && |
2a4188a3 FB |
3970 | (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM && |
3971 | !(pd & IO_MEM_ROMD)) { | |
d0ecd2aa FB |
3972 | /* do nothing */ |
3973 | } else { | |
3974 | unsigned long addr1; | |
3975 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3976 | /* ROM/RAM case */ | |
5579c7f3 | 3977 | ptr = qemu_get_ram_ptr(addr1); |
d0ecd2aa | 3978 | memcpy(ptr, buf, l); |
050a0ddf | 3979 | qemu_put_ram_ptr(ptr); |
d0ecd2aa FB |
3980 | } |
3981 | len -= l; | |
3982 | buf += l; | |
3983 | addr += l; | |
3984 | } | |
3985 | } | |
3986 | ||
6d16c2f8 AL |
3987 | typedef struct { |
3988 | void *buffer; | |
c227f099 AL |
3989 | target_phys_addr_t addr; |
3990 | target_phys_addr_t len; | |
6d16c2f8 AL |
3991 | } BounceBuffer; |
3992 | ||
3993 | static BounceBuffer bounce; | |
3994 | ||
ba223c29 AL |
3995 | typedef struct MapClient { |
3996 | void *opaque; | |
3997 | void (*callback)(void *opaque); | |
72cf2d4f | 3998 | QLIST_ENTRY(MapClient) link; |
ba223c29 AL |
3999 | } MapClient; |
4000 | ||
72cf2d4f BS |
4001 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
4002 | = QLIST_HEAD_INITIALIZER(map_client_list); | |
ba223c29 AL |
4003 | |
4004 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) | |
4005 | { | |
4006 | MapClient *client = qemu_malloc(sizeof(*client)); | |
4007 | ||
4008 | client->opaque = opaque; | |
4009 | client->callback = callback; | |
72cf2d4f | 4010 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
ba223c29 AL |
4011 | return client; |
4012 | } | |
4013 | ||
4014 | void cpu_unregister_map_client(void *_client) | |
4015 | { | |
4016 | MapClient *client = (MapClient *)_client; | |
4017 | ||
72cf2d4f | 4018 | QLIST_REMOVE(client, link); |
34d5e948 | 4019 | qemu_free(client); |
ba223c29 AL |
4020 | } |
4021 | ||
4022 | static void cpu_notify_map_clients(void) | |
4023 | { | |
4024 | MapClient *client; | |
4025 | ||
72cf2d4f BS |
4026 | while (!QLIST_EMPTY(&map_client_list)) { |
4027 | client = QLIST_FIRST(&map_client_list); | |
ba223c29 | 4028 | client->callback(client->opaque); |
34d5e948 | 4029 | cpu_unregister_map_client(client); |
ba223c29 AL |
4030 | } |
4031 | } | |
4032 | ||
6d16c2f8 AL |
4033 | /* Map a physical memory region into a host virtual address. |
4034 | * May map a subset of the requested range, given by and returned in *plen. | |
4035 | * May return NULL if resources needed to perform the mapping are exhausted. | |
4036 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
4037 | * Use cpu_register_map_client() to know when retrying the map operation is |
4038 | * likely to succeed. | |
6d16c2f8 | 4039 | */ |
c227f099 AL |
4040 | void *cpu_physical_memory_map(target_phys_addr_t addr, |
4041 | target_phys_addr_t *plen, | |
6d16c2f8 AL |
4042 | int is_write) |
4043 | { | |
c227f099 | 4044 | target_phys_addr_t len = *plen; |
38bee5dc | 4045 | target_phys_addr_t todo = 0; |
6d16c2f8 | 4046 | int l; |
c227f099 | 4047 | target_phys_addr_t page; |
6d16c2f8 AL |
4048 | unsigned long pd; |
4049 | PhysPageDesc *p; | |
38bee5dc | 4050 | target_phys_addr_t addr1 = addr; |
6d16c2f8 AL |
4051 | |
4052 | while (len > 0) { | |
4053 | page = addr & TARGET_PAGE_MASK; | |
4054 | l = (page + TARGET_PAGE_SIZE) - addr; | |
4055 | if (l > len) | |
4056 | l = len; | |
4057 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
4058 | if (!p) { | |
4059 | pd = IO_MEM_UNASSIGNED; | |
4060 | } else { | |
4061 | pd = p->phys_offset; | |
4062 | } | |
4063 | ||
4064 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
38bee5dc | 4065 | if (todo || bounce.buffer) { |
6d16c2f8 AL |
4066 | break; |
4067 | } | |
4068 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE); | |
4069 | bounce.addr = addr; | |
4070 | bounce.len = l; | |
4071 | if (!is_write) { | |
54f7b4a3 | 4072 | cpu_physical_memory_read(addr, bounce.buffer, l); |
6d16c2f8 | 4073 | } |
38bee5dc SS |
4074 | |
4075 | *plen = l; | |
4076 | return bounce.buffer; | |
6d16c2f8 AL |
4077 | } |
4078 | ||
4079 | len -= l; | |
4080 | addr += l; | |
38bee5dc | 4081 | todo += l; |
6d16c2f8 | 4082 | } |
38bee5dc SS |
4083 | *plen = todo; |
4084 | return qemu_ram_ptr_length(addr1, plen); | |
6d16c2f8 AL |
4085 | } |
4086 | ||
4087 | /* Unmaps a memory region previously mapped by cpu_physical_memory_map(). | |
4088 | * Will also mark the memory as dirty if is_write == 1. access_len gives | |
4089 | * the amount of memory that was actually read or written by the caller. | |
4090 | */ | |
c227f099 AL |
4091 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, |
4092 | int is_write, target_phys_addr_t access_len) | |
6d16c2f8 AL |
4093 | { |
4094 | if (buffer != bounce.buffer) { | |
4095 | if (is_write) { | |
e890261f | 4096 | ram_addr_t addr1 = qemu_ram_addr_from_host_nofail(buffer); |
6d16c2f8 AL |
4097 | while (access_len) { |
4098 | unsigned l; | |
4099 | l = TARGET_PAGE_SIZE; | |
4100 | if (l > access_len) | |
4101 | l = access_len; | |
4102 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
4103 | /* invalidate code */ | |
4104 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
4105 | /* set dirty bit */ | |
f7c11b53 YT |
4106 | cpu_physical_memory_set_dirty_flags( |
4107 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
6d16c2f8 AL |
4108 | } |
4109 | addr1 += l; | |
4110 | access_len -= l; | |
4111 | } | |
4112 | } | |
050a0ddf | 4113 | if (xen_mapcache_enabled()) { |
712c2b41 | 4114 | qemu_invalidate_entry(buffer); |
050a0ddf | 4115 | } |
6d16c2f8 AL |
4116 | return; |
4117 | } | |
4118 | if (is_write) { | |
4119 | cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len); | |
4120 | } | |
f8a83245 | 4121 | qemu_vfree(bounce.buffer); |
6d16c2f8 | 4122 | bounce.buffer = NULL; |
ba223c29 | 4123 | cpu_notify_map_clients(); |
6d16c2f8 | 4124 | } |
d0ecd2aa | 4125 | |
8df1cd07 | 4126 | /* warning: addr must be aligned */ |
c227f099 | 4127 | uint32_t ldl_phys(target_phys_addr_t addr) |
8df1cd07 FB |
4128 | { |
4129 | int io_index; | |
4130 | uint8_t *ptr; | |
4131 | uint32_t val; | |
4132 | unsigned long pd; | |
4133 | PhysPageDesc *p; | |
4134 | ||
4135 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4136 | if (!p) { | |
4137 | pd = IO_MEM_UNASSIGNED; | |
4138 | } else { | |
4139 | pd = p->phys_offset; | |
4140 | } | |
3b46e624 | 4141 | |
5fafdf24 | 4142 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 4143 | !(pd & IO_MEM_ROMD)) { |
8df1cd07 FB |
4144 | /* I/O case */ |
4145 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
4146 | if (p) |
4147 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
4148 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
4149 | } else { | |
4150 | /* RAM case */ | |
5579c7f3 | 4151 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
8df1cd07 FB |
4152 | (addr & ~TARGET_PAGE_MASK); |
4153 | val = ldl_p(ptr); | |
4154 | } | |
4155 | return val; | |
4156 | } | |
4157 | ||
84b7b8e7 | 4158 | /* warning: addr must be aligned */ |
c227f099 | 4159 | uint64_t ldq_phys(target_phys_addr_t addr) |
84b7b8e7 FB |
4160 | { |
4161 | int io_index; | |
4162 | uint8_t *ptr; | |
4163 | uint64_t val; | |
4164 | unsigned long pd; | |
4165 | PhysPageDesc *p; | |
4166 | ||
4167 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4168 | if (!p) { | |
4169 | pd = IO_MEM_UNASSIGNED; | |
4170 | } else { | |
4171 | pd = p->phys_offset; | |
4172 | } | |
3b46e624 | 4173 | |
2a4188a3 FB |
4174 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
4175 | !(pd & IO_MEM_ROMD)) { | |
84b7b8e7 FB |
4176 | /* I/O case */ |
4177 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
4178 | if (p) |
4179 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
84b7b8e7 FB |
4180 | #ifdef TARGET_WORDS_BIGENDIAN |
4181 | val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32; | |
4182 | val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4); | |
4183 | #else | |
4184 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); | |
4185 | val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32; | |
4186 | #endif | |
4187 | } else { | |
4188 | /* RAM case */ | |
5579c7f3 | 4189 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
84b7b8e7 FB |
4190 | (addr & ~TARGET_PAGE_MASK); |
4191 | val = ldq_p(ptr); | |
4192 | } | |
4193 | return val; | |
4194 | } | |
4195 | ||
aab33094 | 4196 | /* XXX: optimize */ |
c227f099 | 4197 | uint32_t ldub_phys(target_phys_addr_t addr) |
aab33094 FB |
4198 | { |
4199 | uint8_t val; | |
4200 | cpu_physical_memory_read(addr, &val, 1); | |
4201 | return val; | |
4202 | } | |
4203 | ||
733f0b02 | 4204 | /* warning: addr must be aligned */ |
c227f099 | 4205 | uint32_t lduw_phys(target_phys_addr_t addr) |
aab33094 | 4206 | { |
733f0b02 MT |
4207 | int io_index; |
4208 | uint8_t *ptr; | |
4209 | uint64_t val; | |
4210 | unsigned long pd; | |
4211 | PhysPageDesc *p; | |
4212 | ||
4213 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4214 | if (!p) { | |
4215 | pd = IO_MEM_UNASSIGNED; | |
4216 | } else { | |
4217 | pd = p->phys_offset; | |
4218 | } | |
4219 | ||
4220 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && | |
4221 | !(pd & IO_MEM_ROMD)) { | |
4222 | /* I/O case */ | |
4223 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
4224 | if (p) | |
4225 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
4226 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr); | |
4227 | } else { | |
4228 | /* RAM case */ | |
4229 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + | |
4230 | (addr & ~TARGET_PAGE_MASK); | |
4231 | val = lduw_p(ptr); | |
4232 | } | |
4233 | return val; | |
aab33094 FB |
4234 | } |
4235 | ||
8df1cd07 FB |
4236 | /* warning: addr must be aligned. The ram page is not masked as dirty |
4237 | and the code inside is not invalidated. It is useful if the dirty | |
4238 | bits are used to track modified PTEs */ | |
c227f099 | 4239 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) |
8df1cd07 FB |
4240 | { |
4241 | int io_index; | |
4242 | uint8_t *ptr; | |
4243 | unsigned long pd; | |
4244 | PhysPageDesc *p; | |
4245 | ||
4246 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4247 | if (!p) { | |
4248 | pd = IO_MEM_UNASSIGNED; | |
4249 | } else { | |
4250 | pd = p->phys_offset; | |
4251 | } | |
3b46e624 | 4252 | |
3a7d929e | 4253 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 | 4254 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 PB |
4255 | if (p) |
4256 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
4257 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
4258 | } else { | |
74576198 | 4259 | unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
5579c7f3 | 4260 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 4261 | stl_p(ptr, val); |
74576198 AL |
4262 | |
4263 | if (unlikely(in_migration)) { | |
4264 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
4265 | /* invalidate code */ | |
4266 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
4267 | /* set dirty bit */ | |
f7c11b53 YT |
4268 | cpu_physical_memory_set_dirty_flags( |
4269 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
74576198 AL |
4270 | } |
4271 | } | |
8df1cd07 FB |
4272 | } |
4273 | } | |
4274 | ||
c227f099 | 4275 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) |
bc98a7ef JM |
4276 | { |
4277 | int io_index; | |
4278 | uint8_t *ptr; | |
4279 | unsigned long pd; | |
4280 | PhysPageDesc *p; | |
4281 | ||
4282 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4283 | if (!p) { | |
4284 | pd = IO_MEM_UNASSIGNED; | |
4285 | } else { | |
4286 | pd = p->phys_offset; | |
4287 | } | |
3b46e624 | 4288 | |
bc98a7ef JM |
4289 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
4290 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
4291 | if (p) |
4292 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
bc98a7ef JM |
4293 | #ifdef TARGET_WORDS_BIGENDIAN |
4294 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32); | |
4295 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val); | |
4296 | #else | |
4297 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); | |
4298 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32); | |
4299 | #endif | |
4300 | } else { | |
5579c7f3 | 4301 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bc98a7ef JM |
4302 | (addr & ~TARGET_PAGE_MASK); |
4303 | stq_p(ptr, val); | |
4304 | } | |
4305 | } | |
4306 | ||
8df1cd07 | 4307 | /* warning: addr must be aligned */ |
c227f099 | 4308 | void stl_phys(target_phys_addr_t addr, uint32_t val) |
8df1cd07 FB |
4309 | { |
4310 | int io_index; | |
4311 | uint8_t *ptr; | |
4312 | unsigned long pd; | |
4313 | PhysPageDesc *p; | |
4314 | ||
4315 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4316 | if (!p) { | |
4317 | pd = IO_MEM_UNASSIGNED; | |
4318 | } else { | |
4319 | pd = p->phys_offset; | |
4320 | } | |
3b46e624 | 4321 | |
3a7d929e | 4322 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 | 4323 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 PB |
4324 | if (p) |
4325 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
4326 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
4327 | } else { | |
4328 | unsigned long addr1; | |
4329 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
4330 | /* RAM case */ | |
5579c7f3 | 4331 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 4332 | stl_p(ptr, val); |
3a7d929e FB |
4333 | if (!cpu_physical_memory_is_dirty(addr1)) { |
4334 | /* invalidate code */ | |
4335 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
4336 | /* set dirty bit */ | |
f7c11b53 YT |
4337 | cpu_physical_memory_set_dirty_flags(addr1, |
4338 | (0xff & ~CODE_DIRTY_FLAG)); | |
3a7d929e | 4339 | } |
8df1cd07 FB |
4340 | } |
4341 | } | |
4342 | ||
aab33094 | 4343 | /* XXX: optimize */ |
c227f099 | 4344 | void stb_phys(target_phys_addr_t addr, uint32_t val) |
aab33094 FB |
4345 | { |
4346 | uint8_t v = val; | |
4347 | cpu_physical_memory_write(addr, &v, 1); | |
4348 | } | |
4349 | ||
733f0b02 | 4350 | /* warning: addr must be aligned */ |
c227f099 | 4351 | void stw_phys(target_phys_addr_t addr, uint32_t val) |
aab33094 | 4352 | { |
733f0b02 MT |
4353 | int io_index; |
4354 | uint8_t *ptr; | |
4355 | unsigned long pd; | |
4356 | PhysPageDesc *p; | |
4357 | ||
4358 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
4359 | if (!p) { | |
4360 | pd = IO_MEM_UNASSIGNED; | |
4361 | } else { | |
4362 | pd = p->phys_offset; | |
4363 | } | |
4364 | ||
4365 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
4366 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
4367 | if (p) | |
4368 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
4369 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val); | |
4370 | } else { | |
4371 | unsigned long addr1; | |
4372 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
4373 | /* RAM case */ | |
4374 | ptr = qemu_get_ram_ptr(addr1); | |
4375 | stw_p(ptr, val); | |
4376 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
4377 | /* invalidate code */ | |
4378 | tb_invalidate_phys_page_range(addr1, addr1 + 2, 0); | |
4379 | /* set dirty bit */ | |
4380 | cpu_physical_memory_set_dirty_flags(addr1, | |
4381 | (0xff & ~CODE_DIRTY_FLAG)); | |
4382 | } | |
4383 | } | |
aab33094 FB |
4384 | } |
4385 | ||
4386 | /* XXX: optimize */ | |
c227f099 | 4387 | void stq_phys(target_phys_addr_t addr, uint64_t val) |
aab33094 FB |
4388 | { |
4389 | val = tswap64(val); | |
71d2b725 | 4390 | cpu_physical_memory_write(addr, &val, 8); |
aab33094 FB |
4391 | } |
4392 | ||
5e2972fd | 4393 | /* virtual memory access for debug (includes writing to ROM) */ |
5fafdf24 | 4394 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
b448f2f3 | 4395 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
4396 | { |
4397 | int l; | |
c227f099 | 4398 | target_phys_addr_t phys_addr; |
9b3c35e0 | 4399 | target_ulong page; |
13eb76e0 FB |
4400 | |
4401 | while (len > 0) { | |
4402 | page = addr & TARGET_PAGE_MASK; | |
4403 | phys_addr = cpu_get_phys_page_debug(env, page); | |
4404 | /* if no physical page mapped, return an error */ | |
4405 | if (phys_addr == -1) | |
4406 | return -1; | |
4407 | l = (page + TARGET_PAGE_SIZE) - addr; | |
4408 | if (l > len) | |
4409 | l = len; | |
5e2972fd | 4410 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
5e2972fd AL |
4411 | if (is_write) |
4412 | cpu_physical_memory_write_rom(phys_addr, buf, l); | |
4413 | else | |
5e2972fd | 4414 | cpu_physical_memory_rw(phys_addr, buf, l, is_write); |
13eb76e0 FB |
4415 | len -= l; |
4416 | buf += l; | |
4417 | addr += l; | |
4418 | } | |
4419 | return 0; | |
4420 | } | |
a68fe89c | 4421 | #endif |
13eb76e0 | 4422 | |
2e70f6ef PB |
4423 | /* in deterministic execution mode, instructions doing device I/Os |
4424 | must be at the end of the TB */ | |
4425 | void cpu_io_recompile(CPUState *env, void *retaddr) | |
4426 | { | |
4427 | TranslationBlock *tb; | |
4428 | uint32_t n, cflags; | |
4429 | target_ulong pc, cs_base; | |
4430 | uint64_t flags; | |
4431 | ||
4432 | tb = tb_find_pc((unsigned long)retaddr); | |
4433 | if (!tb) { | |
4434 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", | |
4435 | retaddr); | |
4436 | } | |
4437 | n = env->icount_decr.u16.low + tb->icount; | |
618ba8e6 | 4438 | cpu_restore_state(tb, env, (unsigned long)retaddr); |
2e70f6ef | 4439 | /* Calculate how many instructions had been executed before the fault |
bf20dc07 | 4440 | occurred. */ |
2e70f6ef PB |
4441 | n = n - env->icount_decr.u16.low; |
4442 | /* Generate a new TB ending on the I/O insn. */ | |
4443 | n++; | |
4444 | /* On MIPS and SH, delay slot instructions can only be restarted if | |
4445 | they were already the first instruction in the TB. If this is not | |
bf20dc07 | 4446 | the first instruction in a TB then re-execute the preceding |
2e70f6ef PB |
4447 | branch. */ |
4448 | #if defined(TARGET_MIPS) | |
4449 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { | |
4450 | env->active_tc.PC -= 4; | |
4451 | env->icount_decr.u16.low++; | |
4452 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
4453 | } | |
4454 | #elif defined(TARGET_SH4) | |
4455 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 | |
4456 | && n > 1) { | |
4457 | env->pc -= 2; | |
4458 | env->icount_decr.u16.low++; | |
4459 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); | |
4460 | } | |
4461 | #endif | |
4462 | /* This should never happen. */ | |
4463 | if (n > CF_COUNT_MASK) | |
4464 | cpu_abort(env, "TB too big during recompile"); | |
4465 | ||
4466 | cflags = n | CF_LAST_IO; | |
4467 | pc = tb->pc; | |
4468 | cs_base = tb->cs_base; | |
4469 | flags = tb->flags; | |
4470 | tb_phys_invalidate(tb, -1); | |
4471 | /* FIXME: In theory this could raise an exception. In practice | |
4472 | we have already translated the block once so it's probably ok. */ | |
4473 | tb_gen_code(env, pc, cs_base, flags, cflags); | |
bf20dc07 | 4474 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
2e70f6ef PB |
4475 | the first in the TB) then we end up generating a whole new TB and |
4476 | repeating the fault, which is horribly inefficient. | |
4477 | Better would be to execute just this insn uncached, or generate a | |
4478 | second new TB. */ | |
4479 | cpu_resume_from_signal(env, NULL); | |
4480 | } | |
4481 | ||
b3755a91 PB |
4482 | #if !defined(CONFIG_USER_ONLY) |
4483 | ||
055403b2 | 4484 | void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) |
e3db7226 FB |
4485 | { |
4486 | int i, target_code_size, max_target_code_size; | |
4487 | int direct_jmp_count, direct_jmp2_count, cross_page; | |
4488 | TranslationBlock *tb; | |
3b46e624 | 4489 | |
e3db7226 FB |
4490 | target_code_size = 0; |
4491 | max_target_code_size = 0; | |
4492 | cross_page = 0; | |
4493 | direct_jmp_count = 0; | |
4494 | direct_jmp2_count = 0; | |
4495 | for(i = 0; i < nb_tbs; i++) { | |
4496 | tb = &tbs[i]; | |
4497 | target_code_size += tb->size; | |
4498 | if (tb->size > max_target_code_size) | |
4499 | max_target_code_size = tb->size; | |
4500 | if (tb->page_addr[1] != -1) | |
4501 | cross_page++; | |
4502 | if (tb->tb_next_offset[0] != 0xffff) { | |
4503 | direct_jmp_count++; | |
4504 | if (tb->tb_next_offset[1] != 0xffff) { | |
4505 | direct_jmp2_count++; | |
4506 | } | |
4507 | } | |
4508 | } | |
4509 | /* XXX: avoid using doubles ? */ | |
57fec1fe | 4510 | cpu_fprintf(f, "Translation buffer state:\n"); |
055403b2 | 4511 | cpu_fprintf(f, "gen code size %td/%ld\n", |
26a5f13b FB |
4512 | code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size); |
4513 | cpu_fprintf(f, "TB count %d/%d\n", | |
4514 | nb_tbs, code_gen_max_blocks); | |
5fafdf24 | 4515 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
e3db7226 FB |
4516 | nb_tbs ? target_code_size / nb_tbs : 0, |
4517 | max_target_code_size); | |
055403b2 | 4518 | cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)\n", |
e3db7226 FB |
4519 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0, |
4520 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0); | |
5fafdf24 TS |
4521 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", |
4522 | cross_page, | |
e3db7226 FB |
4523 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); |
4524 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", | |
5fafdf24 | 4525 | direct_jmp_count, |
e3db7226 FB |
4526 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, |
4527 | direct_jmp2_count, | |
4528 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); | |
57fec1fe | 4529 | cpu_fprintf(f, "\nStatistics:\n"); |
e3db7226 FB |
4530 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); |
4531 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); | |
4532 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); | |
b67d9a52 | 4533 | tcg_dump_info(f, cpu_fprintf); |
e3db7226 FB |
4534 | } |
4535 | ||
61382a50 FB |
4536 | #define MMUSUFFIX _cmmu |
4537 | #define GETPC() NULL | |
4538 | #define env cpu_single_env | |
b769d8fe | 4539 | #define SOFTMMU_CODE_ACCESS |
61382a50 FB |
4540 | |
4541 | #define SHIFT 0 | |
4542 | #include "softmmu_template.h" | |
4543 | ||
4544 | #define SHIFT 1 | |
4545 | #include "softmmu_template.h" | |
4546 | ||
4547 | #define SHIFT 2 | |
4548 | #include "softmmu_template.h" | |
4549 | ||
4550 | #define SHIFT 3 | |
4551 | #include "softmmu_template.h" | |
4552 | ||
4553 | #undef env | |
4554 | ||
4555 | #endif |