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Commit | Line | Data |
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93d89f63 IY |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This library is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * Lesser General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU Lesser General Public | |
16 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
6b620ca3 PB |
17 | * |
18 | * Contributions after 2012-01-13 are licensed under the terms of the | |
19 | * GNU GPL, version 2 or (at your option) any later version. | |
93d89f63 | 20 | */ |
71e8a915 | 21 | |
b6a0aa05 | 22 | #include "qemu/osdep.h" |
0d09e41a | 23 | #include "hw/i386/pc.h" |
fff123b8 | 24 | #include "hw/southbridge/piix.h" |
64552b6b | 25 | #include "hw/irq.h" |
0d09e41a PB |
26 | #include "hw/isa/apm.h" |
27 | #include "hw/i2c/pm_smbus.h" | |
83c9f4ca | 28 | #include "hw/pci/pci.h" |
a27bd6c7 | 29 | #include "hw/qdev-properties.h" |
0d09e41a | 30 | #include "hw/acpi/acpi.h" |
54d31236 | 31 | #include "sysemu/runstate.h" |
9c17d615 | 32 | #include "sysemu/sysemu.h" |
da278d58 | 33 | #include "sysemu/xen.h" |
da34e65c | 34 | #include "qapi/error.h" |
1de7afc9 | 35 | #include "qemu/range.h" |
022c62cb | 36 | #include "exec/address-spaces.h" |
9e047b98 | 37 | #include "hw/acpi/pcihp.h" |
81cea5e7 | 38 | #include "hw/acpi/cpu_hotplug.h" |
5e1b5d93 | 39 | #include "hw/acpi/cpu.h" |
c24d5e0b | 40 | #include "hw/hotplug.h" |
34774320 | 41 | #include "hw/mem/pc-dimm.h" |
132a908b | 42 | #include "hw/mem/nvdimm.h" |
34774320 | 43 | #include "hw/acpi/memory_hotplug.h" |
43f50410 | 44 | #include "hw/acpi/acpi_dev_interface.h" |
d6454270 | 45 | #include "migration/vmstate.h" |
2e5b09fd | 46 | #include "hw/core/cpu.h" |
b37d56ec | 47 | #include "trace.h" |
50d8ff8b | 48 | |
ac404095 | 49 | #define GPE_BASE 0xafe0 |
23910d3f | 50 | #define GPE_LEN 4 |
c177684c | 51 | |
ac404095 | 52 | struct pci_status { |
7faa8075 | 53 | uint32_t up; /* deprecated, maintained for migration compatibility */ |
ac404095 IY |
54 | uint32_t down; |
55 | }; | |
56 | ||
93d89f63 | 57 | typedef struct PIIX4PMState { |
6a6b5580 AF |
58 | /*< private >*/ |
59 | PCIDevice parent_obj; | |
60 | /*< public >*/ | |
56e5b2a1 | 61 | |
af11110b | 62 | MemoryRegion io; |
277e9340 MT |
63 | uint32_t io_base; |
64 | ||
b65b93f2 | 65 | MemoryRegion io_gpe; |
355bf2e5 | 66 | ACPIREGS ar; |
93d89f63 IY |
67 | |
68 | APMState apm; | |
69 | ||
93d89f63 | 70 | PMSMBus smb; |
e8ec0571 | 71 | uint32_t smb_io_base; |
93d89f63 IY |
72 | |
73 | qemu_irq irq; | |
93d89f63 | 74 | qemu_irq smi_irq; |
61e66c62 | 75 | int smm_enabled; |
6141dbfe | 76 | Notifier machine_ready; |
d010f91c | 77 | Notifier powerdown_notifier; |
ac404095 | 78 | |
9e047b98 | 79 | AcpiPciHpState acpi_pci_hotplug; |
0affda04 | 80 | bool use_acpi_hotplug_bridge; |
9e047b98 | 81 | |
459ae5ea GN |
82 | uint8_t disable_s3; |
83 | uint8_t disable_s4; | |
84 | uint8_t s4_val; | |
b8622725 | 85 | |
16bcab97 | 86 | bool cpu_hotplug_legacy; |
81cea5e7 | 87 | AcpiCpuHotplug gpe_cpu; |
5e1b5d93 | 88 | CPUHotplugState cpuhp_state; |
34774320 IM |
89 | |
90 | MemHotplugState acpi_memory_hotplug; | |
93d89f63 IY |
91 | } PIIX4PMState; |
92 | ||
74e445f6 PC |
93 | #define PIIX4_PM(obj) \ |
94 | OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) | |
95 | ||
56e5b2a1 GH |
96 | static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
97 | PCIBus *bus, PIIX4PMState *s); | |
ac404095 | 98 | |
93d89f63 IY |
99 | #define ACPI_ENABLE 0xf1 |
100 | #define ACPI_DISABLE 0xf0 | |
101 | ||
355bf2e5 | 102 | static void pm_tmr_timer(ACPIREGS *ar) |
93d89f63 | 103 | { |
355bf2e5 | 104 | PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
06313503 | 105 | acpi_update_sci(&s->ar, s->irq); |
93d89f63 IY |
106 | } |
107 | ||
93d89f63 IY |
108 | static void apm_ctrl_changed(uint32_t val, void *arg) |
109 | { | |
110 | PIIX4PMState *s = arg; | |
6a6b5580 | 111 | PCIDevice *d = PCI_DEVICE(s); |
93d89f63 IY |
112 | |
113 | /* ACPI specs 3.0, 4.7.2.5 */ | |
355bf2e5 | 114 | acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
afd6895b PB |
115 | if (val == ACPI_ENABLE || val == ACPI_DISABLE) { |
116 | return; | |
117 | } | |
93d89f63 | 118 | |
6a6b5580 | 119 | if (d->config[0x5b] & (1 << 1)) { |
93d89f63 IY |
120 | if (s->smi_irq) { |
121 | qemu_irq_raise(s->smi_irq); | |
122 | } | |
123 | } | |
124 | } | |
125 | ||
93d89f63 IY |
126 | static void pm_io_space_update(PIIX4PMState *s) |
127 | { | |
6a6b5580 | 128 | PCIDevice *d = PCI_DEVICE(s); |
93d89f63 | 129 | |
277e9340 MT |
130 | s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); |
131 | s->io_base &= 0xffc0; | |
93d89f63 | 132 | |
af11110b | 133 | memory_region_transaction_begin(); |
6a6b5580 | 134 | memory_region_set_enabled(&s->io, d->config[0x80] & 1); |
277e9340 | 135 | memory_region_set_address(&s->io, s->io_base); |
af11110b | 136 | memory_region_transaction_commit(); |
93d89f63 IY |
137 | } |
138 | ||
24fe083d GH |
139 | static void smbus_io_space_update(PIIX4PMState *s) |
140 | { | |
6a6b5580 AF |
141 | PCIDevice *d = PCI_DEVICE(s); |
142 | ||
143 | s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); | |
24fe083d GH |
144 | s->smb_io_base &= 0xffc0; |
145 | ||
146 | memory_region_transaction_begin(); | |
6a6b5580 | 147 | memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); |
24fe083d GH |
148 | memory_region_set_address(&s->smb.io, s->smb_io_base); |
149 | memory_region_transaction_commit(); | |
93d89f63 IY |
150 | } |
151 | ||
152 | static void pm_write_config(PCIDevice *d, | |
153 | uint32_t address, uint32_t val, int len) | |
154 | { | |
155 | pci_default_write_config(d, address, val, len); | |
24fe083d GH |
156 | if (range_covers_byte(address, len, 0x80) || |
157 | ranges_overlap(address, len, 0x40, 4)) { | |
93d89f63 | 158 | pm_io_space_update((PIIX4PMState *)d); |
24fe083d GH |
159 | } |
160 | if (range_covers_byte(address, len, 0xd2) || | |
161 | ranges_overlap(address, len, 0x90, 4)) { | |
162 | smbus_io_space_update((PIIX4PMState *)d); | |
163 | } | |
93d89f63 IY |
164 | } |
165 | ||
166 | static int vmstate_acpi_post_load(void *opaque, int version_id) | |
167 | { | |
168 | PIIX4PMState *s = opaque; | |
169 | ||
170 | pm_io_space_update(s); | |
2b4e573c | 171 | smbus_io_space_update(s); |
93d89f63 IY |
172 | return 0; |
173 | } | |
174 | ||
23910d3f IY |
175 | #define VMSTATE_GPE_ARRAY(_field, _state) \ |
176 | { \ | |
177 | .name = (stringify(_field)), \ | |
178 | .version_id = 0, \ | |
23910d3f IY |
179 | .info = &vmstate_info_uint16, \ |
180 | .size = sizeof(uint16_t), \ | |
b0b873a0 | 181 | .flags = VMS_SINGLE | VMS_POINTER, \ |
23910d3f IY |
182 | .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ |
183 | } | |
184 | ||
4cf3e6f3 AW |
185 | static const VMStateDescription vmstate_gpe = { |
186 | .name = "gpe", | |
187 | .version_id = 1, | |
188 | .minimum_version_id = 1, | |
d49805ae | 189 | .fields = (VMStateField[]) { |
23910d3f IY |
190 | VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
191 | VMSTATE_GPE_ARRAY(en, ACPIGPE), | |
4cf3e6f3 AW |
192 | VMSTATE_END_OF_LIST() |
193 | } | |
194 | }; | |
195 | ||
196 | static const VMStateDescription vmstate_pci_status = { | |
197 | .name = "pci_status", | |
198 | .version_id = 1, | |
199 | .minimum_version_id = 1, | |
d49805ae | 200 | .fields = (VMStateField[]) { |
e358edc8 IM |
201 | VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), |
202 | VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), | |
4cf3e6f3 AW |
203 | VMSTATE_END_OF_LIST() |
204 | } | |
205 | }; | |
206 | ||
0affda04 | 207 | static bool vmstate_test_use_acpi_hotplug_bridge(void *opaque, int version_id) |
9e047b98 MT |
208 | { |
209 | PIIX4PMState *s = opaque; | |
0affda04 | 210 | return s->use_acpi_hotplug_bridge; |
9e047b98 MT |
211 | } |
212 | ||
0affda04 AS |
213 | static bool vmstate_test_no_use_acpi_hotplug_bridge(void *opaque, |
214 | int version_id) | |
9e047b98 MT |
215 | { |
216 | PIIX4PMState *s = opaque; | |
0affda04 | 217 | return !s->use_acpi_hotplug_bridge; |
9e047b98 MT |
218 | } |
219 | ||
f816a62d IM |
220 | static bool vmstate_test_use_memhp(void *opaque) |
221 | { | |
222 | PIIX4PMState *s = opaque; | |
223 | return s->acpi_memory_hotplug.is_enabled; | |
224 | } | |
225 | ||
226 | static const VMStateDescription vmstate_memhp_state = { | |
227 | .name = "piix4_pm/memhp", | |
228 | .version_id = 1, | |
229 | .minimum_version_id = 1, | |
230 | .minimum_version_id_old = 1, | |
5cd8cada | 231 | .needed = vmstate_test_use_memhp, |
f816a62d IM |
232 | .fields = (VMStateField[]) { |
233 | VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), | |
234 | VMSTATE_END_OF_LIST() | |
235 | } | |
236 | }; | |
237 | ||
679dd1a9 IM |
238 | static bool vmstate_test_use_cpuhp(void *opaque) |
239 | { | |
240 | PIIX4PMState *s = opaque; | |
241 | return !s->cpu_hotplug_legacy; | |
242 | } | |
243 | ||
244 | static int vmstate_cpuhp_pre_load(void *opaque) | |
245 | { | |
246 | Object *obj = OBJECT(opaque); | |
247 | object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort); | |
248 | return 0; | |
249 | } | |
250 | ||
251 | static const VMStateDescription vmstate_cpuhp_state = { | |
252 | .name = "piix4_pm/cpuhp", | |
253 | .version_id = 1, | |
254 | .minimum_version_id = 1, | |
255 | .minimum_version_id_old = 1, | |
256 | .needed = vmstate_test_use_cpuhp, | |
257 | .pre_load = vmstate_cpuhp_pre_load, | |
258 | .fields = (VMStateField[]) { | |
259 | VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState), | |
260 | VMSTATE_END_OF_LIST() | |
261 | } | |
262 | }; | |
263 | ||
4ab2f2a8 CM |
264 | static bool piix4_vmstate_need_smbus(void *opaque, int version_id) |
265 | { | |
266 | return pm_smbus_vmstate_needed(); | |
267 | } | |
268 | ||
b0b873a0 MT |
269 | /* qemu-kvm 1.2 uses version 3 but advertised as 2 |
270 | * To support incoming qemu-kvm 1.2 migration, change version_id | |
271 | * and minimum_version_id to 2 below (which breaks migration from | |
272 | * qemu 1.2). | |
273 | * | |
274 | */ | |
93d89f63 IY |
275 | static const VMStateDescription vmstate_acpi = { |
276 | .name = "piix4_pm", | |
b0b873a0 MT |
277 | .version_id = 3, |
278 | .minimum_version_id = 3, | |
93d89f63 | 279 | .post_load = vmstate_acpi_post_load, |
d49805ae | 280 | .fields = (VMStateField[]) { |
6a6b5580 | 281 | VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), |
355bf2e5 GH |
282 | VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
283 | VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), | |
284 | VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), | |
93d89f63 | 285 | VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), |
4ab2f2a8 CM |
286 | VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3, |
287 | pmsmb_vmstate, PMSMBus), | |
e720677e | 288 | VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), |
355bf2e5 GH |
289 | VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), |
290 | VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), | |
e358edc8 IM |
291 | VMSTATE_STRUCT_TEST( |
292 | acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], | |
293 | PIIX4PMState, | |
0affda04 | 294 | vmstate_test_no_use_acpi_hotplug_bridge, |
e358edc8 IM |
295 | 2, vmstate_pci_status, |
296 | struct AcpiPciHpPciStatus), | |
9e047b98 | 297 | VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, |
0affda04 | 298 | vmstate_test_use_acpi_hotplug_bridge), |
93d89f63 | 299 | VMSTATE_END_OF_LIST() |
f816a62d | 300 | }, |
5cd8cada JQ |
301 | .subsections = (const VMStateDescription*[]) { |
302 | &vmstate_memhp_state, | |
679dd1a9 | 303 | &vmstate_cpuhp_state, |
5cd8cada | 304 | NULL |
93d89f63 IY |
305 | } |
306 | }; | |
307 | ||
217e8ef9 | 308 | static void piix4_pm_reset(DeviceState *dev) |
93d89f63 | 309 | { |
217e8ef9 | 310 | PIIX4PMState *s = PIIX4_PM(dev); |
6a6b5580 AF |
311 | PCIDevice *d = PCI_DEVICE(s); |
312 | uint8_t *pci_conf = d->config; | |
93d89f63 IY |
313 | |
314 | pci_conf[0x58] = 0; | |
315 | pci_conf[0x59] = 0; | |
316 | pci_conf[0x5a] = 0; | |
317 | pci_conf[0x5b] = 0; | |
318 | ||
4d09d37c GN |
319 | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
320 | pci_conf[0x80] = 0; | |
321 | ||
61e66c62 | 322 | if (!s->smm_enabled) { |
93d89f63 IY |
323 | /* Mark SMM as already inited (until KVM supports SMM). */ |
324 | pci_conf[0x5B] = 0x02; | |
325 | } | |
c046e8c4 | 326 | pm_io_space_update(s); |
e358edc8 | 327 | acpi_pcihp_reset(&s->acpi_pci_hotplug); |
93d89f63 IY |
328 | } |
329 | ||
d010f91c | 330 | static void piix4_pm_powerdown_req(Notifier *n, void *opaque) |
93d89f63 | 331 | { |
d010f91c | 332 | PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); |
93d89f63 | 333 | |
355bf2e5 GH |
334 | assert(s != NULL); |
335 | acpi_pm1_evt_power_down(&s->ar); | |
93d89f63 IY |
336 | } |
337 | ||
ec266f40 DH |
338 | static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev, |
339 | DeviceState *dev, Error **errp) | |
340 | { | |
9040e6df WY |
341 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); |
342 | ||
ec266f40 DH |
343 | if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
344 | acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp); | |
9040e6df WY |
345 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
346 | if (!s->acpi_memory_hotplug.is_enabled) { | |
347 | error_setg(errp, | |
348 | "memory hotplug is not enabled: %s.memory-hotplug-support " | |
349 | "is not set", object_get_typename(OBJECT(s))); | |
350 | } | |
351 | } else if ( | |
ec266f40 DH |
352 | !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
353 | error_setg(errp, "acpi: device pre plug request for not supported" | |
354 | " device type: %s", object_get_typename(OBJECT(dev))); | |
355 | } | |
356 | } | |
357 | ||
f1adc360 IM |
358 | static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, |
359 | DeviceState *dev, Error **errp) | |
9e047b98 | 360 | { |
c24d5e0b | 361 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); |
f1adc360 | 362 | |
9040e6df | 363 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
75f27498 XG |
364 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
365 | nvdimm_acpi_plug_cb(hotplug_dev, dev); | |
366 | } else { | |
367 | acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug, | |
368 | dev, errp); | |
369 | } | |
34774320 | 370 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
2bed1ba7 | 371 | acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); |
5e1b5d93 IM |
372 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
373 | if (s->cpu_hotplug_legacy) { | |
374 | legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp); | |
375 | } else { | |
376 | acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); | |
377 | } | |
f1adc360 | 378 | } else { |
ec266f40 | 379 | g_assert_not_reached(); |
f1adc360 | 380 | } |
c24d5e0b | 381 | } |
9e047b98 | 382 | |
14d5a28f IM |
383 | static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
384 | DeviceState *dev, Error **errp) | |
c24d5e0b IM |
385 | { |
386 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); | |
f1adc360 | 387 | |
64fec58e TC |
388 | if (s->acpi_memory_hotplug.is_enabled && |
389 | object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
0058c082 | 390 | acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug, |
64fec58e TC |
391 | dev, errp); |
392 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { | |
c97adf3c DH |
393 | acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug, |
394 | dev, errp); | |
8872c25a IM |
395 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && |
396 | !s->cpu_hotplug_legacy) { | |
397 | acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp); | |
f1adc360 IM |
398 | } else { |
399 | error_setg(errp, "acpi: device unplug request for not supported device" | |
400 | " type: %s", object_get_typename(OBJECT(dev))); | |
401 | } | |
9e047b98 MT |
402 | } |
403 | ||
c0e57a60 TC |
404 | static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, |
405 | DeviceState *dev, Error **errp) | |
406 | { | |
f7d3e29d TC |
407 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); |
408 | ||
409 | if (s->acpi_memory_hotplug.is_enabled && | |
410 | object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
411 | acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp); | |
c97adf3c DH |
412 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
413 | acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, | |
414 | errp); | |
8872c25a IM |
415 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && |
416 | !s->cpu_hotplug_legacy) { | |
417 | acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); | |
f7d3e29d TC |
418 | } else { |
419 | error_setg(errp, "acpi: device unplug for not supported device" | |
420 | " type: %s", object_get_typename(OBJECT(dev))); | |
421 | } | |
c0e57a60 TC |
422 | } |
423 | ||
9e8dd451 | 424 | static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
6141dbfe PB |
425 | { |
426 | PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); | |
6a6b5580 AF |
427 | PCIDevice *d = PCI_DEVICE(s); |
428 | MemoryRegion *io_as = pci_address_space_io(d); | |
6141dbfe PB |
429 | uint8_t *pci_conf; |
430 | ||
6a6b5580 | 431 | pci_conf = d->config; |
b6f32962 | 432 | pci_conf[0x5f] = 0x10 | |
3ce10901 | 433 | (memory_region_present(io_as, 0x378) ? 0x80 : 0); |
6141dbfe | 434 | pci_conf[0x63] = 0x60; |
3ce10901 PB |
435 | pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | |
436 | (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); | |
6141dbfe PB |
437 | } |
438 | ||
277e9340 MT |
439 | static void piix4_pm_add_propeties(PIIX4PMState *s) |
440 | { | |
441 | static const uint8_t acpi_enable_cmd = ACPI_ENABLE; | |
442 | static const uint8_t acpi_disable_cmd = ACPI_DISABLE; | |
443 | static const uint32_t gpe0_blk = GPE_BASE; | |
444 | static const uint32_t gpe0_blk_len = GPE_LEN; | |
445 | static const uint16_t sci_int = 9; | |
446 | ||
447 | object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, | |
d2623129 | 448 | &acpi_enable_cmd, OBJ_PROP_FLAG_READ); |
277e9340 | 449 | object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, |
d2623129 | 450 | &acpi_disable_cmd, OBJ_PROP_FLAG_READ); |
277e9340 | 451 | object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, |
d2623129 | 452 | &gpe0_blk, OBJ_PROP_FLAG_READ); |
277e9340 | 453 | object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, |
d2623129 | 454 | &gpe0_blk_len, OBJ_PROP_FLAG_READ); |
277e9340 | 455 | object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, |
d2623129 | 456 | &sci_int, OBJ_PROP_FLAG_READ); |
277e9340 | 457 | object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, |
d2623129 | 458 | &s->io_base, OBJ_PROP_FLAG_READ); |
277e9340 MT |
459 | } |
460 | ||
9af21dbe | 461 | static void piix4_pm_realize(PCIDevice *dev, Error **errp) |
93d89f63 | 462 | { |
74e445f6 | 463 | PIIX4PMState *s = PIIX4_PM(dev); |
93d89f63 IY |
464 | uint8_t *pci_conf; |
465 | ||
6a6b5580 | 466 | pci_conf = dev->config; |
93d89f63 IY |
467 | pci_conf[0x06] = 0x80; |
468 | pci_conf[0x07] = 0x02; | |
93d89f63 | 469 | pci_conf[0x09] = 0x00; |
93d89f63 IY |
470 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
471 | ||
93d89f63 | 472 | /* APM */ |
42d8a3cf | 473 | apm_init(dev, &s->apm, apm_ctrl_changed, s); |
93d89f63 | 474 | |
61e66c62 | 475 | if (!s->smm_enabled) { |
93d89f63 IY |
476 | /* Mark SMM as already inited to prevent SMM from running. KVM does not |
477 | * support SMM mode. */ | |
478 | pci_conf[0x5B] = 0x02; | |
479 | } | |
480 | ||
481 | /* XXX: which specification is used ? The i82731AB has different | |
482 | mappings */ | |
e8ec0571 IY |
483 | pci_conf[0x90] = s->smb_io_base | 1; |
484 | pci_conf[0x91] = s->smb_io_base >> 8; | |
93d89f63 | 485 | pci_conf[0xd2] = 0x09; |
45726b6e | 486 | pm_smbus_init(DEVICE(dev), &s->smb, true); |
24fe083d | 487 | memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); |
56e5b2a1 GH |
488 | memory_region_add_subregion(pci_address_space_io(dev), |
489 | s->smb_io_base, &s->smb.io); | |
93d89f63 | 490 | |
64bde0f3 | 491 | memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); |
af11110b | 492 | memory_region_set_enabled(&s->io, false); |
56e5b2a1 GH |
493 | memory_region_add_subregion(pci_address_space_io(dev), |
494 | 0, &s->io); | |
93d89f63 | 495 | |
77d58b1e | 496 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
b5a7c024 | 497 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
9a10bbb4 | 498 | acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val); |
355bf2e5 | 499 | acpi_gpe_init(&s->ar, GPE_LEN); |
93d89f63 | 500 | |
d010f91c IM |
501 | s->powerdown_notifier.notify = piix4_pm_powerdown_req; |
502 | qemu_register_powerdown_notifier(&s->powerdown_notifier); | |
93d89f63 | 503 | |
6141dbfe PB |
504 | s->machine_ready.notify = piix4_pm_machine_ready; |
505 | qemu_add_machine_init_done_notifier(&s->machine_ready); | |
56e5b2a1 | 506 | |
fd56e061 DG |
507 | piix4_acpi_system_hot_add_init(pci_address_space_io(dev), |
508 | pci_get_bus(dev), s); | |
9bc6bfdf | 509 | qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s)); |
e8ec0571 | 510 | |
277e9340 | 511 | piix4_pm_add_propeties(s); |
e8ec0571 IY |
512 | } |
513 | ||
a5c82852 AF |
514 | I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, |
515 | qemu_irq sci_irq, qemu_irq smi_irq, | |
61e66c62 | 516 | int smm_enabled, DeviceState **piix4_pm) |
e8ec0571 | 517 | { |
9307d06d | 518 | PCIDevice *pci_dev; |
74e445f6 | 519 | DeviceState *dev; |
e8ec0571 IY |
520 | PIIX4PMState *s; |
521 | ||
9307d06d MA |
522 | pci_dev = pci_new(devfn, TYPE_PIIX4_PM); |
523 | dev = DEVICE(pci_dev); | |
74e445f6 | 524 | qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); |
781bbd6b IM |
525 | if (piix4_pm) { |
526 | *piix4_pm = dev; | |
527 | } | |
93d89f63 | 528 | |
74e445f6 | 529 | s = PIIX4_PM(dev); |
93d89f63 | 530 | s->irq = sci_irq; |
93d89f63 | 531 | s->smi_irq = smi_irq; |
61e66c62 | 532 | s->smm_enabled = smm_enabled; |
91ab2ed7 | 533 | if (xen_enabled()) { |
0affda04 | 534 | s->use_acpi_hotplug_bridge = false; |
91ab2ed7 | 535 | } |
e8ec0571 | 536 | |
9307d06d | 537 | pci_realize_and_unref(pci_dev, bus, &error_fatal); |
93d89f63 IY |
538 | |
539 | return s->smb.smbus; | |
540 | } | |
541 | ||
b65b93f2 | 542 | static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) |
93d89f63 | 543 | { |
633aa0ac | 544 | PIIX4PMState *s = opaque; |
355bf2e5 | 545 | uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
93d89f63 | 546 | |
b37d56ec | 547 | trace_piix4_gpe_readb(addr, width, val); |
93d89f63 IY |
548 | return val; |
549 | } | |
550 | ||
b65b93f2 GH |
551 | static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, |
552 | unsigned width) | |
93d89f63 | 553 | { |
633aa0ac | 554 | PIIX4PMState *s = opaque; |
633aa0ac | 555 | |
b37d56ec | 556 | trace_piix4_gpe_writeb(addr, width, val); |
355bf2e5 | 557 | acpi_gpe_ioport_writeb(&s->ar, addr, val); |
06313503 | 558 | acpi_update_sci(&s->ar, s->irq); |
93d89f63 IY |
559 | } |
560 | ||
b65b93f2 GH |
561 | static const MemoryRegionOps piix4_gpe_ops = { |
562 | .read = gpe_readb, | |
563 | .write = gpe_writeb, | |
564 | .valid.min_access_size = 1, | |
565 | .valid.max_access_size = 4, | |
566 | .impl.min_access_size = 1, | |
567 | .impl.max_access_size = 1, | |
568 | .endianness = DEVICE_LITTLE_ENDIAN, | |
569 | }; | |
570 | ||
16bcab97 IM |
571 | |
572 | static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp) | |
573 | { | |
574 | PIIX4PMState *s = PIIX4_PM(obj); | |
575 | ||
576 | return s->cpu_hotplug_legacy; | |
577 | } | |
578 | ||
579 | static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp) | |
580 | { | |
581 | PIIX4PMState *s = PIIX4_PM(obj); | |
582 | ||
679dd1a9 IM |
583 | assert(!value); |
584 | if (s->cpu_hotplug_legacy && value == false) { | |
585 | acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state, | |
586 | PIIX4_CPU_HOTPLUG_IO_BASE); | |
587 | } | |
16bcab97 IM |
588 | s->cpu_hotplug_legacy = value; |
589 | } | |
590 | ||
56e5b2a1 GH |
591 | static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
592 | PCIBus *bus, PIIX4PMState *s) | |
93d89f63 | 593 | { |
64bde0f3 PB |
594 | memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, |
595 | "acpi-gpe0", GPE_LEN); | |
56e5b2a1 | 596 | memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); |
ac404095 | 597 | |
78c2d872 | 598 | acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, |
0affda04 | 599 | s->use_acpi_hotplug_bridge); |
b8622725 | 600 | |
16bcab97 IM |
601 | s->cpu_hotplug_legacy = true; |
602 | object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", | |
603 | piix4_get_cpu_hotplug_legacy, | |
d2623129 | 604 | piix4_set_cpu_hotplug_legacy); |
96e3e12b IM |
605 | legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, |
606 | PIIX4_CPU_HOTPLUG_IO_BASE); | |
34774320 IM |
607 | |
608 | if (s->acpi_memory_hotplug.is_enabled) { | |
80db0e78 IM |
609 | acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug, |
610 | ACPI_MEMORY_HOTPLUG_BASE); | |
34774320 | 611 | } |
93d89f63 | 612 | } |
5fdae20c | 613 | |
43f50410 IM |
614 | static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) |
615 | { | |
616 | PIIX4PMState *s = PIIX4_PM(adev); | |
617 | ||
618 | acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); | |
76623d00 IM |
619 | if (!s->cpu_hotplug_legacy) { |
620 | acpi_cpu_ospm_status(&s->cpuhp_state, list); | |
621 | } | |
43f50410 IM |
622 | } |
623 | ||
eaf23bf7 IM |
624 | static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) |
625 | { | |
626 | PIIX4PMState *s = PIIX4_PM(adev); | |
627 | ||
628 | acpi_send_gpe_event(&s->ar, s->irq, ev); | |
629 | } | |
630 | ||
5fdae20c IM |
631 | static Property piix4_pm_properties[] = { |
632 | DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), | |
633 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), | |
634 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), | |
635 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), | |
636 | DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, | |
0affda04 | 637 | use_acpi_hotplug_bridge, true), |
34774320 IM |
638 | DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, |
639 | acpi_memory_hotplug.is_enabled, true), | |
5fdae20c IM |
640 | DEFINE_PROP_END_OF_LIST(), |
641 | }; | |
642 | ||
643 | static void piix4_pm_class_init(ObjectClass *klass, void *data) | |
644 | { | |
645 | DeviceClass *dc = DEVICE_CLASS(klass); | |
646 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
c24d5e0b | 647 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); |
43f50410 | 648 | AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); |
5fdae20c | 649 | |
9af21dbe | 650 | k->realize = piix4_pm_realize; |
5fdae20c IM |
651 | k->config_write = pm_write_config; |
652 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
653 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; | |
654 | k->revision = 0x03; | |
655 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
217e8ef9 | 656 | dc->reset = piix4_pm_reset; |
5fdae20c IM |
657 | dc->desc = "PM"; |
658 | dc->vmsd = &vmstate_acpi; | |
4f67d30b | 659 | device_class_set_props(dc, piix4_pm_properties); |
5fdae20c IM |
660 | /* |
661 | * Reason: part of PIIX4 southbridge, needs to be wired up, | |
662 | * e.g. by mips_malta_init() | |
663 | */ | |
e90f2a8c | 664 | dc->user_creatable = false; |
2897ae02 | 665 | dc->hotpluggable = false; |
ec266f40 | 666 | hc->pre_plug = piix4_device_pre_plug_cb; |
f1adc360 | 667 | hc->plug = piix4_device_plug_cb; |
14d5a28f | 668 | hc->unplug_request = piix4_device_unplug_request_cb; |
c0e57a60 | 669 | hc->unplug = piix4_device_unplug_cb; |
43f50410 | 670 | adevc->ospm_status = piix4_ospm_status; |
eaf23bf7 | 671 | adevc->send_event = piix4_send_gpe; |
ac35f13b | 672 | adevc->madt_cpu = pc_madt_cpu_entry; |
5fdae20c IM |
673 | } |
674 | ||
675 | static const TypeInfo piix4_pm_info = { | |
676 | .name = TYPE_PIIX4_PM, | |
677 | .parent = TYPE_PCI_DEVICE, | |
678 | .instance_size = sizeof(PIIX4PMState), | |
679 | .class_init = piix4_pm_class_init, | |
c24d5e0b IM |
680 | .interfaces = (InterfaceInfo[]) { |
681 | { TYPE_HOTPLUG_HANDLER }, | |
43f50410 | 682 | { TYPE_ACPI_DEVICE_IF }, |
fd3b02c8 | 683 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
c24d5e0b IM |
684 | { } |
685 | } | |
5fdae20c IM |
686 | }; |
687 | ||
688 | static void piix4_pm_register_types(void) | |
689 | { | |
690 | type_register_static(&piix4_pm_info); | |
691 | } | |
692 | ||
693 | type_init(piix4_pm_register_types) |