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Commit | Line | Data |
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93d89f63 IY |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This library is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * Lesser General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU Lesser General Public | |
16 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
17 | */ | |
18 | #include "hw.h" | |
19 | #include "pc.h" | |
20 | #include "apm.h" | |
21 | #include "pm_smbus.h" | |
22 | #include "pci.h" | |
93d89f63 | 23 | #include "acpi.h" |
666daa68 | 24 | #include "sysemu.h" |
bf1b0071 | 25 | #include "range.h" |
93d89f63 IY |
26 | |
27 | //#define DEBUG | |
28 | ||
50d8ff8b IY |
29 | #ifdef DEBUG |
30 | # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
31 | #else | |
32 | # define PIIX4_DPRINTF(format, ...) do { } while (0) | |
33 | #endif | |
34 | ||
93d89f63 IY |
35 | #define ACPI_DBG_IO_ADDR 0xb044 |
36 | ||
ac404095 IY |
37 | #define GPE_BASE 0xafe0 |
38 | #define PCI_BASE 0xae00 | |
39 | #define PCI_EJ_BASE 0xae08 | |
668643b0 | 40 | #define PCI_RMV_BASE 0xae0c |
ac404095 | 41 | |
4441a287 GN |
42 | #define PIIX4_PCI_HOTPLUG_STATUS 2 |
43 | ||
ac404095 IY |
44 | struct gpe_regs { |
45 | uint16_t sts; /* status */ | |
46 | uint16_t en; /* enabled */ | |
47 | }; | |
48 | ||
49 | struct pci_status { | |
50 | uint32_t up; | |
51 | uint32_t down; | |
52 | }; | |
53 | ||
93d89f63 IY |
54 | typedef struct PIIX4PMState { |
55 | PCIDevice dev; | |
2871a3f6 | 56 | IORange ioport; |
04dc308f | 57 | ACPIPM1EVT pm1a; |
93d89f63 IY |
58 | uint16_t pmcntrl; |
59 | ||
60 | APMState apm; | |
61 | ||
a54d41a8 | 62 | ACPIPMTimer tmr; |
93d89f63 IY |
63 | |
64 | PMSMBus smb; | |
e8ec0571 | 65 | uint32_t smb_io_base; |
93d89f63 IY |
66 | |
67 | qemu_irq irq; | |
68 | qemu_irq cmos_s3; | |
69 | qemu_irq smi_irq; | |
70 | int kvm_enabled; | |
ac404095 IY |
71 | |
72 | /* for pci hotplug */ | |
73 | struct gpe_regs gpe; | |
74 | struct pci_status pci0_status; | |
668643b0 | 75 | uint32_t pci0_hotplug_enable; |
93d89f63 IY |
76 | } PIIX4PMState; |
77 | ||
ac404095 IY |
78 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s); |
79 | ||
93d89f63 IY |
80 | #define ACPI_ENABLE 0xf1 |
81 | #define ACPI_DISABLE 0xf0 | |
82 | ||
93d89f63 IY |
83 | static void pm_update_sci(PIIX4PMState *s) |
84 | { | |
85 | int sci_level, pmsts; | |
93d89f63 | 86 | |
04dc308f IY |
87 | pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time); |
88 | sci_level = (((pmsts & s->pm1a.en) & | |
93d89f63 IY |
89 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
90 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
91 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
633aa0ac GN |
92 | ACPI_BITMASK_TIMER_ENABLE)) != 0) || |
93 | (((s->gpe.sts & s->gpe.en) & PIIX4_PCI_HOTPLUG_STATUS) != 0); | |
94 | ||
93d89f63 IY |
95 | qemu_set_irq(s->irq, sci_level); |
96 | /* schedule a timer interruption if needed */ | |
04dc308f | 97 | acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 98 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
93d89f63 IY |
99 | } |
100 | ||
a54d41a8 | 101 | static void pm_tmr_timer(ACPIPMTimer *tmr) |
93d89f63 | 102 | { |
a54d41a8 | 103 | PIIX4PMState *s = container_of(tmr, PIIX4PMState, tmr); |
93d89f63 IY |
104 | pm_update_sci(s); |
105 | } | |
106 | ||
2871a3f6 AK |
107 | static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width, |
108 | uint64_t val) | |
93d89f63 | 109 | { |
2871a3f6 AK |
110 | PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); |
111 | ||
112 | if (width != 2) { | |
113 | PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n", | |
114 | (unsigned)addr, width, (unsigned)val); | |
115 | } | |
116 | ||
93d89f63 IY |
117 | switch(addr) { |
118 | case 0x00: | |
04dc308f IY |
119 | acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val); |
120 | pm_update_sci(s); | |
93d89f63 IY |
121 | break; |
122 | case 0x02: | |
04dc308f | 123 | s->pm1a.en = val; |
93d89f63 IY |
124 | pm_update_sci(s); |
125 | break; | |
126 | case 0x04: | |
127 | { | |
128 | int sus_typ; | |
129 | s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE); | |
130 | if (val & ACPI_BITMASK_SLEEP_ENABLE) { | |
131 | /* change suspend type */ | |
132 | sus_typ = (val >> 10) & 7; | |
133 | switch(sus_typ) { | |
134 | case 0: /* soft power off */ | |
135 | qemu_system_shutdown_request(); | |
136 | break; | |
137 | case 1: | |
138 | /* ACPI_BITMASK_WAKE_STATUS should be set on resume. | |
139 | Pretend that resume was caused by power button */ | |
04dc308f IY |
140 | s->pm1a.sts |= (ACPI_BITMASK_WAKE_STATUS | |
141 | ACPI_BITMASK_POWER_BUTTON_STATUS); | |
93d89f63 IY |
142 | qemu_system_reset_request(); |
143 | if (s->cmos_s3) { | |
144 | qemu_irq_raise(s->cmos_s3); | |
145 | } | |
146 | default: | |
147 | break; | |
148 | } | |
149 | } | |
150 | } | |
151 | break; | |
152 | default: | |
153 | break; | |
154 | } | |
59df4c11 WC |
155 | PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr, |
156 | (unsigned int)val); | |
93d89f63 IY |
157 | } |
158 | ||
2871a3f6 AK |
159 | static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width, |
160 | uint64_t *data) | |
93d89f63 | 161 | { |
2871a3f6 | 162 | PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); |
93d89f63 IY |
163 | uint32_t val; |
164 | ||
93d89f63 IY |
165 | switch(addr) { |
166 | case 0x00: | |
04dc308f | 167 | val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time); |
93d89f63 IY |
168 | break; |
169 | case 0x02: | |
04dc308f | 170 | val = s->pm1a.en; |
93d89f63 IY |
171 | break; |
172 | case 0x04: | |
173 | val = s->pmcntrl; | |
174 | break; | |
93d89f63 | 175 | case 0x08: |
a54d41a8 | 176 | val = acpi_pm_tmr_get(&s->tmr); |
93d89f63 IY |
177 | break; |
178 | default: | |
179 | val = 0; | |
180 | break; | |
181 | } | |
59df4c11 | 182 | PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val); |
2871a3f6 | 183 | *data = val; |
93d89f63 IY |
184 | } |
185 | ||
2871a3f6 AK |
186 | static const IORangeOps pm_iorange_ops = { |
187 | .read = pm_ioport_read, | |
188 | .write = pm_ioport_write, | |
189 | }; | |
190 | ||
93d89f63 IY |
191 | static void apm_ctrl_changed(uint32_t val, void *arg) |
192 | { | |
193 | PIIX4PMState *s = arg; | |
194 | ||
195 | /* ACPI specs 3.0, 4.7.2.5 */ | |
196 | if (val == ACPI_ENABLE) { | |
197 | s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE; | |
198 | } else if (val == ACPI_DISABLE) { | |
199 | s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE; | |
200 | } | |
201 | ||
202 | if (s->dev.config[0x5b] & (1 << 1)) { | |
203 | if (s->smi_irq) { | |
204 | qemu_irq_raise(s->smi_irq); | |
205 | } | |
206 | } | |
207 | } | |
208 | ||
209 | static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) | |
210 | { | |
50d8ff8b | 211 | PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val); |
93d89f63 IY |
212 | } |
213 | ||
214 | static void pm_io_space_update(PIIX4PMState *s) | |
215 | { | |
216 | uint32_t pm_io_base; | |
217 | ||
218 | if (s->dev.config[0x80] & 1) { | |
219 | pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40)); | |
220 | pm_io_base &= 0xffc0; | |
221 | ||
222 | /* XXX: need to improve memory and ioport allocation */ | |
50d8ff8b | 223 | PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base); |
2871a3f6 AK |
224 | iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64); |
225 | ioport_register(&s->ioport); | |
93d89f63 IY |
226 | } |
227 | } | |
228 | ||
229 | static void pm_write_config(PCIDevice *d, | |
230 | uint32_t address, uint32_t val, int len) | |
231 | { | |
232 | pci_default_write_config(d, address, val, len); | |
233 | if (range_covers_byte(address, len, 0x80)) | |
234 | pm_io_space_update((PIIX4PMState *)d); | |
235 | } | |
236 | ||
237 | static int vmstate_acpi_post_load(void *opaque, int version_id) | |
238 | { | |
239 | PIIX4PMState *s = opaque; | |
240 | ||
241 | pm_io_space_update(s); | |
242 | return 0; | |
243 | } | |
244 | ||
4cf3e6f3 AW |
245 | static const VMStateDescription vmstate_gpe = { |
246 | .name = "gpe", | |
247 | .version_id = 1, | |
248 | .minimum_version_id = 1, | |
249 | .minimum_version_id_old = 1, | |
250 | .fields = (VMStateField []) { | |
251 | VMSTATE_UINT16(sts, struct gpe_regs), | |
252 | VMSTATE_UINT16(en, struct gpe_regs), | |
253 | VMSTATE_END_OF_LIST() | |
254 | } | |
255 | }; | |
256 | ||
257 | static const VMStateDescription vmstate_pci_status = { | |
258 | .name = "pci_status", | |
259 | .version_id = 1, | |
260 | .minimum_version_id = 1, | |
261 | .minimum_version_id_old = 1, | |
262 | .fields = (VMStateField []) { | |
263 | VMSTATE_UINT32(up, struct pci_status), | |
264 | VMSTATE_UINT32(down, struct pci_status), | |
265 | VMSTATE_END_OF_LIST() | |
266 | } | |
267 | }; | |
268 | ||
93d89f63 IY |
269 | static const VMStateDescription vmstate_acpi = { |
270 | .name = "piix4_pm", | |
4cf3e6f3 | 271 | .version_id = 2, |
93d89f63 IY |
272 | .minimum_version_id = 1, |
273 | .minimum_version_id_old = 1, | |
274 | .post_load = vmstate_acpi_post_load, | |
275 | .fields = (VMStateField []) { | |
276 | VMSTATE_PCI_DEVICE(dev, PIIX4PMState), | |
04dc308f IY |
277 | VMSTATE_UINT16(pm1a.sts, PIIX4PMState), |
278 | VMSTATE_UINT16(pm1a.en, PIIX4PMState), | |
93d89f63 IY |
279 | VMSTATE_UINT16(pmcntrl, PIIX4PMState), |
280 | VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), | |
a54d41a8 IY |
281 | VMSTATE_TIMER(tmr.timer, PIIX4PMState), |
282 | VMSTATE_INT64(tmr.overflow_time, PIIX4PMState), | |
4cf3e6f3 AW |
283 | VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, struct gpe_regs), |
284 | VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status, | |
285 | struct pci_status), | |
93d89f63 IY |
286 | VMSTATE_END_OF_LIST() |
287 | } | |
288 | }; | |
289 | ||
668643b0 MT |
290 | static void piix4_update_hotplug(PIIX4PMState *s) |
291 | { | |
292 | PCIDevice *dev = &s->dev; | |
293 | BusState *bus = qdev_get_parent_bus(&dev->qdev); | |
294 | DeviceState *qdev, *next; | |
295 | ||
296 | s->pci0_hotplug_enable = ~0; | |
297 | ||
298 | QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) { | |
299 | PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev); | |
300 | PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, qdev); | |
301 | int slot = PCI_SLOT(pdev->devfn); | |
302 | ||
303 | if (info->no_hotplug) { | |
304 | s->pci0_hotplug_enable &= ~(1 << slot); | |
305 | } | |
306 | } | |
307 | } | |
308 | ||
93d89f63 IY |
309 | static void piix4_reset(void *opaque) |
310 | { | |
311 | PIIX4PMState *s = opaque; | |
312 | uint8_t *pci_conf = s->dev.config; | |
313 | ||
314 | pci_conf[0x58] = 0; | |
315 | pci_conf[0x59] = 0; | |
316 | pci_conf[0x5a] = 0; | |
317 | pci_conf[0x5b] = 0; | |
318 | ||
319 | if (s->kvm_enabled) { | |
320 | /* Mark SMM as already inited (until KVM supports SMM). */ | |
321 | pci_conf[0x5B] = 0x02; | |
322 | } | |
668643b0 | 323 | piix4_update_hotplug(s); |
93d89f63 IY |
324 | } |
325 | ||
326 | static void piix4_powerdown(void *opaque, int irq, int power_failing) | |
327 | { | |
328 | PIIX4PMState *s = opaque; | |
04dc308f IY |
329 | ACPIPM1EVT *pm1a = s? &s->pm1a: NULL; |
330 | ACPIPMTimer *tmr = s? &s->tmr: NULL; | |
93d89f63 | 331 | |
04dc308f | 332 | acpi_pm1_evt_power_down(pm1a, tmr); |
93d89f63 IY |
333 | } |
334 | ||
e8ec0571 | 335 | static int piix4_pm_initfn(PCIDevice *dev) |
93d89f63 | 336 | { |
e8ec0571 | 337 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 IY |
338 | uint8_t *pci_conf; |
339 | ||
93d89f63 IY |
340 | pci_conf = s->dev.config; |
341 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); | |
342 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3); | |
343 | pci_conf[0x06] = 0x80; | |
344 | pci_conf[0x07] = 0x02; | |
345 | pci_conf[0x08] = 0x03; // revision number | |
346 | pci_conf[0x09] = 0x00; | |
347 | pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER); | |
93d89f63 IY |
348 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
349 | ||
350 | pci_conf[0x40] = 0x01; /* PM io base read only bit */ | |
351 | ||
352 | /* APM */ | |
353 | apm_init(&s->apm, apm_ctrl_changed, s); | |
354 | ||
355 | register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); | |
356 | ||
93d89f63 IY |
357 | if (s->kvm_enabled) { |
358 | /* Mark SMM as already inited to prevent SMM from running. KVM does not | |
359 | * support SMM mode. */ | |
360 | pci_conf[0x5B] = 0x02; | |
361 | } | |
362 | ||
363 | /* XXX: which specification is used ? The i82731AB has different | |
364 | mappings */ | |
365 | pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10; | |
366 | pci_conf[0x63] = 0x60; | |
367 | pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) | | |
368 | (serial_hds[1] != NULL ? 0x90 : 0); | |
369 | ||
e8ec0571 IY |
370 | pci_conf[0x90] = s->smb_io_base | 1; |
371 | pci_conf[0x91] = s->smb_io_base >> 8; | |
93d89f63 | 372 | pci_conf[0xd2] = 0x09; |
e8ec0571 IY |
373 | register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb); |
374 | register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb); | |
93d89f63 | 375 | |
a54d41a8 | 376 | acpi_pm_tmr_init(&s->tmr, pm_tmr_timer); |
93d89f63 IY |
377 | |
378 | qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1); | |
379 | ||
e8ec0571 IY |
380 | pm_smbus_init(&s->dev.qdev, &s->smb); |
381 | qemu_register_reset(piix4_reset, s); | |
ac404095 | 382 | piix4_acpi_system_hot_add_init(dev->bus, s); |
e8ec0571 IY |
383 | |
384 | return 0; | |
385 | } | |
386 | ||
387 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, | |
388 | qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq, | |
389 | int kvm_enabled) | |
390 | { | |
391 | PCIDevice *dev; | |
392 | PIIX4PMState *s; | |
393 | ||
394 | dev = pci_create(bus, devfn, "PIIX4_PM"); | |
395 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); | |
93d89f63 | 396 | |
e8ec0571 | 397 | s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 IY |
398 | s->irq = sci_irq; |
399 | s->cmos_s3 = cmos_s3; | |
400 | s->smi_irq = smi_irq; | |
e8ec0571 IY |
401 | s->kvm_enabled = kvm_enabled; |
402 | ||
403 | qdev_init_nofail(&dev->qdev); | |
93d89f63 IY |
404 | |
405 | return s->smb.smbus; | |
406 | } | |
407 | ||
e8ec0571 IY |
408 | static PCIDeviceInfo piix4_pm_info = { |
409 | .qdev.name = "PIIX4_PM", | |
410 | .qdev.desc = "PM", | |
411 | .qdev.size = sizeof(PIIX4PMState), | |
412 | .qdev.vmsd = &vmstate_acpi, | |
0965f12d GH |
413 | .qdev.no_user = 1, |
414 | .no_hotplug = 1, | |
e8ec0571 IY |
415 | .init = piix4_pm_initfn, |
416 | .config_write = pm_write_config, | |
417 | .qdev.props = (Property[]) { | |
418 | DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), | |
419 | DEFINE_PROP_END_OF_LIST(), | |
420 | } | |
421 | }; | |
422 | ||
423 | static void piix4_pm_register(void) | |
424 | { | |
425 | pci_qdev_register(&piix4_pm_info); | |
426 | } | |
427 | ||
428 | device_init(piix4_pm_register); | |
429 | ||
93d89f63 IY |
430 | static uint32_t gpe_read_val(uint16_t val, uint32_t addr) |
431 | { | |
432 | if (addr & 1) | |
433 | return (val >> 8) & 0xff; | |
434 | return val & 0xff; | |
435 | } | |
436 | ||
437 | static uint32_t gpe_readb(void *opaque, uint32_t addr) | |
438 | { | |
439 | uint32_t val = 0; | |
633aa0ac GN |
440 | PIIX4PMState *s = opaque; |
441 | struct gpe_regs *g = &s->gpe; | |
442 | ||
93d89f63 IY |
443 | switch (addr) { |
444 | case GPE_BASE: | |
445 | case GPE_BASE + 1: | |
446 | val = gpe_read_val(g->sts, addr); | |
447 | break; | |
448 | case GPE_BASE + 2: | |
449 | case GPE_BASE + 3: | |
450 | val = gpe_read_val(g->en, addr); | |
451 | break; | |
452 | default: | |
453 | break; | |
454 | } | |
455 | ||
50d8ff8b | 456 | PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); |
93d89f63 IY |
457 | return val; |
458 | } | |
459 | ||
460 | static void gpe_write_val(uint16_t *cur, int addr, uint32_t val) | |
461 | { | |
462 | if (addr & 1) | |
463 | *cur = (*cur & 0xff) | (val << 8); | |
464 | else | |
465 | *cur = (*cur & 0xff00) | (val & 0xff); | |
466 | } | |
467 | ||
468 | static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val) | |
469 | { | |
470 | uint16_t x1, x0 = val & 0xff; | |
471 | int shift = (addr & 1) ? 8 : 0; | |
472 | ||
473 | x1 = (*cur >> shift) & 0xff; | |
474 | ||
475 | x1 = x1 & ~x0; | |
476 | ||
477 | *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift); | |
478 | } | |
479 | ||
480 | static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) | |
481 | { | |
633aa0ac GN |
482 | PIIX4PMState *s = opaque; |
483 | struct gpe_regs *g = &s->gpe; | |
484 | ||
93d89f63 IY |
485 | switch (addr) { |
486 | case GPE_BASE: | |
487 | case GPE_BASE + 1: | |
488 | gpe_reset_val(&g->sts, addr, val); | |
489 | break; | |
490 | case GPE_BASE + 2: | |
491 | case GPE_BASE + 3: | |
492 | gpe_write_val(&g->en, addr, val); | |
493 | break; | |
494 | default: | |
495 | break; | |
633aa0ac GN |
496 | } |
497 | ||
498 | pm_update_sci(s); | |
93d89f63 | 499 | |
50d8ff8b | 500 | PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); |
93d89f63 IY |
501 | } |
502 | ||
503 | static uint32_t pcihotplug_read(void *opaque, uint32_t addr) | |
504 | { | |
505 | uint32_t val = 0; | |
506 | struct pci_status *g = opaque; | |
507 | switch (addr) { | |
508 | case PCI_BASE: | |
509 | val = g->up; | |
510 | break; | |
511 | case PCI_BASE + 4: | |
512 | val = g->down; | |
513 | break; | |
514 | default: | |
515 | break; | |
516 | } | |
517 | ||
50d8ff8b | 518 | PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val); |
93d89f63 IY |
519 | return val; |
520 | } | |
521 | ||
522 | static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val) | |
523 | { | |
524 | struct pci_status *g = opaque; | |
525 | switch (addr) { | |
526 | case PCI_BASE: | |
527 | g->up = val; | |
528 | break; | |
529 | case PCI_BASE + 4: | |
530 | g->down = val; | |
531 | break; | |
532 | } | |
533 | ||
50d8ff8b | 534 | PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val); |
93d89f63 IY |
535 | } |
536 | ||
537 | static uint32_t pciej_read(void *opaque, uint32_t addr) | |
538 | { | |
50d8ff8b | 539 | PIIX4_DPRINTF("pciej read %x\n", addr); |
93d89f63 IY |
540 | return 0; |
541 | } | |
542 | ||
543 | static void pciej_write(void *opaque, uint32_t addr, uint32_t val) | |
544 | { | |
545 | BusState *bus = opaque; | |
546 | DeviceState *qdev, *next; | |
547 | PCIDevice *dev; | |
548 | int slot = ffs(val) - 1; | |
549 | ||
550 | QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) { | |
551 | dev = DO_UPCAST(PCIDevice, qdev, qdev); | |
552 | if (PCI_SLOT(dev->devfn) == slot) { | |
553 | qdev_free(qdev); | |
554 | } | |
555 | } | |
556 | ||
557 | ||
50d8ff8b | 558 | PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val); |
93d89f63 IY |
559 | } |
560 | ||
668643b0 MT |
561 | static uint32_t pcirmv_read(void *opaque, uint32_t addr) |
562 | { | |
563 | PIIX4PMState *s = opaque; | |
564 | ||
565 | return s->pci0_hotplug_enable; | |
566 | } | |
567 | ||
568 | static void pcirmv_write(void *opaque, uint32_t addr, uint32_t val) | |
569 | { | |
570 | return; | |
571 | } | |
572 | ||
4cff0a59 MT |
573 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
574 | PCIHotplugState state); | |
93d89f63 | 575 | |
ac404095 | 576 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) |
93d89f63 | 577 | { |
ac404095 | 578 | struct pci_status *pci0_status = &s->pci0_status; |
93d89f63 | 579 | |
633aa0ac GN |
580 | register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, s); |
581 | register_ioport_read(GPE_BASE, 4, 1, gpe_readb, s); | |
ac404095 IY |
582 | |
583 | register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status); | |
584 | register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, pci0_status); | |
93d89f63 IY |
585 | |
586 | register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus); | |
587 | register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, bus); | |
588 | ||
668643b0 MT |
589 | register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s); |
590 | register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s); | |
591 | ||
ac404095 | 592 | pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); |
93d89f63 IY |
593 | } |
594 | ||
ac404095 | 595 | static void enable_device(PIIX4PMState *s, int slot) |
93d89f63 | 596 | { |
4441a287 | 597 | s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS; |
ac404095 | 598 | s->pci0_status.up |= (1 << slot); |
93d89f63 IY |
599 | } |
600 | ||
ac404095 | 601 | static void disable_device(PIIX4PMState *s, int slot) |
93d89f63 | 602 | { |
4441a287 | 603 | s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS; |
ac404095 | 604 | s->pci0_status.down |= (1 << slot); |
93d89f63 IY |
605 | } |
606 | ||
4cff0a59 MT |
607 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
608 | PCIHotplugState state) | |
93d89f63 IY |
609 | { |
610 | int slot = PCI_SLOT(dev->devfn); | |
ac404095 IY |
611 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, |
612 | DO_UPCAST(PCIDevice, qdev, qdev)); | |
93d89f63 | 613 | |
4cff0a59 MT |
614 | /* Don't send event when device is enabled during qemu machine creation: |
615 | * it is present on boot, no hotplug event is necessary. We do send an | |
616 | * event when the device is disabled later. */ | |
617 | if (state == PCI_COLDPLUG_ENABLED) { | |
5beb8ad5 | 618 | return 0; |
4cff0a59 | 619 | } |
5beb8ad5 | 620 | |
ac404095 IY |
621 | s->pci0_status.up = 0; |
622 | s->pci0_status.down = 0; | |
4cff0a59 | 623 | if (state == PCI_HOTPLUG_ENABLED) { |
ac404095 IY |
624 | enable_device(s, slot); |
625 | } else { | |
626 | disable_device(s, slot); | |
627 | } | |
633aa0ac GN |
628 | |
629 | pm_update_sci(s); | |
630 | ||
93d89f63 IY |
631 | return 0; |
632 | } |