[qemu.git] / hw / acpi_piix4.c

/*
 * ACPI implementation
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License version 2 as published by the Free Software Foundation.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>
 */
#include "hw.h"
#include "pc.h"
#include "apm.h"
#include "pm_smbus.h"
#include "pci.h"
#include "acpi.h"

//#define DEBUG

#ifdef DEBUG
# define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
#else
# define PIIX4_DPRINTF(format, ...)     do { } while (0)
#endif

#define ACPI_DBG_IO_ADDR  0xb044

#define GPE_BASE 0xafe0
#define PCI_BASE 0xae00
#define PCI_EJ_BASE 0xae08

struct gpe_regs {
    uint16_t sts; /* status */
    uint16_t en;  /* enabled */
};

struct pci_status {
    uint32_t up;
    uint32_t down;
};

typedef struct PIIX4PMState {
    PCIDevice dev;
    uint16_t pmsts;
    uint16_t pmen;
    uint16_t pmcntrl;

    APMState apm;

    QEMUTimer *tmr_timer;
    int64_t tmr_overflow_time;

    PMSMBus smb;
    uint32_t smb_io_base;

    qemu_irq irq;
    qemu_irq cmos_s3;
    qemu_irq smi_irq;
    int kvm_enabled;

    /* for pci hotplug */
    struct gpe_regs gpe;
    struct pci_status pci0_status;
} PIIX4PMState;

static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);

#define ACPI_ENABLE 0xf1
#define ACPI_DISABLE 0xf0

static uint32_t get_pmtmr(PIIX4PMState *s)
{
    uint32_t d;
    d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
    return d & 0xffffff;
}

static int get_pmsts(PIIX4PMState *s)
{
    int64_t d;

    d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
                 get_ticks_per_sec());
    if (d >= s->tmr_overflow_time)
        s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
    return s->pmsts;
}

static void pm_update_sci(PIIX4PMState *s)
{
    int sci_level, pmsts;
    int64_t expire_time;

    pmsts = get_pmsts(s);
    sci_level = (((pmsts & s->pmen) &
                  (ACPI_BITMASK_RT_CLOCK_ENABLE |
                   ACPI_BITMASK_POWER_BUTTON_ENABLE |
                   ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
                   ACPI_BITMASK_TIMER_ENABLE)) != 0);
    qemu_set_irq(s->irq, sci_level);
    /* schedule a timer interruption if needed */
    if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
        !(pmsts & ACPI_BITMASK_TIMER_STATUS)) {
        expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(),
                               PM_TIMER_FREQUENCY);
        qemu_mod_timer(s->tmr_timer, expire_time);
    } else {
        qemu_del_timer(s->tmr_timer);
    }
}

static void pm_tmr_timer(void *opaque)
{
    PIIX4PMState *s = opaque;
    pm_update_sci(s);
}

static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
{
    PIIX4PMState *s = opaque;
    addr &= 0x3f;
    switch(addr) {
    case 0x00:
        {
            int64_t d;
            int pmsts;
            pmsts = get_pmsts(s);
            if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
                /* if TMRSTS is reset, then compute the new overflow time */
                d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
                             get_ticks_per_sec());
                s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
            }
            s->pmsts &= ~val;
            pm_update_sci(s);
        }
        break;
    case 0x02:
        s->pmen = val;
        pm_update_sci(s);
        break;
    case 0x04:
        {
            int sus_typ;
            s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
            if (val & ACPI_BITMASK_SLEEP_ENABLE) {
                /* change suspend type */
                sus_typ = (val >> 10) & 7;
                switch(sus_typ) {
                case 0: /* soft power off */
                    qemu_system_shutdown_request();
                    break;
                case 1:
                    /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
                       Pretend that resume was caused by power button */
                    s->pmsts |= (ACPI_BITMASK_WAKE_STATUS |
                                 ACPI_BITMASK_POWER_BUTTON_STATUS);
                    qemu_system_reset_request();
                    if (s->cmos_s3) {
                        qemu_irq_raise(s->cmos_s3);
                    }
                default:
                    break;
                }
            }
        }
        break;
    default:
        break;
    }
    PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr, val);
}

static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;
    uint32_t val;

    addr &= 0x3f;
    switch(addr) {
    case 0x00:
        val = get_pmsts(s);
        break;
    case 0x02:
        val = s->pmen;
        break;
    case 0x04:
        val = s->pmcntrl;
        break;
    default:
        val = 0;
        break;
    }
    PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val);
    return val;
}

static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
{
    //    PIIX4PMState *s = opaque;
    PIIX4_DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr & 0x3f, val);
}

static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;
    uint32_t val;

    addr &= 0x3f;
    switch(addr) {
    case 0x08:
        val = get_pmtmr(s);
        break;
    default:
        val = 0;
        break;
    }
    PIIX4_DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
    return val;
}

static void apm_ctrl_changed(uint32_t val, void *arg)
{
    PIIX4PMState *s = arg;

    /* ACPI specs 3.0, 4.7.2.5 */
    if (val == ACPI_ENABLE) {
        s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE;
    } else if (val == ACPI_DISABLE) {
        s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
    }

    if (s->dev.config[0x5b] & (1 << 1)) {
        if (s->smi_irq) {
            qemu_irq_raise(s->smi_irq);
        }
    }
}

static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
{
    PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
}

static void pm_io_space_update(PIIX4PMState *s)
{
    uint32_t pm_io_base;

    if (s->dev.config[0x80] & 1) {
        pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
        pm_io_base &= 0xffc0;

        /* XXX: need to improve memory and ioport allocation */
        PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
        register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
        register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
        register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
        register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
    }
}

static void pm_write_config(PCIDevice *d,
                            uint32_t address, uint32_t val, int len)
{
    pci_default_write_config(d, address, val, len);
    if (range_covers_byte(address, len, 0x80))
        pm_io_space_update((PIIX4PMState *)d);
}

static int vmstate_acpi_post_load(void *opaque, int version_id)
{
    PIIX4PMState *s = opaque;

    pm_io_space_update(s);
    return 0;
}

static const VMStateDescription vmstate_acpi = {
    .name = "piix4_pm",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .post_load = vmstate_acpi_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
        VMSTATE_UINT16(pmsts, PIIX4PMState),
        VMSTATE_UINT16(pmen, PIIX4PMState),
        VMSTATE_UINT16(pmcntrl, PIIX4PMState),
        VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
        VMSTATE_TIMER(tmr_timer, PIIX4PMState),
        VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
        VMSTATE_END_OF_LIST()
    }
};

static void piix4_reset(void *opaque)
{
    PIIX4PMState *s = opaque;
    uint8_t *pci_conf = s->dev.config;

    pci_conf[0x58] = 0;
    pci_conf[0x59] = 0;
    pci_conf[0x5a] = 0;
    pci_conf[0x5b] = 0;

    if (s->kvm_enabled) {
        /* Mark SMM as already inited (until KVM supports SMM). */
        pci_conf[0x5B] = 0x02;
    }
}

static void piix4_powerdown(void *opaque, int irq, int power_failing)
{
    PIIX4PMState *s = opaque;

    if (!s) {
        qemu_system_shutdown_request();
    } else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
        s->pmsts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
        pm_update_sci(s);
    }
}

static int piix4_pm_initfn(PCIDevice *dev)
{
    PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
    uint8_t *pci_conf;

    pci_conf = s->dev.config;
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
    pci_conf[0x06] = 0x80;
    pci_conf[0x07] = 0x02;
    pci_conf[0x08] = 0x03; // revision number
    pci_conf[0x09] = 0x00;
    pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
    pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
    pci_conf[0x3d] = 0x01; // interrupt pin 1

    pci_conf[0x40] = 0x01; /* PM io base read only bit */

    /* APM */
    apm_init(&s->apm, apm_ctrl_changed, s);

    register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);

    if (s->kvm_enabled) {
        /* Mark SMM as already inited to prevent SMM from running.  KVM does not
         * support SMM mode. */
        pci_conf[0x5B] = 0x02;
    }

    /* XXX: which specification is used ? The i82731AB has different
       mappings */
    pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
    pci_conf[0x63] = 0x60;
    pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
	(serial_hds[1] != NULL ? 0x90 : 0);

    pci_conf[0x90] = s->smb_io_base | 1;
    pci_conf[0x91] = s->smb_io_base >> 8;
    pci_conf[0xd2] = 0x09;
    register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
    register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);

    s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);

    qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);

    pm_smbus_init(&s->dev.qdev, &s->smb);
    qemu_register_reset(piix4_reset, s);
    piix4_acpi_system_hot_add_init(dev->bus, s);

    return 0;
}

i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
                       int kvm_enabled)
{
    PCIDevice *dev;
    PIIX4PMState *s;

    dev = pci_create(bus, devfn, "PIIX4_PM");
    qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);

    s = DO_UPCAST(PIIX4PMState, dev, dev);
    s->irq = sci_irq;
    s->cmos_s3 = cmos_s3;
    s->smi_irq = smi_irq;
    s->kvm_enabled = kvm_enabled;

    qdev_init_nofail(&dev->qdev);

    return s->smb.smbus;
}

static PCIDeviceInfo piix4_pm_info = {
    .qdev.name          = "PIIX4_PM",
    .qdev.desc          = "PM",
    .qdev.size          = sizeof(PIIX4PMState),
    .qdev.vmsd          = &vmstate_acpi,
    .init               = piix4_pm_initfn,
    .config_write       = pm_write_config,
    .qdev.props         = (Property[]) {
        DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void piix4_pm_register(void)
{
    pci_qdev_register(&piix4_pm_info);
}

device_init(piix4_pm_register);

static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
{
    if (addr & 1)
        return (val >> 8) & 0xff;
    return val & 0xff;
}

static uint32_t gpe_readb(void *opaque, uint32_t addr)
{
    uint32_t val = 0;
    struct gpe_regs *g = opaque;
    switch (addr) {
        case GPE_BASE:
        case GPE_BASE + 1:
            val = gpe_read_val(g->sts, addr);
            break;
        case GPE_BASE + 2:
        case GPE_BASE + 3:
            val = gpe_read_val(g->en, addr);
            break;
        default:
            break;
    }

    PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
    return val;
}

static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
{
    if (addr & 1)
        *cur = (*cur & 0xff) | (val << 8);
    else
        *cur = (*cur & 0xff00) | (val & 0xff);
}

static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
{
    uint16_t x1, x0 = val & 0xff;
    int shift = (addr & 1) ? 8 : 0;

    x1 = (*cur >> shift) & 0xff;

    x1 = x1 & ~x0;

    *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
}

static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    struct gpe_regs *g = opaque;
    switch (addr) {
        case GPE_BASE:
        case GPE_BASE + 1:
            gpe_reset_val(&g->sts, addr, val);
            break;
        case GPE_BASE + 2:
        case GPE_BASE + 3:
            gpe_write_val(&g->en, addr, val);
            break;
        default:
            break;
   }

    PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
}

static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
{
    uint32_t val = 0;
    struct pci_status *g = opaque;
    switch (addr) {
        case PCI_BASE:
            val = g->up;
            break;
        case PCI_BASE + 4:
            val = g->down;
            break;
        default:
            break;
    }

    PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
    return val;
}

static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
{
    struct pci_status *g = opaque;
    switch (addr) {
        case PCI_BASE:
            g->up = val;
            break;
        case PCI_BASE + 4:
            g->down = val;
            break;
   }

    PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
}

static uint32_t pciej_read(void *opaque, uint32_t addr)
{
    PIIX4_DPRINTF("pciej read %x\n", addr);
    return 0;
}

static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
{
    BusState *bus = opaque;
    DeviceState *qdev, *next;
    PCIDevice *dev;
    int slot = ffs(val) - 1;

    QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
        dev = DO_UPCAST(PCIDevice, qdev, qdev);
        if (PCI_SLOT(dev->devfn) == slot) {
            qdev_free(qdev);
        }
    }


    PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
}

static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state);

static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
{
    struct gpe_regs *gpe = &s->gpe;
    struct pci_status *pci0_status = &s->pci0_status;

    register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, gpe);
    register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, gpe);

    register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
    register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);

    register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
    register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);

    pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
}

static void enable_device(PIIX4PMState *s, int slot)
{
    s->gpe.sts |= 2;
    s->pci0_status.up |= (1 << slot);
}

static void disable_device(PIIX4PMState *s, int slot)
{
    s->gpe.sts |= 2;
    s->pci0_status.down |= (1 << slot);
}

static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state)
{
    int slot = PCI_SLOT(dev->devfn);
    PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
                                DO_UPCAST(PCIDevice, qdev, qdev));

    s->pci0_status.up = 0;
    s->pci0_status.down = 0;
    if (state) {
        enable_device(s, slot);
    } else {
        disable_device(s, slot);
    }
    if (s->gpe.en & 2) {
        qemu_set_irq(s->irq, 1);
        qemu_set_irq(s->irq, 0);
    }
    return 0;
}
Commit	Line	Data
93d89f63 IY	1	/*
	2	* ACPI implementation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License version 2 as published by the Free Software Foundation.
	9	*
	10	* This library is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* Lesser General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU Lesser General Public
	16	* License along with this library; if not, see <http://www.gnu.org/licenses/>
	17	*/
	18	#include "hw.h"
	19	#include "pc.h"
	20	#include "apm.h"
	21	#include "pm_smbus.h"
	22	#include "pci.h"
93d89f63 IY	23	#include "acpi.h"
	24
	25	//#define DEBUG
	26
50d8ff8b IY	27	#ifdef DEBUG
	28	# define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
	29	#else
	30	# define PIIX4_DPRINTF(format, ...) do { } while (0)
	31	#endif
	32
93d89f63 IY	33	#define ACPI_DBG_IO_ADDR 0xb044
93d89f63 IY	34
ac404095 IY	35	#define GPE_BASE 0xafe0
	36	#define PCI_BASE 0xae00
	37	#define PCI_EJ_BASE 0xae08
	38
	39	struct gpe_regs {
	40	uint16_t sts; /* status */
	41	uint16_t en; /* enabled */
	42	};
	43
	44	struct pci_status {
	45	uint32_t up;
	46	uint32_t down;
	47	};
	48
93d89f63 IY	49	typedef struct PIIX4PMState {
	50	PCIDevice dev;
	51	uint16_t pmsts;
	52	uint16_t pmen;
	53	uint16_t pmcntrl;
	54
	55	APMState apm;
	56
	57	QEMUTimer *tmr_timer;
	58	int64_t tmr_overflow_time;
	59
	60	PMSMBus smb;
e8ec0571	61	uint32_t smb_io_base;
93d89f63 IY	62
	63	qemu_irq irq;
	64	qemu_irq cmos_s3;
	65	qemu_irq smi_irq;
	66	int kvm_enabled;
ac404095 IY	67
	68	/* for pci hotplug */
	69	struct gpe_regs gpe;
	70	struct pci_status pci0_status;
93d89f63 IY	71	} PIIX4PMState;
93d89f63 IY	72
ac404095 IY	73	static void piix4_acpi_system_hot_add_init(PCIBus bus, PIIX4PMState s);
ac404095 IY	74
93d89f63 IY	75	#define ACPI_ENABLE 0xf1
	76	#define ACPI_DISABLE 0xf0
	77
93d89f63 IY	78	static uint32_t get_pmtmr(PIIX4PMState *s)
	79	{
	80	uint32_t d;
	81	d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
	82	return d & 0xffffff;
	83	}
	84
	85	static int get_pmsts(PIIX4PMState *s)
	86	{
	87	int64_t d;
	88
	89	d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
	90	get_ticks_per_sec());
	91	if (d >= s->tmr_overflow_time)
	92	s->pmsts \|= ACPI_BITMASK_TIMER_STATUS;
	93	return s->pmsts;
	94	}
	95
	96	static void pm_update_sci(PIIX4PMState *s)
	97	{
	98	int sci_level, pmsts;
	99	int64_t expire_time;
	100
	101	pmsts = get_pmsts(s);
	102	sci_level = (((pmsts & s->pmen) &
	103	(ACPI_BITMASK_RT_CLOCK_ENABLE \|
	104	ACPI_BITMASK_POWER_BUTTON_ENABLE \|
	105	ACPI_BITMASK_GLOBAL_LOCK_ENABLE \|
	106	ACPI_BITMASK_TIMER_ENABLE)) != 0);
	107	qemu_set_irq(s->irq, sci_level);
	108	/* schedule a timer interruption if needed */
	109	if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
	110	!(pmsts & ACPI_BITMASK_TIMER_STATUS)) {
	111	expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(),
	112	PM_TIMER_FREQUENCY);
	113	qemu_mod_timer(s->tmr_timer, expire_time);
	114	} else {
	115	qemu_del_timer(s->tmr_timer);
	116	}
	117	}
	118
	119	static void pm_tmr_timer(void *opaque)
	120	{
	121	PIIX4PMState *s = opaque;
	122	pm_update_sci(s);
	123	}
	124
	125	static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
	126	{
	127	PIIX4PMState *s = opaque;
	128	addr &= 0x3f;
	129	switch(addr) {
	130	case 0x00:
	131	{
	132	int64_t d;
	133	int pmsts;
	134	pmsts = get_pmsts(s);
	135	if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
	136	/* if TMRSTS is reset, then compute the new overflow time */
	137	d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
	138	get_ticks_per_sec());
	139	s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
	140	}
	141	s->pmsts &= ~val;
142	pm_update_sci(s);
143	}
144	break;
145	case 0x02:
146	s->pmen = val;
147	pm_update_sci(s);
148	break;
149	case 0x04:
150	{
151	int sus_typ;
152	s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
153	if (val & ACPI_BITMASK_SLEEP_ENABLE) {
154	/* change suspend type */
155	sus_typ = (val >> 10) & 7;
156	switch(sus_typ) {
157	case 0: /* soft power off */
158	qemu_system_shutdown_request();
159	break;
160	case 1:
161	/* ACPI_BITMASK_WAKE_STATUS should be set on resume.
162	Pretend that resume was caused by power button */
163	s->pmsts \|= (ACPI_BITMASK_WAKE_STATUS \|
164	ACPI_BITMASK_POWER_BUTTON_STATUS);
165	qemu_system_reset_request();
166	if (s->cmos_s3) {
167	qemu_irq_raise(s->cmos_s3);
168	}
169	default:
170	break;
171	}
172	}
173	}
174	break;
175	default:
176	break;
177	}
50d8ff8b	178	PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr, val);
93d89f63 IY	179	}
	180
	181	static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
	182	{
	183	PIIX4PMState *s = opaque;
	184	uint32_t val;
	185
	186	addr &= 0x3f;
	187	switch(addr) {
	188	case 0x00:
	189	val = get_pmsts(s);
	190	break;
	191	case 0x02:
	192	val = s->pmen;
	193	break;
	194	case 0x04:
	195	val = s->pmcntrl;
	196	break;
	197	default:
	198	val = 0;
	199	break;
	200	}
50d8ff8b	201	PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val);
93d89f63 IY	202	return val;
	203	}
	204
	205	static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
	206	{
	207	// PIIX4PMState *s = opaque;
50d8ff8b	208	PIIX4_DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr & 0x3f, val);
93d89f63 IY	209	}
	210
	211	static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
	212	{
	213	PIIX4PMState *s = opaque;
	214	uint32_t val;
	215
	216	addr &= 0x3f;
	217	switch(addr) {
	218	case 0x08:
	219	val = get_pmtmr(s);
	220	break;
	221	default:
	222	val = 0;
	223	break;
	224	}
50d8ff8b	225	PIIX4_DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
93d89f63 IY	226	return val;
	227	}
	228
	229	static void apm_ctrl_changed(uint32_t val, void *arg)
	230	{
	231	PIIX4PMState *s = arg;
	232
	233	/* ACPI specs 3.0, 4.7.2.5 */
	234	if (val == ACPI_ENABLE) {
	235	s->pmcntrl \|= ACPI_BITMASK_SCI_ENABLE;
	236	} else if (val == ACPI_DISABLE) {
	237	s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
	238	}
	239
	240	if (s->dev.config[0x5b] & (1 << 1)) {
	241	if (s->smi_irq) {
	242	qemu_irq_raise(s->smi_irq);
	243	}
	244	}
	245	}
	246
	247	static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
	248	{
50d8ff8b	249	PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
93d89f63 IY	250	}
	251
	252	static void pm_io_space_update(PIIX4PMState *s)
	253	{
	254	uint32_t pm_io_base;
	255
	256	if (s->dev.config[0x80] & 1) {
	257	pm_io_base = le32_to_cpu((uint32_t )(s->dev.config + 0x40));
	258	pm_io_base &= 0xffc0;
	259
	260	/* XXX: need to improve memory and ioport allocation */
50d8ff8b	261	PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
93d89f63 IY	262	register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
	263	register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
	264	register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
	265	register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
	266	}
	267	}
	268
	269	static void pm_write_config(PCIDevice *d,
	270	uint32_t address, uint32_t val, int len)
	271	{
	272	pci_default_write_config(d, address, val, len);
	273	if (range_covers_byte(address, len, 0x80))
	274	pm_io_space_update((PIIX4PMState *)d);
	275	}
	276
	277	static int vmstate_acpi_post_load(void *opaque, int version_id)
	278	{
	279	PIIX4PMState *s = opaque;
	280
	281	pm_io_space_update(s);
	282	return 0;
	283	}
	284
	285	static const VMStateDescription vmstate_acpi = {
	286	.name = "piix4_pm",
	287	.version_id = 1,
	288	.minimum_version_id = 1,
	289	.minimum_version_id_old = 1,
	290	.post_load = vmstate_acpi_post_load,
	291	.fields = (VMStateField []) {
	292	VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
	293	VMSTATE_UINT16(pmsts, PIIX4PMState),
	294	VMSTATE_UINT16(pmen, PIIX4PMState),
	295	VMSTATE_UINT16(pmcntrl, PIIX4PMState),
	296	VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
	297	VMSTATE_TIMER(tmr_timer, PIIX4PMState),
	298	VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
	299	VMSTATE_END_OF_LIST()
	300	}
	301	};
	302
	303	static void piix4_reset(void *opaque)
	304	{
	305	PIIX4PMState *s = opaque;
	306	uint8_t *pci_conf = s->dev.config;
	307
	308	pci_conf[0x58] = 0;
	309	pci_conf[0x59] = 0;
	310	pci_conf[0x5a] = 0;
	311	pci_conf[0x5b] = 0;
	312
	313	if (s->kvm_enabled) {
	314	/* Mark SMM as already inited (until KVM supports SMM). */
	315	pci_conf[0x5B] = 0x02;
	316	}
	317	}
	318
	319	static void piix4_powerdown(void *opaque, int irq, int power_failing)
	320	{
	321	PIIX4PMState *s = opaque;
	322
	323	if (!s) {
	324	qemu_system_shutdown_request();
	325	} else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
326	s->pmsts \|= ACPI_BITMASK_POWER_BUTTON_STATUS;
327	pm_update_sci(s);
328	}
329	}
330
e8ec0571	331	static int piix4_pm_initfn(PCIDevice *dev)
93d89f63	332	{
e8ec0571	333	PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
93d89f63 IY	334	uint8_t *pci_conf;
93d89f63 IY	335
93d89f63 IY	336	pci_conf = s->dev.config;
	337	pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
	338	pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
	339	pci_conf[0x06] = 0x80;
	340	pci_conf[0x07] = 0x02;
	341	pci_conf[0x08] = 0x03; // revision number
	342	pci_conf[0x09] = 0x00;
	343	pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
	344	pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
	345	pci_conf[0x3d] = 0x01; // interrupt pin 1
	346
	347	pci_conf[0x40] = 0x01; /* PM io base read only bit */
	348
	349	/* APM */
	350	apm_init(&s->apm, apm_ctrl_changed, s);
	351
	352	register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
	353
93d89f63 IY	354	if (s->kvm_enabled) {
	355	/* Mark SMM as already inited to prevent SMM from running. KVM does not
	356	* support SMM mode. */
	357	pci_conf[0x5B] = 0x02;
	358	}
	359
	360	/* XXX: which specification is used ? The i82731AB has different
	361	mappings */
	362	pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) \| 0x10;
	363	pci_conf[0x63] = 0x60;
	364	pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) \|
	365	(serial_hds[1] != NULL ? 0x90 : 0);
	366
e8ec0571 IY	367	pci_conf[0x90] = s->smb_io_base \| 1;
e8ec0571 IY	368	pci_conf[0x91] = s->smb_io_base >> 8;
93d89f63	369	pci_conf[0xd2] = 0x09;
e8ec0571 IY	370	register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
e8ec0571 IY	371	register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
93d89f63 IY	372
	373	s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
	374
	375	qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
	376
e8ec0571 IY	377	pm_smbus_init(&s->dev.qdev, &s->smb);
e8ec0571 IY	378	qemu_register_reset(piix4_reset, s);
ac404095	379	piix4_acpi_system_hot_add_init(dev->bus, s);
e8ec0571 IY	380
	381	return 0;
	382	}
	383
	384	i2c_bus piix4_pm_init(PCIBus bus, int devfn, uint32_t smb_io_base,
	385	qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
	386	int kvm_enabled)
	387	{
	388	PCIDevice *dev;
	389	PIIX4PMState *s;
	390
	391	dev = pci_create(bus, devfn, "PIIX4_PM");
	392	qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
93d89f63	393
e8ec0571	394	s = DO_UPCAST(PIIX4PMState, dev, dev);
93d89f63 IY	395	s->irq = sci_irq;
	396	s->cmos_s3 = cmos_s3;
	397	s->smi_irq = smi_irq;
e8ec0571 IY	398	s->kvm_enabled = kvm_enabled;
	399
	400	qdev_init_nofail(&dev->qdev);
93d89f63 IY	401
	402	return s->smb.smbus;
	403	}
	404
e8ec0571 IY	405	static PCIDeviceInfo piix4_pm_info = {
	406	.qdev.name = "PIIX4_PM",
	407	.qdev.desc = "PM",
	408	.qdev.size = sizeof(PIIX4PMState),
	409	.qdev.vmsd = &vmstate_acpi,
	410	.init = piix4_pm_initfn,
	411	.config_write = pm_write_config,
	412	.qdev.props = (Property[]) {
	413	DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
	414	DEFINE_PROP_END_OF_LIST(),
	415	}
	416	};
	417
	418	static void piix4_pm_register(void)
	419	{
	420	pci_qdev_register(&piix4_pm_info);
	421	}
	422
	423	device_init(piix4_pm_register);
	424
93d89f63 IY	425	static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
	426	{
	427	if (addr & 1)
	428	return (val >> 8) & 0xff;
	429	return val & 0xff;
	430	}
	431
	432	static uint32_t gpe_readb(void *opaque, uint32_t addr)
	433	{
	434	uint32_t val = 0;
	435	struct gpe_regs *g = opaque;
	436	switch (addr) {
	437	case GPE_BASE:
	438	case GPE_BASE + 1:
	439	val = gpe_read_val(g->sts, addr);
	440	break;
	441	case GPE_BASE + 2:
	442	case GPE_BASE + 3:
	443	val = gpe_read_val(g->en, addr);
	444	break;
	445	default:
	446	break;
	447	}
	448
50d8ff8b	449	PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
93d89f63 IY	450	return val;
	451	}
	452
	453	static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
	454	{
	455	if (addr & 1)
	456	cur = (cur & 0xff) \| (val << 8);
	457	else
	458	cur = (cur & 0xff00) \| (val & 0xff);
	459	}
	460
	461	static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
	462	{
	463	uint16_t x1, x0 = val & 0xff;
	464	int shift = (addr & 1) ? 8 : 0;
	465
	466	x1 = (*cur >> shift) & 0xff;
	467
	468	x1 = x1 & ~x0;
	469
	470	cur = (cur & (0xff << (8 - shift))) \| (x1 << shift);
	471	}
	472
	473	static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
	474	{
	475	struct gpe_regs *g = opaque;
	476	switch (addr) {
	477	case GPE_BASE:
	478	case GPE_BASE + 1:
	479	gpe_reset_val(&g->sts, addr, val);
	480	break;
	481	case GPE_BASE + 2:
	482	case GPE_BASE + 3:
	483	gpe_write_val(&g->en, addr, val);
	484	break;
	485	default:
	486	break;
	487	}
	488
50d8ff8b	489	PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
93d89f63 IY	490	}
	491
	492	static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
	493	{
	494	uint32_t val = 0;
	495	struct pci_status *g = opaque;
	496	switch (addr) {
	497	case PCI_BASE:
	498	val = g->up;
	499	break;
	500	case PCI_BASE + 4:
	501	val = g->down;
	502	break;
	503	default:
	504	break;
	505	}
	506
50d8ff8b	507	PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
93d89f63 IY	508	return val;
	509	}
	510
	511	static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
	512	{
	513	struct pci_status *g = opaque;
	514	switch (addr) {
	515	case PCI_BASE:
	516	g->up = val;
	517	break;
	518	case PCI_BASE + 4:
	519	g->down = val;
	520	break;
	521	}
	522
50d8ff8b	523	PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
93d89f63 IY	524	}
	525
	526	static uint32_t pciej_read(void *opaque, uint32_t addr)
	527	{
50d8ff8b	528	PIIX4_DPRINTF("pciej read %x\n", addr);
93d89f63 IY	529	return 0;
	530	}
	531
	532	static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
	533	{
	534	BusState *bus = opaque;
	535	DeviceState qdev, next;
	536	PCIDevice *dev;
	537	int slot = ffs(val) - 1;
	538
	539	QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
	540	dev = DO_UPCAST(PCIDevice, qdev, qdev);
	541	if (PCI_SLOT(dev->devfn) == slot) {
	542	qdev_free(qdev);
	543	}
	544	}
	545
	546
50d8ff8b	547	PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
93d89f63 IY	548	}
93d89f63 IY	549
87c30546	550	static int piix4_device_hotplug(DeviceState qdev, PCIDevice dev, int state);
93d89f63	551
ac404095	552	static void piix4_acpi_system_hot_add_init(PCIBus bus, PIIX4PMState s)
93d89f63	553	{
ac404095 IY	554	struct gpe_regs *gpe = &s->gpe;
ac404095 IY	555	struct pci_status *pci0_status = &s->pci0_status;
93d89f63	556
ac404095 IY	557	register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, gpe);
	558	register_ioport_read(GPE_BASE, 4, 1, gpe_readb, gpe);
	559
	560	register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
	561	register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, pci0_status);
93d89f63 IY	562
	563	register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
	564	register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, bus);
	565
ac404095	566	pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
93d89f63 IY	567	}
93d89f63 IY	568
ac404095	569	static void enable_device(PIIX4PMState *s, int slot)
93d89f63	570	{
ac404095 IY	571	s->gpe.sts \|= 2;
ac404095 IY	572	s->pci0_status.up \|= (1 << slot);
93d89f63 IY	573	}
93d89f63 IY	574
ac404095	575	static void disable_device(PIIX4PMState *s, int slot)
93d89f63	576	{
ac404095 IY	577	s->gpe.sts \|= 2;
ac404095 IY	578	s->pci0_status.down \|= (1 << slot);
93d89f63 IY	579	}
93d89f63 IY	580
87c30546	581	static int piix4_device_hotplug(DeviceState qdev, PCIDevice dev, int state)
93d89f63 IY	582	{
93d89f63 IY	583	int slot = PCI_SLOT(dev->devfn);
ac404095 IY	584	PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
ac404095 IY	585	DO_UPCAST(PCIDevice, qdev, qdev));
93d89f63	586
ac404095 IY	587	s->pci0_status.up = 0;
	588	s->pci0_status.down = 0;
	589	if (state) {
	590	enable_device(s, slot);
	591	} else {
	592	disable_device(s, slot);
	593	}
	594	if (s->gpe.en & 2) {
	595	qemu_set_irq(s->irq, 1);
	596	qemu_set_irq(s->irq, 0);
93d89f63 IY	597	}
	598	return 0;
	599	}