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hw/fsi: Introduce IBM's scratchpad device
[mirror_qemu.git] / hw / arm / exynos4210.c
CommitLineData
0caa7113
EV		 1/*
2 * Samsung exynos4210 SoC emulation
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
5 * Maksim Kozlov <m.kozlov@samsung.com>
6 * Evgeny Voevodin <e.voevodin@samsung.com>
7 * Igor Mitsyanko <i.mitsyanko@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 *
22 */
23
12b16722 24#include "qemu/osdep.h"
da34e65c 25#include "qapi/error.h"
fd8d2bba 26#include "exec/tswap.h"
4771d756 27#include "cpu.h"
9e883790 28#include "hw/cpu/a9mpcore.h"
64552b6b 29#include "hw/irq.h"
12e9493d 30#include "sysemu/blockdev.h"
9c17d615 31#include "sysemu/sysemu.h"
83c9f4ca 32#include "hw/sysbus.h"
12ec8bd5 33#include "hw/arm/boot.h"
83c9f4ca 34#include "hw/loader.h"
a27bd6c7 35#include "hw/qdev-properties.h"
0d09e41a 36#include "hw/arm/exynos4210.h"
c2de81e2 37#include "hw/sd/sdhci.h"
83c9f4ca 38#include "hw/usb/hcd-ehci.h"
d780d056 39#include "target/arm/cpu-qom.h"
0caa7113
EV		 40
41#define EXYNOS4210_CHIPID_ADDR 0x10000000
42
62db8bf3
EV		 43/* PWM */
44#define EXYNOS4210_PWM_BASE_ADDR 0x139D0000
45
7bdf43a7
OO		 46/* RTC */
47#define EXYNOS4210_RTC_BASE_ADDR 0x10070000
48
12c775db
EV		 49/* MCT */
50#define EXYNOS4210_MCT_BASE_ADDR 0x10050000
51
ffbbe7d0
MI		 52/* I2C */
53#define EXYNOS4210_I2C_SHIFT 0x00010000
54#define EXYNOS4210_I2C_BASE_ADDR 0x13860000
55/* Interrupt Group of External Interrupt Combiner for I2C */
56#define EXYNOS4210_I2C_INTG 27
57#define EXYNOS4210_HDMI_INTG 16
58
e5a4914e
MK		 59/* UART's definitions */
60#define EXYNOS4210_UART0_BASE_ADDR 0x13800000
61#define EXYNOS4210_UART1_BASE_ADDR 0x13810000
62#define EXYNOS4210_UART2_BASE_ADDR 0x13820000
63#define EXYNOS4210_UART3_BASE_ADDR 0x13830000
64#define EXYNOS4210_UART0_FIFO_SIZE 256
65#define EXYNOS4210_UART1_FIFO_SIZE 64
66#define EXYNOS4210_UART2_FIFO_SIZE 16
67#define EXYNOS4210_UART3_FIFO_SIZE 16
68/* Interrupt Group of External Interrupt Combiner for UART */
69#define EXYNOS4210_UART_INT_GRP 26
70
0caa7113
EV		 71/* External GIC */
72#define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000
73#define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000
74
75/* Combiner */
76#define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000
77#define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000
78
d77b71c2
KK		 79/* SD/MMC host controllers */
80#define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080
81#define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000
82#define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \
83 0x00010000 * (n))
84#define EXYNOS4210_SDHCI_NUMBER 4
85
df91b48f
MK		 86/* PMU SFR base address */
87#define EXYNOS4210_PMU_BASE_ADDR 0x10020000
88
1e0228fd
KK		 89/* Clock controller SFR base address */
90#define EXYNOS4210_CLK_BASE_ADDR 0x10030000
91
499ca137
KK		 92/* PRNG/HASH SFR base address */
93#define EXYNOS4210_RNG_BASE_ADDR 0x10830400
94
30628cb1
MI		 95/* Display controllers (FIMD) */
96#define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000
97
358d615b
LW		 98/* EHCI */
99#define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
100
59520dc6
GR		 101/* DMA */
102#define EXYNOS4210_PL330_BASE0_ADDR 0x12680000
103#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
104#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
105
93afe073
PM		 106enum ExtGicId {
107 EXT_GIC_ID_MDMA_LCD0 = 66,
108 EXT_GIC_ID_PDMA0,
109 EXT_GIC_ID_PDMA1,
110 EXT_GIC_ID_TIMER0,
111 EXT_GIC_ID_TIMER1,
112 EXT_GIC_ID_TIMER2,
113 EXT_GIC_ID_TIMER3,
114 EXT_GIC_ID_TIMER4,
115 EXT_GIC_ID_MCT_L0,
116 EXT_GIC_ID_WDT,
117 EXT_GIC_ID_RTC_ALARM,
118 EXT_GIC_ID_RTC_TIC,
119 EXT_GIC_ID_GPIO_XB,
120 EXT_GIC_ID_GPIO_XA,
121 EXT_GIC_ID_MCT_L1,
122 EXT_GIC_ID_IEM_APC,
123 EXT_GIC_ID_IEM_IEC,
124 EXT_GIC_ID_NFC,
125 EXT_GIC_ID_UART0,
126 EXT_GIC_ID_UART1,
127 EXT_GIC_ID_UART2,
128 EXT_GIC_ID_UART3,
129 EXT_GIC_ID_UART4,
130 EXT_GIC_ID_MCT_G0,
131 EXT_GIC_ID_I2C0,
132 EXT_GIC_ID_I2C1,
133 EXT_GIC_ID_I2C2,
134 EXT_GIC_ID_I2C3,
135 EXT_GIC_ID_I2C4,
136 EXT_GIC_ID_I2C5,
137 EXT_GIC_ID_I2C6,
138 EXT_GIC_ID_I2C7,
139 EXT_GIC_ID_SPI0,
140 EXT_GIC_ID_SPI1,
141 EXT_GIC_ID_SPI2,
142 EXT_GIC_ID_MCT_G1,
143 EXT_GIC_ID_USB_HOST,
144 EXT_GIC_ID_USB_DEVICE,
145 EXT_GIC_ID_MODEMIF,
146 EXT_GIC_ID_HSMMC0,
147 EXT_GIC_ID_HSMMC1,
148 EXT_GIC_ID_HSMMC2,
149 EXT_GIC_ID_HSMMC3,
150 EXT_GIC_ID_SDMMC,
151 EXT_GIC_ID_MIPI_CSI_4LANE,
152 EXT_GIC_ID_MIPI_DSI_4LANE,
153 EXT_GIC_ID_MIPI_CSI_2LANE,
154 EXT_GIC_ID_MIPI_DSI_2LANE,
155 EXT_GIC_ID_ONENAND_AUDI,
156 EXT_GIC_ID_ROTATOR,
157 EXT_GIC_ID_FIMC0,
158 EXT_GIC_ID_FIMC1,
159 EXT_GIC_ID_FIMC2,
160 EXT_GIC_ID_FIMC3,
161 EXT_GIC_ID_JPEG,
162 EXT_GIC_ID_2D,
163 EXT_GIC_ID_PCIe,
164 EXT_GIC_ID_MIXER,
165 EXT_GIC_ID_HDMI,
166 EXT_GIC_ID_HDMI_I2C,
167 EXT_GIC_ID_MFC,
168 EXT_GIC_ID_TVENC,
169};
170
171enum ExtInt {
172 EXT_GIC_ID_EXTINT0 = 48,
173 EXT_GIC_ID_EXTINT1,
174 EXT_GIC_ID_EXTINT2,
175 EXT_GIC_ID_EXTINT3,
176 EXT_GIC_ID_EXTINT4,
177 EXT_GIC_ID_EXTINT5,
178 EXT_GIC_ID_EXTINT6,
179 EXT_GIC_ID_EXTINT7,
180 EXT_GIC_ID_EXTINT8,
181 EXT_GIC_ID_EXTINT9,
182 EXT_GIC_ID_EXTINT10,
183 EXT_GIC_ID_EXTINT11,
184 EXT_GIC_ID_EXTINT12,
185 EXT_GIC_ID_EXTINT13,
186 EXT_GIC_ID_EXTINT14,
187 EXT_GIC_ID_EXTINT15
188};
189
190/*
191 * External GIC sources which are not from External Interrupt Combiner or
192 * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
193 * which is INTG16 in Internal Interrupt Combiner.
194 */
195
196static const uint32_t
197combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
198 /* int combiner groups 16-19 */
199 { }, { }, { }, { },
200 /* int combiner group 20 */
201 { 0, EXT_GIC_ID_MDMA_LCD0 },
202 /* int combiner group 21 */
203 { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
204 /* int combiner group 22 */
205 { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
206 EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
207 /* int combiner group 23 */
208 { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
209 /* int combiner group 24 */
210 { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
211 /* int combiner group 25 */
212 { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
213 /* int combiner group 26 */
214 { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
215 EXT_GIC_ID_UART4 },
216 /* int combiner group 27 */
217 { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
218 EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
219 EXT_GIC_ID_I2C7 },
220 /* int combiner group 28 */
221 { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
222 /* int combiner group 29 */
223 { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
224 EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
225 /* int combiner group 30 */
226 { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
227 /* int combiner group 31 */
228 { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
229 /* int combiner group 32 */
230 { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
231 /* int combiner group 33 */
232 { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
233 /* int combiner group 34 */
234 { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
235 /* int combiner group 35 */
76124b4c 236 { 0, 0, 0, EXT_GIC_ID_MCT_L1 },
93afe073
PM		 237 /* int combiner group 36 */
238 { EXT_GIC_ID_MIXER },
239 /* int combiner group 37 */
240 { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
241 EXT_GIC_ID_EXTINT7 },
242 /* groups 38-50 */
243 { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
244 /* int combiner group 51 */
76124b4c 245 { EXT_GIC_ID_MCT_L0 },
93afe073
PM		 246 /* group 52 */
247 { },
248 /* int combiner group 53 */
76124b4c 249 { EXT_GIC_ID_WDT },
93afe073
PM		 250 /* groups 54-63 */
251 { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
252};
253
03a46e00
PM		 254#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp) * 8 + (bit))
255#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8)
256#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
257 ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
258
76621953
PM		 259/*
260 * Some interrupt lines go to multiple combiner inputs.
261 * This data structure defines those: each array element is
262 * a list of combiner inputs which are connected together;
263 * the one with the smallest interrupt ID value must be first.
264 * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being
265 * wired to anything so we can use 0 as a terminator.
266 */
267#define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B)
268#define IRQNONE 0
269
270#define COMBINERMAP_SIZE 16
271
272static const int combinermap[COMBINERMAP_SIZE][6] = {
273 /* MDNIE_LCD1 */
274 { IRQNO(0, 4), IRQNO(1, 0), IRQNONE },
275 { IRQNO(0, 5), IRQNO(1, 1), IRQNONE },
276 { IRQNO(0, 6), IRQNO(1, 2), IRQNONE },
277 { IRQNO(0, 7), IRQNO(1, 3), IRQNONE },
278 /* TMU */
279 { IRQNO(2, 4), IRQNO(3, 4), IRQNONE },
280 { IRQNO(2, 5), IRQNO(3, 5), IRQNONE },
281 { IRQNO(2, 6), IRQNO(3, 6), IRQNONE },
282 { IRQNO(2, 7), IRQNO(3, 7), IRQNONE },
283 /* LCD1 */
284 { IRQNO(11, 4), IRQNO(12, 0), IRQNONE },
285 { IRQNO(11, 5), IRQNO(12, 1), IRQNONE },
286 { IRQNO(11, 6), IRQNO(12, 2), IRQNONE },
287 { IRQNO(11, 7), IRQNO(12, 3), IRQNONE },
288 /* Multi-core timer */
289 { IRQNO(1, 4), IRQNO(12, 4), IRQNO(35, 4), IRQNO(51, 4), IRQNO(53, 4), IRQNONE },
290 { IRQNO(1, 5), IRQNO(12, 5), IRQNO(35, 5), IRQNO(51, 5), IRQNO(53, 5), IRQNONE },
291 { IRQNO(1, 6), IRQNO(12, 6), IRQNO(35, 6), IRQNO(51, 6), IRQNO(53, 6), IRQNONE },
292 { IRQNO(1, 7), IRQNO(12, 7), IRQNO(35, 7), IRQNO(51, 7), IRQNO(53, 7), IRQNONE },
293};
294
295#undef IRQNO
296
297static const int *combinermap_entry(int irq)
298{
299 /*
300 * If the interrupt number passed in is the first entry in some
301 * line of the combinermap, return a pointer to that line;
302 * otherwise return NULL.
303 */
304 int i;
305 for (i = 0; i < COMBINERMAP_SIZE; i++) {
306 if (combinermap[i][0] == irq) {
307 return combinermap[i];
308 }
309 }
310 return NULL;
311}
312
313static int mapline_size(const int *mapline)
314{
315 /* Return number of entries in this mapline in total */
316 int i = 0;
317
318 if (!mapline) {
319 /* Not in the map? IRQ goes to exactly one combiner input */
320 return 1;
321 }
322 while (*mapline != IRQNONE) {
323 mapline++;
324 i++;
325 }
326 return i;
327}
328
93afe073
PM		 329/*
330 * Initialize board IRQs.
b3db996f 331 * These IRQs contain split Int/External Combiner and External Gic IRQs.
93afe073
PM		 332 */
333static void exynos4210_init_board_irqs(Exynos4210State *s)
334{
335 uint32_t grp, bit, irq_id, n;
38c2b905 336 DeviceState *extgicdev = DEVICE(&s->ext_gic);
f37fc537
PM		 337 DeviceState *intcdev = DEVICE(&s->int_combiner);
338 DeviceState *extcdev = DEVICE(&s->ext_combiner);
7582d930
PM		 339 int splitcount = 0;
340 DeviceState *splitter;
76621953
PM		 341 const int *mapline;
342 int numlines, splitin, in;
93afe073
PM		 343
344 for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
345 irq_id = 0;
76124b4c 346 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) {
93afe073
PM		 347 /* MCT_G0 is passed to External GIC */
348 irq_id = EXT_GIC_ID_MCT_G0;
349 }
76124b4c 350 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) {
93afe073
PM		 351 /* MCT_G1 is passed to External and GIC */
352 irq_id = EXT_GIC_ID_MCT_G1;
353 }
7582d930 354
76621953
PM		 355 if (s->irq_table[n]) {
356 /*
357 * This must be some non-first entry in a combinermap line,
358 * and we've already filled it in.
359 */
360 continue;
361 }
362 mapline = combinermap_entry(n);
363 /*
364 * We need to connect the IRQ to multiple inputs on both combiners
365 * and possibly also to the external GIC.
366 */
367 numlines = 2 * mapline_size(mapline);
368 if (irq_id) {
369 numlines++;
370 }
7582d930
PM		 371 assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
372 splitter = DEVICE(&s->splitter[splitcount]);
76621953 373 qdev_prop_set_uint16(splitter, "num-lines", numlines);
7582d930
PM		 374 qdev_realize(splitter, NULL, &error_abort);
375 splitcount++;
76621953
PM		 376
377 in = n;
378 splitin = 0;
379 for (;;) {
380 s->irq_table[in] = qdev_get_gpio_in(splitter, 0);
f37fc537
PM		 381 qdev_connect_gpio_out(splitter, splitin,
382 qdev_get_gpio_in(intcdev, in));
383 qdev_connect_gpio_out(splitter, splitin + 1,
384 qdev_get_gpio_in(extcdev, in));
76621953
PM		 385 splitin += 2;
386 if (!mapline) {
387 break;
388 }
389 mapline++;
390 in = *mapline;
391 if (in == IRQNONE) {
392 break;
393 }
394 }
93afe073 395 if (irq_id) {
76621953 396 qdev_connect_gpio_out(splitter, splitin,
7582d930 397 qdev_get_gpio_in(extgicdev, irq_id - 32));
93afe073
PM		 398 }
399 }
400 for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
401 /* these IDs are passed to Internal Combiner and External GIC */
402 grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
403 bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
404 irq_id = combiner_grp_to_gic_id[grp -
405 EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
406
76621953
PM		 407 if (s->irq_table[n]) {
408 /*
409 * This must be some non-first entry in a combinermap line,
410 * and we've already filled it in.
411 */
412 continue;
413 }
414
93afe073 415 if (irq_id) {
7582d930
PM		 416 assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
417 splitter = DEVICE(&s->splitter[splitcount]);
418 qdev_prop_set_uint16(splitter, "num-lines", 2);
419 qdev_realize(splitter, NULL, &error_abort);
420 splitcount++;
421 s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
f37fc537 422 qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n));
7582d930
PM		 423 qdev_connect_gpio_out(splitter, 1,
424 qdev_get_gpio_in(extgicdev, irq_id - 32));
0dee4dac 425 } else {
f37fc537 426 s->irq_table[n] = qdev_get_gpio_in(intcdev, n);
93afe073
PM		 427 }
428 }
7582d930
PM		 429 /*
430 * We check this here to avoid a more obscure assert later when
431 * qdev_assert_realized_properly() checks that we realized every
432 * child object we initialized.
433 */
434 assert(splitcount == EXYNOS4210_NUM_SPLITTERS);
93afe073
PM		 435}
436
437/*
438 * Get IRQ number from exynos4210 IRQ subsystem stub.
439 * To identify IRQ source use internal combiner group and bit number
440 * grp - group number
441 * bit - bit number inside group
442 */
443uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
444{
445 return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
446}
447
0caa7113
EV		 448static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
449 0x09, 0x00, 0x00, 0x00 };
450
11a5e482
IM		 451static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset,
452 unsigned size)
453{
454 assert(offset < sizeof(chipid_and_omr));
455 return chipid_and_omr[offset];
456}
457
458static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset,
459 uint64_t value, unsigned size)
460{
461 return;
462}
463
464static const MemoryRegionOps exynos4210_chipid_and_omr_ops = {
465 .read = exynos4210_chipid_and_omr_read,
466 .write = exynos4210_chipid_and_omr_write,
467 .endianness = DEVICE_NATIVE_ENDIAN,
468 .impl = {
469 .max_access_size = 1,
470 }
471};
472
9543b0cd 473void exynos4210_write_secondary(ARMCPU *cpu,
3f088e36
EV		 474 const struct arm_boot_info *info)
475{
476 int n;
477 uint32_t smpboot[] = {
bf471f79
PM		 478 0xe59f3034, /* ldr r3, External gic_cpu_if */
479 0xe59f2034, /* ldr r2, Internal gic_cpu_if */
480 0xe59f0034, /* ldr r0, startaddr */
3f088e36
EV		 481 0xe3a01001, /* mov r1, #1 */
482 0xe5821000, /* str r1, [r2] */
483 0xe5831000, /* str r1, [r3] */
bf471f79
PM		 484 0xe3a010ff, /* mov r1, #0xff */
485 0xe5821004, /* str r1, [r2, #4] */
486 0xe5831004, /* str r1, [r3, #4] */
487 0xf57ff04f, /* dsb */
3f088e36
EV		 488 0xe320f003, /* wfi */
489 0xe5901000, /* ldr r1, [r0] */
490 0xe1110001, /* tst r1, r1 */
491 0x0afffffb, /* beq <wfi> */
492 0xe12fff11, /* bx r1 */
493 EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
494 0, /* gic_cpu_if: base address of Internal GIC CPU interface */
495 0 /* bootreg: Boot register address is held here */
496 };
497 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
498 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
499 for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
500 smpboot[n] = tswap32(smpboot[n]);
501 }
502 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
503 info->smp_loader_start);
504}
505
f3a6339a
KK		 506static uint64_t exynos4210_calc_affinity(int cpu)
507{
f3a6339a 508 /* Exynos4210 has 0x9 as cluster ID */
4a4ff4c5 509 return (0x9 << ARM_AFF1_SHIFT) | cpu;
f3a6339a
KK		 510}
511
e844f0c5 512static DeviceState *pl330_create(uint32_t base, OrIRQState *orgate,
e9d20b55 513 qemu_irq irq, int nreq, int nevents, int width)
59520dc6
GR		 514{
515 SysBusDevice *busdev;
516 DeviceState *dev;
dab15fbe 517 int i;
59520dc6 518
3e80f690 519 dev = qdev_new("pl330");
77844cc5
WJ		 520 object_property_set_link(OBJECT(dev), "memory",
521 OBJECT(get_system_memory()),
522 &error_fatal);
dab15fbe
GR		 523 qdev_prop_set_uint8(dev, "num_events", nevents);
524 qdev_prop_set_uint8(dev, "num_chnls", 8);
59520dc6 525 qdev_prop_set_uint8(dev, "num_periph_req", nreq);
dab15fbe
GR		 526
527 qdev_prop_set_uint8(dev, "wr_cap", 4);
528 qdev_prop_set_uint8(dev, "wr_q_dep", 8);
529 qdev_prop_set_uint8(dev, "rd_cap", 4);
530 qdev_prop_set_uint8(dev, "rd_q_dep", 8);
531 qdev_prop_set_uint8(dev, "data_width", width);
532 qdev_prop_set_uint16(dev, "data_buffer_dep", width);
59520dc6 533 busdev = SYS_BUS_DEVICE(dev);
3c6ef471 534 sysbus_realize_and_unref(busdev, &error_fatal);
59520dc6 535 sysbus_mmio_map(busdev, 0, base);
dab15fbe 536
5325cc34 537 object_property_set_int(OBJECT(orgate), "num-lines", nevents + 1,
dab15fbe 538 &error_abort);
ce189ab2 539 qdev_realize(DEVICE(orgate), NULL, &error_abort);
dab15fbe
GR		 540
541 for (i = 0; i < nevents + 1; i++) {
542 sysbus_connect_irq(busdev, i, qdev_get_gpio_in(DEVICE(orgate), i));
543 }
544 qdev_connect_gpio_out(DEVICE(orgate), 0, irq);
e9d20b55 545 return dev;
59520dc6
GR		 546}
547
98e4f4fd 548static void exynos4210_realize(DeviceState *socdev, Error **errp)
0caa7113 549{
98e4f4fd
PMD		 550 Exynos4210State *s = EXYNOS4210_SOC(socdev);
551 MemoryRegion *system_mem = get_system_memory();
0caa7113 552 SysBusDevice *busdev;
e9d20b55 553 DeviceState *dev, *uart[4], *pl330[3];
310150c0 554 int i, n;
4719ab91 555
0caa7113 556 for (n = 0; n < EXYNOS4210_NCPUS; n++) {
ba1ba5cc 557 Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9"));
4719ab91 558
61e2f352
GB		 559 /* By default A9 CPUs have EL3 enabled. This board does not currently
560 * support EL3 so the CPU EL3 property is disabled before realization.
561 */
efba1595 562 if (object_property_find(cpuobj, "has_el3")) {
5325cc34 563 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal);
61e2f352
GB		 564 }
565
4719ab91 566 s->cpu[n] = ARM_CPU(cpuobj);
5325cc34
MA		 567 object_property_set_int(cpuobj, "mp-affinity",
568 exynos4210_calc_affinity(n), &error_abort);
569 object_property_set_int(cpuobj, "reset-cbar",
570 EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
571 &error_abort);
ce189ab2 572 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
0caa7113
EV		 573 }
574
0caa7113 575 /* IRQ Gate */
61558e7a 576 for (i = 0; i < EXYNOS4210_NCPUS; i++) {
2bd84b68
PM		 577 DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
578 object_property_set_int(OBJECT(orgate), "num-lines",
579 EXYNOS4210_IRQ_GATE_NINPUTS,
580 &error_abort);
581 qdev_realize(orgate, NULL, &error_abort);
582 qdev_connect_gpio_out(orgate, 0,
583 qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
0caa7113
EV		 584 }
585
586 /* Private memory region and Internal GIC */
5b241728
PM		 587 qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS);
588 busdev = SYS_BUS_DEVICE(&s->a9mpcore);
589 sysbus_realize(busdev, &error_fatal);
0caa7113
EV		 590 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
591 for (n = 0; n < EXYNOS4210_NCPUS; n++) {
2bd84b68
PM		 592 sysbus_connect_irq(busdev, n,
593 qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
0caa7113 594 }
0caa7113
EV		 595
596 /* Cache controller */
597 sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
598
599 /* External GIC */
78cb12a9
PM		 600 qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS);
601 busdev = SYS_BUS_DEVICE(&s->ext_gic);
602 sysbus_realize(busdev, &error_fatal);
0caa7113
EV		 603 /* Map CPU interface */
604 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
605 /* Map Distributer interface */
606 sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
607 for (n = 0; n < EXYNOS4210_NCPUS; n++) {
2bd84b68
PM		 608 sysbus_connect_irq(busdev, n,
609 qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
0caa7113 610 }
0caa7113
EV		 611
612 /* Internal Interrupt Combiner */
cebef07d
PM		 613 busdev = SYS_BUS_DEVICE(&s->int_combiner);
614 sysbus_realize(busdev, &error_fatal);
0caa7113 615 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
c9d4940a
PM		 616 sysbus_connect_irq(busdev, n,
617 qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
0caa7113 618 }
0caa7113
EV		 619 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
620
621 /* External Interrupt Combiner */
cebef07d
PM		 622 qdev_prop_set_uint32(DEVICE(&s->ext_combiner), "external", 1);
623 busdev = SYS_BUS_DEVICE(&s->ext_combiner);
624 sysbus_realize(busdev, &error_fatal);
0caa7113 625 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
38c2b905 626 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
0caa7113 627 }
0caa7113
EV		 628 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
629
630 /* Initialize board IRQs. */
771dee52 631 exynos4210_init_board_irqs(s);
0caa7113
EV		 632
633 /*** Memory ***/
634
635 /* Chip-ID and OMR */
32b9523a
PMD		 636 memory_region_init_io(&s->chipid_mem, OBJECT(socdev),
637 &exynos4210_chipid_and_omr_ops, NULL,
638 "exynos4210.chipid", sizeof(chipid_and_omr));
0caa7113
EV		 639 memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
640 &s->chipid_mem);
641
642 /* Internal ROM */
32b9523a 643 memory_region_init_rom(&s->irom_mem, OBJECT(socdev), "exynos4210.irom",
f8ed85ac 644 EXYNOS4210_IROM_SIZE, &error_fatal);
0caa7113
EV		 645 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
646 &s->irom_mem);
647 /* mirror of iROM */
32b9523a
PMD		 648 memory_region_init_alias(&s->irom_alias_mem, OBJECT(socdev),
649 "exynos4210.irom_alias", &s->irom_mem, 0,
0caa7113 650 EXYNOS4210_IROM_SIZE);
0caa7113
EV		 651 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
652 &s->irom_alias_mem);
653
654 /* Internal RAM */
98a99ce0 655 memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram",
f8ed85ac 656 EXYNOS4210_IRAM_SIZE, &error_fatal);
0caa7113
EV		 657 memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
658 &s->iram_mem);
659
df91b48f
MK		 660 /* PMU.
661 * The only reason of existence at the moment is that secondary CPU boot
662 * loader uses PMU INFORM5 register as a holding pen.
663 */
664 sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
665
1e0228fd 666 sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL);
499ca137 667 sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL);
1e0228fd 668
62db8bf3
EV		 669 /* PWM */
670 sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
671 s->irq_table[exynos4210_get_irq(22, 0)],
672 s->irq_table[exynos4210_get_irq(22, 1)],
673 s->irq_table[exynos4210_get_irq(22, 2)],
674 s->irq_table[exynos4210_get_irq(22, 3)],
675 s->irq_table[exynos4210_get_irq(22, 4)],
676 NULL);
7bdf43a7
OO		 677 /* RTC */
678 sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
679 s->irq_table[exynos4210_get_irq(23, 0)],
680 s->irq_table[exynos4210_get_irq(23, 1)],
681 NULL);
62db8bf3 682
12c775db 683 /* Multi Core Timer */
3e80f690 684 dev = qdev_new("exynos4210.mct");
1356b98d 685 busdev = SYS_BUS_DEVICE(dev);
3c6ef471 686 sysbus_realize_and_unref(busdev, &error_fatal);
12c775db
EV		 687 for (n = 0; n < 4; n++) {
688 /* Connect global timer interrupts to Combiner gpio_in */
689 sysbus_connect_irq(busdev, n,
690 s->irq_table[exynos4210_get_irq(1, 4 + n)]);
691 }
692 /* Connect local timer interrupts to Combiner gpio_in */
693 sysbus_connect_irq(busdev, 4,
694 s->irq_table[exynos4210_get_irq(51, 0)]);
695 sysbus_connect_irq(busdev, 5,
696 s->irq_table[exynos4210_get_irq(35, 3)]);
697 sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
698
ffbbe7d0
MI		 699 /*** I2C ***/
700 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) {
701 uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n;
702 qemu_irq i2c_irq;
703
704 if (n < 8) {
705 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)];
706 } else {
707 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
708 }
709
3e80f690 710 dev = qdev_new("exynos4210.i2c");
1356b98d 711 busdev = SYS_BUS_DEVICE(dev);
3c6ef471 712 sysbus_realize_and_unref(busdev, &error_fatal);
ffbbe7d0
MI		 713 sysbus_connect_irq(busdev, 0, i2c_irq);
714 sysbus_mmio_map(busdev, 0, addr);
a5c82852 715 s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c");
ffbbe7d0
MI		 716 }
717
718
e5a4914e 719 /*** UARTs ***/
e9d20b55 720 uart[0] = exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
5561adf0 721 EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0),
e5a4914e
MK		 722 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
723
e9d20b55 724 uart[1] = exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
5561adf0 725 EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1),
e5a4914e
MK		 726 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
727
e9d20b55 728 uart[2] = exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
5561adf0 729 EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2),
e5a4914e
MK		 730 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
731
e9d20b55 732 uart[3] = exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
5561adf0 733 EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3),
e5a4914e
MK		 734 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
735
d77b71c2
KK		 736 /*** SD/MMC host controllers ***/
737 for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) {
738 DeviceState *carddev;
739 BlockBackend *blk;
740 DriveInfo *di;
741
2edb4434
PMD		 742 /* Compatible with:
743 * - SD Host Controller Specification Version 2.0
744 * - SDIO Specification Version 2.0
745 * - MMC Specification Version 4.3
746 * - SDMA
747 * - ADMA2
748 *
b3db996f 749 * As this part of the Exynos4210 is not publicly available,
2edb4434
PMD		 750 * we used the "HS-MMC Controller S3C2416X RISC Microprocessor"
751 * public datasheet which is very similar (implementing
752 * MMC Specification Version 4.0 being the only difference noted)
753 */
3e80f690 754 dev = qdev_new(TYPE_S3C_SDHCI);
3c675da5 755 qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);
d77b71c2
KK		 756
757 busdev = SYS_BUS_DEVICE(dev);
3c6ef471 758 sysbus_realize_and_unref(busdev, &error_fatal);
d77b71c2
KK		 759 sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n));
760 sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]);
761
762 di = drive_get(IF_SD, 0, n);
763 blk = di ? blk_by_legacy_dinfo(di) : NULL;
3e80f690 764 carddev = qdev_new(TYPE_SD_CARD);
934df912 765 qdev_prop_set_drive(carddev, "drive", blk);
3e80f690
MA		 766 qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
767 &error_fatal);
d77b71c2
KK		 768 }
769
30628cb1
MI		 770 /*** Display controller (FIMD) ***/
771 sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
772 s->irq_table[exynos4210_get_irq(11, 0)],
773 s->irq_table[exynos4210_get_irq(11, 1)],
774 s->irq_table[exynos4210_get_irq(11, 2)],
775 NULL);
776
358d615b
LW		 777 sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
778 s->irq_table[exynos4210_get_irq(28, 3)]);
779
59520dc6 780 /*** DMA controllers ***/
e9d20b55
GR		 781 pl330[0] = pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
782 &s->pl330_irq_orgate[0],
783 s->irq_table[exynos4210_get_irq(21, 0)],
784 32, 32, 32);
785 pl330[1] = pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
786 &s->pl330_irq_orgate[1],
787 s->irq_table[exynos4210_get_irq(21, 1)],
788 32, 32, 32);
789 pl330[2] = pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
790 &s->pl330_irq_orgate[2],
791 s->irq_table[exynos4210_get_irq(20, 1)],
792 1, 31, 64);
793
794 sysbus_connect_irq(SYS_BUS_DEVICE(uart[0]), 1,
795 qdev_get_gpio_in(pl330[0], 15));
796 sysbus_connect_irq(SYS_BUS_DEVICE(uart[1]), 1,
797 qdev_get_gpio_in(pl330[1], 15));
798 sysbus_connect_irq(SYS_BUS_DEVICE(uart[2]), 1,
799 qdev_get_gpio_in(pl330[0], 17));
800 sysbus_connect_irq(SYS_BUS_DEVICE(uart[3]), 1,
801 qdev_get_gpio_in(pl330[1], 17));
dab15fbe
GR		 802}
803
804static void exynos4210_init(Object *obj)
805{
806 Exynos4210State *s = EXYNOS4210_SOC(obj);
807 int i;
808
809 for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) {
810 char *name = g_strdup_printf("pl330-irq-orgate%d", i);
e844f0c5 811 OrIRQState *orgate = &s->pl330_irq_orgate[i];
dab15fbe 812
9fc7fc4d 813 object_initialize_child(obj, name, orgate, TYPE_OR_IRQ);
dab15fbe
GR		 814 g_free(name);
815 }
2bd84b68
PM		 816
817 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) {
818 g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
819 object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
820 }
5b241728 821
7582d930
PM		 822 for (i = 0; i < ARRAY_SIZE(s->splitter); i++) {
823 g_autofree char *name = g_strdup_printf("irq-splitter%d", i);
824 object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ);
825 }
826
5b241728 827 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
78cb12a9 828 object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
cebef07d
PM		 829 object_initialize_child(obj, "int-combiner", &s->int_combiner,
830 TYPE_EXYNOS4210_COMBINER);
831 object_initialize_child(obj, "ext-combiner", &s->ext_combiner,
832 TYPE_EXYNOS4210_COMBINER);
98e4f4fd
PMD		 833}
834
835static void exynos4210_class_init(ObjectClass *klass, void *data)
836{
837 DeviceClass *dc = DEVICE_CLASS(klass);
59520dc6 838
98e4f4fd 839 dc->realize = exynos4210_realize;
0caa7113 840}
98e4f4fd
PMD		 841
842static const TypeInfo exynos4210_info = {
843 .name = TYPE_EXYNOS4210_SOC,
844 .parent = TYPE_SYS_BUS_DEVICE,
845 .instance_size = sizeof(Exynos4210State),
dab15fbe 846 .instance_init = exynos4210_init,
98e4f4fd
PMD		 847 .class_init = exynos4210_class_init,
848};
849
850static void exynos4210_register_types(void)
851{
852 type_register_static(&exynos4210_info);
853}
854
855type_init(exynos4210_register_types)
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