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Commit | Line | Data |
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5fafdf24 | 1 | /* |
b5ff1b31 FB |
2 | * ARM Integrator CP System emulation. |
3 | * | |
a1bb27b1 | 4 | * Copyright (c) 2005-2007 CodeSourcery. |
b5ff1b31 FB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL |
b5ff1b31 FB |
8 | */ |
9 | ||
12b16722 | 10 | #include "qemu/osdep.h" |
da34e65c | 11 | #include "qapi/error.h" |
4771d756 PB |
12 | #include "qemu-common.h" |
13 | #include "cpu.h" | |
83c9f4ca | 14 | #include "hw/sysbus.h" |
bd2be150 | 15 | #include "hw/devices.h" |
83c9f4ca | 16 | #include "hw/boards.h" |
bd2be150 | 17 | #include "hw/arm/arm.h" |
b8616055 | 18 | #include "hw/misc/arm_integrator_debug.h" |
1422e32d | 19 | #include "net/net.h" |
022c62cb | 20 | #include "exec/address-spaces.h" |
9c17d615 | 21 | #include "sysemu/sysemu.h" |
223a72f1 | 22 | #include "qemu/error-report.h" |
f0d1d2c1 | 23 | #include "hw/char/pl011.h" |
b5ff1b31 | 24 | |
257ec289 AF |
25 | #define TYPE_INTEGRATOR_CM "integrator_core" |
26 | #define INTEGRATOR_CM(obj) \ | |
27 | OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM) | |
28 | ||
29 | typedef struct IntegratorCMState { | |
30 | /*< private >*/ | |
31 | SysBusDevice parent_obj; | |
32 | /*< public >*/ | |
33 | ||
71d9bc50 | 34 | MemoryRegion iomem; |
ee6847d1 | 35 | uint32_t memsz; |
211adf4d | 36 | MemoryRegion flash; |
b5ff1b31 FB |
37 | uint32_t cm_osc; |
38 | uint32_t cm_ctrl; | |
39 | uint32_t cm_lock; | |
40 | uint32_t cm_auxosc; | |
41 | uint32_t cm_sdram; | |
42 | uint32_t cm_init; | |
43 | uint32_t cm_flags; | |
44 | uint32_t cm_nvflags; | |
f53977f7 | 45 | uint32_t cm_refcnt_offset; |
b5ff1b31 FB |
46 | uint32_t int_level; |
47 | uint32_t irq_enabled; | |
48 | uint32_t fiq_enabled; | |
257ec289 | 49 | } IntegratorCMState; |
b5ff1b31 FB |
50 | |
51 | static uint8_t integrator_spd[128] = { | |
52 | 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, | |
53 | 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 | |
54 | }; | |
55 | ||
a8170e5e | 56 | static uint64_t integratorcm_read(void *opaque, hwaddr offset, |
71d9bc50 | 57 | unsigned size) |
b5ff1b31 | 58 | { |
257ec289 | 59 | IntegratorCMState *s = opaque; |
b5ff1b31 FB |
60 | if (offset >= 0x100 && offset < 0x200) { |
61 | /* CM_SPD */ | |
62 | if (offset >= 0x180) | |
63 | return 0; | |
64 | return integrator_spd[offset >> 2]; | |
65 | } | |
66 | switch (offset >> 2) { | |
67 | case 0: /* CM_ID */ | |
68 | return 0x411a3001; | |
69 | case 1: /* CM_PROC */ | |
70 | return 0; | |
71 | case 2: /* CM_OSC */ | |
72 | return s->cm_osc; | |
73 | case 3: /* CM_CTRL */ | |
74 | return s->cm_ctrl; | |
75 | case 4: /* CM_STAT */ | |
76 | return 0x00100000; | |
77 | case 5: /* CM_LOCK */ | |
78 | if (s->cm_lock == 0xa05f) { | |
79 | return 0x1a05f; | |
80 | } else { | |
81 | return s->cm_lock; | |
82 | } | |
83 | case 6: /* CM_LMBUSCNT */ | |
84 | /* ??? High frequency timer. */ | |
2ac71179 | 85 | hw_error("integratorcm_read: CM_LMBUSCNT"); |
b5ff1b31 FB |
86 | case 7: /* CM_AUXOSC */ |
87 | return s->cm_auxosc; | |
88 | case 8: /* CM_SDRAM */ | |
89 | return s->cm_sdram; | |
90 | case 9: /* CM_INIT */ | |
91 | return s->cm_init; | |
f53977f7 JP |
92 | case 10: /* CM_REFCNT */ |
93 | /* This register, CM_REFCNT, provides a 32-bit count value. | |
94 | * The count increments at the fixed reference clock frequency of 24MHz | |
95 | * and can be used as a real-time counter. | |
96 | */ | |
97 | return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, | |
98 | 1000) - s->cm_refcnt_offset; | |
b5ff1b31 FB |
99 | case 12: /* CM_FLAGS */ |
100 | return s->cm_flags; | |
101 | case 14: /* CM_NVFLAGS */ | |
102 | return s->cm_nvflags; | |
103 | case 16: /* CM_IRQ_STAT */ | |
104 | return s->int_level & s->irq_enabled; | |
105 | case 17: /* CM_IRQ_RSTAT */ | |
106 | return s->int_level; | |
107 | case 18: /* CM_IRQ_ENSET */ | |
108 | return s->irq_enabled; | |
109 | case 20: /* CM_SOFT_INTSET */ | |
110 | return s->int_level & 1; | |
111 | case 24: /* CM_FIQ_STAT */ | |
112 | return s->int_level & s->fiq_enabled; | |
113 | case 25: /* CM_FIQ_RSTAT */ | |
114 | return s->int_level; | |
115 | case 26: /* CM_FIQ_ENSET */ | |
116 | return s->fiq_enabled; | |
117 | case 32: /* CM_VOLTAGE_CTL0 */ | |
118 | case 33: /* CM_VOLTAGE_CTL1 */ | |
119 | case 34: /* CM_VOLTAGE_CTL2 */ | |
120 | case 35: /* CM_VOLTAGE_CTL3 */ | |
121 | /* ??? Voltage control unimplemented. */ | |
122 | return 0; | |
123 | default: | |
2ac71179 PB |
124 | hw_error("integratorcm_read: Unimplemented offset 0x%x\n", |
125 | (int)offset); | |
b5ff1b31 FB |
126 | return 0; |
127 | } | |
128 | } | |
129 | ||
257ec289 | 130 | static void integratorcm_do_remap(IntegratorCMState *s) |
b5ff1b31 | 131 | { |
563c2bf3 PM |
132 | /* Sync memory region state with CM_CTRL REMAP bit: |
133 | * bit 0 => flash at address 0; bit 1 => RAM | |
134 | */ | |
135 | memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4)); | |
b5ff1b31 FB |
136 | } |
137 | ||
257ec289 | 138 | static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value) |
b5ff1b31 FB |
139 | { |
140 | if (value & 8) { | |
df3f457b | 141 | qemu_system_reset_request(); |
b5ff1b31 | 142 | } |
df3f457b PM |
143 | if ((s->cm_ctrl ^ value) & 1) { |
144 | /* (value & 1) != 0 means the green "MISC LED" is lit. | |
145 | * We don't have any nice place to display LEDs. printf is a bad | |
146 | * idea because Linux uses the LED as a heartbeat and the output | |
147 | * will swamp anything else on the terminal. | |
148 | */ | |
b5ff1b31 | 149 | } |
df3f457b PM |
150 | /* Note that the RESET bit [3] always reads as zero */ |
151 | s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5); | |
563c2bf3 | 152 | integratorcm_do_remap(s); |
b5ff1b31 FB |
153 | } |
154 | ||
257ec289 | 155 | static void integratorcm_update(IntegratorCMState *s) |
b5ff1b31 FB |
156 | { |
157 | /* ??? The CPU irq/fiq is raised when either the core module or base PIC | |
158 | are active. */ | |
159 | if (s->int_level & (s->irq_enabled | s->fiq_enabled)) | |
2ac71179 | 160 | hw_error("Core module interrupt\n"); |
b5ff1b31 FB |
161 | } |
162 | ||
a8170e5e | 163 | static void integratorcm_write(void *opaque, hwaddr offset, |
71d9bc50 | 164 | uint64_t value, unsigned size) |
b5ff1b31 | 165 | { |
257ec289 | 166 | IntegratorCMState *s = opaque; |
b5ff1b31 FB |
167 | switch (offset >> 2) { |
168 | case 2: /* CM_OSC */ | |
169 | if (s->cm_lock == 0xa05f) | |
170 | s->cm_osc = value; | |
171 | break; | |
172 | case 3: /* CM_CTRL */ | |
173 | integratorcm_set_ctrl(s, value); | |
174 | break; | |
175 | case 5: /* CM_LOCK */ | |
176 | s->cm_lock = value & 0xffff; | |
177 | break; | |
178 | case 7: /* CM_AUXOSC */ | |
179 | if (s->cm_lock == 0xa05f) | |
180 | s->cm_auxosc = value; | |
181 | break; | |
182 | case 8: /* CM_SDRAM */ | |
183 | s->cm_sdram = value; | |
184 | break; | |
185 | case 9: /* CM_INIT */ | |
186 | /* ??? This can change the memory bus frequency. */ | |
187 | s->cm_init = value; | |
188 | break; | |
189 | case 12: /* CM_FLAGSS */ | |
190 | s->cm_flags |= value; | |
191 | break; | |
192 | case 13: /* CM_FLAGSC */ | |
193 | s->cm_flags &= ~value; | |
194 | break; | |
195 | case 14: /* CM_NVFLAGSS */ | |
196 | s->cm_nvflags |= value; | |
197 | break; | |
198 | case 15: /* CM_NVFLAGSS */ | |
199 | s->cm_nvflags &= ~value; | |
200 | break; | |
201 | case 18: /* CM_IRQ_ENSET */ | |
202 | s->irq_enabled |= value; | |
203 | integratorcm_update(s); | |
204 | break; | |
205 | case 19: /* CM_IRQ_ENCLR */ | |
206 | s->irq_enabled &= ~value; | |
207 | integratorcm_update(s); | |
208 | break; | |
209 | case 20: /* CM_SOFT_INTSET */ | |
210 | s->int_level |= (value & 1); | |
211 | integratorcm_update(s); | |
212 | break; | |
213 | case 21: /* CM_SOFT_INTCLR */ | |
214 | s->int_level &= ~(value & 1); | |
215 | integratorcm_update(s); | |
216 | break; | |
217 | case 26: /* CM_FIQ_ENSET */ | |
218 | s->fiq_enabled |= value; | |
219 | integratorcm_update(s); | |
220 | break; | |
221 | case 27: /* CM_FIQ_ENCLR */ | |
222 | s->fiq_enabled &= ~value; | |
223 | integratorcm_update(s); | |
224 | break; | |
225 | case 32: /* CM_VOLTAGE_CTL0 */ | |
226 | case 33: /* CM_VOLTAGE_CTL1 */ | |
227 | case 34: /* CM_VOLTAGE_CTL2 */ | |
228 | case 35: /* CM_VOLTAGE_CTL3 */ | |
229 | /* ??? Voltage control unimplemented. */ | |
230 | break; | |
231 | default: | |
2ac71179 PB |
232 | hw_error("integratorcm_write: Unimplemented offset 0x%x\n", |
233 | (int)offset); | |
b5ff1b31 FB |
234 | break; |
235 | } | |
236 | } | |
237 | ||
238 | /* Integrator/CM control registers. */ | |
239 | ||
71d9bc50 BC |
240 | static const MemoryRegionOps integratorcm_ops = { |
241 | .read = integratorcm_read, | |
242 | .write = integratorcm_write, | |
243 | .endianness = DEVICE_NATIVE_ENDIAN, | |
b5ff1b31 FB |
244 | }; |
245 | ||
a1f42e0c | 246 | static void integratorcm_init(Object *obj) |
b5ff1b31 | 247 | { |
a1f42e0c XZ |
248 | IntegratorCMState *s = INTEGRATOR_CM(obj); |
249 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
b5ff1b31 | 250 | |
b5ff1b31 FB |
251 | s->cm_osc = 0x01000048; |
252 | /* ??? What should the high bits of this value be? */ | |
253 | s->cm_auxosc = 0x0007feff; | |
254 | s->cm_sdram = 0x00011122; | |
ee6847d1 | 255 | if (s->memsz >= 256) { |
b5ff1b31 FB |
256 | integrator_spd[31] = 64; |
257 | s->cm_sdram |= 0x10; | |
ee6847d1 | 258 | } else if (s->memsz >= 128) { |
b5ff1b31 FB |
259 | integrator_spd[31] = 32; |
260 | s->cm_sdram |= 0x0c; | |
ee6847d1 | 261 | } else if (s->memsz >= 64) { |
b5ff1b31 FB |
262 | integrator_spd[31] = 16; |
263 | s->cm_sdram |= 0x08; | |
ee6847d1 | 264 | } else if (s->memsz >= 32) { |
b5ff1b31 FB |
265 | integrator_spd[31] = 4; |
266 | s->cm_sdram |= 0x04; | |
267 | } else { | |
268 | integrator_spd[31] = 2; | |
269 | } | |
270 | memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); | |
271 | s->cm_init = 0x00000112; | |
f53977f7 JP |
272 | s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, |
273 | 1000); | |
a1f42e0c | 274 | memory_region_init_ram(&s->flash, obj, "integrator.flash", 0x100000, |
f8ed85ac | 275 | &error_fatal); |
c5705a77 | 276 | vmstate_register_ram_global(&s->flash); |
b5ff1b31 | 277 | |
a1f42e0c | 278 | memory_region_init_io(&s->iomem, obj, &integratorcm_ops, s, |
71d9bc50 | 279 | "integratorcm", 0x00800000); |
750ecd44 | 280 | sysbus_init_mmio(dev, &s->iomem); |
71d9bc50 | 281 | |
563c2bf3 | 282 | integratorcm_do_remap(s); |
b5ff1b31 FB |
283 | /* ??? Save/restore. */ |
284 | } | |
285 | ||
286 | /* Integrator/CP hardware emulation. */ | |
287 | /* Primary interrupt controller. */ | |
288 | ||
91b64626 AF |
289 | #define TYPE_INTEGRATOR_PIC "integrator_pic" |
290 | #define INTEGRATOR_PIC(obj) \ | |
291 | OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC) | |
292 | ||
293 | typedef struct icp_pic_state { | |
294 | /*< private >*/ | |
295 | SysBusDevice parent_obj; | |
296 | /*< public >*/ | |
297 | ||
298 | MemoryRegion iomem; | |
299 | uint32_t level; | |
300 | uint32_t irq_enabled; | |
301 | uint32_t fiq_enabled; | |
302 | qemu_irq parent_irq; | |
303 | qemu_irq parent_fiq; | |
b5ff1b31 FB |
304 | } icp_pic_state; |
305 | ||
b5ff1b31 FB |
306 | static void icp_pic_update(icp_pic_state *s) |
307 | { | |
cdbdb648 | 308 | uint32_t flags; |
b5ff1b31 | 309 | |
d537cf6c PB |
310 | flags = (s->level & s->irq_enabled); |
311 | qemu_set_irq(s->parent_irq, flags != 0); | |
312 | flags = (s->level & s->fiq_enabled); | |
313 | qemu_set_irq(s->parent_fiq, flags != 0); | |
b5ff1b31 FB |
314 | } |
315 | ||
cdbdb648 | 316 | static void icp_pic_set_irq(void *opaque, int irq, int level) |
b5ff1b31 | 317 | { |
80337b66 | 318 | icp_pic_state *s = (icp_pic_state *)opaque; |
b5ff1b31 | 319 | if (level) |
80337b66 | 320 | s->level |= 1 << irq; |
b5ff1b31 | 321 | else |
80337b66 | 322 | s->level &= ~(1 << irq); |
b5ff1b31 FB |
323 | icp_pic_update(s); |
324 | } | |
325 | ||
a8170e5e | 326 | static uint64_t icp_pic_read(void *opaque, hwaddr offset, |
61074e46 | 327 | unsigned size) |
b5ff1b31 FB |
328 | { |
329 | icp_pic_state *s = (icp_pic_state *)opaque; | |
330 | ||
b5ff1b31 FB |
331 | switch (offset >> 2) { |
332 | case 0: /* IRQ_STATUS */ | |
333 | return s->level & s->irq_enabled; | |
334 | case 1: /* IRQ_RAWSTAT */ | |
335 | return s->level; | |
336 | case 2: /* IRQ_ENABLESET */ | |
337 | return s->irq_enabled; | |
338 | case 4: /* INT_SOFTSET */ | |
339 | return s->level & 1; | |
340 | case 8: /* FRQ_STATUS */ | |
341 | return s->level & s->fiq_enabled; | |
342 | case 9: /* FRQ_RAWSTAT */ | |
343 | return s->level; | |
344 | case 10: /* FRQ_ENABLESET */ | |
345 | return s->fiq_enabled; | |
346 | case 3: /* IRQ_ENABLECLR */ | |
347 | case 5: /* INT_SOFTCLR */ | |
348 | case 11: /* FRQ_ENABLECLR */ | |
349 | default: | |
29bfb117 | 350 | printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset); |
b5ff1b31 FB |
351 | return 0; |
352 | } | |
353 | } | |
354 | ||
a8170e5e | 355 | static void icp_pic_write(void *opaque, hwaddr offset, |
61074e46 | 356 | uint64_t value, unsigned size) |
b5ff1b31 FB |
357 | { |
358 | icp_pic_state *s = (icp_pic_state *)opaque; | |
b5ff1b31 FB |
359 | |
360 | switch (offset >> 2) { | |
361 | case 2: /* IRQ_ENABLESET */ | |
362 | s->irq_enabled |= value; | |
363 | break; | |
364 | case 3: /* IRQ_ENABLECLR */ | |
365 | s->irq_enabled &= ~value; | |
366 | break; | |
367 | case 4: /* INT_SOFTSET */ | |
368 | if (value & 1) | |
d537cf6c | 369 | icp_pic_set_irq(s, 0, 1); |
b5ff1b31 FB |
370 | break; |
371 | case 5: /* INT_SOFTCLR */ | |
372 | if (value & 1) | |
d537cf6c | 373 | icp_pic_set_irq(s, 0, 0); |
b5ff1b31 FB |
374 | break; |
375 | case 10: /* FRQ_ENABLESET */ | |
376 | s->fiq_enabled |= value; | |
377 | break; | |
378 | case 11: /* FRQ_ENABLECLR */ | |
379 | s->fiq_enabled &= ~value; | |
380 | break; | |
381 | case 0: /* IRQ_STATUS */ | |
382 | case 1: /* IRQ_RAWSTAT */ | |
383 | case 8: /* FRQ_STATUS */ | |
384 | case 9: /* FRQ_RAWSTAT */ | |
385 | default: | |
29bfb117 | 386 | printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset); |
b5ff1b31 FB |
387 | return; |
388 | } | |
389 | icp_pic_update(s); | |
390 | } | |
391 | ||
61074e46 BC |
392 | static const MemoryRegionOps icp_pic_ops = { |
393 | .read = icp_pic_read, | |
394 | .write = icp_pic_write, | |
395 | .endianness = DEVICE_NATIVE_ENDIAN, | |
b5ff1b31 FB |
396 | }; |
397 | ||
a1f42e0c | 398 | static void icp_pic_init(Object *obj) |
b5ff1b31 | 399 | { |
a1f42e0c XZ |
400 | DeviceState *dev = DEVICE(obj); |
401 | icp_pic_state *s = INTEGRATOR_PIC(obj); | |
402 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
b5ff1b31 | 403 | |
91b64626 AF |
404 | qdev_init_gpio_in(dev, icp_pic_set_irq, 32); |
405 | sysbus_init_irq(sbd, &s->parent_irq); | |
406 | sysbus_init_irq(sbd, &s->parent_fiq); | |
a1f42e0c | 407 | memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s, |
64bde0f3 | 408 | "icp-pic", 0x00800000); |
91b64626 | 409 | sysbus_init_mmio(sbd, &s->iomem); |
b5ff1b31 FB |
410 | } |
411 | ||
b5ff1b31 | 412 | /* CP control registers. */ |
0c36493e | 413 | |
ffc8542a JK |
414 | #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs" |
415 | #define ICP_CONTROL_REGS(obj) \ | |
416 | OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS) | |
417 | ||
418 | typedef struct ICPCtrlRegsState { | |
419 | /*< private >*/ | |
420 | SysBusDevice parent_obj; | |
421 | /*< public >*/ | |
422 | ||
423 | MemoryRegion iomem; | |
83d0cf89 JK |
424 | |
425 | qemu_irq mmc_irq; | |
426 | uint32_t intreg_state; | |
ffc8542a JK |
427 | } ICPCtrlRegsState; |
428 | ||
83d0cf89 JK |
429 | #define ICP_GPIO_MMC_WPROT "mmc-wprot" |
430 | #define ICP_GPIO_MMC_CARDIN "mmc-cardin" | |
431 | ||
432 | #define ICP_INTREG_WPROT (1 << 0) | |
433 | #define ICP_INTREG_CARDIN (1 << 3) | |
434 | ||
a8170e5e | 435 | static uint64_t icp_control_read(void *opaque, hwaddr offset, |
0c36493e | 436 | unsigned size) |
b5ff1b31 | 437 | { |
83d0cf89 JK |
438 | ICPCtrlRegsState *s = opaque; |
439 | ||
b5ff1b31 FB |
440 | switch (offset >> 2) { |
441 | case 0: /* CP_IDFIELD */ | |
442 | return 0x41034003; | |
443 | case 1: /* CP_FLASHPROG */ | |
444 | return 0; | |
445 | case 2: /* CP_INTREG */ | |
83d0cf89 | 446 | return s->intreg_state; |
b5ff1b31 FB |
447 | case 3: /* CP_DECODE */ |
448 | return 0x11; | |
449 | default: | |
2ac71179 | 450 | hw_error("icp_control_read: Bad offset %x\n", (int)offset); |
b5ff1b31 FB |
451 | return 0; |
452 | } | |
453 | } | |
454 | ||
a8170e5e | 455 | static void icp_control_write(void *opaque, hwaddr offset, |
0c36493e | 456 | uint64_t value, unsigned size) |
b5ff1b31 | 457 | { |
83d0cf89 JK |
458 | ICPCtrlRegsState *s = opaque; |
459 | ||
b5ff1b31 | 460 | switch (offset >> 2) { |
b5ff1b31 | 461 | case 2: /* CP_INTREG */ |
83d0cf89 JK |
462 | s->intreg_state &= ~(value & ICP_INTREG_CARDIN); |
463 | qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN)); | |
464 | break; | |
465 | case 1: /* CP_FLASHPROG */ | |
b5ff1b31 FB |
466 | case 3: /* CP_DECODE */ |
467 | /* Nothing interesting implemented yet. */ | |
468 | break; | |
469 | default: | |
2ac71179 | 470 | hw_error("icp_control_write: Bad offset %x\n", (int)offset); |
b5ff1b31 FB |
471 | } |
472 | } | |
b5ff1b31 | 473 | |
0c36493e BC |
474 | static const MemoryRegionOps icp_control_ops = { |
475 | .read = icp_control_read, | |
476 | .write = icp_control_write, | |
477 | .endianness = DEVICE_NATIVE_ENDIAN, | |
b5ff1b31 FB |
478 | }; |
479 | ||
83d0cf89 JK |
480 | static void icp_control_mmc_wprot(void *opaque, int line, int level) |
481 | { | |
482 | ICPCtrlRegsState *s = opaque; | |
483 | ||
484 | s->intreg_state &= ~ICP_INTREG_WPROT; | |
485 | if (level) { | |
486 | s->intreg_state |= ICP_INTREG_WPROT; | |
487 | } | |
488 | } | |
489 | ||
490 | static void icp_control_mmc_cardin(void *opaque, int line, int level) | |
491 | { | |
492 | ICPCtrlRegsState *s = opaque; | |
493 | ||
494 | /* line is released by writing to CP_INTREG */ | |
495 | if (level) { | |
496 | s->intreg_state |= ICP_INTREG_CARDIN; | |
497 | qemu_set_irq(s->mmc_irq, 1); | |
498 | } | |
499 | } | |
500 | ||
ffc8542a | 501 | static void icp_control_init(Object *obj) |
b5ff1b31 | 502 | { |
ffc8542a JK |
503 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
504 | ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj); | |
83d0cf89 | 505 | DeviceState *dev = DEVICE(obj); |
b5ff1b31 | 506 | |
ffc8542a JK |
507 | memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s, |
508 | "icp_ctrl_regs", 0x00800000); | |
509 | sysbus_init_mmio(sbd, &s->iomem); | |
83d0cf89 JK |
510 | |
511 | qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1); | |
512 | qdev_init_gpio_in_named(dev, icp_control_mmc_cardin, | |
513 | ICP_GPIO_MMC_CARDIN, 1); | |
514 | sysbus_init_irq(sbd, &s->mmc_irq); | |
b5ff1b31 FB |
515 | } |
516 | ||
517 | ||
b5ff1b31 FB |
518 | /* Board init. */ |
519 | ||
f93eb9ff AZ |
520 | static struct arm_boot_info integrator_binfo = { |
521 | .loader_start = 0x0, | |
522 | .board_id = 0x113, | |
523 | }; | |
524 | ||
3ef96221 | 525 | static void integratorcp_init(MachineState *machine) |
b5ff1b31 | 526 | { |
3ef96221 MA |
527 | ram_addr_t ram_size = machine->ram_size; |
528 | const char *cpu_model = machine->cpu_model; | |
529 | const char *kernel_filename = machine->kernel_filename; | |
530 | const char *kernel_cmdline = machine->kernel_cmdline; | |
531 | const char *initrd_filename = machine->initrd_filename; | |
223a72f1 GB |
532 | ObjectClass *cpu_oc; |
533 | Object *cpuobj; | |
393a9eab | 534 | ARMCPU *cpu; |
211adf4d AK |
535 | MemoryRegion *address_space_mem = get_system_memory(); |
536 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
537 | MemoryRegion *ram_alias = g_new(MemoryRegion, 1); | |
a7086888 | 538 | qemu_irq pic[32]; |
83d0cf89 | 539 | DeviceState *dev, *sic, *icp; |
a7086888 | 540 | int i; |
b5ff1b31 | 541 | |
393a9eab | 542 | if (!cpu_model) { |
3371d272 | 543 | cpu_model = "arm926"; |
393a9eab | 544 | } |
223a72f1 GB |
545 | |
546 | cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); | |
547 | if (!cpu_oc) { | |
aaed909a FB |
548 | fprintf(stderr, "Unable to find CPU definition\n"); |
549 | exit(1); | |
550 | } | |
393a9eab | 551 | |
223a72f1 GB |
552 | cpuobj = object_new(object_class_get_name(cpu_oc)); |
553 | ||
61e2f352 GB |
554 | /* By default ARM1176 CPUs have EL3 enabled. This board does not |
555 | * currently support EL3 so the CPU EL3 property is disabled before | |
556 | * realization. | |
557 | */ | |
558 | if (object_property_find(cpuobj, "has_el3", NULL)) { | |
007b0657 | 559 | object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); |
61e2f352 GB |
560 | } |
561 | ||
007b0657 | 562 | object_property_set_bool(cpuobj, true, "realized", &error_fatal); |
223a72f1 GB |
563 | |
564 | cpu = ARM_CPU(cpuobj); | |
565 | ||
c8623c02 DM |
566 | memory_region_allocate_system_memory(ram, NULL, "integrator.ram", |
567 | ram_size); | |
b5ff1b31 | 568 | /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ |
1235fc06 | 569 | /* ??? RAM should repeat to fill physical memory space. */ |
b5ff1b31 | 570 | /* SDRAM at address zero*/ |
211adf4d | 571 | memory_region_add_subregion(address_space_mem, 0, ram); |
b5ff1b31 | 572 | /* And again at address 0x80000000 */ |
2c9b15ca | 573 | memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size); |
211adf4d | 574 | memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); |
b5ff1b31 | 575 | |
257ec289 | 576 | dev = qdev_create(NULL, TYPE_INTEGRATOR_CM); |
ee6847d1 | 577 | qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); |
e23a1b33 | 578 | qdev_init_nofail(dev); |
a7086888 PB |
579 | sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); |
580 | ||
91b64626 | 581 | dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000, |
99d228d6 PM |
582 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), |
583 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), | |
584 | NULL); | |
a7086888 | 585 | for (i = 0; i < 32; i++) { |
067a3ddc | 586 | pic[i] = qdev_get_gpio_in(dev, i); |
a7086888 | 587 | } |
83d0cf89 | 588 | sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]); |
6a824ec3 PB |
589 | sysbus_create_varargs("integrator_pit", 0x13000000, |
590 | pic[5], pic[6], pic[7], NULL); | |
a63bdb31 | 591 | sysbus_create_simple("pl031", 0x15000000, pic[8]); |
f0d1d2c1 XZ |
592 | pl011_create(0x16000000, pic[1], serial_hds[0]); |
593 | pl011_create(0x17000000, pic[2], serial_hds[1]); | |
83d0cf89 JK |
594 | icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000, |
595 | qdev_get_gpio_in(sic, 3)); | |
86394e96 PB |
596 | sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); |
597 | sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); | |
b8616055 | 598 | sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0); |
83d0cf89 JK |
599 | |
600 | dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); | |
601 | qdev_connect_gpio_out(dev, 0, | |
602 | qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0)); | |
603 | qdev_connect_gpio_out(dev, 1, | |
604 | qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0)); | |
605 | ||
a005d073 | 606 | if (nd_table[0].used) |
0ae18cee | 607 | smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); |
2e9bdce5 PB |
608 | |
609 | sysbus_create_simple("pl110", 0xc0000000, pic[22]); | |
b5ff1b31 | 610 | |
f93eb9ff AZ |
611 | integrator_binfo.ram_size = ram_size; |
612 | integrator_binfo.kernel_filename = kernel_filename; | |
613 | integrator_binfo.kernel_cmdline = kernel_cmdline; | |
614 | integrator_binfo.initrd_filename = initrd_filename; | |
3aaa8dfa | 615 | arm_load_kernel(cpu, &integrator_binfo); |
b5ff1b31 FB |
616 | } |
617 | ||
e264d29d | 618 | static void integratorcp_machine_init(MachineClass *mc) |
f80f9ec9 | 619 | { |
e264d29d EH |
620 | mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; |
621 | mc->init = integratorcp_init; | |
f80f9ec9 AL |
622 | } |
623 | ||
e264d29d | 624 | DEFINE_MACHINE("integratorcp", integratorcp_machine_init) |
f80f9ec9 | 625 | |
999e12bb | 626 | static Property core_properties[] = { |
257ec289 | 627 | DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), |
999e12bb AL |
628 | DEFINE_PROP_END_OF_LIST(), |
629 | }; | |
630 | ||
631 | static void core_class_init(ObjectClass *klass, void *data) | |
632 | { | |
39bffca2 | 633 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 634 | |
39bffca2 | 635 | dc->props = core_properties; |
999e12bb AL |
636 | } |
637 | ||
8c43a6f0 | 638 | static const TypeInfo core_info = { |
257ec289 | 639 | .name = TYPE_INTEGRATOR_CM, |
39bffca2 | 640 | .parent = TYPE_SYS_BUS_DEVICE, |
257ec289 | 641 | .instance_size = sizeof(IntegratorCMState), |
a1f42e0c | 642 | .instance_init = integratorcm_init, |
39bffca2 | 643 | .class_init = core_class_init, |
999e12bb AL |
644 | }; |
645 | ||
8c43a6f0 | 646 | static const TypeInfo icp_pic_info = { |
91b64626 | 647 | .name = TYPE_INTEGRATOR_PIC, |
39bffca2 AL |
648 | .parent = TYPE_SYS_BUS_DEVICE, |
649 | .instance_size = sizeof(icp_pic_state), | |
a1f42e0c | 650 | .instance_init = icp_pic_init, |
ee6847d1 GH |
651 | }; |
652 | ||
ffc8542a JK |
653 | static const TypeInfo icp_ctrl_regs_info = { |
654 | .name = TYPE_ICP_CONTROL_REGS, | |
655 | .parent = TYPE_SYS_BUS_DEVICE, | |
656 | .instance_size = sizeof(ICPCtrlRegsState), | |
657 | .instance_init = icp_control_init, | |
658 | }; | |
659 | ||
83f7d43a | 660 | static void integratorcp_register_types(void) |
a7086888 | 661 | { |
39bffca2 AL |
662 | type_register_static(&icp_pic_info); |
663 | type_register_static(&core_info); | |
ffc8542a | 664 | type_register_static(&icp_ctrl_regs_info); |
a7086888 PB |
665 | } |
666 | ||
83f7d43a | 667 | type_init(integratorcp_register_types) |