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hw/arm: Hook up FSI module in AST2600
[mirror_qemu.git] / hw / arm / omap2.c
CommitLineData
827df9f3
AZ		 1/*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2007-2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
fad6cb1a 17 * You should have received a copy of the GNU General Public License along
8167ee88 18 * with this program; if not, see <http://www.gnu.org/licenses/>.
827df9f3 19 */
666daa68 20
12b16722 21#include "qemu/osdep.h"
c0dbca36 22#include "qemu/error-report.h"
da34e65c 23#include "qapi/error.h"
e285e867 24#include "exec/address-spaces.h"
12e9493d 25#include "sysemu/blockdev.h"
a82929a2 26#include "sysemu/qtest.h"
71e8a915 27#include "sysemu/reset.h"
54d31236 28#include "sysemu/runstate.h"
64552b6b 29#include "hw/irq.h"
a27bd6c7 30#include "hw/qdev-properties.h"
12ec8bd5 31#include "hw/arm/boot.h"
0d09e41a 32#include "hw/arm/omap.h"
9c17d615 33#include "sysemu/sysemu.h"
1de7afc9 34#include "qemu/timer.h"
4d43a603 35#include "chardev/char-fe.h"
0d09e41a
PB		 36#include "hw/block/flash.h"
37#include "hw/arm/soc_dma.h"
83c9f4ca 38#include "hw/sysbus.h"
b8ab0303 39#include "hw/boards.h"
99570a40 40#include "audio/audio.h"
d780d056 41#include "target/arm/cpu-qom.h"
827df9f3 42
99570a40
AZ		 43/* Enhanced Audio Controller (CODEC only) */
44struct omap_eac_s {
99570a40 45 qemu_irq irq;
9bac7d6c 46 MemoryRegion iomem;
99570a40
AZ		 47
48 uint16_t sysconfig;
49 uint8_t config[4];
50 uint8_t control;
51 uint8_t address;
52 uint16_t data;
53 uint8_t vtol;
54 uint8_t vtsl;
55 uint16_t mixer;
56 uint16_t gain[4];
57 uint8_t att;
58 uint16_t max[7];
59
60 struct {
61 qemu_irq txdrq;
62 qemu_irq rxdrq;
63 uint32_t (*txrx)(void *opaque, uint32_t, int);
64 void *opaque;
65
66#define EAC_BUF_LEN 1024
67 uint32_t rxbuf[EAC_BUF_LEN];
ab17b46d 68 int rxoff;
99570a40
AZ		 69 int rxlen;
70 int rxavail;
71 uint32_t txbuf[EAC_BUF_LEN];
72 int txlen;
73 int txavail;
74
75 int enable;
76 int rate;
77
78 uint16_t config[4];
79
80 /* These need to be moved to the actual codec */
81 QEMUSoundCard card;
82 SWVoiceIn *in_voice;
83 SWVoiceOut *out_voice;
84 int hw_enable;
85 } codec;
86
87 struct {
88 uint8_t control;
89 uint16_t config;
90 } modem, bt;
91};
92
93static inline void omap_eac_interrupt_update(struct omap_eac_s *s)
94{
95 qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */
96}
97
98static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s)
99{
ab17b46d 100 qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) &&
99570a40
AZ		 101 ((s->codec.config[1] >> 12) & 1)); /* DMAREN */
102}
103
104static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s)
105{
106 qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail &&
107 ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */
108}
109
110static inline void omap_eac_in_refill(struct omap_eac_s *s)
111{
ab17b46d
AZ		 112 int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2;
113 int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2;
114 int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start);
115 int recv = 1;
116 uint8_t *buf = (uint8_t *) s->codec.rxbuf + start;
117
118 left -= leftwrap;
119 start = 0;
120 while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start,
121 leftwrap)) > 0) { /* Be defensive */
122 start += recv;
123 leftwrap -= recv;
124 }
125 if (recv <= 0)
126 s->codec.rxavail = 0;
127 else
128 s->codec.rxavail -= start >> 2;
129 s->codec.rxlen += start >> 2;
130
131 if (recv > 0 && left > 0) {
132 start = 0;
133 while (left && (recv = AUD_read(s->codec.in_voice,
134 (uint8_t *) s->codec.rxbuf + start,
135 left)) > 0) { /* Be defensive */
136 start += recv;
137 left -= recv;
138 }
139 if (recv <= 0)
140 s->codec.rxavail = 0;
141 else
142 s->codec.rxavail -= start >> 2;
143 s->codec.rxlen += start >> 2;
144 }
99570a40
AZ		 145}
146
147static inline void omap_eac_out_empty(struct omap_eac_s *s)
148{
ab17b46d
AZ		 149 int left = s->codec.txlen << 2;
150 int start = 0;
151 int sent = 1;
152
153 while (left && (sent = AUD_write(s->codec.out_voice,
154 (uint8_t *) s->codec.txbuf + start,
155 left)) > 0) { /* Be defensive */
156 start += sent;
157 left -= sent;
158 }
99570a40 159
ab17b46d
AZ		 160 if (!sent) {
161 s->codec.txavail = 0;
162 omap_eac_out_dmarequest_update(s);
163 }
99570a40 164
ab17b46d
AZ		 165 if (start)
166 s->codec.txlen = 0;
99570a40
AZ		 167}
168
169static void omap_eac_in_cb(void *opaque, int avail_b)
170{
a75ed3c4 171 struct omap_eac_s *s = opaque;
99570a40
AZ		 172
173 s->codec.rxavail = avail_b >> 2;
ab17b46d 174 omap_eac_in_refill(s);
99570a40 175 /* TODO: possibly discard current buffer if overrun */
ab17b46d 176 omap_eac_in_dmarequest_update(s);
99570a40
AZ		 177}
178
179static void omap_eac_out_cb(void *opaque, int free_b)
180{
a75ed3c4 181 struct omap_eac_s *s = opaque;
99570a40
AZ		 182
183 s->codec.txavail = free_b >> 2;
ab17b46d
AZ		 184 if (s->codec.txlen)
185 omap_eac_out_empty(s);
186 else
187 omap_eac_out_dmarequest_update(s);
99570a40
AZ		 188}
189
190static void omap_eac_enable_update(struct omap_eac_s *s)
191{
192 s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */
193 (s->codec.config[1] & 2) && /* AUDEN */
194 s->codec.hw_enable;
195}
196
197static const int omap_eac_fsint[4] = {
198 8000,
199 11025,
200 22050,
201 44100,
202};
203
204static const int omap_eac_fsint2[8] = {
205 8000,
206 11025,
207 22050,
208 44100,
209 48000,
210 0, 0, 0,
211};
212
213static const int omap_eac_fsint3[16] = {
214 8000,
215 11025,
216 16000,
217 22050,
218 24000,
219 32000,
220 44100,
221 48000,
222 0, 0, 0, 0, 0, 0, 0, 0,
223};
224
225static void omap_eac_rate_update(struct omap_eac_s *s)
226{
227 int fsint[3];
228
229 fsint[2] = (s->codec.config[3] >> 9) & 0xf;
230 fsint[1] = (s->codec.config[2] >> 0) & 0x7;
231 fsint[0] = (s->codec.config[0] >> 6) & 0x3;
232 if (fsint[2] < 0xf)
233 s->codec.rate = omap_eac_fsint3[fsint[2]];
234 else if (fsint[1] < 0x7)
235 s->codec.rate = omap_eac_fsint2[fsint[1]];
236 else
237 s->codec.rate = omap_eac_fsint[fsint[0]];
238}
239
240static void omap_eac_volume_update(struct omap_eac_s *s)
241{
242 /* TODO */
243}
244
245static void omap_eac_format_update(struct omap_eac_s *s)
246{
1ea879e5 247 struct audsettings fmt;
99570a40 248
ab17b46d
AZ		 249 /* The hardware buffers at most one sample */
250 if (s->codec.rxlen)
251 s->codec.rxlen = 1;
99570a40
AZ		 252
253 if (s->codec.in_voice) {
254 AUD_set_active_in(s->codec.in_voice, 0);
255 AUD_close_in(&s->codec.card, s->codec.in_voice);
b9d38e95 256 s->codec.in_voice = NULL;
99570a40
AZ		 257 }
258 if (s->codec.out_voice) {
ab17b46d 259 omap_eac_out_empty(s);
99570a40
AZ		 260 AUD_set_active_out(s->codec.out_voice, 0);
261 AUD_close_out(&s->codec.card, s->codec.out_voice);
b9d38e95 262 s->codec.out_voice = NULL;
ab17b46d 263 s->codec.txavail = 0;
99570a40 264 }
ab17b46d
AZ		 265 /* Discard what couldn't be written */
266 s->codec.txlen = 0;
99570a40
AZ		 267
268 omap_eac_enable_update(s);
269 if (!s->codec.enable)
270 return;
271
272 omap_eac_rate_update(s);
273 fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */
274 fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
275 fmt.freq = s->codec.rate;
276 /* TODO: signedness possibly depends on the CODEC hardware - or
277 * does I2S specify it? */
a07d9df0 278 /* All register writes are 16 bits so we store 16-bit samples
99570a40 279 * in the buffers regardless of AGCFR[B8_16] value. */
85bc5852 280 fmt.fmt = AUDIO_FORMAT_U16;
99570a40
AZ		 281
282 s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice,
283 "eac.codec.in", s, omap_eac_in_cb, &fmt);
284 s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice,
285 "eac.codec.out", s, omap_eac_out_cb, &fmt);
286
287 omap_eac_volume_update(s);
288
289 AUD_set_active_in(s->codec.in_voice, 1);
290 AUD_set_active_out(s->codec.out_voice, 1);
291}
292
293static void omap_eac_reset(struct omap_eac_s *s)
294{
295 s->sysconfig = 0;
296 s->config[0] = 0x0c;
297 s->config[1] = 0x09;
298 s->config[2] = 0xab;
299 s->config[3] = 0x03;
300 s->control = 0x00;
301 s->address = 0x00;
302 s->data = 0x0000;
303 s->vtol = 0x00;
304 s->vtsl = 0x00;
305 s->mixer = 0x0000;
306 s->gain[0] = 0xe7e7;
307 s->gain[1] = 0x6767;
308 s->gain[2] = 0x6767;
309 s->gain[3] = 0x6767;
310 s->att = 0xce;
311 s->max[0] = 0;
312 s->max[1] = 0;
313 s->max[2] = 0;
314 s->max[3] = 0;
315 s->max[4] = 0;
316 s->max[5] = 0;
317 s->max[6] = 0;
318
319 s->modem.control = 0x00;
320 s->modem.config = 0x0000;
321 s->bt.control = 0x00;
322 s->bt.config = 0x0000;
323 s->codec.config[0] = 0x0649;
324 s->codec.config[1] = 0x0000;
325 s->codec.config[2] = 0x0007;
326 s->codec.config[3] = 0x1ffc;
ab17b46d 327 s->codec.rxoff = 0;
99570a40
AZ		 328 s->codec.rxlen = 0;
329 s->codec.txlen = 0;
330 s->codec.rxavail = 0;
331 s->codec.txavail = 0;
332
333 omap_eac_format_update(s);
334 omap_eac_interrupt_update(s);
335}
336
a75ed3c4 337static uint64_t omap_eac_read(void *opaque, hwaddr addr, unsigned size)
99570a40 338{
a75ed3c4 339 struct omap_eac_s *s = opaque;
ab17b46d 340 uint32_t ret;
99570a40 341
9bac7d6c
AK		 342 if (size != 2) {
343 return omap_badwidth_read16(opaque, addr);
344 }
345
8da3ff18 346 switch (addr) {
99570a40
AZ		 347 case 0x000: /* CPCFR1 */
348 return s->config[0];
349 case 0x004: /* CPCFR2 */
350 return s->config[1];
351 case 0x008: /* CPCFR3 */
352 return s->config[2];
353 case 0x00c: /* CPCFR4 */
354 return s->config[3];
355
356 case 0x010: /* CPTCTL */
357 return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) |
358 ((s->codec.txlen < s->codec.txavail) << 5);
359
360 case 0x014: /* CPTTADR */
361 return s->address;
362 case 0x018: /* CPTDATL */
363 return s->data & 0xff;
364 case 0x01c: /* CPTDATH */
365 return s->data >> 8;
366 case 0x020: /* CPTVSLL */
367 return s->vtol;
368 case 0x024: /* CPTVSLH */
369 return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */
370 case 0x040: /* MPCTR */
371 return s->modem.control;
372 case 0x044: /* MPMCCFR */
373 return s->modem.config;
374 case 0x060: /* BPCTR */
375 return s->bt.control;
376 case 0x064: /* BPMCCFR */
377 return s->bt.config;
378 case 0x080: /* AMSCFR */
379 return s->mixer;
380 case 0x084: /* AMVCTR */
381 return s->gain[0];
382 case 0x088: /* AM1VCTR */
383 return s->gain[1];
384 case 0x08c: /* AM2VCTR */
385 return s->gain[2];
386 case 0x090: /* AM3VCTR */
387 return s->gain[3];
388 case 0x094: /* ASTCTR */
389 return s->att;
390 case 0x098: /* APD1LCR */
391 return s->max[0];
392 case 0x09c: /* APD1RCR */
393 return s->max[1];
394 case 0x0a0: /* APD2LCR */
395 return s->max[2];
396 case 0x0a4: /* APD2RCR */
397 return s->max[3];
398 case 0x0a8: /* APD3LCR */
399 return s->max[4];
400 case 0x0ac: /* APD3RCR */
401 return s->max[5];
402 case 0x0b0: /* APD4R */
403 return s->max[6];
404 case 0x0b4: /* ADWR */
405 /* This should be write-only? Docs list it as read-only. */
406 return 0x0000;
407 case 0x0b8: /* ADRDR */
ab17b46d
AZ		 408 if (likely(s->codec.rxlen > 1)) {
409 ret = s->codec.rxbuf[s->codec.rxoff ++];
410 s->codec.rxlen --;
411 s->codec.rxoff &= EAC_BUF_LEN - 1;
412 return ret;
413 } else if (s->codec.rxlen) {
414 ret = s->codec.rxbuf[s->codec.rxoff ++];
415 s->codec.rxlen --;
416 s->codec.rxoff &= EAC_BUF_LEN - 1;
99570a40
AZ		 417 if (s->codec.rxavail)
418 omap_eac_in_refill(s);
ab17b46d
AZ		 419 omap_eac_in_dmarequest_update(s);
420 return ret;
99570a40
AZ		 421 }
422 return 0x0000;
423 case 0x0bc: /* AGCFR */
424 return s->codec.config[0];
425 case 0x0c0: /* AGCTR */
426 return s->codec.config[1] | ((s->codec.config[1] & 2) << 14);
427 case 0x0c4: /* AGCFR2 */
428 return s->codec.config[2];
429 case 0x0c8: /* AGCFR3 */
430 return s->codec.config[3];
431 case 0x0cc: /* MBPDMACTR */
432 case 0x0d0: /* MPDDMARR */
433 case 0x0d8: /* MPUDMARR */
434 case 0x0e4: /* BPDDMARR */
435 case 0x0ec: /* BPUDMARR */
436 return 0x0000;
437
438 case 0x100: /* VERSION_NUMBER */
439 return 0x0010;
440
441 case 0x104: /* SYSCONFIG */
442 return s->sysconfig;
443
444 case 0x108: /* SYSSTATUS */
445 return 1 | 0xe; /* RESETDONE | stuff */
446 }
447
448 OMAP_BAD_REG(addr);
449 return 0;
450}
451
a8170e5e 452static void omap_eac_write(void *opaque, hwaddr addr,
9bac7d6c 453 uint64_t value, unsigned size)
99570a40 454{
a75ed3c4 455 struct omap_eac_s *s = opaque;
99570a40 456
9bac7d6c 457 if (size != 2) {
77a8257e
SW		 458 omap_badwidth_write16(opaque, addr, value);
459 return;
9bac7d6c
AK		 460 }
461
8da3ff18 462 switch (addr) {
99570a40
AZ		 463 case 0x098: /* APD1LCR */
464 case 0x09c: /* APD1RCR */
465 case 0x0a0: /* APD2LCR */
466 case 0x0a4: /* APD2RCR */
467 case 0x0a8: /* APD3LCR */
468 case 0x0ac: /* APD3RCR */
469 case 0x0b0: /* APD4R */
470 case 0x0b8: /* ADRDR */
471 case 0x0d0: /* MPDDMARR */
472 case 0x0d8: /* MPUDMARR */
473 case 0x0e4: /* BPDDMARR */
474 case 0x0ec: /* BPUDMARR */
475 case 0x100: /* VERSION_NUMBER */
476 case 0x108: /* SYSSTATUS */
477 OMAP_RO_REG(addr);
478 return;
479
480 case 0x000: /* CPCFR1 */
481 s->config[0] = value & 0xff;
482 omap_eac_format_update(s);
483 break;
484 case 0x004: /* CPCFR2 */
485 s->config[1] = value & 0xff;
486 omap_eac_format_update(s);
487 break;
488 case 0x008: /* CPCFR3 */
489 s->config[2] = value & 0xff;
490 omap_eac_format_update(s);
491 break;
492 case 0x00c: /* CPCFR4 */
493 s->config[3] = value & 0xff;
494 omap_eac_format_update(s);
495 break;
496
497 case 0x010: /* CPTCTL */
498 /* Assuming TXF and TXE bits are read-only... */
499 s->control = value & 0x5f;
500 omap_eac_interrupt_update(s);
501 break;
502
503 case 0x014: /* CPTTADR */
504 s->address = value & 0xff;
505 break;
506 case 0x018: /* CPTDATL */
507 s->data &= 0xff00;
508 s->data |= value & 0xff;
509 break;
510 case 0x01c: /* CPTDATH */
511 s->data &= 0x00ff;
512 s->data |= value << 8;
513 break;
514 case 0x020: /* CPTVSLL */
515 s->vtol = value & 0xf8;
516 break;
517 case 0x024: /* CPTVSLH */
518 s->vtsl = value & 0x9f;
519 break;
520 case 0x040: /* MPCTR */
521 s->modem.control = value & 0x8f;
522 break;
523 case 0x044: /* MPMCCFR */
524 s->modem.config = value & 0x7fff;
525 break;
526 case 0x060: /* BPCTR */
527 s->bt.control = value & 0x8f;
528 break;
529 case 0x064: /* BPMCCFR */
530 s->bt.config = value & 0x7fff;
531 break;
532 case 0x080: /* AMSCFR */
533 s->mixer = value & 0x0fff;
534 break;
535 case 0x084: /* AMVCTR */
536 s->gain[0] = value & 0xffff;
537 break;
538 case 0x088: /* AM1VCTR */
539 s->gain[1] = value & 0xff7f;
540 break;
541 case 0x08c: /* AM2VCTR */
542 s->gain[2] = value & 0xff7f;
543 break;
544 case 0x090: /* AM3VCTR */
545 s->gain[3] = value & 0xff7f;
546 break;
547 case 0x094: /* ASTCTR */
548 s->att = value & 0xff;
549 break;
550
551 case 0x0b4: /* ADWR */
552 s->codec.txbuf[s->codec.txlen ++] = value;
553 if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
554 s->codec.txlen == s->codec.txavail)) {
555 if (s->codec.txavail)
556 omap_eac_out_empty(s);
ab17b46d
AZ		 557 /* Discard what couldn't be written */
558 s->codec.txlen = 0;
99570a40
AZ		 559 }
560 break;
561
562 case 0x0bc: /* AGCFR */
563 s->codec.config[0] = value & 0x07ff;
564 omap_eac_format_update(s);
565 break;
566 case 0x0c0: /* AGCTR */
567 s->codec.config[1] = value & 0x780f;
568 omap_eac_format_update(s);
569 break;
570 case 0x0c4: /* AGCFR2 */
571 s->codec.config[2] = value & 0x003f;
572 omap_eac_format_update(s);
573 break;
574 case 0x0c8: /* AGCFR3 */
575 s->codec.config[3] = value & 0xffff;
576 omap_eac_format_update(s);
577 break;
578 case 0x0cc: /* MBPDMACTR */
579 case 0x0d4: /* MPDDMAWR */
580 case 0x0e0: /* MPUDMAWR */
581 case 0x0e8: /* BPDDMAWR */
582 case 0x0f0: /* BPUDMAWR */
583 break;
584
585 case 0x104: /* SYSCONFIG */
586 if (value & (1 << 1)) /* SOFTRESET */
587 omap_eac_reset(s);
588 s->sysconfig = value & 0x31d;
589 break;
590
591 default:
592 OMAP_BAD_REG(addr);
593 return;
594 }
595}
596
9bac7d6c
AK		 597static const MemoryRegionOps omap_eac_ops = {
598 .read = omap_eac_read,
599 .write = omap_eac_write,
600 .endianness = DEVICE_NATIVE_ENDIAN,
99570a40
AZ		 601};
602
c1ff227b 603static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
99570a40
AZ		 604 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
605{
b45c03f5 606 struct omap_eac_s *s = g_new0(struct omap_eac_s, 1);
99570a40
AZ		 607
608 s->irq = irq;
609 s->codec.rxdrq = *drq ++;
22ed1d34 610 s->codec.txdrq = *drq;
99570a40
AZ		 611 omap_eac_reset(s);
612
b8ab0303
MK		 613 if (current_machine->audiodev) {
614 s->codec.card.name = g_strdup(current_machine->audiodev);
615 s->codec.card.state = audio_state_by_name(s->codec.card.name, &error_fatal);
616 }
cb94ff5f 617 AUD_register_card("OMAP EAC", &s->codec.card, &error_fatal);
99570a40 618
2c9b15ca 619 memory_region_init_io(&s->iomem, NULL, &omap_eac_ops, s, "omap.eac",
9bac7d6c 620 omap_l4_region_size(ta, 0));
f44336c5 621 omap_l4_attach(ta, 0, &s->iomem);
99570a40
AZ		 622
623 return s;
624}
625
54585ffe
AZ		 626/* STI/XTI (emulation interface) console - reverse engineered only */
627struct omap_sti_s {
54585ffe 628 qemu_irq irq;
9bac7d6c
AK		 629 MemoryRegion iomem;
630 MemoryRegion iomem_fifo;
32a6ebec 631 CharBackend chr;
54585ffe
AZ		 632
633 uint32_t sysconfig;
634 uint32_t systest;
635 uint32_t irqst;
636 uint32_t irqen;
637 uint32_t clkcontrol;
638 uint32_t serial_config;
639};
640
641#define STI_TRACE_CONSOLE_CHANNEL 239
642#define STI_TRACE_CONTROL_CHANNEL 253
643
644static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
645{
646 qemu_set_irq(s->irq, s->irqst & s->irqen);
647}
648
649static void omap_sti_reset(struct omap_sti_s *s)
650{
651 s->sysconfig = 0;
652 s->irqst = 0;
653 s->irqen = 0;
654 s->clkcontrol = 0;
655 s->serial_config = 0;
656
657 omap_sti_interrupt_update(s);
658}
659
a8170e5e 660static uint64_t omap_sti_read(void *opaque, hwaddr addr,
9bac7d6c 661 unsigned size)
54585ffe 662{
a75ed3c4 663 struct omap_sti_s *s = opaque;
54585ffe 664
9bac7d6c
AK		 665 if (size != 4) {
666 return omap_badwidth_read32(opaque, addr);
667 }
668
8da3ff18 669 switch (addr) {
54585ffe
AZ		 670 case 0x00: /* STI_REVISION */
671 return 0x10;
672
673 case 0x10: /* STI_SYSCONFIG */
674 return s->sysconfig;
675
676 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
677 return 0x00;
678
679 case 0x18: /* STI_IRQSTATUS */
680 return s->irqst;
681
682 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
683 return s->irqen;
684
685 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
686 case 0x28: /* STI_RX_DR / XTI_RXDATA */
e927bb00
AZ		 687 /* TODO */
688 return 0;
54585ffe
AZ		 689
690 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
691 return s->clkcontrol;
692
693 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
694 return s->serial_config;
695 }
696
697 OMAP_BAD_REG(addr);
698 return 0;
699}
700
a8170e5e 701static void omap_sti_write(void *opaque, hwaddr addr,
9bac7d6c 702 uint64_t value, unsigned size)
54585ffe 703{
a75ed3c4 704 struct omap_sti_s *s = opaque;
54585ffe 705
9bac7d6c 706 if (size != 4) {
77a8257e
SW		 707 omap_badwidth_write32(opaque, addr, value);
708 return;
9bac7d6c
AK		 709 }
710
8da3ff18 711 switch (addr) {
54585ffe
AZ		 712 case 0x00: /* STI_REVISION */
713 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
714 OMAP_RO_REG(addr);
715 return;
716
717 case 0x10: /* STI_SYSCONFIG */
718 if (value & (1 << 1)) /* SOFTRESET */
719 omap_sti_reset(s);
720 s->sysconfig = value & 0xfe;
721 break;
722
723 case 0x18: /* STI_IRQSTATUS */
724 s->irqst &= ~value;
725 omap_sti_interrupt_update(s);
726 break;
727
728 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
729 s->irqen = value & 0xffff;
730 omap_sti_interrupt_update(s);
731 break;
732
733 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
734 s->clkcontrol = value & 0xff;
735 break;
736
737 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
738 s->serial_config = value & 0xff;
739 break;
740
741 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
742 case 0x28: /* STI_RX_DR / XTI_RXDATA */
e927bb00
AZ		 743 /* TODO */
744 return;
745
54585ffe
AZ		 746 default:
747 OMAP_BAD_REG(addr);
748 return;
749 }
750}
751
9bac7d6c
AK		 752static const MemoryRegionOps omap_sti_ops = {
753 .read = omap_sti_read,
754 .write = omap_sti_write,
755 .endianness = DEVICE_NATIVE_ENDIAN,
54585ffe
AZ		 756};
757
a75ed3c4 758static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr, unsigned size)
54585ffe
AZ		 759{
760 OMAP_BAD_REG(addr);
761 return 0;
762}
763
a8170e5e 764static void omap_sti_fifo_write(void *opaque, hwaddr addr,
9bac7d6c 765 uint64_t value, unsigned size)
54585ffe 766{
a75ed3c4 767 struct omap_sti_s *s = opaque;
8da3ff18 768 int ch = addr >> 6;
54585ffe
AZ		 769 uint8_t byte = value;
770
9bac7d6c 771 if (size != 1) {
77a8257e
SW		 772 omap_badwidth_write8(opaque, addr, size);
773 return;
9bac7d6c
AK		 774 }
775
54585ffe
AZ		 776 if (ch == STI_TRACE_CONTROL_CHANNEL) {
777 /* Flush channel <i>value</i>. */
6ab3fc32
DB		 778 /* XXX this blocks entire thread. Rewrite to use
779 * qemu_chr_fe_write and background I/O callbacks */
5345fdb4 780 qemu_chr_fe_write_all(&s->chr, (const uint8_t *) "\r", 1);
54585ffe
AZ		 781 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
782 if (value == 0xc0 || value == 0xc3) {
783 /* Open channel <i>ch</i>. */
5345fdb4
MAL		 784 } else if (value == 0x00) {
785 qemu_chr_fe_write_all(&s->chr, (const uint8_t *) "\n", 1);
786 } else {
787 qemu_chr_fe_write_all(&s->chr, &byte, 1);
788 }
54585ffe
AZ		 789 }
790}
791
9bac7d6c
AK		 792static const MemoryRegionOps omap_sti_fifo_ops = {
793 .read = omap_sti_fifo_read,
794 .write = omap_sti_fifo_write,
795 .endianness = DEVICE_NATIVE_ENDIAN,
54585ffe
AZ		 796};
797
b1d8e52e 798static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
9bac7d6c 799 MemoryRegion *sysmem,
a8170e5e 800 hwaddr channel_base, qemu_irq irq, omap_clk clk,
0ec7b3e7 801 Chardev *chr)
54585ffe 802{
b45c03f5 803 struct omap_sti_s *s = g_new0(struct omap_sti_s, 1);
54585ffe
AZ		 804
805 s->irq = irq;
806 omap_sti_reset(s);
807
4ad6f6cb 808 qemu_chr_fe_init(&s->chr, chr ?: qemu_chr_new("null", "null", NULL),
32a6ebec 809 &error_abort);
54585ffe 810
2c9b15ca 811 memory_region_init_io(&s->iomem, NULL, &omap_sti_ops, s, "omap.sti",
9bac7d6c 812 omap_l4_region_size(ta, 0));
f44336c5 813 omap_l4_attach(ta, 0, &s->iomem);
54585ffe 814
2c9b15ca 815 memory_region_init_io(&s->iomem_fifo, NULL, &omap_sti_fifo_ops, s,
9bac7d6c
AK		 816 "omap.sti.fifo", 0x10000);
817 memory_region_add_subregion(sysmem, channel_base, &s->iomem_fifo);
54585ffe
AZ		 818
819 return s;
820}
821
827df9f3 822/* L4 Interconnect */
827df9f3
AZ		 823#define L4TA(n) (n)
824#define L4TAO(n) ((n) + 39)
825
2c1d9ecb 826static const struct omap_l4_region_s omap_l4_region[125] = {
827df9f3
AZ		 827 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
828 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
829 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
830 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
831 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
832 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
833 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
834 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
835 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
836 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
837 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
838 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
839 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
840 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
841 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
842 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
843 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
844 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
845 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
846 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
847 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
848 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
849 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
850 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
851 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
852 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
853 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
854 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
855 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
856 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
857 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
858 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
859 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
860 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
861 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
862 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
863 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
864 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
865 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
866 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
867 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
868 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
869 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
870 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
871 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
872 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
873 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
874 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
875 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
876 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
877 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
878 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
879 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
880 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
881 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
882 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
883 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
884 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
885 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
886 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
887 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
888 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
889 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
890 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
891 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
892 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
893 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
894 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
895 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
896 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
897 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
898 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
899 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
900 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
901 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
902 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
903 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
904 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
905 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
906 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
907 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
908 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
909 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
910 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
911 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
912 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
913 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
914 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
915 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
916 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
917 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
918 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
919 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
920 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
921 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
922 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
923 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
924 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
925 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
926 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
927 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
928 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
929 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
930 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
931 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
932 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
933 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
934 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
935 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
936 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
937 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
938 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */
939 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
940 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
941 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
942 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
943 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
944 [117] = { 0xa6000, 0x1000, 32 }, /* AES */
945 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
946 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */
947 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
948 [121] = { 0xb0000, 0x1000, 32 }, /* MG */
949 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
950 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
951 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
952};
953
2c1d9ecb 954static const struct omap_l4_agent_info_s omap_l4_agent_info[54] = {
827df9f3
AZ		 955 { 0, 0, 3, 2 }, /* L4IA initiatior agent */
956 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
957 { L4TAO(2), 5, 2, 1 }, /* 32K timer */
958 { L4TAO(3), 7, 3, 2 }, /* PRCM */
959 { L4TA(1), 10, 2, 1 }, /* BCM */
960 { L4TA(2), 12, 2, 1 }, /* Test JTAG */
961 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */
962 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
963 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */
964 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
965 { L4TA(10), 28, 5, 4 }, /* Display subsystem */
966 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */
967 { L4TA(12), 38, 2, 1 }, /* sDMA */
968 { L4TA(13), 40, 5, 4 }, /* SSI */
969 { L4TAO(4), 45, 2, 1 }, /* USB */
970 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
971 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
972 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
973 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
974 { L4TA(18), 55, 2, 1 }, /* XTI */
975 { L4TA(19), 57, 2, 1 }, /* UART1 */
976 { L4TA(20), 59, 2, 1 }, /* UART2 */
977 { L4TA(21), 61, 2, 1 }, /* UART3 */
978 { L4TAO(5), 63, 2, 1 }, /* I2C1 */
979 { L4TAO(6), 65, 2, 1 }, /* I2C2 */
980 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */
981 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */
982 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
983 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
984 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
985 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
986 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
987 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
988 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
989 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
990 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
991 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
992 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
993 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
994 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
995 { L4TA(32), 97, 2, 1 }, /* EAC */
996 { L4TA(33), 99, 2, 1 }, /* FAC */
997 { L4TA(34), 101, 2, 1 }, /* IPC */
998 { L4TA(35), 103, 2, 1 }, /* SPI1 */
999 { L4TA(36), 105, 2, 1 }, /* SPI2 */
1000 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
1001 { L4TAO(10), 109, 2, 1 },
1002 { L4TAO(11), 111, 2, 1 }, /* RNG */
1003 { L4TAO(12), 113, 2, 1 }, /* DES3DES */
1004 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
1005 { L4TA(37), 117, 2, 1 }, /* AES */
1006 { L4TA(38), 119, 2, 1 }, /* PKA */
1007 { -1, 121, 2, 1 },
1008 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
1009};
1010
2c1d9ecb 1011#define omap_l4ta(bus, cs) \
1012 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TA(cs))
1013#define omap_l4tao(bus, cs) \
1014 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TAO(cs))
827df9f3 1015
827df9f3
AZ		 1016/* Power, Reset, and Clock Management */
1017struct omap_prcm_s {
827df9f3
AZ		 1018 qemu_irq irq[3];
1019 struct omap_mpu_state_s *mpu;
011a98a1
AK		 1020 MemoryRegion iomem0;
1021 MemoryRegion iomem1;
827df9f3
AZ		 1022
1023 uint32_t irqst[3];
1024 uint32_t irqen[3];
1025
1026 uint32_t sysconfig;
1027 uint32_t voltctrl;
1028 uint32_t scratch[20];
1029
1030 uint32_t clksrc[1];
1031 uint32_t clkout[1];
1032 uint32_t clkemul[1];
1033 uint32_t clkpol[1];
1034 uint32_t clksel[8];
1035 uint32_t clken[12];
1036 uint32_t clkctrl[4];
1037 uint32_t clkidle[7];
1038 uint32_t setuptime[2];
1039
1040 uint32_t wkup[3];
1041 uint32_t wken[3];
1042 uint32_t wkst[3];
1043 uint32_t rst[4];
1044 uint32_t rstctrl[1];
1045 uint32_t power[4];
1046 uint32_t rsttime_wkup;
1047
1048 uint32_t ev;
1049 uint32_t evtime[2];
51fec3cc
AZ		 1050
1051 int dpll_lock, apll_lock[2];
827df9f3
AZ		 1052};
1053
1054static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
1055{
1056 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]);
1057 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
1058}
1059
a8170e5e 1060static uint64_t omap_prcm_read(void *opaque, hwaddr addr,
011a98a1 1061 unsigned size)
827df9f3 1062{
a75ed3c4 1063 struct omap_prcm_s *s = opaque;
51fec3cc 1064 uint32_t ret;
827df9f3 1065
011a98a1
AK		 1066 if (size != 4) {
1067 return omap_badwidth_read32(opaque, addr);
1068 }
1069
8da3ff18 1070 switch (addr) {
827df9f3
AZ		 1071 case 0x000: /* PRCM_REVISION */
1072 return 0x10;
1073
1074 case 0x010: /* PRCM_SYSCONFIG */
1075 return s->sysconfig;
1076
1077 case 0x018: /* PRCM_IRQSTATUS_MPU */
1078 return s->irqst[0];
1079
1080 case 0x01c: /* PRCM_IRQENABLE_MPU */
1081 return s->irqen[0];
1082
1083 case 0x050: /* PRCM_VOLTCTRL */
1084 return s->voltctrl;
1085 case 0x054: /* PRCM_VOLTST */
1086 return s->voltctrl & 3;
1087
1088 case 0x060: /* PRCM_CLKSRC_CTRL */
1089 return s->clksrc[0];
1090 case 0x070: /* PRCM_CLKOUT_CTRL */
1091 return s->clkout[0];
1092 case 0x078: /* PRCM_CLKEMUL_CTRL */
1093 return s->clkemul[0];
1094 case 0x080: /* PRCM_CLKCFG_CTRL */
1095 case 0x084: /* PRCM_CLKCFG_STATUS */
1096 return 0;
1097
1098 case 0x090: /* PRCM_VOLTSETUP */
1099 return s->setuptime[0];
1100
1101 case 0x094: /* PRCM_CLKSSETUP */
1102 return s->setuptime[1];
1103
1104 case 0x098: /* PRCM_POLCTRL */
1105 return s->clkpol[0];
1106
1107 case 0x0b0: /* GENERAL_PURPOSE1 */
1108 case 0x0b4: /* GENERAL_PURPOSE2 */
1109 case 0x0b8: /* GENERAL_PURPOSE3 */
1110 case 0x0bc: /* GENERAL_PURPOSE4 */
1111 case 0x0c0: /* GENERAL_PURPOSE5 */
1112 case 0x0c4: /* GENERAL_PURPOSE6 */
1113 case 0x0c8: /* GENERAL_PURPOSE7 */
1114 case 0x0cc: /* GENERAL_PURPOSE8 */
1115 case 0x0d0: /* GENERAL_PURPOSE9 */
1116 case 0x0d4: /* GENERAL_PURPOSE10 */
1117 case 0x0d8: /* GENERAL_PURPOSE11 */
1118 case 0x0dc: /* GENERAL_PURPOSE12 */
1119 case 0x0e0: /* GENERAL_PURPOSE13 */
1120 case 0x0e4: /* GENERAL_PURPOSE14 */
1121 case 0x0e8: /* GENERAL_PURPOSE15 */
1122 case 0x0ec: /* GENERAL_PURPOSE16 */
1123 case 0x0f0: /* GENERAL_PURPOSE17 */
1124 case 0x0f4: /* GENERAL_PURPOSE18 */
1125 case 0x0f8: /* GENERAL_PURPOSE19 */
1126 case 0x0fc: /* GENERAL_PURPOSE20 */
8da3ff18 1127 return s->scratch[(addr - 0xb0) >> 2];
827df9f3
AZ		 1128
1129 case 0x140: /* CM_CLKSEL_MPU */
1130 return s->clksel[0];
1131 case 0x148: /* CM_CLKSTCTRL_MPU */
1132 return s->clkctrl[0];
1133
1134 case 0x158: /* RM_RSTST_MPU */
1135 return s->rst[0];
1136 case 0x1c8: /* PM_WKDEP_MPU */
1137 return s->wkup[0];
1138 case 0x1d4: /* PM_EVGENCTRL_MPU */
1139 return s->ev;
1140 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1141 return s->evtime[0];
1142 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1143 return s->evtime[1];
1144 case 0x1e0: /* PM_PWSTCTRL_MPU */
1145 return s->power[0];
1146 case 0x1e4: /* PM_PWSTST_MPU */
1147 return 0;
1148
1149 case 0x200: /* CM_FCLKEN1_CORE */
1150 return s->clken[0];
1151 case 0x204: /* CM_FCLKEN2_CORE */
1152 return s->clken[1];
1153 case 0x210: /* CM_ICLKEN1_CORE */
1154 return s->clken[2];
1155 case 0x214: /* CM_ICLKEN2_CORE */
1156 return s->clken[3];
1157 case 0x21c: /* CM_ICLKEN4_CORE */
1158 return s->clken[4];
1159
1160 case 0x220: /* CM_IDLEST1_CORE */
1161 /* TODO: check the actual iclk status */
1162 return 0x7ffffff9;
1163 case 0x224: /* CM_IDLEST2_CORE */
1164 /* TODO: check the actual iclk status */
1165 return 0x00000007;
1166 case 0x22c: /* CM_IDLEST4_CORE */
1167 /* TODO: check the actual iclk status */
1168 return 0x0000001f;
1169
1170 case 0x230: /* CM_AUTOIDLE1_CORE */
1171 return s->clkidle[0];
1172 case 0x234: /* CM_AUTOIDLE2_CORE */
1173 return s->clkidle[1];
1174 case 0x238: /* CM_AUTOIDLE3_CORE */
1175 return s->clkidle[2];
1176 case 0x23c: /* CM_AUTOIDLE4_CORE */
1177 return s->clkidle[3];
1178
1179 case 0x240: /* CM_CLKSEL1_CORE */
1180 return s->clksel[1];
1181 case 0x244: /* CM_CLKSEL2_CORE */
1182 return s->clksel[2];
1183
1184 case 0x248: /* CM_CLKSTCTRL_CORE */
1185 return s->clkctrl[1];
1186
1187 case 0x2a0: /* PM_WKEN1_CORE */
1188 return s->wken[0];
1189 case 0x2a4: /* PM_WKEN2_CORE */
1190 return s->wken[1];
1191
1192 case 0x2b0: /* PM_WKST1_CORE */
1193 return s->wkst[0];
1194 case 0x2b4: /* PM_WKST2_CORE */
1195 return s->wkst[1];
1196 case 0x2c8: /* PM_WKDEP_CORE */
1197 return 0x1e;
1198
1199 case 0x2e0: /* PM_PWSTCTRL_CORE */
1200 return s->power[1];
1201 case 0x2e4: /* PM_PWSTST_CORE */
1202 return 0x000030 | (s->power[1] & 0xfc00);
1203
1204 case 0x300: /* CM_FCLKEN_GFX */
1205 return s->clken[5];
1206 case 0x310: /* CM_ICLKEN_GFX */
1207 return s->clken[6];
1208 case 0x320: /* CM_IDLEST_GFX */
1209 /* TODO: check the actual iclk status */
1210 return 0x00000001;
1211 case 0x340: /* CM_CLKSEL_GFX */
1212 return s->clksel[3];
1213 case 0x348: /* CM_CLKSTCTRL_GFX */
1214 return s->clkctrl[2];
1215 case 0x350: /* RM_RSTCTRL_GFX */
1216 return s->rstctrl[0];
1217 case 0x358: /* RM_RSTST_GFX */
1218 return s->rst[1];
1219 case 0x3c8: /* PM_WKDEP_GFX */
1220 return s->wkup[1];
1221
1222 case 0x3e0: /* PM_PWSTCTRL_GFX */
1223 return s->power[2];
1224 case 0x3e4: /* PM_PWSTST_GFX */
1225 return s->power[2] & 3;
1226
1227 case 0x400: /* CM_FCLKEN_WKUP */
1228 return s->clken[7];
1229 case 0x410: /* CM_ICLKEN_WKUP */
1230 return s->clken[8];
1231 case 0x420: /* CM_IDLEST_WKUP */
1232 /* TODO: check the actual iclk status */
1233 return 0x0000003f;
1234 case 0x430: /* CM_AUTOIDLE_WKUP */
1235 return s->clkidle[4];
1236 case 0x440: /* CM_CLKSEL_WKUP */
1237 return s->clksel[4];
1238 case 0x450: /* RM_RSTCTRL_WKUP */
1239 return 0;
1240 case 0x454: /* RM_RSTTIME_WKUP */
1241 return s->rsttime_wkup;
1242 case 0x458: /* RM_RSTST_WKUP */
1243 return s->rst[2];
1244 case 0x4a0: /* PM_WKEN_WKUP */
1245 return s->wken[2];
1246 case 0x4b0: /* PM_WKST_WKUP */
1247 return s->wkst[2];
1248
1249 case 0x500: /* CM_CLKEN_PLL */
1250 return s->clken[9];
1251 case 0x520: /* CM_IDLEST_CKGEN */
51fec3cc 1252 ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8);
827df9f3 1253 if (!(s->clksel[6] & 3))
51fec3cc
AZ		 1254 /* Core uses 32-kHz clock */
1255 ret |= 3 << 0;
1256 else if (!s->dpll_lock)
1257 /* DPLL not locked, core uses ref_clk */
1258 ret |= 1 << 0;
1259 else
1260 /* Core uses DPLL */
1261 ret |= 2 << 0;
1262 return ret;
827df9f3
AZ		 1263 case 0x530: /* CM_AUTOIDLE_PLL */
1264 return s->clkidle[5];
1265 case 0x540: /* CM_CLKSEL1_PLL */
1266 return s->clksel[5];
1267 case 0x544: /* CM_CLKSEL2_PLL */
1268 return s->clksel[6];
1269
1270 case 0x800: /* CM_FCLKEN_DSP */
1271 return s->clken[10];
1272 case 0x810: /* CM_ICLKEN_DSP */
1273 return s->clken[11];
1274 case 0x820: /* CM_IDLEST_DSP */
1275 /* TODO: check the actual iclk status */
1276 return 0x00000103;
1277 case 0x830: /* CM_AUTOIDLE_DSP */
1278 return s->clkidle[6];
1279 case 0x840: /* CM_CLKSEL_DSP */
1280 return s->clksel[7];
1281 case 0x848: /* CM_CLKSTCTRL_DSP */
1282 return s->clkctrl[3];
1283 case 0x850: /* RM_RSTCTRL_DSP */
1284 return 0;
1285 case 0x858: /* RM_RSTST_DSP */
1286 return s->rst[3];
1287 case 0x8c8: /* PM_WKDEP_DSP */
1288 return s->wkup[2];
1289 case 0x8e0: /* PM_PWSTCTRL_DSP */
1290 return s->power[3];
1291 case 0x8e4: /* PM_PWSTST_DSP */
1292 return 0x008030 | (s->power[3] & 0x3003);
1293
1294 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1295 return s->irqst[1];
1296 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1297 return s->irqen[1];
1298
1299 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1300 return s->irqst[2];
1301 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1302 return s->irqen[2];
1303 }
1304
1305 OMAP_BAD_REG(addr);
1306 return 0;
1307}
1308
51fec3cc
AZ		 1309static void omap_prcm_apll_update(struct omap_prcm_s *s)
1310{
1311 int mode[2];
1312
1313 mode[0] = (s->clken[9] >> 6) & 3;
1314 s->apll_lock[0] = (mode[0] == 3);
1315 mode[1] = (s->clken[9] >> 2) & 3;
1316 s->apll_lock[1] = (mode[1] == 3);
1317 /* TODO: update clocks */
1318
16d55035 1319 if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[1] == 2)
51fec3cc 1320 fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
a89f364a 1321 __func__);
51fec3cc
AZ		 1322}
1323
1324static void omap_prcm_dpll_update(struct omap_prcm_s *s)
1325{
1326 omap_clk dpll = omap_findclk(s->mpu, "dpll");
1327 omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll");
1328 omap_clk core = omap_findclk(s->mpu, "core_clk");
1329 int mode = (s->clken[9] >> 0) & 3;
1330 int mult, div;
1331
1332 mult = (s->clksel[5] >> 12) & 0x3ff;
1333 div = (s->clksel[5] >> 8) & 0xf;
1334 if (mult == 0 || mult == 1)
1335 mode = 1; /* Bypass */
1336
1337 s->dpll_lock = 0;
1338 switch (mode) {
1339 case 0:
a89f364a 1340 fprintf(stderr, "%s: bad EN_DPLL\n", __func__);
51fec3cc
AZ		 1341 break;
1342 case 1: /* Low-power bypass mode (Default) */
1343 case 2: /* Fast-relock bypass mode */
1344 omap_clk_setrate(dpll, 1, 1);
1345 omap_clk_setrate(dpll_x2, 1, 1);
1346 break;
1347 case 3: /* Lock mode */
1348 s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */
1349
1350 omap_clk_setrate(dpll, div + 1, mult);
1351 omap_clk_setrate(dpll_x2, div + 1, mult * 2);
1352 break;
1353 }
1354
1355 switch ((s->clksel[6] >> 0) & 3) {
1356 case 0:
1357 omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz"));
1358 break;
1359 case 1:
1360 omap_clk_reparent(core, dpll);
1361 break;
1362 case 2:
1363 /* Default */
1364 omap_clk_reparent(core, dpll_x2);
1365 break;
1366 case 3:
a89f364a 1367 fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __func__);
51fec3cc
AZ		 1368 break;
1369 }
1370}
1371
a8170e5e 1372static void omap_prcm_write(void *opaque, hwaddr addr,
011a98a1 1373 uint64_t value, unsigned size)
827df9f3 1374{
a75ed3c4 1375 struct omap_prcm_s *s = opaque;
827df9f3 1376
011a98a1 1377 if (size != 4) {
77a8257e
SW		 1378 omap_badwidth_write32(opaque, addr, value);
1379 return;
011a98a1
AK		 1380 }
1381
8da3ff18 1382 switch (addr) {
827df9f3
AZ		 1383 case 0x000: /* PRCM_REVISION */
1384 case 0x054: /* PRCM_VOLTST */
1385 case 0x084: /* PRCM_CLKCFG_STATUS */
1386 case 0x1e4: /* PM_PWSTST_MPU */
1387 case 0x220: /* CM_IDLEST1_CORE */
1388 case 0x224: /* CM_IDLEST2_CORE */
1389 case 0x22c: /* CM_IDLEST4_CORE */
1390 case 0x2c8: /* PM_WKDEP_CORE */
1391 case 0x2e4: /* PM_PWSTST_CORE */
1392 case 0x320: /* CM_IDLEST_GFX */
1393 case 0x3e4: /* PM_PWSTST_GFX */
1394 case 0x420: /* CM_IDLEST_WKUP */
1395 case 0x520: /* CM_IDLEST_CKGEN */
1396 case 0x820: /* CM_IDLEST_DSP */
1397 case 0x8e4: /* PM_PWSTST_DSP */
1398 OMAP_RO_REG(addr);
1399 return;
1400
1401 case 0x010: /* PRCM_SYSCONFIG */
1402 s->sysconfig = value & 1;
1403 break;
1404
1405 case 0x018: /* PRCM_IRQSTATUS_MPU */
1406 s->irqst[0] &= ~value;
1407 omap_prcm_int_update(s, 0);
1408 break;
1409 case 0x01c: /* PRCM_IRQENABLE_MPU */
1410 s->irqen[0] = value & 0x3f;
1411 omap_prcm_int_update(s, 0);
1412 break;
1413
1414 case 0x050: /* PRCM_VOLTCTRL */
1415 s->voltctrl = value & 0xf1c3;
1416 break;
1417
1418 case 0x060: /* PRCM_CLKSRC_CTRL */
1419 s->clksrc[0] = value & 0xdb;
1420 /* TODO update clocks */
1421 break;
1422
1423 case 0x070: /* PRCM_CLKOUT_CTRL */
1424 s->clkout[0] = value & 0xbbbb;
1425 /* TODO update clocks */
1426 break;
1427
1428 case 0x078: /* PRCM_CLKEMUL_CTRL */
1429 s->clkemul[0] = value & 1;
1430 /* TODO update clocks */
1431 break;
1432
1433 case 0x080: /* PRCM_CLKCFG_CTRL */
1434 break;
1435
1436 case 0x090: /* PRCM_VOLTSETUP */
1437 s->setuptime[0] = value & 0xffff;
1438 break;
1439 case 0x094: /* PRCM_CLKSSETUP */
1440 s->setuptime[1] = value & 0xffff;
1441 break;
1442
1443 case 0x098: /* PRCM_POLCTRL */
1444 s->clkpol[0] = value & 0x701;
1445 break;
1446
1447 case 0x0b0: /* GENERAL_PURPOSE1 */
1448 case 0x0b4: /* GENERAL_PURPOSE2 */
1449 case 0x0b8: /* GENERAL_PURPOSE3 */
1450 case 0x0bc: /* GENERAL_PURPOSE4 */
1451 case 0x0c0: /* GENERAL_PURPOSE5 */
1452 case 0x0c4: /* GENERAL_PURPOSE6 */
1453 case 0x0c8: /* GENERAL_PURPOSE7 */
1454 case 0x0cc: /* GENERAL_PURPOSE8 */
1455 case 0x0d0: /* GENERAL_PURPOSE9 */
1456 case 0x0d4: /* GENERAL_PURPOSE10 */
1457 case 0x0d8: /* GENERAL_PURPOSE11 */
1458 case 0x0dc: /* GENERAL_PURPOSE12 */
1459 case 0x0e0: /* GENERAL_PURPOSE13 */
1460 case 0x0e4: /* GENERAL_PURPOSE14 */
1461 case 0x0e8: /* GENERAL_PURPOSE15 */
1462 case 0x0ec: /* GENERAL_PURPOSE16 */
1463 case 0x0f0: /* GENERAL_PURPOSE17 */
1464 case 0x0f4: /* GENERAL_PURPOSE18 */
1465 case 0x0f8: /* GENERAL_PURPOSE19 */
1466 case 0x0fc: /* GENERAL_PURPOSE20 */
8da3ff18 1467 s->scratch[(addr - 0xb0) >> 2] = value;
827df9f3
AZ		 1468 break;
1469
1470 case 0x140: /* CM_CLKSEL_MPU */
1471 s->clksel[0] = value & 0x1f;
1472 /* TODO update clocks */
1473 break;
1474 case 0x148: /* CM_CLKSTCTRL_MPU */
1475 s->clkctrl[0] = value & 0x1f;
1476 break;
1477
1478 case 0x158: /* RM_RSTST_MPU */
1479 s->rst[0] &= ~value;
1480 break;
1481 case 0x1c8: /* PM_WKDEP_MPU */
1482 s->wkup[0] = value & 0x15;
1483 break;
1484
1485 case 0x1d4: /* PM_EVGENCTRL_MPU */
1486 s->ev = value & 0x1f;
1487 break;
1488 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1489 s->evtime[0] = value;
1490 break;
1491 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1492 s->evtime[1] = value;
1493 break;
1494
1495 case 0x1e0: /* PM_PWSTCTRL_MPU */
1496 s->power[0] = value & 0xc0f;
1497 break;
1498
1499 case 0x200: /* CM_FCLKEN1_CORE */
1500 s->clken[0] = value & 0xbfffffff;
1501 /* TODO update clocks */
99570a40 1502 /* The EN_EAC bit only gets/puts func_96m_clk. */
827df9f3
AZ		 1503 break;
1504 case 0x204: /* CM_FCLKEN2_CORE */
1505 s->clken[1] = value & 0x00000007;
1506 /* TODO update clocks */
1507 break;
1508 case 0x210: /* CM_ICLKEN1_CORE */
1509 s->clken[2] = value & 0xfffffff9;
1510 /* TODO update clocks */
99570a40 1511 /* The EN_EAC bit only gets/puts core_l4_iclk. */
827df9f3
AZ		 1512 break;
1513 case 0x214: /* CM_ICLKEN2_CORE */
1514 s->clken[3] = value & 0x00000007;
1515 /* TODO update clocks */
1516 break;
1517 case 0x21c: /* CM_ICLKEN4_CORE */
1518 s->clken[4] = value & 0x0000001f;
1519 /* TODO update clocks */
1520 break;
1521
1522 case 0x230: /* CM_AUTOIDLE1_CORE */
1523 s->clkidle[0] = value & 0xfffffff9;
1524 /* TODO update clocks */
1525 break;
1526 case 0x234: /* CM_AUTOIDLE2_CORE */
1527 s->clkidle[1] = value & 0x00000007;
1528 /* TODO update clocks */
1529 break;
1530 case 0x238: /* CM_AUTOIDLE3_CORE */
1531 s->clkidle[2] = value & 0x00000007;
1532 /* TODO update clocks */
1533 break;
1534 case 0x23c: /* CM_AUTOIDLE4_CORE */
1535 s->clkidle[3] = value & 0x0000001f;
1536 /* TODO update clocks */
1537 break;
1538
1539 case 0x240: /* CM_CLKSEL1_CORE */
1540 s->clksel[1] = value & 0x0fffbf7f;
1541 /* TODO update clocks */
1542 break;
1543
1544 case 0x244: /* CM_CLKSEL2_CORE */
1545 s->clksel[2] = value & 0x00fffffc;
1546 /* TODO update clocks */
1547 break;
1548
1549 case 0x248: /* CM_CLKSTCTRL_CORE */
1550 s->clkctrl[1] = value & 0x7;
1551 break;
1552
1553 case 0x2a0: /* PM_WKEN1_CORE */
1554 s->wken[0] = value & 0x04667ff8;
1555 break;
1556 case 0x2a4: /* PM_WKEN2_CORE */
1557 s->wken[1] = value & 0x00000005;
1558 break;
1559
1560 case 0x2b0: /* PM_WKST1_CORE */
1561 s->wkst[0] &= ~value;
1562 break;
1563 case 0x2b4: /* PM_WKST2_CORE */
1564 s->wkst[1] &= ~value;
1565 break;
1566
1567 case 0x2e0: /* PM_PWSTCTRL_CORE */
1568 s->power[1] = (value & 0x00fc3f) | (1 << 2);
1569 break;
1570
1571 case 0x300: /* CM_FCLKEN_GFX */
1572 s->clken[5] = value & 6;
1573 /* TODO update clocks */
1574 break;
1575 case 0x310: /* CM_ICLKEN_GFX */
1576 s->clken[6] = value & 1;
1577 /* TODO update clocks */
1578 break;
1579 case 0x340: /* CM_CLKSEL_GFX */
1580 s->clksel[3] = value & 7;
1581 /* TODO update clocks */
1582 break;
1583 case 0x348: /* CM_CLKSTCTRL_GFX */
1584 s->clkctrl[2] = value & 1;
1585 break;
1586 case 0x350: /* RM_RSTCTRL_GFX */
1587 s->rstctrl[0] = value & 1;
1588 /* TODO: reset */
1589 break;
1590 case 0x358: /* RM_RSTST_GFX */
1591 s->rst[1] &= ~value;
1592 break;
1593 case 0x3c8: /* PM_WKDEP_GFX */
1594 s->wkup[1] = value & 0x13;
1595 break;
1596 case 0x3e0: /* PM_PWSTCTRL_GFX */
1597 s->power[2] = (value & 0x00c0f) | (3 << 2);
1598 break;
1599
1600 case 0x400: /* CM_FCLKEN_WKUP */
1601 s->clken[7] = value & 0xd;
1602 /* TODO update clocks */
1603 break;
1604 case 0x410: /* CM_ICLKEN_WKUP */
1605 s->clken[8] = value & 0x3f;
1606 /* TODO update clocks */
1607 break;
1608 case 0x430: /* CM_AUTOIDLE_WKUP */
1609 s->clkidle[4] = value & 0x0000003f;
1610 /* TODO update clocks */
1611 break;
1612 case 0x440: /* CM_CLKSEL_WKUP */
1613 s->clksel[4] = value & 3;
1614 /* TODO update clocks */
1615 break;
1616 case 0x450: /* RM_RSTCTRL_WKUP */
1617 /* TODO: reset */
1618 if (value & 2)
cf83f140 1619 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
827df9f3
AZ		 1620 break;
1621 case 0x454: /* RM_RSTTIME_WKUP */
1622 s->rsttime_wkup = value & 0x1fff;
1623 break;
1624 case 0x458: /* RM_RSTST_WKUP */
1625 s->rst[2] &= ~value;
1626 break;
1627 case 0x4a0: /* PM_WKEN_WKUP */
1628 s->wken[2] = value & 0x00000005;
1629 break;
1630 case 0x4b0: /* PM_WKST_WKUP */
1631 s->wkst[2] &= ~value;
1632 break;
1633
1634 case 0x500: /* CM_CLKEN_PLL */
51fec3cc
AZ		 1635 if (value & 0xffffff30)
1636 fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
a89f364a 1637 "future compatibility\n", __func__);
51fec3cc
AZ		 1638 if ((s->clken[9] ^ value) & 0xcc) {
1639 s->clken[9] &= ~0xcc;
1640 s->clken[9] |= value & 0xcc;
1641 omap_prcm_apll_update(s);
1642 }
1643 if ((s->clken[9] ^ value) & 3) {
1644 s->clken[9] &= ~3;
1645 s->clken[9] |= value & 3;
1646 omap_prcm_dpll_update(s);
1647 }
827df9f3
AZ		 1648 break;
1649 case 0x530: /* CM_AUTOIDLE_PLL */
1650 s->clkidle[5] = value & 0x000000cf;
1651 /* TODO update clocks */
1652 break;
1653 case 0x540: /* CM_CLKSEL1_PLL */
51fec3cc
AZ		 1654 if (value & 0xfc4000d7)
1655 fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
a89f364a 1656 "future compatibility\n", __func__);
51fec3cc
AZ		 1657 if ((s->clksel[5] ^ value) & 0x003fff00) {
1658 s->clksel[5] = value & 0x03bfff28;
1659 omap_prcm_dpll_update(s);
1660 }
1661 /* TODO update the other clocks */
1662
827df9f3 1663 s->clksel[5] = value & 0x03bfff28;
827df9f3
AZ		 1664 break;
1665 case 0x544: /* CM_CLKSEL2_PLL */
51fec3cc
AZ		 1666 if (value & ~3)
1667 fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
a89f364a 1668 "future compatibility\n", __func__);
51fec3cc
AZ		 1669 if (s->clksel[6] != (value & 3)) {
1670 s->clksel[6] = value & 3;
1671 omap_prcm_dpll_update(s);
1672 }
827df9f3
AZ		 1673 break;
1674
1675 case 0x800: /* CM_FCLKEN_DSP */
1676 s->clken[10] = value & 0x501;
1677 /* TODO update clocks */
1678 break;
1679 case 0x810: /* CM_ICLKEN_DSP */
1680 s->clken[11] = value & 0x2;
1681 /* TODO update clocks */
1682 break;
1683 case 0x830: /* CM_AUTOIDLE_DSP */
1684 s->clkidle[6] = value & 0x2;
1685 /* TODO update clocks */
1686 break;
1687 case 0x840: /* CM_CLKSEL_DSP */
1688 s->clksel[7] = value & 0x3fff;
1689 /* TODO update clocks */
1690 break;
1691 case 0x848: /* CM_CLKSTCTRL_DSP */
1692 s->clkctrl[3] = value & 0x101;
1693 break;
1694 case 0x850: /* RM_RSTCTRL_DSP */
1695 /* TODO: reset */
1696 break;
1697 case 0x858: /* RM_RSTST_DSP */
1698 s->rst[3] &= ~value;
1699 break;
1700 case 0x8c8: /* PM_WKDEP_DSP */
1701 s->wkup[2] = value & 0x13;
1702 break;
1703 case 0x8e0: /* PM_PWSTCTRL_DSP */
1704 s->power[3] = (value & 0x03017) | (3 << 2);
1705 break;
1706
1707 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1708 s->irqst[1] &= ~value;
1709 omap_prcm_int_update(s, 1);
1710 break;
1711 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1712 s->irqen[1] = value & 0x7;
1713 omap_prcm_int_update(s, 1);
1714 break;
1715
1716 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1717 s->irqst[2] &= ~value;
1718 omap_prcm_int_update(s, 2);
1719 break;
1720 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1721 s->irqen[2] = value & 0x7;
1722 omap_prcm_int_update(s, 2);
1723 break;
1724
1725 default:
1726 OMAP_BAD_REG(addr);
1727 return;
1728 }
1729}
1730
011a98a1
AK		 1731static const MemoryRegionOps omap_prcm_ops = {
1732 .read = omap_prcm_read,
1733 .write = omap_prcm_write,
1734 .endianness = DEVICE_NATIVE_ENDIAN,
827df9f3
AZ		 1735};
1736
1737static void omap_prcm_reset(struct omap_prcm_s *s)
1738{
1739 s->sysconfig = 0;
1740 s->irqst[0] = 0;
1741 s->irqst[1] = 0;
1742 s->irqst[2] = 0;
1743 s->irqen[0] = 0;
1744 s->irqen[1] = 0;
1745 s->irqen[2] = 0;
1746 s->voltctrl = 0x1040;
1747 s->ev = 0x14;
1748 s->evtime[0] = 0;
1749 s->evtime[1] = 0;
1750 s->clkctrl[0] = 0;
1751 s->clkctrl[1] = 0;
1752 s->clkctrl[2] = 0;
1753 s->clkctrl[3] = 0;
1754 s->clken[1] = 7;
1755 s->clken[3] = 7;
1756 s->clken[4] = 0;
1757 s->clken[5] = 0;
1758 s->clken[6] = 0;
1759 s->clken[7] = 0xc;
1760 s->clken[8] = 0x3e;
1761 s->clken[9] = 0x0d;
1762 s->clken[10] = 0;
1763 s->clken[11] = 0;
1764 s->clkidle[0] = 0;
1765 s->clkidle[2] = 7;
1766 s->clkidle[3] = 0;
1767 s->clkidle[4] = 0;
1768 s->clkidle[5] = 0x0c;
1769 s->clkidle[6] = 0;
1770 s->clksel[0] = 0x01;
1771 s->clksel[1] = 0x02100121;
1772 s->clksel[2] = 0x00000000;
1773 s->clksel[3] = 0x01;
1774 s->clksel[4] = 0;
1775 s->clksel[7] = 0x0121;
1776 s->wkup[0] = 0x15;
1777 s->wkup[1] = 0x13;
1778 s->wkup[2] = 0x13;
1779 s->wken[0] = 0x04667ff8;
1780 s->wken[1] = 0x00000005;
1781 s->wken[2] = 5;
1782 s->wkst[0] = 0;
1783 s->wkst[1] = 0;
1784 s->wkst[2] = 0;
1785 s->power[0] = 0x00c;
1786 s->power[1] = 4;
1787 s->power[2] = 0x0000c;
1788 s->power[3] = 0x14;
1789 s->rstctrl[0] = 1;
1790 s->rst[3] = 1;
51fec3cc
AZ		 1791 omap_prcm_apll_update(s);
1792 omap_prcm_dpll_update(s);
827df9f3
AZ		 1793}
1794
1795static void omap_prcm_coldreset(struct omap_prcm_s *s)
1796{
1797 s->setuptime[0] = 0;
1798 s->setuptime[1] = 0;
1799 memset(&s->scratch, 0, sizeof(s->scratch));
1800 s->rst[0] = 0x01;
1801 s->rst[1] = 0x00;
1802 s->rst[2] = 0x01;
1803 s->clken[0] = 0;
1804 s->clken[2] = 0;
1805 s->clkidle[1] = 0;
1806 s->clksel[5] = 0;
1807 s->clksel[6] = 2;
1808 s->clksrc[0] = 0x43;
1809 s->clkout[0] = 0x0303;
1810 s->clkemul[0] = 0;
1811 s->clkpol[0] = 0x100;
1812 s->rsttime_wkup = 0x1002;
1813
1814 omap_prcm_reset(s);
1815}
1816
c1ff227b 1817static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
827df9f3
AZ		 1818 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
1819 struct omap_mpu_state_s *mpu)
1820{
b45c03f5 1821 struct omap_prcm_s *s = g_new0(struct omap_prcm_s, 1);
827df9f3
AZ		 1822
1823 s->irq[0] = mpu_int;
1824 s->irq[1] = dsp_int;
1825 s->irq[2] = iva_int;
1826 s->mpu = mpu;
1827 omap_prcm_coldreset(s);
1828
2c9b15ca 1829 memory_region_init_io(&s->iomem0, NULL, &omap_prcm_ops, s, "omap.pcrm0",
011a98a1 1830 omap_l4_region_size(ta, 0));
2c9b15ca 1831 memory_region_init_io(&s->iomem1, NULL, &omap_prcm_ops, s, "omap.pcrm1",
011a98a1 1832 omap_l4_region_size(ta, 1));
f44336c5
AK		 1833 omap_l4_attach(ta, 0, &s->iomem0);
1834 omap_l4_attach(ta, 1, &s->iomem1);
827df9f3
AZ		 1835
1836 return s;
1837}
1838
1839/* System and Pinout control */
1840struct omap_sysctl_s {
827df9f3 1841 struct omap_mpu_state_s *mpu;
011a98a1 1842 MemoryRegion iomem;
827df9f3
AZ		 1843
1844 uint32_t sysconfig;
1845 uint32_t devconfig;
1846 uint32_t psaconfig;
1847 uint32_t padconf[0x45];
1848 uint8_t obs;
1849 uint32_t msuspendmux[5];
1850};
1851
a8170e5e 1852static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
f451387a
AZ		 1853{
1854
a75ed3c4 1855 struct omap_sysctl_s *s = opaque;
f451387a
AZ		 1856 int pad_offset, byte_offset;
1857 int value;
1858
8da3ff18 1859 switch (addr) {
f451387a 1860 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
8da3ff18
PB		 1861 pad_offset = (addr - 0x30) >> 2;
1862 byte_offset = (addr - 0x30) & (4 - 1);
f451387a
AZ		 1863
1864 value = s->padconf[pad_offset];
1865 value = (value >> (byte_offset * 8)) & 0xff;
1866
1867 return value;
1868
1869 default:
1870 break;
1871 }
1872
1873 OMAP_BAD_REG(addr);
1874 return 0;
1875}
1876
a8170e5e 1877static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
827df9f3 1878{
a75ed3c4 1879 struct omap_sysctl_s *s = opaque;
827df9f3 1880
8da3ff18 1881 switch (addr) {
827df9f3
AZ		 1882 case 0x000: /* CONTROL_REVISION */
1883 return 0x20;
1884
1885 case 0x010: /* CONTROL_SYSCONFIG */
1886 return s->sysconfig;
1887
1888 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
8da3ff18 1889 return s->padconf[(addr - 0x30) >> 2];
827df9f3
AZ		 1890
1891 case 0x270: /* CONTROL_DEBOBS */
1892 return s->obs;
1893
1894 case 0x274: /* CONTROL_DEVCONF */
1895 return s->devconfig;
1896
1897 case 0x28c: /* CONTROL_EMU_SUPPORT */
1898 return 0;
1899
1900 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
1901 return s->msuspendmux[0];
1902 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
1903 return s->msuspendmux[1];
1904 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
1905 return s->msuspendmux[2];
1906 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
1907 return s->msuspendmux[3];
1908 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
1909 return s->msuspendmux[4];
1910 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
1911 return 0;
1912
1913 case 0x2b8: /* CONTROL_PSA_CTRL */
1914 return s->psaconfig;
1915 case 0x2bc: /* CONTROL_PSA_CMD */
1916 case 0x2c0: /* CONTROL_PSA_VALUE */
1917 return 0;
1918
1919 case 0x2b0: /* CONTROL_SEC_CTRL */
1920 return 0x800000f1;
1921 case 0x2d0: /* CONTROL_SEC_EMU */
1922 return 0x80000015;
1923 case 0x2d4: /* CONTROL_SEC_TAP */
1924 return 0x8000007f;
1925 case 0x2b4: /* CONTROL_SEC_TEST */
1926 case 0x2f0: /* CONTROL_SEC_STATUS */
1927 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
1928 /* Secure mode is not present on general-pusrpose device. Outside
1929 * secure mode these values cannot be read or written. */
1930 return 0;
1931
1932 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
1933 return 0xff;
1934 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
1935 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
1936 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
1937 /* No secure mode so no Extended Secure RAM present. */
1938 return 0;
1939
1940 case 0x2f8: /* CONTROL_STATUS */
1941 /* Device Type => General-purpose */
1942 return 0x0300;
1943 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
1944
1945 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
1946 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
1947 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
1948 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
1949 return 0xdecafbad;
1950
1951 case 0x310: /* CONTROL_RAND_KEY_0 */
1952 case 0x314: /* CONTROL_RAND_KEY_1 */
1953 case 0x318: /* CONTROL_RAND_KEY_2 */
1954 case 0x31c: /* CONTROL_RAND_KEY_3 */
1955 case 0x320: /* CONTROL_CUST_KEY_0 */
1956 case 0x324: /* CONTROL_CUST_KEY_1 */
1957 case 0x330: /* CONTROL_TEST_KEY_0 */
1958 case 0x334: /* CONTROL_TEST_KEY_1 */
1959 case 0x338: /* CONTROL_TEST_KEY_2 */
1960 case 0x33c: /* CONTROL_TEST_KEY_3 */
1961 case 0x340: /* CONTROL_TEST_KEY_4 */
1962 case 0x344: /* CONTROL_TEST_KEY_5 */
1963 case 0x348: /* CONTROL_TEST_KEY_6 */
1964 case 0x34c: /* CONTROL_TEST_KEY_7 */
1965 case 0x350: /* CONTROL_TEST_KEY_8 */
1966 case 0x354: /* CONTROL_TEST_KEY_9 */
1967 /* Can only be accessed in secure mode and when C_FieldAccEnable
1968 * bit is set in CONTROL_SEC_CTRL.
1969 * TODO: otherwise an interconnect access error is generated. */
1970 return 0;
1971 }
1972
1973 OMAP_BAD_REG(addr);
1974 return 0;
1975}
1976
a75ed3c4 1977static void omap_sysctl_write8(void *opaque, hwaddr addr, uint32_t value)
f451387a 1978{
a75ed3c4 1979 struct omap_sysctl_s *s = opaque;
f451387a
AZ		 1980 int pad_offset, byte_offset;
1981 int prev_value;
1982
8da3ff18 1983 switch (addr) {
f451387a 1984 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
8da3ff18
PB		 1985 pad_offset = (addr - 0x30) >> 2;
1986 byte_offset = (addr - 0x30) & (4 - 1);
f451387a
AZ		 1987
1988 prev_value = s->padconf[pad_offset];
1989 prev_value &= ~(0xff << (byte_offset * 8));
1990 prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f;
1991 s->padconf[pad_offset] = prev_value;
1992 break;
1993
1994 default:
1995 OMAP_BAD_REG(addr);
1996 break;
1997 }
1998}
1999
a75ed3c4 2000static void omap_sysctl_write(void *opaque, hwaddr addr, uint32_t value)
827df9f3 2001{
a75ed3c4 2002 struct omap_sysctl_s *s = opaque;
827df9f3 2003
8da3ff18 2004 switch (addr) {
827df9f3
AZ		 2005 case 0x000: /* CONTROL_REVISION */
2006 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
2007 case 0x2c0: /* CONTROL_PSA_VALUE */
2008 case 0x2f8: /* CONTROL_STATUS */
2009 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
2010 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
2011 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
2012 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
2013 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
2014 case 0x310: /* CONTROL_RAND_KEY_0 */
2015 case 0x314: /* CONTROL_RAND_KEY_1 */
2016 case 0x318: /* CONTROL_RAND_KEY_2 */
2017 case 0x31c: /* CONTROL_RAND_KEY_3 */
2018 case 0x320: /* CONTROL_CUST_KEY_0 */
2019 case 0x324: /* CONTROL_CUST_KEY_1 */
2020 case 0x330: /* CONTROL_TEST_KEY_0 */
2021 case 0x334: /* CONTROL_TEST_KEY_1 */
2022 case 0x338: /* CONTROL_TEST_KEY_2 */
2023 case 0x33c: /* CONTROL_TEST_KEY_3 */
2024 case 0x340: /* CONTROL_TEST_KEY_4 */
2025 case 0x344: /* CONTROL_TEST_KEY_5 */
2026 case 0x348: /* CONTROL_TEST_KEY_6 */
2027 case 0x34c: /* CONTROL_TEST_KEY_7 */
2028 case 0x350: /* CONTROL_TEST_KEY_8 */
2029 case 0x354: /* CONTROL_TEST_KEY_9 */
2030 OMAP_RO_REG(addr);
2031 return;
2032
2033 case 0x010: /* CONTROL_SYSCONFIG */
2034 s->sysconfig = value & 0x1e;
2035 break;
2036
2037 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
2038 /* XXX: should check constant bits */
8da3ff18 2039 s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f;
827df9f3
AZ		 2040 break;
2041
2042 case 0x270: /* CONTROL_DEBOBS */
2043 s->obs = value & 0xff;
2044 break;
2045
2046 case 0x274: /* CONTROL_DEVCONF */
2047 s->devconfig = value & 0xffffc7ff;
2048 break;
2049
2050 case 0x28c: /* CONTROL_EMU_SUPPORT */
2051 break;
2052
2053 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
2054 s->msuspendmux[0] = value & 0x3fffffff;
2055 break;
2056 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
2057 s->msuspendmux[1] = value & 0x3fffffff;
2058 break;
2059 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
2060 s->msuspendmux[2] = value & 0x3fffffff;
2061 break;
2062 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
2063 s->msuspendmux[3] = value & 0x3fffffff;
2064 break;
2065 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
2066 s->msuspendmux[4] = value & 0x3fffffff;
2067 break;
2068
2069 case 0x2b8: /* CONTROL_PSA_CTRL */
2070 s->psaconfig = value & 0x1c;
2071 s->psaconfig |= (value & 0x20) ? 2 : 1;
2072 break;
2073 case 0x2bc: /* CONTROL_PSA_CMD */
2074 break;
2075
2076 case 0x2b0: /* CONTROL_SEC_CTRL */
2077 case 0x2b4: /* CONTROL_SEC_TEST */
2078 case 0x2d0: /* CONTROL_SEC_EMU */
2079 case 0x2d4: /* CONTROL_SEC_TAP */
2080 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
2081 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
2082 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
2083 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
2084 case 0x2f0: /* CONTROL_SEC_STATUS */
2085 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
2086 break;
2087
2088 default:
2089 OMAP_BAD_REG(addr);
2090 return;
2091 }
2092}
2093
fc14cf0e
PM		 2094static uint64_t omap_sysctl_readfn(void *opaque, hwaddr addr,
2095 unsigned size)
2096{
2097 switch (size) {
2098 case 1:
2099 return omap_sysctl_read8(opaque, addr);
2100 case 2:
2101 return omap_badwidth_read32(opaque, addr); /* TODO */
2102 case 4:
2103 return omap_sysctl_read(opaque, addr);
2104 default:
2105 g_assert_not_reached();
2106 }
2107}
2108
2109static void omap_sysctl_writefn(void *opaque, hwaddr addr,
2110 uint64_t value, unsigned size)
2111{
2112 switch (size) {
2113 case 1:
2114 omap_sysctl_write8(opaque, addr, value);
2115 break;
2116 case 2:
2117 omap_badwidth_write32(opaque, addr, value); /* TODO */
2118 break;
2119 case 4:
2120 omap_sysctl_write(opaque, addr, value);
2121 break;
2122 default:
2123 g_assert_not_reached();
2124 }
2125}
2126
011a98a1 2127static const MemoryRegionOps omap_sysctl_ops = {
fc14cf0e
PM		 2128 .read = omap_sysctl_readfn,
2129 .write = omap_sysctl_writefn,
2130 .valid.min_access_size = 1,
2131 .valid.max_access_size = 4,
011a98a1 2132 .endianness = DEVICE_NATIVE_ENDIAN,
827df9f3
AZ		 2133};
2134
2135static void omap_sysctl_reset(struct omap_sysctl_s *s)
2136{
2137 /* (power-on reset) */
2138 s->sysconfig = 0;
2139 s->obs = 0;
2140 s->devconfig = 0x0c000000;
2141 s->msuspendmux[0] = 0x00000000;
2142 s->msuspendmux[1] = 0x00000000;
2143 s->msuspendmux[2] = 0x00000000;
2144 s->msuspendmux[3] = 0x00000000;
2145 s->msuspendmux[4] = 0x00000000;
2146 s->psaconfig = 1;
2147
2148 s->padconf[0x00] = 0x000f0f0f;
2149 s->padconf[0x01] = 0x00000000;
2150 s->padconf[0x02] = 0x00000000;
2151 s->padconf[0x03] = 0x00000000;
2152 s->padconf[0x04] = 0x00000000;
2153 s->padconf[0x05] = 0x00000000;
2154 s->padconf[0x06] = 0x00000000;
2155 s->padconf[0x07] = 0x00000000;
2156 s->padconf[0x08] = 0x08080800;
2157 s->padconf[0x09] = 0x08080808;
2158 s->padconf[0x0a] = 0x08080808;
2159 s->padconf[0x0b] = 0x08080808;
2160 s->padconf[0x0c] = 0x08080808;
2161 s->padconf[0x0d] = 0x08080800;
2162 s->padconf[0x0e] = 0x08080808;
2163 s->padconf[0x0f] = 0x08080808;
2164 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */
2165 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */
2166 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */
2167 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */
2168 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */
2169 s->padconf[0x15] = 0x18181818;
2170 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */
2171 s->padconf[0x17] = 0x1f001f00;
2172 s->padconf[0x18] = 0x1f1f1f1f;
2173 s->padconf[0x19] = 0x00000000;
2174 s->padconf[0x1a] = 0x1f180000;
2175 s->padconf[0x1b] = 0x00001f1f;
2176 s->padconf[0x1c] = 0x1f001f00;
2177 s->padconf[0x1d] = 0x00000000;
2178 s->padconf[0x1e] = 0x00000000;
2179 s->padconf[0x1f] = 0x08000000;
2180 s->padconf[0x20] = 0x08080808;
2181 s->padconf[0x21] = 0x08080808;
2182 s->padconf[0x22] = 0x0f080808;
2183 s->padconf[0x23] = 0x0f0f0f0f;
2184 s->padconf[0x24] = 0x000f0f0f;
2185 s->padconf[0x25] = 0x1f1f1f0f;
2186 s->padconf[0x26] = 0x080f0f1f;
2187 s->padconf[0x27] = 0x070f1808;
2188 s->padconf[0x28] = 0x0f070707;
2189 s->padconf[0x29] = 0x000f0f1f;
2190 s->padconf[0x2a] = 0x0f0f0f1f;
2191 s->padconf[0x2b] = 0x08000000;
2192 s->padconf[0x2c] = 0x0000001f;
2193 s->padconf[0x2d] = 0x0f0f1f00;
2194 s->padconf[0x2e] = 0x1f1f0f0f;
2195 s->padconf[0x2f] = 0x0f1f1f1f;
2196 s->padconf[0x30] = 0x0f0f0f0f;
2197 s->padconf[0x31] = 0x0f1f0f1f;
2198 s->padconf[0x32] = 0x0f0f0f0f;
2199 s->padconf[0x33] = 0x0f1f0f1f;
2200 s->padconf[0x34] = 0x1f1f0f0f;
2201 s->padconf[0x35] = 0x0f0f1f1f;
2202 s->padconf[0x36] = 0x0f0f1f0f;
2203 s->padconf[0x37] = 0x0f0f0f0f;
2204 s->padconf[0x38] = 0x1f18180f;
2205 s->padconf[0x39] = 0x1f1f1f1f;
2206 s->padconf[0x3a] = 0x00001f1f;
2207 s->padconf[0x3b] = 0x00000000;
2208 s->padconf[0x3c] = 0x00000000;
2209 s->padconf[0x3d] = 0x0f0f0f0f;
2210 s->padconf[0x3e] = 0x18000f0f;
2211 s->padconf[0x3f] = 0x00070000;
2212 s->padconf[0x40] = 0x00000707;
2213 s->padconf[0x41] = 0x0f1f0700;
2214 s->padconf[0x42] = 0x1f1f070f;
2215 s->padconf[0x43] = 0x0008081f;
2216 s->padconf[0x44] = 0x00000800;
2217}
2218
c1ff227b 2219static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
827df9f3
AZ		 2220 omap_clk iclk, struct omap_mpu_state_s *mpu)
2221{
b45c03f5 2222 struct omap_sysctl_s *s = g_new0(struct omap_sysctl_s, 1);
827df9f3
AZ		 2223
2224 s->mpu = mpu;
2225 omap_sysctl_reset(s);
2226
2c9b15ca 2227 memory_region_init_io(&s->iomem, NULL, &omap_sysctl_ops, s, "omap.sysctl",
011a98a1 2228 omap_l4_region_size(ta, 0));
f44336c5 2229 omap_l4_attach(ta, 0, &s->iomem);
827df9f3
AZ		 2230
2231 return s;
2232}
2233
827df9f3
AZ		 2234/* General chip reset */
2235static void omap2_mpu_reset(void *opaque)
2236{
a75ed3c4 2237 struct omap_mpu_state_s *mpu = opaque;
827df9f3 2238
827df9f3
AZ		 2239 omap_dma_reset(mpu->dma);
2240 omap_prcm_reset(mpu->prcm);
2241 omap_sysctl_reset(mpu->sysc);
2242 omap_gp_timer_reset(mpu->gptimer[0]);
2243 omap_gp_timer_reset(mpu->gptimer[1]);
2244 omap_gp_timer_reset(mpu->gptimer[2]);
2245 omap_gp_timer_reset(mpu->gptimer[3]);
2246 omap_gp_timer_reset(mpu->gptimer[4]);
2247 omap_gp_timer_reset(mpu->gptimer[5]);
2248 omap_gp_timer_reset(mpu->gptimer[6]);
2249 omap_gp_timer_reset(mpu->gptimer[7]);
2250 omap_gp_timer_reset(mpu->gptimer[8]);
2251 omap_gp_timer_reset(mpu->gptimer[9]);
2252 omap_gp_timer_reset(mpu->gptimer[10]);
2253 omap_gp_timer_reset(mpu->gptimer[11]);
011d87d0 2254 omap_synctimer_reset(mpu->synctimer);
827df9f3
AZ		 2255 omap_sdrc_reset(mpu->sdrc);
2256 omap_gpmc_reset(mpu->gpmc);
2257 omap_dss_reset(mpu->dss);
2258 omap_uart_reset(mpu->uart[0]);
2259 omap_uart_reset(mpu->uart[1]);
2260 omap_uart_reset(mpu->uart[2]);
2261 omap_mmc_reset(mpu->mmc);
827df9f3
AZ		 2262 omap_mcspi_reset(mpu->mcspi[0]);
2263 omap_mcspi_reset(mpu->mcspi[1]);
5f4ef08b 2264 cpu_reset(CPU(mpu->cpu));
827df9f3
AZ		 2265}
2266
2267static int omap2_validate_addr(struct omap_mpu_state_s *s,
a8170e5e 2268 hwaddr addr)
827df9f3
AZ		 2269{
2270 return 1;
2271}
2272
2273static const struct dma_irq_map omap2_dma_irq_map[] = {
2274 { 0, OMAP_INT_24XX_SDMA_IRQ0 },
2275 { 0, OMAP_INT_24XX_SDMA_IRQ1 },
2276 { 0, OMAP_INT_24XX_SDMA_IRQ2 },
2277 { 0, OMAP_INT_24XX_SDMA_IRQ3 },
2278};
2279
e285e867 2280struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
ba1ba5cc 2281 const char *cpu_type)
827df9f3 2282{
b45c03f5 2283 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
827df9f3 2284 qemu_irq dma_irqs[4];
751c6a17 2285 DriveInfo *dinfo;
827df9f3 2286 int i;
77831c20
JR		 2287 SysBusDevice *busdev;
2288 struct omap_target_agent_s *ta;
e285e867 2289 MemoryRegion *sysmem = get_system_memory();
827df9f3
AZ		 2290
2291 /* Core */
2292 s->mpu_model = omap2420;
ba1ba5cc 2293 s->cpu = ARM_CPU(cpu_create(cpu_type));
827df9f3
AZ		 2294 s->sram_size = OMAP242X_SRAM_SIZE;
2295
f3c7d038 2296 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0);
827df9f3
AZ		 2297
2298 /* Clocks */
2299 omap_clk_init(s);
2300
2301 /* Memory-mapped stuff */
98a99ce0 2302 memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size,
f8ed85ac 2303 &error_fatal);
011a98a1 2304 memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram);
827df9f3 2305
f3226149 2306 s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54);
827df9f3
AZ		 2307
2308 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
3e80f690 2309 s->ih[0] = qdev_new("omap2-intc");
0919ac78 2310 qdev_prop_set_uint8(s->ih[0], "revision", 0x21);
bab592a2
MAL		 2311 omap_intc_set_fclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_fclk"));
2312 omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_iclk"));
1356b98d 2313 busdev = SYS_BUS_DEVICE(s->ih[0]);
3c6ef471 2314 sysbus_realize_and_unref(busdev, &error_fatal);
437f0f10
PM		 2315 sysbus_connect_irq(busdev, 0,
2316 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
2317 sysbus_connect_irq(busdev, 1,
2318 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
0919ac78 2319 sysbus_mmio_map(busdev, 0, 0x480fe000);
827df9f3 2320 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
0919ac78
PM		 2321 qdev_get_gpio_in(s->ih[0],
2322 OMAP_INT_24XX_PRCM_MPU_IRQ),
2323 NULL, NULL, s);
827df9f3
AZ		 2324
2325 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
2326 omap_findclk(s, "omapctrl_iclk"), s);
2327
0919ac78
PM		 2328 for (i = 0; i < 4; i++) {
2329 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap2_dma_irq_map[i].ih],
2330 omap2_dma_irq_map[i].intr);
2331 }
7405165e 2332 s->dma = omap_dma4_init(0x48056000, dma_irqs, sysmem, s, 256, 32,
827df9f3
AZ		 2333 omap_findclk(s, "sdma_iclk"),
2334 omap_findclk(s, "sdma_fclk"));
2335 s->port->addr_valid = omap2_validate_addr;
2336
afbb5194 2337 /* Register SDRAM and SRAM ports for fast DMA transfers. */
e285e867
PMD		 2338 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(sdram),
2339 OMAP2_Q2_BASE, memory_region_size(sdram));
011a98a1 2340 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sram),
90aeba9d 2341 OMAP2_SRAM_BASE, s->sram_size);
afbb5194 2342
aee39503 2343 s->uart[0] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 19),
0919ac78
PM		 2344 qdev_get_gpio_in(s->ih[0],
2345 OMAP_INT_24XX_UART1_IRQ),
827df9f3
AZ		 2346 omap_findclk(s, "uart1_fclk"),
2347 omap_findclk(s, "uart1_iclk"),
2348 s->drq[OMAP24XX_DMA_UART1_TX],
6a8aabd3
SW		 2349 s->drq[OMAP24XX_DMA_UART1_RX],
2350 "uart1",
9bca0edb 2351 serial_hd(0));
aee39503 2352 s->uart[1] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 20),
0919ac78
PM		 2353 qdev_get_gpio_in(s->ih[0],
2354 OMAP_INT_24XX_UART2_IRQ),
827df9f3
AZ		 2355 omap_findclk(s, "uart2_fclk"),
2356 omap_findclk(s, "uart2_iclk"),
2357 s->drq[OMAP24XX_DMA_UART2_TX],
2358 s->drq[OMAP24XX_DMA_UART2_RX],
6a8aabd3 2359 "uart2",
9bca0edb 2360 serial_hd(0) ? serial_hd(1) : NULL);
aee39503 2361 s->uart[2] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 21),
0919ac78
PM		 2362 qdev_get_gpio_in(s->ih[0],
2363 OMAP_INT_24XX_UART3_IRQ),
827df9f3
AZ		 2364 omap_findclk(s, "uart3_fclk"),
2365 omap_findclk(s, "uart3_iclk"),
2366 s->drq[OMAP24XX_DMA_UART3_TX],
2367 s->drq[OMAP24XX_DMA_UART3_RX],
6a8aabd3 2368 "uart3",
9bca0edb 2369 serial_hd(0) && serial_hd(1) ? serial_hd(2) : NULL);
827df9f3
AZ		 2370
2371 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
0919ac78 2372 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER1),
827df9f3
AZ		 2373 omap_findclk(s, "wu_gpt1_clk"),
2374 omap_findclk(s, "wu_l4_iclk"));
2375 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
0919ac78 2376 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER2),
827df9f3
AZ		 2377 omap_findclk(s, "core_gpt2_clk"),
2378 omap_findclk(s, "core_l4_iclk"));
2379 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
0919ac78 2380 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER3),
827df9f3
AZ		 2381 omap_findclk(s, "core_gpt3_clk"),
2382 omap_findclk(s, "core_l4_iclk"));
2383 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
0919ac78 2384 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER4),
827df9f3
AZ		 2385 omap_findclk(s, "core_gpt4_clk"),
2386 omap_findclk(s, "core_l4_iclk"));
2387 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
0919ac78 2388 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER5),
827df9f3
AZ		 2389 omap_findclk(s, "core_gpt5_clk"),
2390 omap_findclk(s, "core_l4_iclk"));
2391 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
0919ac78 2392 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER6),
827df9f3
AZ		 2393 omap_findclk(s, "core_gpt6_clk"),
2394 omap_findclk(s, "core_l4_iclk"));
2395 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
0919ac78 2396 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER7),
827df9f3
AZ		 2397 omap_findclk(s, "core_gpt7_clk"),
2398 omap_findclk(s, "core_l4_iclk"));
2399 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
0919ac78 2400 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER8),
827df9f3
AZ		 2401 omap_findclk(s, "core_gpt8_clk"),
2402 omap_findclk(s, "core_l4_iclk"));
2403 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
0919ac78 2404 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER9),
827df9f3
AZ		 2405 omap_findclk(s, "core_gpt9_clk"),
2406 omap_findclk(s, "core_l4_iclk"));
2407 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
0919ac78 2408 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER10),
827df9f3
AZ		 2409 omap_findclk(s, "core_gpt10_clk"),
2410 omap_findclk(s, "core_l4_iclk"));
2411 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
0919ac78 2412 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER11),
827df9f3
AZ		 2413 omap_findclk(s, "core_gpt11_clk"),
2414 omap_findclk(s, "core_l4_iclk"));
2415 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
0919ac78 2416 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER12),
827df9f3
AZ		 2417 omap_findclk(s, "core_gpt12_clk"),
2418 omap_findclk(s, "core_l4_iclk"));
2419
2420 omap_tap_init(omap_l4ta(s->l4, 2), s);
2421
011d87d0 2422 s->synctimer = omap_synctimer_init(omap_l4tao(s->l4, 2), s,
827df9f3
AZ		 2423 omap_findclk(s, "clk32-kHz"),
2424 omap_findclk(s, "core_l4_iclk"));
2425
3e80f690 2426 s->i2c[0] = qdev_new("omap_i2c");
54e17933 2427 qdev_prop_set_uint8(s->i2c[0], "revision", 0x34);
0fd20c53
MAL		 2428 omap_i2c_set_iclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.iclk"));
2429 omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.fclk"));
1356b98d 2430 busdev = SYS_BUS_DEVICE(s->i2c[0]);
3c6ef471 2431 sysbus_realize_and_unref(busdev, &error_fatal);
54e17933
JR		 2432 sysbus_connect_irq(busdev, 0,
2433 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ));
2434 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C1_TX]);
2435 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C1_RX]);
2436 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 5), 0));
2437
3e80f690 2438 s->i2c[1] = qdev_new("omap_i2c");
54e17933 2439 qdev_prop_set_uint8(s->i2c[1], "revision", 0x34);
0fd20c53
MAL		 2440 omap_i2c_set_iclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.iclk"));
2441 omap_i2c_set_fclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.fclk"));
1356b98d 2442 busdev = SYS_BUS_DEVICE(s->i2c[1]);
3c6ef471 2443 sysbus_realize_and_unref(busdev, &error_fatal);
54e17933
JR		 2444 sysbus_connect_irq(busdev, 0,
2445 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ));
2446 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C2_TX]);
2447 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C2_RX]);
2448 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 6), 0));
827df9f3 2449
3e80f690 2450 s->gpio = qdev_new("omap2-gpio");
77831c20 2451 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
ba2aba83
MAL		 2452 omap2_gpio_set_iclk(OMAP2_GPIO(s->gpio), omap_findclk(s, "gpio_iclk"));
2453 omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 0, omap_findclk(s, "gpio1_dbclk"));
2454 omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 1, omap_findclk(s, "gpio2_dbclk"));
2455 omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 2, omap_findclk(s, "gpio3_dbclk"));
2456 omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 3, omap_findclk(s, "gpio4_dbclk"));
77831c20 2457 if (s->mpu_model == omap2430) {
ba2aba83
MAL		 2458 omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 4,
2459 omap_findclk(s, "gpio5_dbclk"));
77831c20 2460 }
1356b98d 2461 busdev = SYS_BUS_DEVICE(s->gpio);
3c6ef471 2462 sysbus_realize_and_unref(busdev, &error_fatal);
0919ac78
PM		 2463 sysbus_connect_irq(busdev, 0,
2464 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1));
2465 sysbus_connect_irq(busdev, 3,
2466 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK2));
2467 sysbus_connect_irq(busdev, 6,
2468 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK3));
2469 sysbus_connect_irq(busdev, 9,
2470 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK4));
f45b885f
PM		 2471 if (s->mpu_model == omap2430) {
2472 sysbus_connect_irq(busdev, 12,
2473 qdev_get_gpio_in(s->ih[0],
2474 OMAP_INT_243X_GPIO_BANK5));
2475 }
77831c20
JR		 2476 ta = omap_l4ta(s->l4, 3);
2477 sysbus_mmio_map(busdev, 0, omap_l4_region_base(ta, 1));
2478 sysbus_mmio_map(busdev, 1, omap_l4_region_base(ta, 0));
2479 sysbus_mmio_map(busdev, 2, omap_l4_region_base(ta, 2));
2480 sysbus_mmio_map(busdev, 3, omap_l4_region_base(ta, 4));
2481 sysbus_mmio_map(busdev, 4, omap_l4_region_base(ta, 5));
827df9f3 2482
6a0148e7 2483 s->sdrc = omap_sdrc_init(sysmem, 0x68009000);
0919ac78
PM		 2484 s->gpmc = omap_gpmc_init(s, 0x6800a000,
2485 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPMC_IRQ),
eee0a1c6 2486 s->drq[OMAP24XX_DMA_GPMC]);
827df9f3 2487
751c6a17 2488 dinfo = drive_get(IF_SD, 0, 0);
a82929a2
TH		 2489 if (!dinfo && !qtest_enabled()) {
2490 warn_report("missing SecureDigital device");
827df9f3 2491 }
fa1d36df 2492 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9),
a82929a2 2493 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
0919ac78 2494 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MMC_IRQ),
827df9f3
AZ		 2495 &s->drq[OMAP24XX_DMA_MMC1_TX],
2496 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
2497
2498 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
0919ac78 2499 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI1_IRQ),
827df9f3
AZ		 2500 &s->drq[OMAP24XX_DMA_SPI1_TX0],
2501 omap_findclk(s, "spi1_fclk"),
2502 omap_findclk(s, "spi1_iclk"));
2503 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
0919ac78 2504 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI2_IRQ),
827df9f3
AZ		 2505 &s->drq[OMAP24XX_DMA_SPI2_TX0],
2506 omap_findclk(s, "spi2_fclk"),
2507 omap_findclk(s, "spi2_iclk"));
2508
4852e5d8 2509 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), sysmem, 0x68000800,
827df9f3 2510 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
0919ac78
PM		 2511 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_DSS_IRQ),
2512 s->drq[OMAP24XX_DMA_DSS],
827df9f3
AZ		 2513 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
2514 omap_findclk(s, "dss_54m_clk"),
2515 omap_findclk(s, "dss_l3_iclk"),
2516 omap_findclk(s, "dss_l4_iclk"));
2517
9bac7d6c 2518 omap_sti_init(omap_l4ta(s->l4, 18), sysmem, 0x54000000,
0919ac78
PM		 2519 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_STI),
2520 omap_findclk(s, "emul_ck"),
9bca0edb
PM		 2521 serial_hd(0) && serial_hd(1) && serial_hd(2) ?
2522 serial_hd(3) : NULL);
54585ffe 2523
99570a40 2524 s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
0919ac78 2525 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_EAC_IRQ),
99570a40
AZ		 2526 /* Ten consecutive lines */
2527 &s->drq[OMAP24XX_DMA_EAC_AC_RD],
2528 omap_findclk(s, "func_96m_clk"),
2529 omap_findclk(s, "core_l4_iclk"));
2530
b3db996f 2531 /* All register mappings (including those not currently implemented):
827df9f3
AZ		 2532 * SystemControlMod 48000000 - 48000fff
2533 * SystemControlL4 48001000 - 48001fff
2534 * 32kHz Timer Mod 48004000 - 48004fff
2535 * 32kHz Timer L4 48005000 - 48005fff
2536 * PRCM ModA 48008000 - 480087ff
2537 * PRCM ModB 48008800 - 48008fff
2538 * PRCM L4 48009000 - 48009fff
2539 * TEST-BCM Mod 48012000 - 48012fff
2540 * TEST-BCM L4 48013000 - 48013fff
2541 * TEST-TAP Mod 48014000 - 48014fff
2542 * TEST-TAP L4 48015000 - 48015fff
2543 * GPIO1 Mod 48018000 - 48018fff
2544 * GPIO Top 48019000 - 48019fff
2545 * GPIO2 Mod 4801a000 - 4801afff
2546 * GPIO L4 4801b000 - 4801bfff
2547 * GPIO3 Mod 4801c000 - 4801cfff
2548 * GPIO4 Mod 4801e000 - 4801efff
2549 * WDTIMER1 Mod 48020000 - 48010fff
2550 * WDTIMER Top 48021000 - 48011fff
2551 * WDTIMER2 Mod 48022000 - 48012fff
2552 * WDTIMER L4 48023000 - 48013fff
2553 * WDTIMER3 Mod 48024000 - 48014fff
2554 * WDTIMER3 L4 48025000 - 48015fff
2555 * WDTIMER4 Mod 48026000 - 48016fff
2556 * WDTIMER4 L4 48027000 - 48017fff
2557 * GPTIMER1 Mod 48028000 - 48018fff
2558 * GPTIMER1 L4 48029000 - 48019fff
2559 * GPTIMER2 Mod 4802a000 - 4801afff
2560 * GPTIMER2 L4 4802b000 - 4801bfff
2561 * L4-Config AP 48040000 - 480407ff
2562 * L4-Config IP 48040800 - 48040fff
2563 * L4-Config LA 48041000 - 48041fff
2564 * ARM11ETB Mod 48048000 - 48049fff
2565 * ARM11ETB L4 4804a000 - 4804afff
2566 * DISPLAY Top 48050000 - 480503ff
2567 * DISPLAY DISPC 48050400 - 480507ff
2568 * DISPLAY RFBI 48050800 - 48050bff
2569 * DISPLAY VENC 48050c00 - 48050fff
2570 * DISPLAY L4 48051000 - 48051fff
2571 * CAMERA Top 48052000 - 480523ff
2572 * CAMERA core 48052400 - 480527ff
2573 * CAMERA DMA 48052800 - 48052bff
2574 * CAMERA MMU 48052c00 - 48052fff
2575 * CAMERA L4 48053000 - 48053fff
2576 * SDMA Mod 48056000 - 48056fff
2577 * SDMA L4 48057000 - 48057fff
2578 * SSI Top 48058000 - 48058fff
2579 * SSI GDD 48059000 - 48059fff
2580 * SSI Port1 4805a000 - 4805afff
2581 * SSI Port2 4805b000 - 4805bfff
2582 * SSI L4 4805c000 - 4805cfff
2583 * USB Mod 4805e000 - 480fefff
2584 * USB L4 4805f000 - 480fffff
2585 * WIN_TRACER1 Mod 48060000 - 48060fff
2586 * WIN_TRACER1 L4 48061000 - 48061fff
2587 * WIN_TRACER2 Mod 48062000 - 48062fff
2588 * WIN_TRACER2 L4 48063000 - 48063fff
2589 * WIN_TRACER3 Mod 48064000 - 48064fff
2590 * WIN_TRACER3 L4 48065000 - 48065fff
2591 * WIN_TRACER4 Top 48066000 - 480660ff
2592 * WIN_TRACER4 ETT 48066100 - 480661ff
2593 * WIN_TRACER4 WT 48066200 - 480662ff
2594 * WIN_TRACER4 L4 48067000 - 48067fff
2595 * XTI Mod 48068000 - 48068fff
2596 * XTI L4 48069000 - 48069fff
2597 * UART1 Mod 4806a000 - 4806afff
2598 * UART1 L4 4806b000 - 4806bfff
2599 * UART2 Mod 4806c000 - 4806cfff
2600 * UART2 L4 4806d000 - 4806dfff
2601 * UART3 Mod 4806e000 - 4806efff
2602 * UART3 L4 4806f000 - 4806ffff
2603 * I2C1 Mod 48070000 - 48070fff
2604 * I2C1 L4 48071000 - 48071fff
2605 * I2C2 Mod 48072000 - 48072fff
2606 * I2C2 L4 48073000 - 48073fff
2607 * McBSP1 Mod 48074000 - 48074fff
2608 * McBSP1 L4 48075000 - 48075fff
2609 * McBSP2 Mod 48076000 - 48076fff
2610 * McBSP2 L4 48077000 - 48077fff
2611 * GPTIMER3 Mod 48078000 - 48078fff
2612 * GPTIMER3 L4 48079000 - 48079fff
2613 * GPTIMER4 Mod 4807a000 - 4807afff
2614 * GPTIMER4 L4 4807b000 - 4807bfff
2615 * GPTIMER5 Mod 4807c000 - 4807cfff
2616 * GPTIMER5 L4 4807d000 - 4807dfff
2617 * GPTIMER6 Mod 4807e000 - 4807efff
2618 * GPTIMER6 L4 4807f000 - 4807ffff
2619 * GPTIMER7 Mod 48080000 - 48080fff
2620 * GPTIMER7 L4 48081000 - 48081fff
2621 * GPTIMER8 Mod 48082000 - 48082fff
2622 * GPTIMER8 L4 48083000 - 48083fff
2623 * GPTIMER9 Mod 48084000 - 48084fff
2624 * GPTIMER9 L4 48085000 - 48085fff
2625 * GPTIMER10 Mod 48086000 - 48086fff
2626 * GPTIMER10 L4 48087000 - 48087fff
2627 * GPTIMER11 Mod 48088000 - 48088fff
2628 * GPTIMER11 L4 48089000 - 48089fff
2629 * GPTIMER12 Mod 4808a000 - 4808afff
2630 * GPTIMER12 L4 4808b000 - 4808bfff
2631 * EAC Mod 48090000 - 48090fff
2632 * EAC L4 48091000 - 48091fff
2633 * FAC Mod 48092000 - 48092fff
2634 * FAC L4 48093000 - 48093fff
2635 * MAILBOX Mod 48094000 - 48094fff
2636 * MAILBOX L4 48095000 - 48095fff
2637 * SPI1 Mod 48098000 - 48098fff
2638 * SPI1 L4 48099000 - 48099fff
2639 * SPI2 Mod 4809a000 - 4809afff
2640 * SPI2 L4 4809b000 - 4809bfff
2641 * MMC/SDIO Mod 4809c000 - 4809cfff
2642 * MMC/SDIO L4 4809d000 - 4809dfff
2643 * MS_PRO Mod 4809e000 - 4809efff
2644 * MS_PRO L4 4809f000 - 4809ffff
2645 * RNG Mod 480a0000 - 480a0fff
2646 * RNG L4 480a1000 - 480a1fff
2647 * DES3DES Mod 480a2000 - 480a2fff
2648 * DES3DES L4 480a3000 - 480a3fff
2649 * SHA1MD5 Mod 480a4000 - 480a4fff
2650 * SHA1MD5 L4 480a5000 - 480a5fff
2651 * AES Mod 480a6000 - 480a6fff
2652 * AES L4 480a7000 - 480a7fff
2653 * PKA Mod 480a8000 - 480a9fff
2654 * PKA L4 480aa000 - 480aafff
2655 * MG Mod 480b0000 - 480b0fff
2656 * MG L4 480b1000 - 480b1fff
2657 * HDQ/1-wire Mod 480b2000 - 480b2fff
2658 * HDQ/1-wire L4 480b3000 - 480b3fff
2659 * MPU interrupt 480fe000 - 480fefff
54585ffe 2660 * STI channel base 54000000 - 5400ffff
827df9f3
AZ		 2661 * IVA RAM 5c000000 - 5c01ffff
2662 * IVA ROM 5c020000 - 5c027fff
2663 * IMG_BUF_A 5c040000 - 5c040fff
2664 * IMG_BUF_B 5c042000 - 5c042fff
2665 * VLCDS 5c048000 - 5c0487ff
2666 * IMX_COEF 5c049000 - 5c04afff
2667 * IMX_CMD 5c051000 - 5c051fff
2668 * VLCDQ 5c053000 - 5c0533ff
2669 * VLCDH 5c054000 - 5c054fff
2670 * SEQ_CMD 5c055000 - 5c055fff
2671 * IMX_REG 5c056000 - 5c0560ff
2672 * VLCD_REG 5c056100 - 5c0561ff
2673 * SEQ_REG 5c056200 - 5c0562ff
2674 * IMG_BUF_REG 5c056300 - 5c0563ff
2675 * SEQIRQ_REG 5c056400 - 5c0564ff
2676 * OCP_REG 5c060000 - 5c060fff
2677 * SYSC_REG 5c070000 - 5c070fff
2678 * MMU_REG 5d000000 - 5d000fff
2679 * sDMA R 68000400 - 680005ff
2680 * sDMA W 68000600 - 680007ff
2681 * Display Control 68000800 - 680009ff
2682 * DSP subsystem 68000a00 - 68000bff
2683 * MPU subsystem 68000c00 - 68000dff
2684 * IVA subsystem 68001000 - 680011ff
2685 * USB 68001200 - 680013ff
2686 * Camera 68001400 - 680015ff
2687 * VLYNQ (firewall) 68001800 - 68001bff
2688 * VLYNQ 68001e00 - 68001fff
2689 * SSI 68002000 - 680021ff
2690 * L4 68002400 - 680025ff
2691 * DSP (firewall) 68002800 - 68002bff
2692 * DSP subsystem 68002e00 - 68002fff
2693 * IVA (firewall) 68003000 - 680033ff
2694 * IVA 68003600 - 680037ff
2695 * GFX 68003a00 - 68003bff
2696 * CMDWR emulation 68003c00 - 68003dff
2697 * SMS 68004000 - 680041ff
2698 * OCM 68004200 - 680043ff
2699 * GPMC 68004400 - 680045ff
2700 * RAM (firewall) 68005000 - 680053ff
2701 * RAM (err login) 68005400 - 680057ff
2702 * ROM (firewall) 68005800 - 68005bff
2703 * ROM (err login) 68005c00 - 68005fff
2704 * GPMC (firewall) 68006000 - 680063ff
2705 * GPMC (err login) 68006400 - 680067ff
2706 * SMS (err login) 68006c00 - 68006fff
2707 * SMS registers 68008000 - 68008fff
2708 * SDRC registers 68009000 - 68009fff
2709 * GPMC registers 6800a000 6800afff
2710 */
2711
a08d4367 2712 qemu_register_reset(omap2_mpu_reset, s);
827df9f3
AZ		 2713
2714 return s;
2715}
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