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Commit | Line | Data |
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5fafdf24 | 1 | /* |
e69954b9 PB |
2 | * ARM RealView Baseboard System emulation. |
3 | * | |
a1bb27b1 | 4 | * Copyright (c) 2006-2007 CodeSourcery. |
e69954b9 PB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
e69954b9 PB |
8 | */ |
9 | ||
12b16722 | 10 | #include "qemu/osdep.h" |
da34e65c | 11 | #include "qapi/error.h" |
4771d756 PB |
12 | #include "qemu-common.h" |
13 | #include "cpu.h" | |
83c9f4ca | 14 | #include "hw/sysbus.h" |
bd2be150 | 15 | #include "hw/arm/arm.h" |
0d09e41a | 16 | #include "hw/arm/primecell.h" |
bd2be150 | 17 | #include "hw/devices.h" |
83c9f4ca | 18 | #include "hw/pci/pci.h" |
1422e32d | 19 | #include "net/net.h" |
9c17d615 | 20 | #include "sysemu/sysemu.h" |
83c9f4ca | 21 | #include "hw/boards.h" |
0d09e41a | 22 | #include "hw/i2c/i2c.h" |
022c62cb | 23 | #include "exec/address-spaces.h" |
b5a3ca3e | 24 | #include "qemu/error-report.h" |
f0d1d2c1 | 25 | #include "hw/char/pl011.h" |
c2de81e2 PMD |
26 | #include "hw/cpu/a9mpcore.h" |
27 | #include "hw/intc/realview_gic.h" | |
e69954b9 | 28 | |
0ef849d7 | 29 | #define SMP_BOOT_ADDR 0xe0000000 |
078758d0 | 30 | #define SMP_BOOTREG_ADDR 0x10000030 |
eee48504 | 31 | |
e69954b9 PB |
32 | /* Board init. */ |
33 | ||
f93eb9ff | 34 | static struct arm_boot_info realview_binfo = { |
0ef849d7 | 35 | .smp_loader_start = SMP_BOOT_ADDR, |
078758d0 | 36 | .smp_bootreg_addr = SMP_BOOTREG_ADDR, |
f93eb9ff AZ |
37 | }; |
38 | ||
f7c70325 | 39 | /* The following two lists must be consistent. */ |
c988bfad PB |
40 | enum realview_board_type { |
41 | BOARD_EB, | |
0ef849d7 | 42 | BOARD_EB_MPCORE, |
f7c70325 PB |
43 | BOARD_PB_A8, |
44 | BOARD_PBX_A9, | |
45 | }; | |
46 | ||
d05ac8fa | 47 | static const int realview_board_id[] = { |
f7c70325 PB |
48 | 0x33b, |
49 | 0x33b, | |
50 | 0x769, | |
51 | 0x76d | |
c988bfad PB |
52 | }; |
53 | ||
3ef96221 | 54 | static void realview_init(MachineState *machine, |
db4ff6f1 | 55 | enum realview_board_type board_type) |
e69954b9 | 56 | { |
9077f01b AF |
57 | ARMCPU *cpu = NULL; |
58 | CPUARMState *env; | |
35e87820 | 59 | MemoryRegion *sysmem = get_system_memory(); |
b1ab03af | 60 | MemoryRegion *ram_lo; |
35e87820 AK |
61 | MemoryRegion *ram_hi = g_new(MemoryRegion, 1); |
62 | MemoryRegion *ram_alias = g_new(MemoryRegion, 1); | |
63 | MemoryRegion *ram_hack = g_new(MemoryRegion, 1); | |
03a0e944 | 64 | DeviceState *dev, *sysctl, *gpio2, *pl041; |
c988bfad | 65 | SysBusDevice *busdev; |
fe7e8758 | 66 | qemu_irq pic[64]; |
26883c69 | 67 | qemu_irq mmc_irq[2]; |
29b358f9 | 68 | PCIBus *pci_bus = NULL; |
e69954b9 | 69 | NICInfo *nd; |
a5c82852 | 70 | I2CBus *i2c; |
e69954b9 | 71 | int n; |
0ef849d7 | 72 | int done_nic = 0; |
9ee6e8bb | 73 | qemu_irq cpu_irq[4]; |
f7c70325 PB |
74 | int is_mpcore = 0; |
75 | int is_pb = 0; | |
26e92f65 | 76 | uint32_t proc_id = 0; |
0ef849d7 PB |
77 | uint32_t sys_id; |
78 | ram_addr_t low_ram_size; | |
3ef96221 | 79 | ram_addr_t ram_size = machine->ram_size; |
b5a3ca3e | 80 | hwaddr periphbase = 0; |
e69954b9 | 81 | |
f7c70325 PB |
82 | switch (board_type) { |
83 | case BOARD_EB: | |
84 | break; | |
85 | case BOARD_EB_MPCORE: | |
86 | is_mpcore = 1; | |
b5a3ca3e | 87 | periphbase = 0x10100000; |
f7c70325 PB |
88 | break; |
89 | case BOARD_PB_A8: | |
90 | is_pb = 1; | |
91 | break; | |
92 | case BOARD_PBX_A9: | |
93 | is_mpcore = 1; | |
94 | is_pb = 1; | |
b5a3ca3e | 95 | periphbase = 0x1f000000; |
f7c70325 PB |
96 | break; |
97 | } | |
b5a3ca3e | 98 | |
c988bfad | 99 | for (n = 0; n < smp_cpus; n++) { |
ba1ba5cc | 100 | Object *cpuobj = object_new(machine->cpu_type); |
b5a3ca3e | 101 | |
61e2f352 GB |
102 | /* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board |
103 | * does not currently support EL3 so the CPU EL3 property is disabled | |
104 | * before realization. | |
105 | */ | |
106 | if (object_property_find(cpuobj, "has_el3", NULL)) { | |
007b0657 | 107 | object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); |
61e2f352 GB |
108 | } |
109 | ||
b5a3ca3e | 110 | if (is_pb && is_mpcore) { |
007b0657 MA |
111 | object_property_set_int(cpuobj, periphbase, "reset-cbar", |
112 | &error_fatal); | |
b5a3ca3e PM |
113 | } |
114 | ||
007b0657 | 115 | object_property_set_bool(cpuobj, true, "realized", &error_fatal); |
b5a3ca3e PM |
116 | |
117 | cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ); | |
aaed909a | 118 | } |
b5a3ca3e | 119 | cpu = ARM_CPU(first_cpu); |
9077f01b | 120 | env = &cpu->env; |
26e92f65 | 121 | if (arm_feature(env, ARM_FEATURE_V7)) { |
f7c70325 PB |
122 | if (is_mpcore) { |
123 | proc_id = 0x0c000000; | |
124 | } else { | |
125 | proc_id = 0x0e000000; | |
126 | } | |
26e92f65 PB |
127 | } else if (arm_feature(env, ARM_FEATURE_V6K)) { |
128 | proc_id = 0x06000000; | |
129 | } else if (arm_feature(env, ARM_FEATURE_V6)) { | |
130 | proc_id = 0x04000000; | |
131 | } else { | |
132 | proc_id = 0x02000000; | |
133 | } | |
aaed909a | 134 | |
21a88941 PB |
135 | if (is_pb && ram_size > 0x20000000) { |
136 | /* Core tile RAM. */ | |
b1ab03af | 137 | ram_lo = g_new(MemoryRegion, 1); |
21a88941 PB |
138 | low_ram_size = ram_size - 0x20000000; |
139 | ram_size = 0x20000000; | |
98a99ce0 | 140 | memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size, |
f8ed85ac | 141 | &error_fatal); |
35e87820 | 142 | memory_region_add_subregion(sysmem, 0x20000000, ram_lo); |
21a88941 PB |
143 | } |
144 | ||
98a99ce0 | 145 | memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size, |
f8ed85ac | 146 | &error_fatal); |
0ef849d7 PB |
147 | low_ram_size = ram_size; |
148 | if (low_ram_size > 0x10000000) | |
149 | low_ram_size = 0x10000000; | |
e69954b9 | 150 | /* SDRAM at address zero. */ |
2c9b15ca | 151 | memory_region_init_alias(ram_alias, NULL, "realview.alias", |
35e87820 AK |
152 | ram_hi, 0, low_ram_size); |
153 | memory_region_add_subregion(sysmem, 0, ram_alias); | |
0ef849d7 PB |
154 | if (is_pb) { |
155 | /* And again at a high address. */ | |
35e87820 | 156 | memory_region_add_subregion(sysmem, 0x70000000, ram_hi); |
0ef849d7 PB |
157 | } else { |
158 | ram_size = low_ram_size; | |
159 | } | |
e69954b9 | 160 | |
0ef849d7 | 161 | sys_id = is_pb ? 0x01780500 : 0xc1400400; |
26883c69 PM |
162 | sysctl = qdev_create(NULL, "realview_sysctl"); |
163 | qdev_prop_set_uint32(sysctl, "sys_id", sys_id); | |
26883c69 | 164 | qdev_prop_set_uint32(sysctl, "proc_id", proc_id); |
7a65c8cc | 165 | qdev_init_nofail(sysctl); |
1356b98d | 166 | sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); |
9ee6e8bb | 167 | |
c988bfad | 168 | if (is_mpcore) { |
c2de81e2 | 169 | dev = qdev_create(NULL, is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore"); |
c988bfad PB |
170 | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); |
171 | qdev_init_nofail(dev); | |
1356b98d | 172 | busdev = SYS_BUS_DEVICE(dev); |
96eacf64 | 173 | sysbus_mmio_map(busdev, 0, periphbase); |
c988bfad PB |
174 | for (n = 0; n < smp_cpus; n++) { |
175 | sysbus_connect_irq(busdev, n, cpu_irq[n]); | |
176 | } | |
96eacf64 PM |
177 | sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL); |
178 | /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ | |
179 | realview_binfo.gic_cpu_if_addr = periphbase + 0x100; | |
9ee6e8bb | 180 | } else { |
0ef849d7 PB |
181 | uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; |
182 | /* For now just create the nIRQ GIC, and ignore the others. */ | |
c2de81e2 | 183 | dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]); |
fe7e8758 PB |
184 | } |
185 | for (n = 0; n < 64; n++) { | |
067a3ddc | 186 | pic[n] = qdev_get_gpio_in(dev, n); |
9ee6e8bb PB |
187 | } |
188 | ||
03a0e944 PM |
189 | pl041 = qdev_create(NULL, "pl041"); |
190 | qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); | |
191 | qdev_init_nofail(pl041); | |
1356b98d AF |
192 | sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); |
193 | sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]); | |
03a0e944 | 194 | |
86394e96 PB |
195 | sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]); |
196 | sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]); | |
e69954b9 | 197 | |
9bca0edb PM |
198 | pl011_create(0x10009000, pic[12], serial_hd(0)); |
199 | pl011_create(0x1000a000, pic[13], serial_hd(1)); | |
200 | pl011_create(0x1000b000, pic[14], serial_hd(2)); | |
201 | pl011_create(0x1000c000, pic[15], serial_hd(3)); | |
e69954b9 PB |
202 | |
203 | /* DMA controller is optional, apparently. */ | |
112a829f PM |
204 | dev = qdev_create(NULL, "pl081"); |
205 | object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream", | |
206 | &error_fatal); | |
207 | qdev_init_nofail(dev); | |
208 | busdev = SYS_BUS_DEVICE(dev); | |
209 | sysbus_mmio_map(busdev, 0, 0x10030000); | |
210 | sysbus_connect_irq(busdev, 0, pic[24]); | |
e69954b9 | 211 | |
6a824ec3 PB |
212 | sysbus_create_simple("sp804", 0x10011000, pic[4]); |
213 | sysbus_create_simple("sp804", 0x10012000, pic[5]); | |
e69954b9 | 214 | |
26883c69 PM |
215 | sysbus_create_simple("pl061", 0x10013000, pic[6]); |
216 | sysbus_create_simple("pl061", 0x10014000, pic[7]); | |
217 | gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]); | |
218 | ||
acb9b722 | 219 | sysbus_create_simple("pl111", 0x10020000, pic[23]); |
e69954b9 | 220 | |
26883c69 PM |
221 | dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL); |
222 | /* Wire up MMC card detect and read-only signals. These have | |
223 | * to go to both the PL061 GPIO and the sysctl register. | |
224 | * Note that the PL181 orders these lines (readonly,inserted) | |
225 | * and the PL061 has them the other way about. Also the card | |
226 | * detect line is inverted. | |
227 | */ | |
228 | mmc_irq[0] = qemu_irq_split( | |
229 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), | |
230 | qdev_get_gpio_in(gpio2, 1)); | |
231 | mmc_irq[1] = qemu_irq_split( | |
232 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), | |
233 | qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); | |
234 | qdev_connect_gpio_out(dev, 0, mmc_irq[0]); | |
235 | qdev_connect_gpio_out(dev, 1, mmc_irq[1]); | |
a1bb27b1 | 236 | |
a63bdb31 | 237 | sysbus_create_simple("pl031", 0x10017000, pic[10]); |
7e1543c2 | 238 | |
0ef849d7 | 239 | if (!is_pb) { |
7d6e771f | 240 | dev = qdev_create(NULL, "realview_pci"); |
1356b98d | 241 | busdev = SYS_BUS_DEVICE(dev); |
7d6e771f | 242 | qdev_init_nofail(dev); |
7468d73a | 243 | sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */ |
a2bff788 PM |
244 | sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */ |
245 | sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */ | |
246 | sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */ | |
89a32d32 PM |
247 | sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */ |
248 | sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */ | |
249 | sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */ | |
7d6e771f PM |
250 | sysbus_connect_irq(busdev, 0, pic[48]); |
251 | sysbus_connect_irq(busdev, 1, pic[49]); | |
252 | sysbus_connect_irq(busdev, 2, pic[50]); | |
253 | sysbus_connect_irq(busdev, 3, pic[51]); | |
0ef849d7 | 254 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); |
4bcbe0b6 | 255 | if (machine_usb(machine)) { |
afb9a60e | 256 | pci_create_simple(pci_bus, -1, "pci-ohci"); |
0ef849d7 PB |
257 | } |
258 | n = drive_get_max_bus(IF_SCSI); | |
259 | while (n >= 0) { | |
877eb21d MCA |
260 | dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a")); |
261 | lsi53c8xx_handle_legacy_cmdline(dev); | |
0ef849d7 PB |
262 | n--; |
263 | } | |
e69954b9 PB |
264 | } |
265 | for(n = 0; n < nb_nics; n++) { | |
266 | nd = &nd_table[n]; | |
0ae18cee | 267 | |
e6b3c8ca PM |
268 | if (!done_nic && (!nd->model || |
269 | strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) { | |
0ef849d7 PB |
270 | if (is_pb) { |
271 | lan9118_init(nd, 0x4e000000, pic[28]); | |
272 | } else { | |
273 | smc91c111_init(nd, 0x4e000000, pic[28]); | |
274 | } | |
275 | done_nic = 1; | |
e69954b9 | 276 | } else { |
29b358f9 DG |
277 | if (pci_bus) { |
278 | pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL); | |
279 | } | |
e69954b9 PB |
280 | } |
281 | } | |
282 | ||
d1157ca4 | 283 | dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL); |
a5c82852 | 284 | i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); |
eee48504 PB |
285 | i2c_create_slave(i2c, "ds1338", 0x68); |
286 | ||
e69954b9 PB |
287 | /* Memory map for RealView Emulation Baseboard: */ |
288 | /* 0x10000000 System registers. */ | |
289 | /* 0x10001000 System controller. */ | |
eee48504 | 290 | /* 0x10002000 Two-Wire Serial Bus. */ |
e69954b9 PB |
291 | /* 0x10003000 Reserved. */ |
292 | /* 0x10004000 AACI. */ | |
293 | /* 0x10005000 MCI. */ | |
294 | /* 0x10006000 KMI0. */ | |
295 | /* 0x10007000 KMI1. */ | |
0ef849d7 | 296 | /* 0x10008000 Character LCD. (EB) */ |
e69954b9 PB |
297 | /* 0x10009000 UART0. */ |
298 | /* 0x1000a000 UART1. */ | |
299 | /* 0x1000b000 UART2. */ | |
300 | /* 0x1000c000 UART3. */ | |
301 | /* 0x1000d000 SSPI. */ | |
302 | /* 0x1000e000 SCI. */ | |
303 | /* 0x1000f000 Reserved. */ | |
304 | /* 0x10010000 Watchdog. */ | |
305 | /* 0x10011000 Timer 0+1. */ | |
306 | /* 0x10012000 Timer 2+3. */ | |
307 | /* 0x10013000 GPIO 0. */ | |
308 | /* 0x10014000 GPIO 1. */ | |
309 | /* 0x10015000 GPIO 2. */ | |
0ef849d7 | 310 | /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */ |
7e1543c2 | 311 | /* 0x10017000 RTC. */ |
e69954b9 PB |
312 | /* 0x10018000 DMC. */ |
313 | /* 0x10019000 PCI controller config. */ | |
314 | /* 0x10020000 CLCD. */ | |
315 | /* 0x10030000 DMA Controller. */ | |
0ef849d7 PB |
316 | /* 0x10040000 GIC1. (EB) */ |
317 | /* 0x10050000 GIC2. (EB) */ | |
318 | /* 0x10060000 GIC3. (EB) */ | |
319 | /* 0x10070000 GIC4. (EB) */ | |
e69954b9 | 320 | /* 0x10080000 SMC. */ |
0ef849d7 PB |
321 | /* 0x1e000000 GIC1. (PB) */ |
322 | /* 0x1e001000 GIC2. (PB) */ | |
323 | /* 0x1e002000 GIC3. (PB) */ | |
324 | /* 0x1e003000 GIC4. (PB) */ | |
e69954b9 PB |
325 | /* 0x40000000 NOR flash. */ |
326 | /* 0x44000000 DoC flash. */ | |
327 | /* 0x48000000 SRAM. */ | |
328 | /* 0x4c000000 Configuration flash. */ | |
329 | /* 0x4e000000 Ethernet. */ | |
330 | /* 0x4f000000 USB. */ | |
331 | /* 0x50000000 PISMO. */ | |
332 | /* 0x54000000 PISMO. */ | |
333 | /* 0x58000000 PISMO. */ | |
334 | /* 0x5c000000 PISMO. */ | |
335 | /* 0x60000000 PCI. */ | |
a2bff788 PM |
336 | /* 0x60000000 PCI Self Config. */ |
337 | /* 0x61000000 PCI Config. */ | |
338 | /* 0x62000000 PCI IO. */ | |
339 | /* 0x63000000 PCI mem 0. */ | |
340 | /* 0x64000000 PCI mem 1. */ | |
341 | /* 0x68000000 PCI mem 2. */ | |
e69954b9 | 342 | |
7ffab4d7 PB |
343 | /* ??? Hack to map an additional page of ram for the secondary CPU |
344 | startup code. I guess this works on real hardware because the | |
345 | BootROM happens to be in ROM/flash or in memory that isn't clobbered | |
346 | until after Linux boots the secondary CPUs. */ | |
98a99ce0 | 347 | memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000, |
f8ed85ac | 348 | &error_fatal); |
35e87820 | 349 | memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); |
7ffab4d7 | 350 | |
f93eb9ff | 351 | realview_binfo.ram_size = ram_size; |
3ef96221 MA |
352 | realview_binfo.kernel_filename = machine->kernel_filename; |
353 | realview_binfo.kernel_cmdline = machine->kernel_cmdline; | |
354 | realview_binfo.initrd_filename = machine->initrd_filename; | |
c988bfad | 355 | realview_binfo.nb_cpus = smp_cpus; |
f7c70325 | 356 | realview_binfo.board_id = realview_board_id[board_type]; |
21a88941 | 357 | realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0); |
182735ef | 358 | arm_load_kernel(ARM_CPU(first_cpu), &realview_binfo); |
e69954b9 PB |
359 | } |
360 | ||
3ef96221 | 361 | static void realview_eb_init(MachineState *machine) |
c988bfad | 362 | { |
3ef96221 | 363 | realview_init(machine, BOARD_EB); |
c988bfad PB |
364 | } |
365 | ||
3ef96221 | 366 | static void realview_eb_mpcore_init(MachineState *machine) |
c988bfad | 367 | { |
3ef96221 | 368 | realview_init(machine, BOARD_EB_MPCORE); |
c988bfad PB |
369 | } |
370 | ||
3ef96221 | 371 | static void realview_pb_a8_init(MachineState *machine) |
0ef849d7 | 372 | { |
3ef96221 | 373 | realview_init(machine, BOARD_PB_A8); |
0ef849d7 PB |
374 | } |
375 | ||
3ef96221 | 376 | static void realview_pbx_a9_init(MachineState *machine) |
f7c70325 | 377 | { |
3ef96221 | 378 | realview_init(machine, BOARD_PBX_A9); |
f7c70325 PB |
379 | } |
380 | ||
8a661aea | 381 | static void realview_eb_class_init(ObjectClass *oc, void *data) |
e264d29d | 382 | { |
8a661aea AF |
383 | MachineClass *mc = MACHINE_CLASS(oc); |
384 | ||
e264d29d EH |
385 | mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)"; |
386 | mc->init = realview_eb_init; | |
387 | mc->block_default_type = IF_SCSI; | |
4672cbd7 | 388 | mc->ignore_memory_transaction_failures = true; |
ba1ba5cc | 389 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); |
e264d29d | 390 | } |
c988bfad | 391 | |
8a661aea AF |
392 | static const TypeInfo realview_eb_type = { |
393 | .name = MACHINE_TYPE_NAME("realview-eb"), | |
394 | .parent = TYPE_MACHINE, | |
395 | .class_init = realview_eb_class_init, | |
396 | }; | |
f80f9ec9 | 397 | |
8a661aea | 398 | static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data) |
e264d29d | 399 | { |
8a661aea AF |
400 | MachineClass *mc = MACHINE_CLASS(oc); |
401 | ||
e264d29d EH |
402 | mc->desc = "ARM RealView Emulation Baseboard (ARM11MPCore)"; |
403 | mc->init = realview_eb_mpcore_init; | |
404 | mc->block_default_type = IF_SCSI; | |
405 | mc->max_cpus = 4; | |
4672cbd7 | 406 | mc->ignore_memory_transaction_failures = true; |
ba1ba5cc | 407 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore"); |
e264d29d | 408 | } |
f7c70325 | 409 | |
8a661aea AF |
410 | static const TypeInfo realview_eb_mpcore_type = { |
411 | .name = MACHINE_TYPE_NAME("realview-eb-mpcore"), | |
412 | .parent = TYPE_MACHINE, | |
413 | .class_init = realview_eb_mpcore_class_init, | |
414 | }; | |
e264d29d | 415 | |
8a661aea | 416 | static void realview_pb_a8_class_init(ObjectClass *oc, void *data) |
e264d29d | 417 | { |
8a661aea AF |
418 | MachineClass *mc = MACHINE_CLASS(oc); |
419 | ||
e264d29d EH |
420 | mc->desc = "ARM RealView Platform Baseboard for Cortex-A8"; |
421 | mc->init = realview_pb_a8_init; | |
4672cbd7 | 422 | mc->ignore_memory_transaction_failures = true; |
ba1ba5cc | 423 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8"); |
e264d29d EH |
424 | } |
425 | ||
8a661aea AF |
426 | static const TypeInfo realview_pb_a8_type = { |
427 | .name = MACHINE_TYPE_NAME("realview-pb-a8"), | |
428 | .parent = TYPE_MACHINE, | |
429 | .class_init = realview_pb_a8_class_init, | |
430 | }; | |
0ef849d7 | 431 | |
8a661aea | 432 | static void realview_pbx_a9_class_init(ObjectClass *oc, void *data) |
f80f9ec9 | 433 | { |
8a661aea AF |
434 | MachineClass *mc = MACHINE_CLASS(oc); |
435 | ||
e264d29d EH |
436 | mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9"; |
437 | mc->init = realview_pbx_a9_init; | |
e264d29d | 438 | mc->max_cpus = 4; |
4672cbd7 | 439 | mc->ignore_memory_transaction_failures = true; |
ba1ba5cc | 440 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); |
f80f9ec9 AL |
441 | } |
442 | ||
8a661aea AF |
443 | static const TypeInfo realview_pbx_a9_type = { |
444 | .name = MACHINE_TYPE_NAME("realview-pbx-a9"), | |
445 | .parent = TYPE_MACHINE, | |
446 | .class_init = realview_pbx_a9_class_init, | |
447 | }; | |
448 | ||
449 | static void realview_machine_init(void) | |
450 | { | |
451 | type_register_static(&realview_eb_type); | |
452 | type_register_static(&realview_eb_mpcore_type); | |
453 | type_register_static(&realview_pb_a8_type); | |
454 | type_register_static(&realview_pbx_a9_type); | |
455 | } | |
456 | ||
0e6aac87 | 457 | type_init(realview_machine_init) |