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527773ee EA |
1 | /* |
2 | * Copyright (C) 2014-2016 Broadcom Corporation | |
3 | * Copyright (c) 2017 Red Hat, Inc. | |
4 | * Written by Prem Mallappa, Eric Auger | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * Author: Prem Mallappa <pmallapp@broadcom.com> | |
16 | * | |
17 | */ | |
18 | ||
19 | #include "qemu/osdep.h" | |
527773ee EA |
20 | #include "trace.h" |
21 | #include "exec/target_page.h" | |
2e5b09fd | 22 | #include "hw/core/cpu.h" |
527773ee EA |
23 | #include "hw/qdev-properties.h" |
24 | #include "qapi/error.h" | |
cc27ed81 | 25 | #include "qemu/jhash.h" |
0b8fa32f | 26 | #include "qemu/module.h" |
527773ee EA |
27 | |
28 | #include "qemu/error-report.h" | |
29 | #include "hw/arm/smmu-common.h" | |
93641948 EA |
30 | #include "smmu-internal.h" |
31 | ||
cc27ed81 EA |
32 | /* IOTLB Management */ |
33 | ||
60a61f1b EA |
34 | static guint smmu_iotlb_key_hash(gconstpointer v) |
35 | { | |
36 | SMMUIOTLBKey *key = (SMMUIOTLBKey *)v; | |
37 | uint32_t a, b, c; | |
38 | ||
39 | /* Jenkins hash */ | |
40 | a = b = c = JHASH_INITVAL + sizeof(*key); | |
9e54dee7 | 41 | a += key->asid + key->level + key->tg; |
60a61f1b EA |
42 | b += extract64(key->iova, 0, 32); |
43 | c += extract64(key->iova, 32, 32); | |
44 | ||
45 | __jhash_mix(a, b, c); | |
46 | __jhash_final(a, b, c); | |
47 | ||
48 | return c; | |
49 | } | |
50 | ||
51 | static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2) | |
52 | { | |
9e54dee7 | 53 | SMMUIOTLBKey *k1 = (SMMUIOTLBKey *)v1, *k2 = (SMMUIOTLBKey *)v2; |
60a61f1b | 54 | |
9e54dee7 EA |
55 | return (k1->asid == k2->asid) && (k1->iova == k2->iova) && |
56 | (k1->level == k2->level) && (k1->tg == k2->tg); | |
60a61f1b EA |
57 | } |
58 | ||
9e54dee7 EA |
59 | SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova, |
60 | uint8_t tg, uint8_t level) | |
60a61f1b | 61 | { |
9e54dee7 | 62 | SMMUIOTLBKey key = {.asid = asid, .iova = iova, .tg = tg, .level = level}; |
60a61f1b EA |
63 | |
64 | return key; | |
65 | } | |
66 | ||
a7550158 | 67 | SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, |
9e54dee7 | 68 | SMMUTransTableInfo *tt, hwaddr iova) |
6808bca9 | 69 | { |
9e54dee7 EA |
70 | uint8_t tg = (tt->granule_sz - 10) / 2; |
71 | uint8_t inputsize = 64 - tt->tsz; | |
72 | uint8_t stride = tt->granule_sz - 3; | |
73 | uint8_t level = 4 - (inputsize - 4) / stride; | |
74 | SMMUTLBEntry *entry = NULL; | |
75 | ||
76 | while (level <= 3) { | |
77 | uint64_t subpage_size = 1ULL << level_shift(level, tt->granule_sz); | |
78 | uint64_t mask = subpage_size - 1; | |
79 | SMMUIOTLBKey key; | |
80 | ||
81 | key = smmu_get_iotlb_key(cfg->asid, iova & ~mask, tg, level); | |
82 | entry = g_hash_table_lookup(bs->iotlb, &key); | |
83 | if (entry) { | |
84 | break; | |
85 | } | |
86 | level++; | |
87 | } | |
6808bca9 EA |
88 | |
89 | if (entry) { | |
90 | cfg->iotlb_hits++; | |
91 | trace_smmu_iotlb_lookup_hit(cfg->asid, iova, | |
92 | cfg->iotlb_hits, cfg->iotlb_misses, | |
93 | 100 * cfg->iotlb_hits / | |
94 | (cfg->iotlb_hits + cfg->iotlb_misses)); | |
95 | } else { | |
96 | cfg->iotlb_misses++; | |
97 | trace_smmu_iotlb_lookup_miss(cfg->asid, iova, | |
98 | cfg->iotlb_hits, cfg->iotlb_misses, | |
99 | 100 * cfg->iotlb_hits / | |
100 | (cfg->iotlb_hits + cfg->iotlb_misses)); | |
101 | } | |
102 | return entry; | |
103 | } | |
104 | ||
a7550158 | 105 | void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *new) |
6808bca9 EA |
106 | { |
107 | SMMUIOTLBKey *key = g_new0(SMMUIOTLBKey, 1); | |
9e54dee7 | 108 | uint8_t tg = (new->granule - 10) / 2; |
6808bca9 EA |
109 | |
110 | if (g_hash_table_size(bs->iotlb) >= SMMU_IOTLB_MAX_SIZE) { | |
111 | smmu_iotlb_inv_all(bs); | |
112 | } | |
113 | ||
9e54dee7 EA |
114 | *key = smmu_get_iotlb_key(cfg->asid, new->entry.iova, tg, new->level); |
115 | trace_smmu_iotlb_insert(cfg->asid, new->entry.iova, tg, new->level); | |
a7550158 | 116 | g_hash_table_insert(bs->iotlb, key, new); |
6808bca9 EA |
117 | } |
118 | ||
9de9fa5c | 119 | void smmu_iotlb_inv_all(SMMUState *s) |
cc27ed81 EA |
120 | { |
121 | trace_smmu_iotlb_inv_all(); | |
122 | g_hash_table_remove_all(s->iotlb); | |
123 | } | |
124 | ||
125 | static gboolean smmu_hash_remove_by_asid(gpointer key, gpointer value, | |
126 | gpointer user_data) | |
127 | { | |
128 | uint16_t asid = *(uint16_t *)user_data; | |
129 | SMMUIOTLBKey *iotlb_key = (SMMUIOTLBKey *)key; | |
130 | ||
60a61f1b | 131 | return SMMU_IOTLB_ASID(*iotlb_key) == asid; |
cc27ed81 EA |
132 | } |
133 | ||
9e54dee7 EA |
134 | static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value, |
135 | gpointer user_data) | |
cc27ed81 | 136 | { |
9e54dee7 EA |
137 | SMMUTLBEntry *iter = (SMMUTLBEntry *)value; |
138 | IOMMUTLBEntry *entry = &iter->entry; | |
139 | SMMUIOTLBPageInvInfo *info = (SMMUIOTLBPageInvInfo *)user_data; | |
140 | SMMUIOTLBKey iotlb_key = *(SMMUIOTLBKey *)key; | |
141 | ||
142 | if (info->asid >= 0 && info->asid != SMMU_IOTLB_ASID(iotlb_key)) { | |
143 | return false; | |
144 | } | |
d5291561 EA |
145 | return ((info->iova & ~entry->addr_mask) == entry->iova) || |
146 | ((entry->iova & ~info->mask) == info->iova); | |
9e54dee7 EA |
147 | } |
148 | ||
9de9fa5c PMD |
149 | void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, |
150 | uint8_t tg, uint64_t num_pages, uint8_t ttl) | |
9e54dee7 | 151 | { |
6d9cd115 EA |
152 | /* if tg is not set we use 4KB range invalidation */ |
153 | uint8_t granule = tg ? tg * 2 + 10 : 12; | |
154 | ||
a4b6e1be | 155 | if (ttl && (num_pages == 1) && (asid >= 0)) { |
d5291561 | 156 | SMMUIOTLBKey key = smmu_get_iotlb_key(asid, iova, tg, ttl); |
cc27ed81 | 157 | |
6d9cd115 EA |
158 | if (g_hash_table_remove(s->iotlb, &key)) { |
159 | return; | |
160 | } | |
161 | /* | |
162 | * if the entry is not found, let's see if it does not | |
163 | * belong to a larger IOTLB entry | |
164 | */ | |
165 | } | |
d5291561 | 166 | |
6d9cd115 EA |
167 | SMMUIOTLBPageInvInfo info = { |
168 | .asid = asid, .iova = iova, | |
169 | .mask = (num_pages * 1 << granule) - 1}; | |
d5291561 | 170 | |
6d9cd115 EA |
171 | g_hash_table_foreach_remove(s->iotlb, |
172 | smmu_hash_remove_by_asid_iova, | |
173 | &info); | |
cc27ed81 EA |
174 | } |
175 | ||
9de9fa5c | 176 | void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid) |
cc27ed81 EA |
177 | { |
178 | trace_smmu_iotlb_inv_asid(asid); | |
179 | g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid); | |
180 | } | |
181 | ||
93641948 EA |
182 | /* VMSAv8-64 Translation */ |
183 | ||
184 | /** | |
185 | * get_pte - Get the content of a page table entry located at | |
186 | * @base_addr[@index] | |
187 | */ | |
188 | static int get_pte(dma_addr_t baseaddr, uint32_t index, uint64_t *pte, | |
189 | SMMUPTWEventInfo *info) | |
190 | { | |
191 | int ret; | |
192 | dma_addr_t addr = baseaddr + index * sizeof(*pte); | |
193 | ||
194 | /* TODO: guarantee 64-bit single-copy atomicity */ | |
ba06fe8a PMD |
195 | ret = dma_memory_read(&address_space_memory, addr, pte, sizeof(*pte), |
196 | MEMTXATTRS_UNSPECIFIED); | |
93641948 EA |
197 | |
198 | if (ret != MEMTX_OK) { | |
199 | info->type = SMMU_PTW_ERR_WALK_EABT; | |
200 | info->addr = addr; | |
201 | return -EINVAL; | |
202 | } | |
203 | trace_smmu_get_pte(baseaddr, index, addr, *pte); | |
204 | return 0; | |
205 | } | |
206 | ||
207 | /* VMSAv8-64 Translation Table Format Descriptor Decoding */ | |
208 | ||
209 | /** | |
210 | * get_page_pte_address - returns the L3 descriptor output address, | |
211 | * ie. the page frame | |
212 | * ARM ARM spec: Figure D4-17 VMSAv8-64 level 3 descriptor format | |
213 | */ | |
214 | static inline hwaddr get_page_pte_address(uint64_t pte, int granule_sz) | |
215 | { | |
216 | return PTE_ADDRESS(pte, granule_sz); | |
217 | } | |
218 | ||
219 | /** | |
220 | * get_table_pte_address - return table descriptor output address, | |
221 | * ie. address of next level table | |
222 | * ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats | |
223 | */ | |
224 | static inline hwaddr get_table_pte_address(uint64_t pte, int granule_sz) | |
225 | { | |
226 | return PTE_ADDRESS(pte, granule_sz); | |
227 | } | |
228 | ||
229 | /** | |
230 | * get_block_pte_address - return block descriptor output address and block size | |
231 | * ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats | |
232 | */ | |
233 | static inline hwaddr get_block_pte_address(uint64_t pte, int level, | |
234 | int granule_sz, uint64_t *bsz) | |
235 | { | |
118eee6c | 236 | int n = level_shift(level, granule_sz); |
93641948 | 237 | |
118eee6c | 238 | *bsz = 1ULL << n; |
93641948 EA |
239 | return PTE_ADDRESS(pte, n); |
240 | } | |
241 | ||
242 | SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova) | |
243 | { | |
244 | bool tbi = extract64(iova, 55, 1) ? TBI1(cfg->tbi) : TBI0(cfg->tbi); | |
245 | uint8_t tbi_byte = tbi * 8; | |
246 | ||
247 | if (cfg->tt[0].tsz && | |
248 | !extract64(iova, 64 - cfg->tt[0].tsz, cfg->tt[0].tsz - tbi_byte)) { | |
249 | /* there is a ttbr0 region and we are in it (high bits all zero) */ | |
250 | return &cfg->tt[0]; | |
251 | } else if (cfg->tt[1].tsz && | |
e431b8f6 | 252 | sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) { |
93641948 EA |
253 | /* there is a ttbr1 region and we are in it (high bits all one) */ |
254 | return &cfg->tt[1]; | |
255 | } else if (!cfg->tt[0].tsz) { | |
256 | /* ttbr0 region is "everything not in the ttbr1 region" */ | |
257 | return &cfg->tt[0]; | |
258 | } else if (!cfg->tt[1].tsz) { | |
259 | /* ttbr1 region is "everything not in the ttbr0 region" */ | |
260 | return &cfg->tt[1]; | |
261 | } | |
262 | /* in the gap between the two regions, this is a Translation fault */ | |
263 | return NULL; | |
264 | } | |
265 | ||
266 | /** | |
267 | * smmu_ptw_64 - VMSAv8-64 Walk of the page tables for a given IOVA | |
268 | * @cfg: translation config | |
269 | * @iova: iova to translate | |
270 | * @perm: access type | |
a7550158 | 271 | * @tlbe: SMMUTLBEntry (out) |
93641948 EA |
272 | * @info: handle to an error info |
273 | * | |
274 | * Return 0 on success, < 0 on error. In case of error, @info is filled | |
275 | * and tlbe->perm is set to IOMMU_NONE. | |
276 | * Upon success, @tlbe is filled with translated_addr and entry | |
277 | * permission rights. | |
278 | */ | |
279 | static int smmu_ptw_64(SMMUTransCfg *cfg, | |
280 | dma_addr_t iova, IOMMUAccessFlags perm, | |
a7550158 | 281 | SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) |
93641948 EA |
282 | { |
283 | dma_addr_t baseaddr, indexmask; | |
284 | int stage = cfg->stage; | |
285 | SMMUTransTableInfo *tt = select_tt(cfg, iova); | |
286 | uint8_t level, granule_sz, inputsize, stride; | |
287 | ||
288 | if (!tt || tt->disabled) { | |
289 | info->type = SMMU_PTW_ERR_TRANSLATION; | |
290 | goto error; | |
291 | } | |
292 | ||
293 | granule_sz = tt->granule_sz; | |
294 | stride = granule_sz - 3; | |
295 | inputsize = 64 - tt->tsz; | |
296 | level = 4 - (inputsize - 4) / stride; | |
297 | indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; | |
298 | baseaddr = extract64(tt->ttb, 0, 48); | |
299 | baseaddr &= ~indexmask; | |
300 | ||
93641948 EA |
301 | while (level <= 3) { |
302 | uint64_t subpage_size = 1ULL << level_shift(level, granule_sz); | |
303 | uint64_t mask = subpage_size - 1; | |
304 | uint32_t offset = iova_level_offset(iova, inputsize, level, granule_sz); | |
1733837d | 305 | uint64_t pte, gpa; |
93641948 EA |
306 | dma_addr_t pte_addr = baseaddr + offset * sizeof(pte); |
307 | uint8_t ap; | |
308 | ||
309 | if (get_pte(baseaddr, offset, &pte, info)) { | |
310 | goto error; | |
311 | } | |
312 | trace_smmu_ptw_level(level, iova, subpage_size, | |
313 | baseaddr, offset, pte); | |
314 | ||
315 | if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) { | |
316 | trace_smmu_ptw_invalid_pte(stage, level, baseaddr, | |
317 | pte_addr, offset, pte); | |
1733837d | 318 | break; |
93641948 EA |
319 | } |
320 | ||
1733837d EA |
321 | if (is_table_pte(pte, level)) { |
322 | ap = PTE_APTABLE(pte); | |
93641948 | 323 | |
e7c3b9d9 | 324 | if (is_permission_fault(ap, perm) && !tt->had) { |
93641948 EA |
325 | info->type = SMMU_PTW_ERR_PERMISSION; |
326 | goto error; | |
327 | } | |
1733837d EA |
328 | baseaddr = get_table_pte_address(pte, granule_sz); |
329 | level++; | |
330 | continue; | |
331 | } else if (is_page_pte(pte, level)) { | |
332 | gpa = get_page_pte_address(pte, granule_sz); | |
93641948 EA |
333 | trace_smmu_ptw_page_pte(stage, level, iova, |
334 | baseaddr, pte_addr, pte, gpa); | |
1733837d | 335 | } else { |
93641948 | 336 | uint64_t block_size; |
93641948 | 337 | |
1733837d EA |
338 | gpa = get_block_pte_address(pte, level, granule_sz, |
339 | &block_size); | |
93641948 EA |
340 | trace_smmu_ptw_block_pte(stage, level, baseaddr, |
341 | pte_addr, pte, iova, gpa, | |
342 | block_size >> 20); | |
93641948 | 343 | } |
1733837d | 344 | ap = PTE_AP(pte); |
93641948 EA |
345 | if (is_permission_fault(ap, perm)) { |
346 | info->type = SMMU_PTW_ERR_PERMISSION; | |
347 | goto error; | |
348 | } | |
93641948 | 349 | |
9e54dee7 EA |
350 | tlbe->entry.translated_addr = gpa; |
351 | tlbe->entry.iova = iova & ~mask; | |
352 | tlbe->entry.addr_mask = mask; | |
a7550158 EA |
353 | tlbe->entry.perm = PTE_AP_TO_PERM(ap); |
354 | tlbe->level = level; | |
355 | tlbe->granule = granule_sz; | |
1733837d EA |
356 | return 0; |
357 | } | |
93641948 EA |
358 | info->type = SMMU_PTW_ERR_TRANSLATION; |
359 | ||
360 | error: | |
a7550158 | 361 | tlbe->entry.perm = IOMMU_NONE; |
93641948 EA |
362 | return -EINVAL; |
363 | } | |
364 | ||
365 | /** | |
366 | * smmu_ptw - Walk the page tables for an IOVA, according to @cfg | |
367 | * | |
368 | * @cfg: translation configuration | |
369 | * @iova: iova to translate | |
370 | * @perm: tentative access type | |
371 | * @tlbe: returned entry | |
372 | * @info: ptw event handle | |
373 | * | |
374 | * return 0 on success | |
375 | */ | |
9de9fa5c PMD |
376 | int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, |
377 | SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) | |
93641948 EA |
378 | { |
379 | if (!cfg->aa64) { | |
380 | /* | |
381 | * This code path is not entered as we check this while decoding | |
382 | * the configuration data in the derived SMMU model. | |
383 | */ | |
384 | g_assert_not_reached(); | |
385 | } | |
386 | ||
387 | return smmu_ptw_64(cfg, iova, perm, tlbe, info); | |
388 | } | |
527773ee | 389 | |
cac994ef EA |
390 | /** |
391 | * The bus number is used for lookup when SID based invalidation occurs. | |
392 | * In that case we lazily populate the SMMUPciBus array from the bus hash | |
393 | * table. At the time the SMMUPciBus is created (smmu_find_add_as), the bus | |
394 | * numbers may not be always initialized yet. | |
395 | */ | |
396 | SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num) | |
397 | { | |
398 | SMMUPciBus *smmu_pci_bus = s->smmu_pcibus_by_bus_num[bus_num]; | |
5ca0e6fe | 399 | GHashTableIter iter; |
cac994ef | 400 | |
5ca0e6fe PMD |
401 | if (smmu_pci_bus) { |
402 | return smmu_pci_bus; | |
403 | } | |
cac994ef | 404 | |
5ca0e6fe PMD |
405 | g_hash_table_iter_init(&iter, s->smmu_pcibus_by_busptr); |
406 | while (g_hash_table_iter_next(&iter, NULL, (void **)&smmu_pci_bus)) { | |
407 | if (pci_bus_num(smmu_pci_bus->bus) == bus_num) { | |
408 | s->smmu_pcibus_by_bus_num[bus_num] = smmu_pci_bus; | |
409 | return smmu_pci_bus; | |
cac994ef EA |
410 | } |
411 | } | |
5ca0e6fe PMD |
412 | |
413 | return NULL; | |
cac994ef EA |
414 | } |
415 | ||
416 | static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) | |
417 | { | |
418 | SMMUState *s = opaque; | |
419 | SMMUPciBus *sbus = g_hash_table_lookup(s->smmu_pcibus_by_busptr, bus); | |
420 | SMMUDevice *sdev; | |
6ce9297b | 421 | static unsigned int index; |
cac994ef EA |
422 | |
423 | if (!sbus) { | |
424 | sbus = g_malloc0(sizeof(SMMUPciBus) + | |
425 | sizeof(SMMUDevice *) * SMMU_PCI_DEVFN_MAX); | |
426 | sbus->bus = bus; | |
427 | g_hash_table_insert(s->smmu_pcibus_by_busptr, bus, sbus); | |
428 | } | |
429 | ||
430 | sdev = sbus->pbdev[devfn]; | |
431 | if (!sdev) { | |
6ce9297b EA |
432 | char *name = g_strdup_printf("%s-%d-%d", s->mrtypename, devfn, index++); |
433 | ||
cac994ef EA |
434 | sdev = sbus->pbdev[devfn] = g_new0(SMMUDevice, 1); |
435 | ||
436 | sdev->smmu = s; | |
437 | sdev->bus = bus; | |
438 | sdev->devfn = devfn; | |
439 | ||
440 | memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), | |
441 | s->mrtypename, | |
ca3fbed8 | 442 | OBJECT(s), name, UINT64_MAX); |
cac994ef EA |
443 | address_space_init(&sdev->as, |
444 | MEMORY_REGION(&sdev->iommu), name); | |
445 | trace_smmu_add_mr(name); | |
446 | g_free(name); | |
447 | } | |
448 | ||
449 | return &sdev->as; | |
450 | } | |
451 | ||
32cfd7f3 EA |
452 | IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid) |
453 | { | |
454 | uint8_t bus_n, devfn; | |
455 | SMMUPciBus *smmu_bus; | |
456 | SMMUDevice *smmu; | |
457 | ||
458 | bus_n = PCI_BUS_NUM(sid); | |
459 | smmu_bus = smmu_find_smmu_pcibus(s, bus_n); | |
460 | if (smmu_bus) { | |
b78aae9b | 461 | devfn = SMMU_PCI_DEVFN(sid); |
32cfd7f3 EA |
462 | smmu = smmu_bus->pbdev[devfn]; |
463 | if (smmu) { | |
464 | return &smmu->iommu; | |
465 | } | |
466 | } | |
467 | return NULL; | |
468 | } | |
469 | ||
832e4222 | 470 | /* Unmap all notifiers attached to @mr */ |
1e793dd6 | 471 | static void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr) |
832e4222 EA |
472 | { |
473 | IOMMUNotifier *n; | |
474 | ||
475 | trace_smmu_inv_notifiers_mr(mr->parent_obj.name); | |
476 | IOMMU_NOTIFIER_FOREACH(n, mr) { | |
98332f64 | 477 | memory_region_unmap_iommu_notifier_range(n); |
832e4222 EA |
478 | } |
479 | } | |
480 | ||
481 | /* Unmap all notifiers of all mr's */ | |
482 | void smmu_inv_notifiers_all(SMMUState *s) | |
483 | { | |
c6370441 | 484 | SMMUDevice *sdev; |
832e4222 | 485 | |
c6370441 EA |
486 | QLIST_FOREACH(sdev, &s->devices_with_notifiers, next) { |
487 | smmu_inv_notifiers_mr(&sdev->iommu); | |
832e4222 EA |
488 | } |
489 | } | |
490 | ||
527773ee EA |
491 | static void smmu_base_realize(DeviceState *dev, Error **errp) |
492 | { | |
cac994ef | 493 | SMMUState *s = ARM_SMMU(dev); |
527773ee EA |
494 | SMMUBaseClass *sbc = ARM_SMMU_GET_CLASS(dev); |
495 | Error *local_err = NULL; | |
496 | ||
497 | sbc->parent_realize(dev, &local_err); | |
498 | if (local_err) { | |
499 | error_propagate(errp, local_err); | |
500 | return; | |
501 | } | |
32cfd7f3 | 502 | s->configs = g_hash_table_new_full(NULL, NULL, NULL, g_free); |
cc27ed81 EA |
503 | s->iotlb = g_hash_table_new_full(smmu_iotlb_key_hash, smmu_iotlb_key_equal, |
504 | g_free, g_free); | |
cac994ef EA |
505 | s->smmu_pcibus_by_busptr = g_hash_table_new(NULL, NULL); |
506 | ||
507 | if (s->primary_bus) { | |
508 | pci_setup_iommu(s->primary_bus, smmu_find_add_as, s); | |
509 | } else { | |
510 | error_setg(errp, "SMMU is not attached to any PCI bus!"); | |
511 | } | |
527773ee EA |
512 | } |
513 | ||
3c1a7c41 | 514 | static void smmu_base_reset_hold(Object *obj) |
527773ee | 515 | { |
3c1a7c41 | 516 | SMMUState *s = ARM_SMMU(obj); |
32cfd7f3 EA |
517 | |
518 | g_hash_table_remove_all(s->configs); | |
cc27ed81 | 519 | g_hash_table_remove_all(s->iotlb); |
527773ee EA |
520 | } |
521 | ||
522 | static Property smmu_dev_properties[] = { | |
523 | DEFINE_PROP_UINT8("bus_num", SMMUState, bus_num, 0), | |
c45e7619 PMD |
524 | DEFINE_PROP_LINK("primary-bus", SMMUState, primary_bus, |
525 | TYPE_PCI_BUS, PCIBus *), | |
527773ee EA |
526 | DEFINE_PROP_END_OF_LIST(), |
527 | }; | |
528 | ||
529 | static void smmu_base_class_init(ObjectClass *klass, void *data) | |
530 | { | |
531 | DeviceClass *dc = DEVICE_CLASS(klass); | |
3c1a7c41 | 532 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
527773ee EA |
533 | SMMUBaseClass *sbc = ARM_SMMU_CLASS(klass); |
534 | ||
4f67d30b | 535 | device_class_set_props(dc, smmu_dev_properties); |
527773ee EA |
536 | device_class_set_parent_realize(dc, smmu_base_realize, |
537 | &sbc->parent_realize); | |
3c1a7c41 | 538 | rc->phases.hold = smmu_base_reset_hold; |
527773ee EA |
539 | } |
540 | ||
541 | static const TypeInfo smmu_base_info = { | |
542 | .name = TYPE_ARM_SMMU, | |
543 | .parent = TYPE_SYS_BUS_DEVICE, | |
544 | .instance_size = sizeof(SMMUState), | |
545 | .class_data = NULL, | |
546 | .class_size = sizeof(SMMUBaseClass), | |
547 | .class_init = smmu_base_class_init, | |
548 | .abstract = true, | |
549 | }; | |
550 | ||
551 | static void smmu_base_register_types(void) | |
552 | { | |
553 | type_register_static(&smmu_base_info); | |
554 | } | |
555 | ||
556 | type_init(smmu_base_register_types) | |
557 |