[mirror_qemu.git] / hw / arm / stm32f205_soc.c

/*
 * STM32F205 SoC
 *
 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "hw/arm/boot.h"
#include "exec/address-spaces.h"
#include "hw/arm/stm32f205_soc.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-clock.h"
#include "sysemu/sysemu.h"

/* At the moment only Timer 2 to 5 are modelled */
static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
    0x40000800, 0x40000C00 };
static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
    0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
    0x40012200 };
static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
    0x40003C00 };

static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
#define ADC_IRQ 18
static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};

static void stm32f205_soc_initfn(Object *obj)
{
    STM32F205State *s = STM32F205_SOC(obj);
    int i;

    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);

    object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F2XX_SYSCFG);

    for (i = 0; i < STM_NUM_USARTS; i++) {
        object_initialize_child(obj, "usart[*]", &s->usart[i],
                                TYPE_STM32F2XX_USART);
    }

    for (i = 0; i < STM_NUM_TIMERS; i++) {
        object_initialize_child(obj, "timer[*]", &s->timer[i],
                                TYPE_STM32F2XX_TIMER);
    }

    s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));

    for (i = 0; i < STM_NUM_ADCS; i++) {
        object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC);
    }

    for (i = 0; i < STM_NUM_SPIS; i++) {
        object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
    }

    s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
    s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
}

static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
{
    STM32F205State *s = STM32F205_SOC(dev_soc);
    DeviceState *dev, *armv7m;
    SysBusDevice *busdev;
    int i;

    MemoryRegion *system_memory = get_system_memory();

    /*
     * We use s->refclk internally and only define it with qdev_init_clock_in()
     * so it is correctly parented and not leaked on an init/deinit; it is not
     * intended as an externally exposed clock.
     */
    if (clock_has_source(s->refclk)) {
        error_setg(errp, "refclk clock must not be wired up by the board code");
        return;
    }

    if (!clock_has_source(s->sysclk)) {
        error_setg(errp, "sysclk clock must be wired up by the board code");
        return;
    }

    /*
     * TODO: ideally we should model the SoC RCC and its ability to
     * change the sysclk frequency and define different sysclk sources.
     */

    /* The refclk always runs at frequency HCLK / 8 */
    clock_set_mul_div(s->refclk, 8, 1);
    clock_set_source(s->refclk, s->sysclk);

    memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash",
                           FLASH_SIZE, &error_fatal);
    memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
                             "STM32F205.flash.alias", &s->flash, 0, FLASH_SIZE);

    memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
    memory_region_add_subregion(system_memory, 0, &s->flash_alias);

    memory_region_init_ram(&s->sram, NULL, "STM32F205.sram", SRAM_SIZE,
                           &error_fatal);
    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);

    armv7m = DEVICE(&s->armv7m);
    qdev_prop_set_uint32(armv7m, "num-irq", 96);
    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
    qdev_prop_set_bit(armv7m, "enable-bitband", true);
    qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
    qdev_connect_clock_in(armv7m, "refclk", s->refclk);
    object_property_set_link(OBJECT(&s->armv7m), "memory",
                             OBJECT(get_system_memory()), &error_abort);
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
        return;
    }

    /* System configuration controller */
    dev = DEVICE(&s->syscfg);
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) {
        return;
    }
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, 0x40013800);

    /* Attach UART (uses USART registers) and USART controllers */
    for (i = 0; i < STM_NUM_USARTS; i++) {
        dev = DEVICE(&(s->usart[i]));
        qdev_prop_set_chr(dev, "chardev", serial_hd(i));
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
            return;
        }
        busdev = SYS_BUS_DEVICE(dev);
        sysbus_mmio_map(busdev, 0, usart_addr[i]);
        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
    }

    /* Timer 2 to 5 */
    for (i = 0; i < STM_NUM_TIMERS; i++) {
        dev = DEVICE(&(s->timer[i]));
        qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) {
            return;
        }
        busdev = SYS_BUS_DEVICE(dev);
        sysbus_mmio_map(busdev, 0, timer_addr[i]);
        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
    }

    /* ADC 1 to 3 */
    object_property_set_int(OBJECT(s->adc_irqs), "num-lines", STM_NUM_ADCS,
                            &error_abort);
    if (!qdev_realize(DEVICE(s->adc_irqs), NULL, errp)) {
        return;
    }
    qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
                          qdev_get_gpio_in(armv7m, ADC_IRQ));

    for (i = 0; i < STM_NUM_ADCS; i++) {
        dev = DEVICE(&(s->adc[i]));
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), errp)) {
            return;
        }
        busdev = SYS_BUS_DEVICE(dev);
        sysbus_mmio_map(busdev, 0, adc_addr[i]);
        sysbus_connect_irq(busdev, 0,
                           qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
    }

    /* SPI 1 and 2 */
    for (i = 0; i < STM_NUM_SPIS; i++) {
        dev = DEVICE(&(s->spi[i]));
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
            return;
        }
        busdev = SYS_BUS_DEVICE(dev);
        sysbus_mmio_map(busdev, 0, spi_addr[i]);
        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
    }
}

static Property stm32f205_soc_properties[] = {
    DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
    DEFINE_PROP_END_OF_LIST(),
};

static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = stm32f205_soc_realize;
    device_class_set_props(dc, stm32f205_soc_properties);
}

static const TypeInfo stm32f205_soc_info = {
    .name          = TYPE_STM32F205_SOC,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(STM32F205State),
    .instance_init = stm32f205_soc_initfn,
    .class_init    = stm32f205_soc_class_init,
};

static void stm32f205_soc_types(void)
{
    type_register_static(&stm32f205_soc_info);
}

type_init(stm32f205_soc_types)
Commit	Line	Data
db635521 AF	1	/*
	2	* STM32F205 SoC
	3	*
	4	* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
12b16722	25	#include "qemu/osdep.h"
da34e65c	26	#include "qapi/error.h"
0b8fa32f	27	#include "qemu/module.h"
12ec8bd5	28	#include "hw/arm/boot.h"
db635521 AF	29	#include "exec/address-spaces.h"
db635521 AF	30	#include "hw/arm/stm32f205_soc.h"
a27bd6c7	31	#include "hw/qdev-properties.h"
68ba05fb	32	#include "hw/qdev-clock.h"
46517dd4	33	#include "sysemu/sysemu.h"
db635521 AF	34
	35	/* At the moment only Timer 2 to 5 are modelled */
	36	static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
	37	0x40000800, 0x40000C00 };
	38	static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
	39	0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
b63041c8 AF	40	static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
b63041c8 AF	41	0x40012200 };
540a8f34 AF	42	static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
540a8f34 AF	43	0x40003C00 };
db635521 AF	44
	45	static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
	46	static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
b63041c8	47	#define ADC_IRQ 18
540a8f34	48	static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};
db635521 AF	49
	50	static void stm32f205_soc_initfn(Object *obj)
	51	{
	52	STM32F205State *s = STM32F205_SOC(obj);
	53	int i;
	54
db873cc5	55	object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
b72e2f68	56
db873cc5	57	object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F2XX_SYSCFG);
db635521 AF	58
db635521 AF	59	for (i = 0; i < STM_NUM_USARTS; i++) {
db873cc5 MA	60	object_initialize_child(obj, "usart[*]", &s->usart[i],
db873cc5 MA	61	TYPE_STM32F2XX_USART);
db635521 AF	62	}
	63
	64	for (i = 0; i < STM_NUM_TIMERS; i++) {
db873cc5 MA	65	object_initialize_child(obj, "timer[*]", &s->timer[i],
db873cc5 MA	66	TYPE_STM32F2XX_TIMER);
db635521	67	}
b63041c8 AF	68
	69	s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));
	70
	71	for (i = 0; i < STM_NUM_ADCS; i++) {
db873cc5	72	object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC);
b63041c8	73	}
540a8f34 AF	74
540a8f34 AF	75	for (i = 0; i < STM_NUM_SPIS; i++) {
db873cc5	76	object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
540a8f34	77	}
68ba05fb PM	78
	79	s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
	80	s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
db635521 AF	81	}
	82
	83	static void stm32f205_soc_realize(DeviceState dev_soc, Error *errp)
	84	{
	85	STM32F205State *s = STM32F205_SOC(dev_soc);
8a85e065	86	DeviceState dev, armv7m;
81fed1d0	87	SysBusDevice *busdev;
db635521 AF	88	int i;
	89
	90	MemoryRegion *system_memory = get_system_memory();
db635521	91
68ba05fb PM	92	/*
	93	* We use s->refclk internally and only define it with qdev_init_clock_in()
	94	* so it is correctly parented and not leaked on an init/deinit; it is not
	95	* intended as an externally exposed clock.
	96	*/
	97	if (clock_has_source(s->refclk)) {
	98	error_setg(errp, "refclk clock must not be wired up by the board code");
	99	return;
	100	}
	101
	102	if (!clock_has_source(s->sysclk)) {
	103	error_setg(errp, "sysclk clock must be wired up by the board code");
	104	return;
	105	}
	106
	107	/*
	108	* TODO: ideally we should model the SoC RCC and its ability to
	109	* change the sysclk frequency and define different sysclk sources.
	110	*/
	111
	112	/* The refclk always runs at frequency HCLK / 8 */
	113	clock_set_mul_div(s->refclk, 8, 1);
	114	clock_set_source(s->refclk, s->sysclk);
	115
cabc613f	116	memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash",
32b9523a	117	FLASH_SIZE, &error_fatal);
cabc613f PM	118	memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
cabc613f PM	119	"STM32F205.flash.alias", &s->flash, 0, FLASH_SIZE);
db635521	120
cabc613f PM	121	memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
cabc613f PM	122	memory_region_add_subregion(system_memory, 0, &s->flash_alias);
db635521	123
cabc613f	124	memory_region_init_ram(&s->sram, NULL, "STM32F205.sram", SRAM_SIZE,
f8ed85ac	125	&error_fatal);
cabc613f	126	memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
db635521	127
8a85e065 PM	128	armv7m = DEVICE(&s->armv7m);
8a85e065 PM	129	qdev_prop_set_uint32(armv7m, "num-irq", 96);
ba1ba5cc	130	qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
a1c5a062	131	qdev_prop_set_bit(armv7m, "enable-bitband", true);
68ba05fb PM	132	qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
68ba05fb PM	133	qdev_connect_clock_in(armv7m, "refclk", s->refclk);
5325cc34 MA	134	object_property_set_link(OBJECT(&s->armv7m), "memory",
5325cc34 MA	135	OBJECT(get_system_memory()), &error_abort);
668f62ec	136	if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
b72e2f68 PM	137	return;
b72e2f68 PM	138	}
db635521 AF	139
db635521 AF	140	/* System configuration controller */
81fed1d0	141	dev = DEVICE(&s->syscfg);
668f62ec	142	if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) {
db635521 AF	143	return;
db635521 AF	144	}
81fed1d0 AF	145	busdev = SYS_BUS_DEVICE(dev);
81fed1d0 AF	146	sysbus_mmio_map(busdev, 0, 0x40013800);
db635521 AF	147
	148	/* Attach UART (uses USART registers) and USART controllers */
	149	for (i = 0; i < STM_NUM_USARTS; i++) {
81fed1d0	150	dev = DEVICE(&(s->usart[i]));
fc38a112	151	qdev_prop_set_chr(dev, "chardev", serial_hd(i));
668f62ec	152	if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
db635521 AF	153	return;
db635521 AF	154	}
81fed1d0 AF	155	busdev = SYS_BUS_DEVICE(dev);
81fed1d0 AF	156	sysbus_mmio_map(busdev, 0, usart_addr[i]);
8a85e065	157	sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
db635521 AF	158	}
	159
	160	/* Timer 2 to 5 */
	161	for (i = 0; i < STM_NUM_TIMERS; i++) {
81fed1d0 AF	162	dev = DEVICE(&(s->timer[i]));
81fed1d0 AF	163	qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
668f62ec	164	if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) {
db635521 AF	165	return;
db635521 AF	166	}
81fed1d0 AF	167	busdev = SYS_BUS_DEVICE(dev);
81fed1d0 AF	168	sysbus_mmio_map(busdev, 0, timer_addr[i]);
8a85e065	169	sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
db635521	170	}
b63041c8 AF	171
b63041c8 AF	172	/* ADC 1 to 3 */
5325cc34 MA	173	object_property_set_int(OBJECT(s->adc_irqs), "num-lines", STM_NUM_ADCS,
5325cc34 MA	174	&error_abort);
668f62ec	175	if (!qdev_realize(DEVICE(s->adc_irqs), NULL, errp)) {
b63041c8 AF	176	return;
	177	}
	178	qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
8a85e065	179	qdev_get_gpio_in(armv7m, ADC_IRQ));
b63041c8 AF	180
	181	for (i = 0; i < STM_NUM_ADCS; i++) {
	182	dev = DEVICE(&(s->adc[i]));
668f62ec	183	if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), errp)) {
b63041c8 AF	184	return;
	185	}
	186	busdev = SYS_BUS_DEVICE(dev);
	187	sysbus_mmio_map(busdev, 0, adc_addr[i]);
	188	sysbus_connect_irq(busdev, 0,
	189	qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
	190	}
540a8f34 AF	191
	192	/* SPI 1 and 2 */
	193	for (i = 0; i < STM_NUM_SPIS; i++) {
	194	dev = DEVICE(&(s->spi[i]));
668f62ec	195	if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
540a8f34 AF	196	return;
	197	}
	198	busdev = SYS_BUS_DEVICE(dev);
	199	sysbus_mmio_map(busdev, 0, spi_addr[i]);
8a85e065	200	sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
540a8f34	201	}
db635521 AF	202	}
	203
	204	static Property stm32f205_soc_properties[] = {
ba1ba5cc	205	DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
db635521 AF	206	DEFINE_PROP_END_OF_LIST(),
	207	};
	208
	209	static void stm32f205_soc_class_init(ObjectClass klass, void data)
	210	{
	211	DeviceClass *dc = DEVICE_CLASS(klass);
	212
	213	dc->realize = stm32f205_soc_realize;
4f67d30b	214	device_class_set_props(dc, stm32f205_soc_properties);
db635521 AF	215	}
	216
	217	static const TypeInfo stm32f205_soc_info = {
	218	.name = TYPE_STM32F205_SOC,
	219	.parent = TYPE_SYS_BUS_DEVICE,
	220	.instance_size = sizeof(STM32F205State),
	221	.instance_init = stm32f205_soc_initfn,
	222	.class_init = stm32f205_soc_class_init,
	223	};
	224
	225	static void stm32f205_soc_types(void)
	226	{
	227	type_register_static(&stm32f205_soc_info);
	228	}
	229
	230	type_init(stm32f205_soc_types)