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Commit | Line | Data |
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5fafdf24 | 1 | /* |
9ee6e8bb | 2 | * ARM Generic/Distributed Interrupt Controller |
e69954b9 | 3 | * |
9ee6e8bb | 4 | * Copyright (c) 2006-2007 CodeSourcery. |
e69954b9 PB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
e69954b9 PB |
8 | */ |
9 | ||
9ee6e8bb | 10 | /* This file contains implementation code for the RealView EB interrupt |
0d256bdc PM |
11 | * controller, MPCore distributed interrupt controller and ARMv7-M |
12 | * Nested Vectored Interrupt Controller. | |
13 | * It is compiled in two ways: | |
14 | * (1) as a standalone file to produce a sysbus device which is a GIC | |
15 | * that can be used on the realview board and as one of the builtin | |
16 | * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) | |
17 | * (2) by being directly #included into armv7m_nvic.c to produce the | |
18 | * armv7m_nvic device. | |
19 | */ | |
e69954b9 | 20 | |
496dbcd1 PM |
21 | #include "sysbus.h" |
22 | ||
a32134aa ML |
23 | /* Maximum number of possible interrupts, determined by the GIC architecture */ |
24 | #define GIC_MAXIRQ 1020 | |
69253800 RR |
25 | /* First 32 are private to each CPU (SGIs and PPIs). */ |
26 | #define GIC_INTERNAL 32 | |
386e2955 | 27 | /* Maximum number of possible CPU interfaces, determined by GIC architecture */ |
386e2955 | 28 | #define NCPU 8 |
386e2955 | 29 | |
e69954b9 PB |
30 | //#define DEBUG_GIC |
31 | ||
32 | #ifdef DEBUG_GIC | |
001faf32 BS |
33 | #define DPRINTF(fmt, ...) \ |
34 | do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0) | |
e69954b9 | 35 | #else |
001faf32 | 36 | #define DPRINTF(fmt, ...) do {} while(0) |
e69954b9 PB |
37 | #endif |
38 | ||
9ee6e8bb PB |
39 | #ifdef NVIC |
40 | static const uint8_t gic_id[] = | |
41 | { 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 }; | |
9ee6e8bb PB |
42 | /* The NVIC has 16 internal vectors. However these are not exposed |
43 | through the normal GIC interface. */ | |
44 | #define GIC_BASE_IRQ 32 | |
45 | #else | |
e69954b9 PB |
46 | static const uint8_t gic_id[] = |
47 | { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; | |
9ee6e8bb PB |
48 | #define GIC_BASE_IRQ 0 |
49 | #endif | |
e69954b9 | 50 | |
fe7e8758 PB |
51 | #define FROM_SYSBUSGIC(type, dev) \ |
52 | DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev)) | |
53 | ||
e69954b9 PB |
54 | typedef struct gic_irq_state |
55 | { | |
41bf234d RV |
56 | /* The enable bits are only banked for per-cpu interrupts. */ |
57 | unsigned enabled:NCPU; | |
9ee6e8bb PB |
58 | unsigned pending:NCPU; |
59 | unsigned active:NCPU; | |
a45db6c6 | 60 | unsigned level:NCPU; |
9ee6e8bb | 61 | unsigned model:1; /* 0 = N:N, 1 = 1:N */ |
e69954b9 PB |
62 | unsigned trigger:1; /* nonzero = edge triggered. */ |
63 | } gic_irq_state; | |
64 | ||
386e2955 | 65 | #define ALL_CPU_MASK ((unsigned)(((1 << NCPU) - 1))) |
c988bfad | 66 | #define NUM_CPU(s) ((s)->num_cpu) |
9ee6e8bb | 67 | |
41bf234d RV |
68 | #define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm) |
69 | #define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm) | |
70 | #define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0) | |
9ee6e8bb PB |
71 | #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm) |
72 | #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm) | |
73 | #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0) | |
74 | #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm) | |
75 | #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm) | |
76 | #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0) | |
e69954b9 PB |
77 | #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1 |
78 | #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0 | |
79 | #define GIC_TEST_MODEL(irq) s->irq_state[irq].model | |
9ee6e8bb PB |
80 | #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm) |
81 | #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm) | |
57d69a91 | 82 | #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0) |
e69954b9 PB |
83 | #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1 |
84 | #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0 | |
85 | #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger | |
69253800 RR |
86 | #define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \ |
87 | s->priority1[irq][cpu] : \ | |
88 | s->priority2[(irq) - GIC_INTERNAL]) | |
9ee6e8bb PB |
89 | #ifdef NVIC |
90 | #define GIC_TARGET(irq) 1 | |
91 | #else | |
92 | #define GIC_TARGET(irq) s->irq_target[irq] | |
93 | #endif | |
e69954b9 PB |
94 | |
95 | typedef struct gic_state | |
96 | { | |
fe7e8758 | 97 | SysBusDevice busdev; |
9ee6e8bb | 98 | qemu_irq parent_irq[NCPU]; |
e69954b9 | 99 | int enabled; |
9ee6e8bb | 100 | int cpu_enabled[NCPU]; |
e69954b9 | 101 | |
a32134aa | 102 | gic_irq_state irq_state[GIC_MAXIRQ]; |
a32134aa | 103 | int irq_target[GIC_MAXIRQ]; |
69253800 RR |
104 | int priority1[GIC_INTERNAL][NCPU]; |
105 | int priority2[GIC_MAXIRQ - GIC_INTERNAL]; | |
a32134aa | 106 | int last_active[GIC_MAXIRQ][NCPU]; |
9ee6e8bb PB |
107 | |
108 | int priority_mask[NCPU]; | |
109 | int running_irq[NCPU]; | |
110 | int running_priority[NCPU]; | |
111 | int current_pending[NCPU]; | |
112 | ||
496dbcd1 | 113 | uint32_t num_cpu; |
c988bfad | 114 | |
e2c56465 | 115 | MemoryRegion iomem; /* Distributor */ |
e2c56465 PM |
116 | /* This is just so we can have an opaque pointer which identifies |
117 | * both this GIC and which CPU interface we should be accessing. | |
118 | */ | |
119 | struct gic_state *backref[NCPU]; | |
120 | MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */ | |
a32134aa | 121 | uint32_t num_irq; |
e69954b9 PB |
122 | } gic_state; |
123 | ||
926c4aff PM |
124 | static inline int gic_get_current_cpu(gic_state *s) |
125 | { | |
926c4aff PM |
126 | if (s->num_cpu > 1) { |
127 | return cpu_single_env->cpu_index; | |
128 | } | |
926c4aff PM |
129 | return 0; |
130 | } | |
131 | ||
e69954b9 PB |
132 | /* TODO: Many places that call this routine could be optimized. */ |
133 | /* Update interrupt status after enabled or pending bits have been changed. */ | |
134 | static void gic_update(gic_state *s) | |
135 | { | |
136 | int best_irq; | |
137 | int best_prio; | |
138 | int irq; | |
9ee6e8bb PB |
139 | int level; |
140 | int cpu; | |
141 | int cm; | |
142 | ||
c988bfad | 143 | for (cpu = 0; cpu < NUM_CPU(s); cpu++) { |
9ee6e8bb PB |
144 | cm = 1 << cpu; |
145 | s->current_pending[cpu] = 1023; | |
146 | if (!s->enabled || !s->cpu_enabled[cpu]) { | |
c79981ce | 147 | qemu_irq_lower(s->parent_irq[cpu]); |
9ee6e8bb PB |
148 | return; |
149 | } | |
150 | best_prio = 0x100; | |
151 | best_irq = 1023; | |
a32134aa | 152 | for (irq = 0; irq < s->num_irq; irq++) { |
41bf234d | 153 | if (GIC_TEST_ENABLED(irq, cm) && GIC_TEST_PENDING(irq, cm)) { |
9ee6e8bb PB |
154 | if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { |
155 | best_prio = GIC_GET_PRIORITY(irq, cpu); | |
156 | best_irq = irq; | |
157 | } | |
e69954b9 PB |
158 | } |
159 | } | |
9ee6e8bb PB |
160 | level = 0; |
161 | if (best_prio <= s->priority_mask[cpu]) { | |
162 | s->current_pending[cpu] = best_irq; | |
163 | if (best_prio < s->running_priority[cpu]) { | |
164 | DPRINTF("Raised pending IRQ %d\n", best_irq); | |
165 | level = 1; | |
166 | } | |
e69954b9 | 167 | } |
9ee6e8bb | 168 | qemu_set_irq(s->parent_irq[cpu], level); |
e69954b9 PB |
169 | } |
170 | } | |
171 | ||
b7dc1a59 PM |
172 | #ifdef NVIC |
173 | static void gic_set_pending_private(gic_state *s, int cpu, int irq) | |
9ee6e8bb PB |
174 | { |
175 | int cm = 1 << cpu; | |
176 | ||
177 | if (GIC_TEST_PENDING(irq, cm)) | |
178 | return; | |
179 | ||
180 | DPRINTF("Set %d pending cpu %d\n", irq, cpu); | |
181 | GIC_SET_PENDING(irq, cm); | |
182 | gic_update(s); | |
183 | } | |
b7dc1a59 | 184 | #endif |
9ee6e8bb PB |
185 | |
186 | /* Process a change in an external IRQ input. */ | |
e69954b9 PB |
187 | static void gic_set_irq(void *opaque, int irq, int level) |
188 | { | |
544d1afa PM |
189 | /* Meaning of the 'irq' parameter: |
190 | * [0..N-1] : external interrupts | |
191 | * [N..N+31] : PPI (internal) interrupts for CPU 0 | |
192 | * [N+32..N+63] : PPI (internal interrupts for CPU 1 | |
193 | * ... | |
194 | */ | |
e69954b9 | 195 | gic_state *s = (gic_state *)opaque; |
544d1afa PM |
196 | int cm, target; |
197 | if (irq < (s->num_irq - GIC_INTERNAL)) { | |
198 | /* The first external input line is internal interrupt 32. */ | |
199 | cm = ALL_CPU_MASK; | |
200 | irq += GIC_INTERNAL; | |
201 | target = GIC_TARGET(irq); | |
202 | } else { | |
203 | int cpu; | |
204 | irq -= (s->num_irq - GIC_INTERNAL); | |
205 | cpu = irq / GIC_INTERNAL; | |
206 | irq %= GIC_INTERNAL; | |
207 | cm = 1 << cpu; | |
208 | target = cm; | |
209 | } | |
210 | ||
211 | if (level == GIC_TEST_LEVEL(irq, cm)) { | |
e69954b9 | 212 | return; |
544d1afa | 213 | } |
e69954b9 PB |
214 | |
215 | if (level) { | |
544d1afa PM |
216 | GIC_SET_LEVEL(irq, cm); |
217 | if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { | |
218 | DPRINTF("Set %d pending mask %x\n", irq, target); | |
219 | GIC_SET_PENDING(irq, target); | |
e69954b9 PB |
220 | } |
221 | } else { | |
544d1afa | 222 | GIC_CLEAR_LEVEL(irq, cm); |
e69954b9 PB |
223 | } |
224 | gic_update(s); | |
225 | } | |
226 | ||
9ee6e8bb | 227 | static void gic_set_running_irq(gic_state *s, int cpu, int irq) |
e69954b9 | 228 | { |
9ee6e8bb PB |
229 | s->running_irq[cpu] = irq; |
230 | if (irq == 1023) { | |
231 | s->running_priority[cpu] = 0x100; | |
232 | } else { | |
233 | s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); | |
234 | } | |
e69954b9 PB |
235 | gic_update(s); |
236 | } | |
237 | ||
9ee6e8bb | 238 | static uint32_t gic_acknowledge_irq(gic_state *s, int cpu) |
e69954b9 PB |
239 | { |
240 | int new_irq; | |
9ee6e8bb PB |
241 | int cm = 1 << cpu; |
242 | new_irq = s->current_pending[cpu]; | |
243 | if (new_irq == 1023 | |
244 | || GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) { | |
e69954b9 PB |
245 | DPRINTF("ACK no pending IRQ\n"); |
246 | return 1023; | |
247 | } | |
9ee6e8bb PB |
248 | s->last_active[new_irq][cpu] = s->running_irq[cpu]; |
249 | /* Clear pending flags for both level and edge triggered interrupts. | |
250 | Level triggered IRQs will be reasserted once they become inactive. */ | |
251 | GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm); | |
252 | gic_set_running_irq(s, cpu, new_irq); | |
e69954b9 PB |
253 | DPRINTF("ACK %d\n", new_irq); |
254 | return new_irq; | |
255 | } | |
256 | ||
9ee6e8bb | 257 | static void gic_complete_irq(gic_state * s, int cpu, int irq) |
e69954b9 PB |
258 | { |
259 | int update = 0; | |
9ee6e8bb | 260 | int cm = 1 << cpu; |
df628ff1 | 261 | DPRINTF("EOI %d\n", irq); |
a32134aa | 262 | if (irq >= s->num_irq) { |
217bfb44 PM |
263 | /* This handles two cases: |
264 | * 1. If software writes the ID of a spurious interrupt [ie 1023] | |
265 | * to the GICC_EOIR, the GIC ignores that write. | |
266 | * 2. If software writes the number of a non-existent interrupt | |
267 | * this must be a subcase of "value written does not match the last | |
268 | * valid interrupt value read from the Interrupt Acknowledge | |
269 | * register" and so this is UNPREDICTABLE. We choose to ignore it. | |
270 | */ | |
271 | return; | |
272 | } | |
9ee6e8bb | 273 | if (s->running_irq[cpu] == 1023) |
e69954b9 | 274 | return; /* No active IRQ. */ |
217bfb44 PM |
275 | /* Mark level triggered interrupts as pending if they are still |
276 | raised. */ | |
277 | if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) | |
278 | && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { | |
279 | DPRINTF("Set %d pending mask %x\n", irq, cm); | |
280 | GIC_SET_PENDING(irq, cm); | |
281 | update = 1; | |
e69954b9 | 282 | } |
9ee6e8bb | 283 | if (irq != s->running_irq[cpu]) { |
e69954b9 | 284 | /* Complete an IRQ that is not currently running. */ |
9ee6e8bb PB |
285 | int tmp = s->running_irq[cpu]; |
286 | while (s->last_active[tmp][cpu] != 1023) { | |
287 | if (s->last_active[tmp][cpu] == irq) { | |
288 | s->last_active[tmp][cpu] = s->last_active[irq][cpu]; | |
e69954b9 PB |
289 | break; |
290 | } | |
9ee6e8bb | 291 | tmp = s->last_active[tmp][cpu]; |
e69954b9 PB |
292 | } |
293 | if (update) { | |
294 | gic_update(s); | |
295 | } | |
296 | } else { | |
297 | /* Complete the current running IRQ. */ | |
9ee6e8bb | 298 | gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); |
e69954b9 PB |
299 | } |
300 | } | |
301 | ||
c227f099 | 302 | static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) |
e69954b9 PB |
303 | { |
304 | gic_state *s = (gic_state *)opaque; | |
305 | uint32_t res; | |
306 | int irq; | |
307 | int i; | |
9ee6e8bb PB |
308 | int cpu; |
309 | int cm; | |
310 | int mask; | |
e69954b9 | 311 | |
926c4aff | 312 | cpu = gic_get_current_cpu(s); |
9ee6e8bb | 313 | cm = 1 << cpu; |
e69954b9 | 314 | if (offset < 0x100) { |
9ee6e8bb | 315 | #ifndef NVIC |
e69954b9 PB |
316 | if (offset == 0) |
317 | return s->enabled; | |
318 | if (offset == 4) | |
a32134aa | 319 | return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5); |
e69954b9 PB |
320 | if (offset < 0x08) |
321 | return 0; | |
b79f2265 RH |
322 | if (offset >= 0x80) { |
323 | /* Interrupt Security , RAZ/WI */ | |
324 | return 0; | |
325 | } | |
9ee6e8bb | 326 | #endif |
e69954b9 PB |
327 | goto bad_reg; |
328 | } else if (offset < 0x200) { | |
329 | /* Interrupt Set/Clear Enable. */ | |
330 | if (offset < 0x180) | |
331 | irq = (offset - 0x100) * 8; | |
332 | else | |
333 | irq = (offset - 0x180) * 8; | |
9ee6e8bb | 334 | irq += GIC_BASE_IRQ; |
a32134aa | 335 | if (irq >= s->num_irq) |
e69954b9 PB |
336 | goto bad_reg; |
337 | res = 0; | |
338 | for (i = 0; i < 8; i++) { | |
41bf234d | 339 | if (GIC_TEST_ENABLED(irq + i, cm)) { |
e69954b9 PB |
340 | res |= (1 << i); |
341 | } | |
342 | } | |
343 | } else if (offset < 0x300) { | |
344 | /* Interrupt Set/Clear Pending. */ | |
345 | if (offset < 0x280) | |
346 | irq = (offset - 0x200) * 8; | |
347 | else | |
348 | irq = (offset - 0x280) * 8; | |
9ee6e8bb | 349 | irq += GIC_BASE_IRQ; |
a32134aa | 350 | if (irq >= s->num_irq) |
e69954b9 PB |
351 | goto bad_reg; |
352 | res = 0; | |
69253800 | 353 | mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; |
e69954b9 | 354 | for (i = 0; i < 8; i++) { |
9ee6e8bb | 355 | if (GIC_TEST_PENDING(irq + i, mask)) { |
e69954b9 PB |
356 | res |= (1 << i); |
357 | } | |
358 | } | |
359 | } else if (offset < 0x400) { | |
360 | /* Interrupt Active. */ | |
9ee6e8bb | 361 | irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; |
a32134aa | 362 | if (irq >= s->num_irq) |
e69954b9 PB |
363 | goto bad_reg; |
364 | res = 0; | |
69253800 | 365 | mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; |
e69954b9 | 366 | for (i = 0; i < 8; i++) { |
9ee6e8bb | 367 | if (GIC_TEST_ACTIVE(irq + i, mask)) { |
e69954b9 PB |
368 | res |= (1 << i); |
369 | } | |
370 | } | |
371 | } else if (offset < 0x800) { | |
372 | /* Interrupt Priority. */ | |
9ee6e8bb | 373 | irq = (offset - 0x400) + GIC_BASE_IRQ; |
a32134aa | 374 | if (irq >= s->num_irq) |
e69954b9 | 375 | goto bad_reg; |
9ee6e8bb PB |
376 | res = GIC_GET_PRIORITY(irq, cpu); |
377 | #ifndef NVIC | |
e69954b9 PB |
378 | } else if (offset < 0xc00) { |
379 | /* Interrupt CPU Target. */ | |
9ee6e8bb | 380 | irq = (offset - 0x800) + GIC_BASE_IRQ; |
a32134aa | 381 | if (irq >= s->num_irq) |
e69954b9 | 382 | goto bad_reg; |
9ee6e8bb PB |
383 | if (irq >= 29 && irq <= 31) { |
384 | res = cm; | |
385 | } else { | |
386 | res = GIC_TARGET(irq); | |
387 | } | |
e69954b9 PB |
388 | } else if (offset < 0xf00) { |
389 | /* Interrupt Configuration. */ | |
9ee6e8bb | 390 | irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ; |
a32134aa | 391 | if (irq >= s->num_irq) |
e69954b9 PB |
392 | goto bad_reg; |
393 | res = 0; | |
394 | for (i = 0; i < 4; i++) { | |
395 | if (GIC_TEST_MODEL(irq + i)) | |
396 | res |= (1 << (i * 2)); | |
397 | if (GIC_TEST_TRIGGER(irq + i)) | |
398 | res |= (2 << (i * 2)); | |
399 | } | |
9ee6e8bb | 400 | #endif |
e69954b9 PB |
401 | } else if (offset < 0xfe0) { |
402 | goto bad_reg; | |
403 | } else /* offset >= 0xfe0 */ { | |
404 | if (offset & 3) { | |
405 | res = 0; | |
406 | } else { | |
407 | res = gic_id[(offset - 0xfe0) >> 2]; | |
408 | } | |
409 | } | |
410 | return res; | |
411 | bad_reg: | |
2ac71179 | 412 | hw_error("gic_dist_readb: Bad offset %x\n", (int)offset); |
e69954b9 PB |
413 | return 0; |
414 | } | |
415 | ||
c227f099 | 416 | static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset) |
e69954b9 PB |
417 | { |
418 | uint32_t val; | |
419 | val = gic_dist_readb(opaque, offset); | |
420 | val |= gic_dist_readb(opaque, offset + 1) << 8; | |
421 | return val; | |
422 | } | |
423 | ||
c227f099 | 424 | static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset) |
e69954b9 PB |
425 | { |
426 | uint32_t val; | |
9ee6e8bb PB |
427 | #ifdef NVIC |
428 | gic_state *s = (gic_state *)opaque; | |
429 | uint32_t addr; | |
8da3ff18 | 430 | addr = offset; |
9ee6e8bb | 431 | if (addr < 0x100 || addr > 0xd00) |
fe7e8758 | 432 | return nvic_readl(s, addr); |
9ee6e8bb | 433 | #endif |
e69954b9 PB |
434 | val = gic_dist_readw(opaque, offset); |
435 | val |= gic_dist_readw(opaque, offset + 2) << 16; | |
436 | return val; | |
437 | } | |
438 | ||
c227f099 | 439 | static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, |
e69954b9 PB |
440 | uint32_t value) |
441 | { | |
442 | gic_state *s = (gic_state *)opaque; | |
443 | int irq; | |
444 | int i; | |
9ee6e8bb | 445 | int cpu; |
e69954b9 | 446 | |
926c4aff | 447 | cpu = gic_get_current_cpu(s); |
e69954b9 | 448 | if (offset < 0x100) { |
9ee6e8bb PB |
449 | #ifdef NVIC |
450 | goto bad_reg; | |
451 | #else | |
e69954b9 PB |
452 | if (offset == 0) { |
453 | s->enabled = (value & 1); | |
454 | DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis"); | |
455 | } else if (offset < 4) { | |
456 | /* ignored. */ | |
b79f2265 RH |
457 | } else if (offset >= 0x80) { |
458 | /* Interrupt Security Registers, RAZ/WI */ | |
e69954b9 PB |
459 | } else { |
460 | goto bad_reg; | |
461 | } | |
9ee6e8bb | 462 | #endif |
e69954b9 PB |
463 | } else if (offset < 0x180) { |
464 | /* Interrupt Set Enable. */ | |
9ee6e8bb | 465 | irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; |
a32134aa | 466 | if (irq >= s->num_irq) |
e69954b9 | 467 | goto bad_reg; |
9ee6e8bb PB |
468 | if (irq < 16) |
469 | value = 0xff; | |
e69954b9 PB |
470 | for (i = 0; i < 8; i++) { |
471 | if (value & (1 << i)) { | |
69253800 RR |
472 | int mask = (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq); |
473 | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; | |
41bf234d RV |
474 | |
475 | if (!GIC_TEST_ENABLED(irq + i, cm)) { | |
e69954b9 | 476 | DPRINTF("Enabled IRQ %d\n", irq + i); |
41bf234d RV |
477 | } |
478 | GIC_SET_ENABLED(irq + i, cm); | |
e69954b9 PB |
479 | /* If a raised level triggered IRQ enabled then mark |
480 | is as pending. */ | |
9ee6e8bb PB |
481 | if (GIC_TEST_LEVEL(irq + i, mask) |
482 | && !GIC_TEST_TRIGGER(irq + i)) { | |
483 | DPRINTF("Set %d pending mask %x\n", irq + i, mask); | |
484 | GIC_SET_PENDING(irq + i, mask); | |
485 | } | |
e69954b9 PB |
486 | } |
487 | } | |
488 | } else if (offset < 0x200) { | |
489 | /* Interrupt Clear Enable. */ | |
9ee6e8bb | 490 | irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; |
a32134aa | 491 | if (irq >= s->num_irq) |
e69954b9 | 492 | goto bad_reg; |
9ee6e8bb PB |
493 | if (irq < 16) |
494 | value = 0; | |
e69954b9 PB |
495 | for (i = 0; i < 8; i++) { |
496 | if (value & (1 << i)) { | |
69253800 | 497 | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; |
41bf234d RV |
498 | |
499 | if (GIC_TEST_ENABLED(irq + i, cm)) { | |
e69954b9 | 500 | DPRINTF("Disabled IRQ %d\n", irq + i); |
41bf234d RV |
501 | } |
502 | GIC_CLEAR_ENABLED(irq + i, cm); | |
e69954b9 PB |
503 | } |
504 | } | |
505 | } else if (offset < 0x280) { | |
506 | /* Interrupt Set Pending. */ | |
9ee6e8bb | 507 | irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; |
a32134aa | 508 | if (irq >= s->num_irq) |
e69954b9 | 509 | goto bad_reg; |
9ee6e8bb PB |
510 | if (irq < 16) |
511 | irq = 0; | |
512 | ||
e69954b9 PB |
513 | for (i = 0; i < 8; i++) { |
514 | if (value & (1 << i)) { | |
9ee6e8bb | 515 | GIC_SET_PENDING(irq + i, GIC_TARGET(irq)); |
e69954b9 PB |
516 | } |
517 | } | |
518 | } else if (offset < 0x300) { | |
519 | /* Interrupt Clear Pending. */ | |
9ee6e8bb | 520 | irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; |
a32134aa | 521 | if (irq >= s->num_irq) |
e69954b9 PB |
522 | goto bad_reg; |
523 | for (i = 0; i < 8; i++) { | |
9ee6e8bb PB |
524 | /* ??? This currently clears the pending bit for all CPUs, even |
525 | for per-CPU interrupts. It's unclear whether this is the | |
526 | corect behavior. */ | |
e69954b9 | 527 | if (value & (1 << i)) { |
9ee6e8bb | 528 | GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); |
e69954b9 PB |
529 | } |
530 | } | |
531 | } else if (offset < 0x400) { | |
532 | /* Interrupt Active. */ | |
533 | goto bad_reg; | |
534 | } else if (offset < 0x800) { | |
535 | /* Interrupt Priority. */ | |
9ee6e8bb | 536 | irq = (offset - 0x400) + GIC_BASE_IRQ; |
a32134aa | 537 | if (irq >= s->num_irq) |
e69954b9 | 538 | goto bad_reg; |
69253800 | 539 | if (irq < GIC_INTERNAL) { |
9ee6e8bb PB |
540 | s->priority1[irq][cpu] = value; |
541 | } else { | |
69253800 | 542 | s->priority2[irq - GIC_INTERNAL] = value; |
9ee6e8bb PB |
543 | } |
544 | #ifndef NVIC | |
e69954b9 PB |
545 | } else if (offset < 0xc00) { |
546 | /* Interrupt CPU Target. */ | |
9ee6e8bb | 547 | irq = (offset - 0x800) + GIC_BASE_IRQ; |
a32134aa | 548 | if (irq >= s->num_irq) |
e69954b9 | 549 | goto bad_reg; |
9ee6e8bb PB |
550 | if (irq < 29) |
551 | value = 0; | |
69253800 | 552 | else if (irq < GIC_INTERNAL) |
9ee6e8bb PB |
553 | value = ALL_CPU_MASK; |
554 | s->irq_target[irq] = value & ALL_CPU_MASK; | |
e69954b9 PB |
555 | } else if (offset < 0xf00) { |
556 | /* Interrupt Configuration. */ | |
9ee6e8bb | 557 | irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; |
a32134aa | 558 | if (irq >= s->num_irq) |
e69954b9 | 559 | goto bad_reg; |
69253800 | 560 | if (irq < GIC_INTERNAL) |
9ee6e8bb | 561 | value |= 0xaa; |
e69954b9 PB |
562 | for (i = 0; i < 4; i++) { |
563 | if (value & (1 << (i * 2))) { | |
564 | GIC_SET_MODEL(irq + i); | |
565 | } else { | |
566 | GIC_CLEAR_MODEL(irq + i); | |
567 | } | |
568 | if (value & (2 << (i * 2))) { | |
569 | GIC_SET_TRIGGER(irq + i); | |
570 | } else { | |
571 | GIC_CLEAR_TRIGGER(irq + i); | |
572 | } | |
573 | } | |
9ee6e8bb | 574 | #endif |
e69954b9 | 575 | } else { |
9ee6e8bb | 576 | /* 0xf00 is only handled for 32-bit writes. */ |
e69954b9 PB |
577 | goto bad_reg; |
578 | } | |
579 | gic_update(s); | |
580 | return; | |
581 | bad_reg: | |
2ac71179 | 582 | hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset); |
e69954b9 PB |
583 | } |
584 | ||
c227f099 | 585 | static void gic_dist_writew(void *opaque, target_phys_addr_t offset, |
e69954b9 PB |
586 | uint32_t value) |
587 | { | |
e69954b9 PB |
588 | gic_dist_writeb(opaque, offset, value & 0xff); |
589 | gic_dist_writeb(opaque, offset + 1, value >> 8); | |
590 | } | |
591 | ||
c227f099 | 592 | static void gic_dist_writel(void *opaque, target_phys_addr_t offset, |
e69954b9 PB |
593 | uint32_t value) |
594 | { | |
9ee6e8bb PB |
595 | gic_state *s = (gic_state *)opaque; |
596 | #ifdef NVIC | |
597 | uint32_t addr; | |
8da3ff18 | 598 | addr = offset; |
9ee6e8bb | 599 | if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) { |
fe7e8758 | 600 | nvic_writel(s, addr, value); |
9ee6e8bb PB |
601 | return; |
602 | } | |
603 | #endif | |
8da3ff18 | 604 | if (offset == 0xf00) { |
9ee6e8bb PB |
605 | int cpu; |
606 | int irq; | |
607 | int mask; | |
608 | ||
926c4aff | 609 | cpu = gic_get_current_cpu(s); |
9ee6e8bb PB |
610 | irq = value & 0x3ff; |
611 | switch ((value >> 24) & 3) { | |
612 | case 0: | |
613 | mask = (value >> 16) & ALL_CPU_MASK; | |
614 | break; | |
615 | case 1: | |
fa250144 | 616 | mask = ALL_CPU_MASK ^ (1 << cpu); |
9ee6e8bb PB |
617 | break; |
618 | case 2: | |
fa250144 | 619 | mask = 1 << cpu; |
9ee6e8bb PB |
620 | break; |
621 | default: | |
622 | DPRINTF("Bad Soft Int target filter\n"); | |
623 | mask = ALL_CPU_MASK; | |
624 | break; | |
625 | } | |
626 | GIC_SET_PENDING(irq, mask); | |
627 | gic_update(s); | |
628 | return; | |
629 | } | |
e69954b9 PB |
630 | gic_dist_writew(opaque, offset, value & 0xffff); |
631 | gic_dist_writew(opaque, offset + 2, value >> 16); | |
632 | } | |
633 | ||
755c0802 AK |
634 | static const MemoryRegionOps gic_dist_ops = { |
635 | .old_mmio = { | |
636 | .read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, }, | |
637 | .write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, }, | |
638 | }, | |
639 | .endianness = DEVICE_NATIVE_ENDIAN, | |
e69954b9 PB |
640 | }; |
641 | ||
9ee6e8bb PB |
642 | #ifndef NVIC |
643 | static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset) | |
e69954b9 | 644 | { |
e69954b9 PB |
645 | switch (offset) { |
646 | case 0x00: /* Control */ | |
9ee6e8bb | 647 | return s->cpu_enabled[cpu]; |
e69954b9 | 648 | case 0x04: /* Priority mask */ |
9ee6e8bb | 649 | return s->priority_mask[cpu]; |
e69954b9 PB |
650 | case 0x08: /* Binary Point */ |
651 | /* ??? Not implemented. */ | |
652 | return 0; | |
653 | case 0x0c: /* Acknowledge */ | |
9ee6e8bb | 654 | return gic_acknowledge_irq(s, cpu); |
66a0a2cb | 655 | case 0x14: /* Running Priority */ |
9ee6e8bb | 656 | return s->running_priority[cpu]; |
e69954b9 | 657 | case 0x18: /* Highest Pending Interrupt */ |
9ee6e8bb | 658 | return s->current_pending[cpu]; |
e69954b9 | 659 | default: |
2ac71179 | 660 | hw_error("gic_cpu_read: Bad offset %x\n", (int)offset); |
e69954b9 PB |
661 | return 0; |
662 | } | |
663 | } | |
664 | ||
9ee6e8bb | 665 | static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value) |
e69954b9 | 666 | { |
e69954b9 PB |
667 | switch (offset) { |
668 | case 0x00: /* Control */ | |
9ee6e8bb | 669 | s->cpu_enabled[cpu] = (value & 1); |
f7c70325 | 670 | DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled ? "En" : "Dis"); |
e69954b9 PB |
671 | break; |
672 | case 0x04: /* Priority mask */ | |
9ee6e8bb | 673 | s->priority_mask[cpu] = (value & 0xff); |
e69954b9 PB |
674 | break; |
675 | case 0x08: /* Binary Point */ | |
676 | /* ??? Not implemented. */ | |
677 | break; | |
678 | case 0x10: /* End Of Interrupt */ | |
9ee6e8bb | 679 | return gic_complete_irq(s, cpu, value & 0x3ff); |
e69954b9 | 680 | default: |
2ac71179 | 681 | hw_error("gic_cpu_write: Bad offset %x\n", (int)offset); |
e69954b9 PB |
682 | return; |
683 | } | |
684 | gic_update(s); | |
685 | } | |
e2c56465 PM |
686 | |
687 | /* Wrappers to read/write the GIC CPU interface for the current CPU */ | |
688 | static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr, | |
689 | unsigned size) | |
690 | { | |
691 | gic_state *s = (gic_state *)opaque; | |
926c4aff | 692 | return gic_cpu_read(s, gic_get_current_cpu(s), addr); |
e2c56465 PM |
693 | } |
694 | ||
695 | static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr, | |
696 | uint64_t value, unsigned size) | |
697 | { | |
698 | gic_state *s = (gic_state *)opaque; | |
926c4aff | 699 | gic_cpu_write(s, gic_get_current_cpu(s), addr, value); |
e2c56465 PM |
700 | } |
701 | ||
702 | /* Wrappers to read/write the GIC CPU interface for a specific CPU. | |
703 | * These just decode the opaque pointer into gic_state* + cpu id. | |
704 | */ | |
705 | static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr, | |
706 | unsigned size) | |
707 | { | |
708 | gic_state **backref = (gic_state **)opaque; | |
709 | gic_state *s = *backref; | |
710 | int id = (backref - s->backref); | |
0e4a398a | 711 | return gic_cpu_read(s, id, addr); |
e2c56465 PM |
712 | } |
713 | ||
714 | static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr, | |
715 | uint64_t value, unsigned size) | |
716 | { | |
717 | gic_state **backref = (gic_state **)opaque; | |
718 | gic_state *s = *backref; | |
719 | int id = (backref - s->backref); | |
0e4a398a | 720 | gic_cpu_write(s, id, addr, value); |
e2c56465 PM |
721 | } |
722 | ||
723 | static const MemoryRegionOps gic_thiscpu_ops = { | |
724 | .read = gic_thiscpu_read, | |
725 | .write = gic_thiscpu_write, | |
726 | .endianness = DEVICE_NATIVE_ENDIAN, | |
727 | }; | |
728 | ||
729 | static const MemoryRegionOps gic_cpu_ops = { | |
730 | .read = gic_do_cpu_read, | |
731 | .write = gic_do_cpu_write, | |
732 | .endianness = DEVICE_NATIVE_ENDIAN, | |
733 | }; | |
9ee6e8bb | 734 | #endif |
e69954b9 | 735 | |
aecff692 | 736 | static void gic_reset(DeviceState *dev) |
e69954b9 | 737 | { |
aecff692 | 738 | gic_state *s = FROM_SYSBUS(gic_state, sysbus_from_qdev(dev)); |
e69954b9 | 739 | int i; |
a32134aa | 740 | memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); |
c988bfad | 741 | for (i = 0 ; i < NUM_CPU(s); i++) { |
9ee6e8bb PB |
742 | s->priority_mask[i] = 0xf0; |
743 | s->current_pending[i] = 1023; | |
744 | s->running_irq[i] = 1023; | |
745 | s->running_priority[i] = 0x100; | |
9ee6e8bb | 746 | s->cpu_enabled[i] = 0; |
9ee6e8bb | 747 | } |
e57ec016 | 748 | for (i = 0; i < 16; i++) { |
41bf234d | 749 | GIC_SET_ENABLED(i, ALL_CPU_MASK); |
e69954b9 PB |
750 | GIC_SET_TRIGGER(i); |
751 | } | |
752 | s->enabled = 0; | |
e69954b9 PB |
753 | } |
754 | ||
23e39294 PB |
755 | static void gic_save(QEMUFile *f, void *opaque) |
756 | { | |
757 | gic_state *s = (gic_state *)opaque; | |
758 | int i; | |
759 | int j; | |
760 | ||
761 | qemu_put_be32(f, s->enabled); | |
c988bfad | 762 | for (i = 0; i < NUM_CPU(s); i++) { |
23e39294 | 763 | qemu_put_be32(f, s->cpu_enabled[i]); |
69253800 | 764 | for (j = 0; j < GIC_INTERNAL; j++) |
23e39294 | 765 | qemu_put_be32(f, s->priority1[j][i]); |
a32134aa | 766 | for (j = 0; j < s->num_irq; j++) |
23e39294 PB |
767 | qemu_put_be32(f, s->last_active[j][i]); |
768 | qemu_put_be32(f, s->priority_mask[i]); | |
769 | qemu_put_be32(f, s->running_irq[i]); | |
770 | qemu_put_be32(f, s->running_priority[i]); | |
771 | qemu_put_be32(f, s->current_pending[i]); | |
772 | } | |
69253800 | 773 | for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) { |
23e39294 PB |
774 | qemu_put_be32(f, s->priority2[i]); |
775 | } | |
a32134aa | 776 | for (i = 0; i < s->num_irq; i++) { |
c2e2343e | 777 | qemu_put_be32(f, s->irq_target[i]); |
23e39294 PB |
778 | qemu_put_byte(f, s->irq_state[i].enabled); |
779 | qemu_put_byte(f, s->irq_state[i].pending); | |
780 | qemu_put_byte(f, s->irq_state[i].active); | |
781 | qemu_put_byte(f, s->irq_state[i].level); | |
782 | qemu_put_byte(f, s->irq_state[i].model); | |
783 | qemu_put_byte(f, s->irq_state[i].trigger); | |
784 | } | |
785 | } | |
786 | ||
787 | static int gic_load(QEMUFile *f, void *opaque, int version_id) | |
788 | { | |
789 | gic_state *s = (gic_state *)opaque; | |
790 | int i; | |
791 | int j; | |
792 | ||
acd68428 | 793 | if (version_id != 3) { |
23e39294 | 794 | return -EINVAL; |
acd68428 | 795 | } |
23e39294 PB |
796 | |
797 | s->enabled = qemu_get_be32(f); | |
c988bfad | 798 | for (i = 0; i < NUM_CPU(s); i++) { |
23e39294 | 799 | s->cpu_enabled[i] = qemu_get_be32(f); |
69253800 | 800 | for (j = 0; j < GIC_INTERNAL; j++) |
23e39294 | 801 | s->priority1[j][i] = qemu_get_be32(f); |
a32134aa | 802 | for (j = 0; j < s->num_irq; j++) |
23e39294 PB |
803 | s->last_active[j][i] = qemu_get_be32(f); |
804 | s->priority_mask[i] = qemu_get_be32(f); | |
805 | s->running_irq[i] = qemu_get_be32(f); | |
806 | s->running_priority[i] = qemu_get_be32(f); | |
807 | s->current_pending[i] = qemu_get_be32(f); | |
808 | } | |
69253800 | 809 | for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) { |
23e39294 PB |
810 | s->priority2[i] = qemu_get_be32(f); |
811 | } | |
a32134aa | 812 | for (i = 0; i < s->num_irq; i++) { |
c2e2343e | 813 | s->irq_target[i] = qemu_get_be32(f); |
23e39294 PB |
814 | s->irq_state[i].enabled = qemu_get_byte(f); |
815 | s->irq_state[i].pending = qemu_get_byte(f); | |
816 | s->irq_state[i].active = qemu_get_byte(f); | |
817 | s->irq_state[i].level = qemu_get_byte(f); | |
818 | s->irq_state[i].model = qemu_get_byte(f); | |
819 | s->irq_state[i].trigger = qemu_get_byte(f); | |
820 | } | |
821 | ||
822 | return 0; | |
823 | } | |
824 | ||
a32134aa | 825 | static void gic_init(gic_state *s, int num_irq) |
e69954b9 | 826 | { |
9ee6e8bb | 827 | int i; |
e69954b9 | 828 | |
386e2955 PM |
829 | if (s->num_cpu > NCPU) { |
830 | hw_error("requested %u CPUs exceeds GIC maximum %d\n", | |
c48c6522 | 831 | s->num_cpu, NCPU); |
386e2955 | 832 | } |
a32134aa ML |
833 | s->num_irq = num_irq + GIC_BASE_IRQ; |
834 | if (s->num_irq > GIC_MAXIRQ) { | |
835 | hw_error("requested %u interrupt lines exceeds GIC maximum %d\n", | |
836 | num_irq, GIC_MAXIRQ); | |
837 | } | |
41c1e2f5 RR |
838 | /* ITLinesNumber is represented as (N / 32) - 1 (see |
839 | * gic_dist_readb) so this is an implementation imposed | |
840 | * restriction, not an architectural one: | |
841 | */ | |
842 | if (s->num_irq < 32 || (s->num_irq % 32)) { | |
843 | hw_error("%d interrupt lines unsupported: not divisible by 32\n", | |
844 | num_irq); | |
845 | } | |
846 | ||
544d1afa PM |
847 | i = s->num_irq - GIC_INTERNAL; |
848 | #ifndef NVIC | |
849 | /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. | |
850 | * GPIO array layout is thus: | |
851 | * [0..N-1] SPIs | |
852 | * [N..N+31] PPIs for CPU 0 | |
853 | * [N+32..N+63] PPIs for CPU 1 | |
854 | * ... | |
855 | */ | |
c48c6522 | 856 | i += (GIC_INTERNAL * s->num_cpu); |
544d1afa PM |
857 | #endif |
858 | qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, i); | |
c988bfad | 859 | for (i = 0; i < NUM_CPU(s); i++) { |
fe7e8758 | 860 | sysbus_init_irq(&s->busdev, &s->parent_irq[i]); |
e69954b9 | 861 | } |
755c0802 | 862 | memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000); |
e2c56465 PM |
863 | #ifndef NVIC |
864 | /* Memory regions for the CPU interfaces (NVIC doesn't have these): | |
865 | * a region for "CPU interface for this core", then a region for | |
866 | * "CPU interface for core 0", "for core 1", ... | |
867 | * NB that the memory region size of 0x100 applies for the 11MPCore | |
868 | * and also cores following the GIC v1 spec (ie A9). | |
869 | * GIC v2 defines a larger memory region (0x1000) so this will need | |
870 | * to be extended when we implement A15. | |
871 | */ | |
872 | memory_region_init_io(&s->cpuiomem[0], &gic_thiscpu_ops, s, | |
873 | "gic_cpu", 0x100); | |
874 | for (i = 0; i < NUM_CPU(s); i++) { | |
875 | s->backref[i] = s; | |
876 | memory_region_init_io(&s->cpuiomem[i+1], &gic_cpu_ops, &s->backref[i], | |
877 | "gic_cpu", 0x100); | |
878 | } | |
879 | #endif | |
880 | ||
acd68428 | 881 | register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s); |
e69954b9 | 882 | } |
496dbcd1 | 883 | |
0d256bdc | 884 | #ifndef NVIC |
496dbcd1 PM |
885 | |
886 | static int arm_gic_init(SysBusDevice *dev) | |
887 | { | |
888 | /* Device instance init function for the GIC sysbus device */ | |
889 | int i; | |
890 | gic_state *s = FROM_SYSBUS(gic_state, dev); | |
c48c6522 | 891 | gic_init(s, s->num_irq); |
496dbcd1 PM |
892 | /* Distributor */ |
893 | sysbus_init_mmio(dev, &s->iomem); | |
894 | /* cpu interfaces (one for "current cpu" plus one per cpu) */ | |
895 | for (i = 0; i <= NUM_CPU(s); i++) { | |
896 | sysbus_init_mmio(dev, &s->cpuiomem[i]); | |
897 | } | |
898 | return 0; | |
899 | } | |
900 | ||
901 | static Property arm_gic_properties[] = { | |
902 | DEFINE_PROP_UINT32("num-cpu", gic_state, num_cpu, 1), | |
903 | DEFINE_PROP_UINT32("num-irq", gic_state, num_irq, 32), | |
904 | DEFINE_PROP_END_OF_LIST(), | |
905 | }; | |
906 | ||
907 | static void arm_gic_class_init(ObjectClass *klass, void *data) | |
908 | { | |
909 | DeviceClass *dc = DEVICE_CLASS(klass); | |
910 | SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); | |
911 | sbc->init = arm_gic_init; | |
912 | dc->props = arm_gic_properties; | |
aecff692 | 913 | dc->reset = gic_reset; |
496dbcd1 PM |
914 | dc->no_user = 1; |
915 | } | |
916 | ||
917 | static TypeInfo arm_gic_info = { | |
918 | .name = "arm_gic", | |
919 | .parent = TYPE_SYS_BUS_DEVICE, | |
920 | .instance_size = sizeof(gic_state), | |
921 | .class_init = arm_gic_class_init, | |
922 | }; | |
923 | ||
924 | static void arm_gic_register_types(void) | |
925 | { | |
926 | type_register_static(&arm_gic_info); | |
927 | } | |
928 | ||
929 | type_init(arm_gic_register_types) | |
930 | ||
931 | #endif |