[qemu.git] / hw / arm_sysctl.c

/*
 * Status and system control registers for ARM RealView/Versatile boards.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "hw.h"
#include "qemu-timer.h"
#include "sysbus.h"
#include "primecell.h"
#include "sysemu.h"

#define LOCK_VALUE 0xa05f

typedef struct {
    SysBusDevice busdev;
    MemoryRegion iomem;
    qemu_irq pl110_mux_ctrl;

    uint32_t sys_id;
    uint32_t leds;
    uint16_t lockval;
    uint32_t cfgdata1;
    uint32_t cfgdata2;
    uint32_t flags;
    uint32_t nvflags;
    uint32_t resetlevel;
    uint32_t proc_id;
    uint32_t sys_mci;
    uint32_t sys_cfgdata;
    uint32_t sys_cfgctrl;
    uint32_t sys_cfgstat;
    uint32_t sys_clcd;
} arm_sysctl_state;

static const VMStateDescription vmstate_arm_sysctl = {
    .name = "realview_sysctl",
    .version_id = 3,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(leds, arm_sysctl_state),
        VMSTATE_UINT16(lockval, arm_sysctl_state),
        VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
        VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
        VMSTATE_UINT32(flags, arm_sysctl_state),
        VMSTATE_UINT32(nvflags, arm_sysctl_state),
        VMSTATE_UINT32(resetlevel, arm_sysctl_state),
        VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
        VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
        VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
        VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
        VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
        VMSTATE_END_OF_LIST()
    }
};

/* The PB926 actually uses a different format for
 * its SYS_ID register. Fortunately the bits which are
 * board type on later boards are distinct.
 */
#define BOARD_ID_PB926 0x100
#define BOARD_ID_EB 0x140
#define BOARD_ID_PBA8 0x178
#define BOARD_ID_PBX 0x182
#define BOARD_ID_VEXPRESS 0x190

static int board_id(arm_sysctl_state *s)
{
    /* Extract the board ID field from the SYS_ID register value */
    return (s->sys_id >> 16) & 0xfff;
}

static void arm_sysctl_reset(DeviceState *d)
{
    arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sysbus_from_qdev(d));

    s->leds = 0;
    s->lockval = 0;
    s->cfgdata1 = 0;
    s->cfgdata2 = 0;
    s->flags = 0;
    s->resetlevel = 0;
    if (board_id(s) == BOARD_ID_VEXPRESS) {
        /* On VExpress this register will RAZ/WI */
        s->sys_clcd = 0;
    } else {
        /* All others: CLCDID 0x1f, indicating VGA */
        s->sys_clcd = 0x1f00;
    }
}

static uint64_t arm_sysctl_read(void *opaque, target_phys_addr_t offset,
                                unsigned size)
{
    arm_sysctl_state *s = (arm_sysctl_state *)opaque;

    switch (offset) {
    case 0x00: /* ID */
        return s->sys_id;
    case 0x04: /* SW */
        /* General purpose hardware switches.
           We don't have a useful way of exposing these to the user.  */
        return 0;
    case 0x08: /* LED */
        return s->leds;
    case 0x20: /* LOCK */
        return s->lockval;
    case 0x0c: /* OSC0 */
    case 0x10: /* OSC1 */
    case 0x14: /* OSC2 */
    case 0x18: /* OSC3 */
    case 0x1c: /* OSC4 */
    case 0x24: /* 100HZ */
        /* ??? Implement these.  */
        return 0;
    case 0x28: /* CFGDATA1 */
        return s->cfgdata1;
    case 0x2c: /* CFGDATA2 */
        return s->cfgdata2;
    case 0x30: /* FLAGS */
        return s->flags;
    case 0x38: /* NVFLAGS */
        return s->nvflags;
    case 0x40: /* RESETCTL */
        if (board_id(s) == BOARD_ID_VEXPRESS) {
            /* reserved: RAZ/WI */
            return 0;
        }
        return s->resetlevel;
    case 0x44: /* PCICTL */
        return 1;
    case 0x48: /* MCI */
        return s->sys_mci;
    case 0x4c: /* FLASH */
        return 0;
    case 0x50: /* CLCD */
        return s->sys_clcd;
    case 0x54: /* CLCDSER */
        return 0;
    case 0x58: /* BOOTCS */
        return 0;
    case 0x5c: /* 24MHz */
        return muldiv64(qemu_get_clock_ns(vm_clock), 24000000, get_ticks_per_sec());
    case 0x60: /* MISC */
        return 0;
    case 0x84: /* PROCID0 */
        return s->proc_id;
    case 0x88: /* PROCID1 */
        return 0xff000000;
    case 0x64: /* DMAPSR0 */
    case 0x68: /* DMAPSR1 */
    case 0x6c: /* DMAPSR2 */
    case 0x70: /* IOSEL */
    case 0x74: /* PLDCTL */
    case 0x80: /* BUSID */
    case 0x8c: /* OSCRESET0 */
    case 0x90: /* OSCRESET1 */
    case 0x94: /* OSCRESET2 */
    case 0x98: /* OSCRESET3 */
    case 0x9c: /* OSCRESET4 */
    case 0xc0: /* SYS_TEST_OSC0 */
    case 0xc4: /* SYS_TEST_OSC1 */
    case 0xc8: /* SYS_TEST_OSC2 */
    case 0xcc: /* SYS_TEST_OSC3 */
    case 0xd0: /* SYS_TEST_OSC4 */
        return 0;
    case 0xa0: /* SYS_CFGDATA */
        if (board_id(s) != BOARD_ID_VEXPRESS) {
            goto bad_reg;
        }
        return s->sys_cfgdata;
    case 0xa4: /* SYS_CFGCTRL */
        if (board_id(s) != BOARD_ID_VEXPRESS) {
            goto bad_reg;
        }
        return s->sys_cfgctrl;
    case 0xa8: /* SYS_CFGSTAT */
        if (board_id(s) != BOARD_ID_VEXPRESS) {
            goto bad_reg;
        }
        return s->sys_cfgstat;
    default:
    bad_reg:
        printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset);
        return 0;
    }
}

static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
                             uint64_t val, unsigned size)
{
    arm_sysctl_state *s = (arm_sysctl_state *)opaque;

    switch (offset) {
    case 0x08: /* LED */
        s->leds = val;
    case 0x0c: /* OSC0 */
    case 0x10: /* OSC1 */
    case 0x14: /* OSC2 */
    case 0x18: /* OSC3 */
    case 0x1c: /* OSC4 */
        /* ??? */
        break;
    case 0x20: /* LOCK */
        if (val == LOCK_VALUE)
            s->lockval = val;
        else
            s->lockval = val & 0x7fff;
        break;
    case 0x28: /* CFGDATA1 */
        /* ??? Need to implement this.  */
        s->cfgdata1 = val;
        break;
    case 0x2c: /* CFGDATA2 */
        /* ??? Need to implement this.  */
        s->cfgdata2 = val;
        break;
    case 0x30: /* FLAGSSET */
        s->flags |= val;
        break;
    case 0x34: /* FLAGSCLR */
        s->flags &= ~val;
        break;
    case 0x38: /* NVFLAGSSET */
        s->nvflags |= val;
        break;
    case 0x3c: /* NVFLAGSCLR */
        s->nvflags &= ~val;
        break;
    case 0x40: /* RESETCTL */
        if (board_id(s) == BOARD_ID_VEXPRESS) {
            /* reserved: RAZ/WI */
            break;
        }
        if (s->lockval == LOCK_VALUE) {
            s->resetlevel = val;
            if (val & 0x100)
                qemu_system_reset_request ();
        }
        break;
    case 0x44: /* PCICTL */
        /* nothing to do.  */
        break;
    case 0x4c: /* FLASH */
        break;
    case 0x50: /* CLCD */
        switch (board_id(s)) {
        case BOARD_ID_PB926:
            /* On 926 bits 13:8 are R/O, bits 1:0 control
             * the mux that defines how to interpret the PL110
             * graphics format, and other bits are r/w but we
             * don't implement them to do anything.
             */
            s->sys_clcd &= 0x3f00;
            s->sys_clcd |= val & ~0x3f00;
            qemu_set_irq(s->pl110_mux_ctrl, val & 3);
            break;
        case BOARD_ID_EB:
            /* The EB is the same except that there is no mux since
             * the EB has a PL111.
             */
            s->sys_clcd &= 0x3f00;
            s->sys_clcd |= val & ~0x3f00;
            break;
        case BOARD_ID_PBA8:
        case BOARD_ID_PBX:
            /* On PBA8 and PBX bit 7 is r/w and all other bits
             * are either r/o or RAZ/WI.
             */
            s->sys_clcd &= (1 << 7);
            s->sys_clcd |= val & ~(1 << 7);
            break;
        case BOARD_ID_VEXPRESS:
        default:
            /* On VExpress this register is unimplemented and will RAZ/WI */
            break;
        }
    case 0x54: /* CLCDSER */
    case 0x64: /* DMAPSR0 */
    case 0x68: /* DMAPSR1 */
    case 0x6c: /* DMAPSR2 */
    case 0x70: /* IOSEL */
    case 0x74: /* PLDCTL */
    case 0x80: /* BUSID */
    case 0x84: /* PROCID0 */
    case 0x88: /* PROCID1 */
    case 0x8c: /* OSCRESET0 */
    case 0x90: /* OSCRESET1 */
    case 0x94: /* OSCRESET2 */
    case 0x98: /* OSCRESET3 */
    case 0x9c: /* OSCRESET4 */
        break;
    case 0xa0: /* SYS_CFGDATA */
        if (board_id(s) != BOARD_ID_VEXPRESS) {
            goto bad_reg;
        }
        s->sys_cfgdata = val;
        return;
    case 0xa4: /* SYS_CFGCTRL */
        if (board_id(s) != BOARD_ID_VEXPRESS) {
            goto bad_reg;
        }
        s->sys_cfgctrl = val & ~(3 << 18);
        s->sys_cfgstat = 1;            /* complete */
        switch (s->sys_cfgctrl) {
        case 0xc0800000:            /* SYS_CFG_SHUTDOWN to motherboard */
            qemu_system_shutdown_request();
            break;
        case 0xc0900000:            /* SYS_CFG_REBOOT to motherboard */
            qemu_system_reset_request();
            break;
        default:
            s->sys_cfgstat |= 2;        /* error */
        }
        return;
    case 0xa8: /* SYS_CFGSTAT */
        if (board_id(s) != BOARD_ID_VEXPRESS) {
            goto bad_reg;
        }
        s->sys_cfgstat = val & 3;
        return;
    default:
    bad_reg:
        printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset);
        return;
    }
}

static const MemoryRegionOps arm_sysctl_ops = {
    .read = arm_sysctl_read,
    .write = arm_sysctl_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void arm_sysctl_gpio_set(void *opaque, int line, int level)
{
    arm_sysctl_state *s = (arm_sysctl_state *)opaque;
    switch (line) {
    case ARM_SYSCTL_GPIO_MMC_WPROT:
    {
        /* For PB926 and EB write-protect is bit 2 of SYS_MCI;
         * for all later boards it is bit 1.
         */
        int bit = 2;
        if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) {
            bit = 4;
        }
        s->sys_mci &= ~bit;
        if (level) {
            s->sys_mci |= bit;
        }
        break;
    }
    case ARM_SYSCTL_GPIO_MMC_CARDIN:
        s->sys_mci &= ~1;
        if (level) {
            s->sys_mci |= 1;
        }
        break;
    }
}

static int arm_sysctl_init1(SysBusDevice *dev)
{
    arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);

    memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
    sysbus_init_mmio_region(dev, &s->iomem);
    qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
    qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1);
    return 0;
}

/* Legacy helper function.  */
void arm_sysctl_init(uint32_t base, uint32_t sys_id, uint32_t proc_id)
{
    DeviceState *dev;

    dev = qdev_create(NULL, "realview_sysctl");
    qdev_prop_set_uint32(dev, "sys_id", sys_id);
    qdev_init_nofail(dev);
    qdev_prop_set_uint32(dev, "proc_id", proc_id);
    sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
}

static SysBusDeviceInfo arm_sysctl_info = {
    .init = arm_sysctl_init1,
    .qdev.name  = "realview_sysctl",
    .qdev.size  = sizeof(arm_sysctl_state),
    .qdev.vmsd = &vmstate_arm_sysctl,
    .qdev.reset = arm_sysctl_reset,
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
        DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void arm_sysctl_register_devices(void)
{
    sysbus_register_withprop(&arm_sysctl_info);
}

device_init(arm_sysctl_register_devices)
Commit	Line	Data
5fafdf24	1	/*
e69954b9 PB	2	* Status and system control registers for ARM RealView/Versatile boards.
e69954b9 PB	3	*
9ee6e8bb	4	* Copyright (c) 2006-2007 CodeSourcery.
e69954b9 PB	5	* Written by Paul Brook
e69954b9 PB	6	*
8e31bf38	7	* This code is licensed under the GPL.
e69954b9 PB	8	*/
e69954b9 PB	9
042eb37a DJ	10	#include "hw.h"
042eb37a DJ	11	#include "qemu-timer.h"
82634c2d	12	#include "sysbus.h"
9596ebb7	13	#include "primecell.h"
87ecb68b	14	#include "sysemu.h"
e69954b9 PB	15
	16	#define LOCK_VALUE 0xa05f
	17
	18	typedef struct {
82634c2d	19	SysBusDevice busdev;
460d7c53	20	MemoryRegion iomem;
242ea2c6 PM	21	qemu_irq pl110_mux_ctrl;
242ea2c6 PM	22
e69954b9 PB	23	uint32_t sys_id;
	24	uint32_t leds;
	25	uint16_t lockval;
	26	uint32_t cfgdata1;
	27	uint32_t cfgdata2;
	28	uint32_t flags;
	29	uint32_t nvflags;
	30	uint32_t resetlevel;
26e92f65	31	uint32_t proc_id;
b50ff6f5	32	uint32_t sys_mci;
34933c8c PM	33	uint32_t sys_cfgdata;
	34	uint32_t sys_cfgctrl;
	35	uint32_t sys_cfgstat;
242ea2c6	36	uint32_t sys_clcd;
e69954b9 PB	37	} arm_sysctl_state;
e69954b9 PB	38
b5ad0ae7 PM	39	static const VMStateDescription vmstate_arm_sysctl = {
b5ad0ae7 PM	40	.name = "realview_sysctl",
242ea2c6	41	.version_id = 3,
b5ad0ae7 PM	42	.minimum_version_id = 1,
	43	.fields = (VMStateField[]) {
	44	VMSTATE_UINT32(leds, arm_sysctl_state),
	45	VMSTATE_UINT16(lockval, arm_sysctl_state),
	46	VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
	47	VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
	48	VMSTATE_UINT32(flags, arm_sysctl_state),
	49	VMSTATE_UINT32(nvflags, arm_sysctl_state),
	50	VMSTATE_UINT32(resetlevel, arm_sysctl_state),
34933c8c PM	51	VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
	52	VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
	53	VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
	54	VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
242ea2c6	55	VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
b5ad0ae7 PM	56	VMSTATE_END_OF_LIST()
	57	}
	58	};
	59
b50ff6f5 PM	60	/* The PB926 actually uses a different format for
	61	* its SYS_ID register. Fortunately the bits which are
	62	* board type on later boards are distinct.
	63	*/
	64	#define BOARD_ID_PB926 0x100
	65	#define BOARD_ID_EB 0x140
	66	#define BOARD_ID_PBA8 0x178
	67	#define BOARD_ID_PBX 0x182
34933c8c	68	#define BOARD_ID_VEXPRESS 0x190
b50ff6f5 PM	69
	70	static int board_id(arm_sysctl_state *s)
	71	{
	72	/* Extract the board ID field from the SYS_ID register value */
	73	return (s->sys_id >> 16) & 0xfff;
	74	}
	75
be0f204a PB	76	static void arm_sysctl_reset(DeviceState *d)
	77	{
	78	arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sysbus_from_qdev(d));
	79
	80	s->leds = 0;
	81	s->lockval = 0;
	82	s->cfgdata1 = 0;
	83	s->cfgdata2 = 0;
	84	s->flags = 0;
	85	s->resetlevel = 0;
242ea2c6 PM	86	if (board_id(s) == BOARD_ID_VEXPRESS) {
	87	/* On VExpress this register will RAZ/WI */
	88	s->sys_clcd = 0;
	89	} else {
	90	/* All others: CLCDID 0x1f, indicating VGA */
	91	s->sys_clcd = 0x1f00;
	92	}
be0f204a PB	93	}
be0f204a PB	94
460d7c53 AK	95	static uint64_t arm_sysctl_read(void *opaque, target_phys_addr_t offset,
460d7c53 AK	96	unsigned size)
e69954b9 PB	97	{
	98	arm_sysctl_state s = (arm_sysctl_state )opaque;
	99
e69954b9 PB	100	switch (offset) {
	101	case 0x00: /* ID */
	102	return s->sys_id;
	103	case 0x04: /* SW */
	104	/* General purpose hardware switches.
	105	We don't have a useful way of exposing these to the user. */
	106	return 0;
	107	case 0x08: /* LED */
	108	return s->leds;
	109	case 0x20: /* LOCK */
	110	return s->lockval;
	111	case 0x0c: /* OSC0 */
	112	case 0x10: /* OSC1 */
	113	case 0x14: /* OSC2 */
	114	case 0x18: /* OSC3 */
	115	case 0x1c: /* OSC4 */
	116	case 0x24: /* 100HZ */
	117	/* ??? Implement these. */
	118	return 0;
	119	case 0x28: /* CFGDATA1 */
	120	return s->cfgdata1;
	121	case 0x2c: /* CFGDATA2 */
	122	return s->cfgdata2;
	123	case 0x30: /* FLAGS */
	124	return s->flags;
	125	case 0x38: /* NVFLAGS */
	126	return s->nvflags;
	127	case 0x40: /* RESETCTL */
34933c8c PM	128	if (board_id(s) == BOARD_ID_VEXPRESS) {
	129	/* reserved: RAZ/WI */
	130	return 0;
	131	}
e69954b9 PB	132	return s->resetlevel;
	133	case 0x44: /* PCICTL */
	134	return 1;
	135	case 0x48: /* MCI */
b50ff6f5	136	return s->sys_mci;
e69954b9 PB	137	case 0x4c: /* FLASH */
	138	return 0;
	139	case 0x50: /* CLCD */
242ea2c6	140	return s->sys_clcd;
e69954b9 PB	141	case 0x54: /* CLCDSER */
	142	return 0;
	143	case 0x58: /* BOOTCS */
	144	return 0;
	145	case 0x5c: /* 24MHz */
74475455	146	return muldiv64(qemu_get_clock_ns(vm_clock), 24000000, get_ticks_per_sec());
e69954b9 PB	147	case 0x60: /* MISC */
	148	return 0;
	149	case 0x84: /* PROCID0 */
26e92f65	150	return s->proc_id;
e69954b9 PB	151	case 0x88: /* PROCID1 */
	152	return 0xff000000;
	153	case 0x64: /* DMAPSR0 */
	154	case 0x68: /* DMAPSR1 */
	155	case 0x6c: /* DMAPSR2 */
	156	case 0x70: /* IOSEL */
	157	case 0x74: /* PLDCTL */
	158	case 0x80: /* BUSID */
	159	case 0x8c: /* OSCRESET0 */
	160	case 0x90: /* OSCRESET1 */
	161	case 0x94: /* OSCRESET2 */
	162	case 0x98: /* OSCRESET3 */
	163	case 0x9c: /* OSCRESET4 */
	164	case 0xc0: /* SYS_TEST_OSC0 */
	165	case 0xc4: /* SYS_TEST_OSC1 */
	166	case 0xc8: /* SYS_TEST_OSC2 */
	167	case 0xcc: /* SYS_TEST_OSC3 */
	168	case 0xd0: /* SYS_TEST_OSC4 */
	169	return 0;
34933c8c PM	170	case 0xa0: /* SYS_CFGDATA */
	171	if (board_id(s) != BOARD_ID_VEXPRESS) {
	172	goto bad_reg;
	173	}
	174	return s->sys_cfgdata;
	175	case 0xa4: /* SYS_CFGCTRL */
	176	if (board_id(s) != BOARD_ID_VEXPRESS) {
	177	goto bad_reg;
	178	}
	179	return s->sys_cfgctrl;
	180	case 0xa8: /* SYS_CFGSTAT */
	181	if (board_id(s) != BOARD_ID_VEXPRESS) {
	182	goto bad_reg;
	183	}
	184	return s->sys_cfgstat;
e69954b9	185	default:
34933c8c	186	bad_reg:
e69954b9 PB	187	printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset);
	188	return 0;
	189	}
	190	}
	191
c227f099	192	static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
460d7c53	193	uint64_t val, unsigned size)
e69954b9 PB	194	{
e69954b9 PB	195	arm_sysctl_state s = (arm_sysctl_state )opaque;
e69954b9 PB	196
	197	switch (offset) {
	198	case 0x08: /* LED */
	199	s->leds = val;
	200	case 0x0c: /* OSC0 */
	201	case 0x10: /* OSC1 */
	202	case 0x14: /* OSC2 */
	203	case 0x18: /* OSC3 */
	204	case 0x1c: /* OSC4 */
	205	/* ??? */
	206	break;
	207	case 0x20: /* LOCK */
	208	if (val == LOCK_VALUE)
	209	s->lockval = val;
	210	else
	211	s->lockval = val & 0x7fff;
	212	break;
	213	case 0x28: /* CFGDATA1 */
	214	/* ??? Need to implement this. */
	215	s->cfgdata1 = val;
	216	break;
	217	case 0x2c: /* CFGDATA2 */
	218	/* ??? Need to implement this. */
	219	s->cfgdata2 = val;
	220	break;
	221	case 0x30: /* FLAGSSET */
	222	s->flags \|= val;
	223	break;
	224	case 0x34: /* FLAGSCLR */
	225	s->flags &= ~val;
	226	break;
	227	case 0x38: /* NVFLAGSSET */
	228	s->nvflags \|= val;
	229	break;
	230	case 0x3c: /* NVFLAGSCLR */
	231	s->nvflags &= ~val;
	232	break;
	233	case 0x40: /* RESETCTL */
34933c8c PM	234	if (board_id(s) == BOARD_ID_VEXPRESS) {
	235	/* reserved: RAZ/WI */
	236	break;
	237	}
e69954b9 PB	238	if (s->lockval == LOCK_VALUE) {
	239	s->resetlevel = val;
	240	if (val & 0x100)
f3d6b95e	241	qemu_system_reset_request ();
e69954b9 PB	242	}
	243	break;
	244	case 0x44: /* PCICTL */
	245	/* nothing to do. */
	246	break;
	247	case 0x4c: /* FLASH */
242ea2c6	248	break;
e69954b9	249	case 0x50: /* CLCD */
242ea2c6 PM	250	switch (board_id(s)) {
	251	case BOARD_ID_PB926:
	252	/* On 926 bits 13:8 are R/O, bits 1:0 control
	253	* the mux that defines how to interpret the PL110
	254	* graphics format, and other bits are r/w but we
	255	* don't implement them to do anything.
	256	*/
	257	s->sys_clcd &= 0x3f00;
	258	s->sys_clcd \|= val & ~0x3f00;
	259	qemu_set_irq(s->pl110_mux_ctrl, val & 3);
	260	break;
	261	case BOARD_ID_EB:
	262	/* The EB is the same except that there is no mux since
	263	* the EB has a PL111.
	264	*/
	265	s->sys_clcd &= 0x3f00;
	266	s->sys_clcd \|= val & ~0x3f00;
	267	break;
	268	case BOARD_ID_PBA8:
	269	case BOARD_ID_PBX:
	270	/* On PBA8 and PBX bit 7 is r/w and all other bits
	271	* are either r/o or RAZ/WI.
	272	*/
	273	s->sys_clcd &= (1 << 7);
	274	s->sys_clcd \|= val & ~(1 << 7);
	275	break;
	276	case BOARD_ID_VEXPRESS:
	277	default:
	278	/* On VExpress this register is unimplemented and will RAZ/WI */
	279	break;
	280	}
e69954b9 PB	281	case 0x54: /* CLCDSER */
	282	case 0x64: /* DMAPSR0 */
	283	case 0x68: /* DMAPSR1 */
	284	case 0x6c: /* DMAPSR2 */
	285	case 0x70: /* IOSEL */
	286	case 0x74: /* PLDCTL */
	287	case 0x80: /* BUSID */
	288	case 0x84: /* PROCID0 */
	289	case 0x88: /* PROCID1 */
	290	case 0x8c: /* OSCRESET0 */
	291	case 0x90: /* OSCRESET1 */
	292	case 0x94: /* OSCRESET2 */
	293	case 0x98: /* OSCRESET3 */
	294	case 0x9c: /* OSCRESET4 */
	295	break;
34933c8c PM	296	case 0xa0: /* SYS_CFGDATA */
	297	if (board_id(s) != BOARD_ID_VEXPRESS) {
	298	goto bad_reg;
	299	}
	300	s->sys_cfgdata = val;
	301	return;
	302	case 0xa4: /* SYS_CFGCTRL */
	303	if (board_id(s) != BOARD_ID_VEXPRESS) {
	304	goto bad_reg;
	305	}
	306	s->sys_cfgctrl = val & ~(3 << 18);
	307	s->sys_cfgstat = 1; /* complete */
	308	switch (s->sys_cfgctrl) {
	309	case 0xc0800000: /* SYS_CFG_SHUTDOWN to motherboard */
	310	qemu_system_shutdown_request();
	311	break;
	312	case 0xc0900000: /* SYS_CFG_REBOOT to motherboard */
	313	qemu_system_reset_request();
	314	break;
	315	default:
	316	s->sys_cfgstat \|= 2; /* error */
	317	}
	318	return;
	319	case 0xa8: /* SYS_CFGSTAT */
	320	if (board_id(s) != BOARD_ID_VEXPRESS) {
	321	goto bad_reg;
	322	}
	323	s->sys_cfgstat = val & 3;
	324	return;
e69954b9	325	default:
34933c8c	326	bad_reg:
e69954b9 PB	327	printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset);
	328	return;
	329	}
	330	}
	331
460d7c53 AK	332	static const MemoryRegionOps arm_sysctl_ops = {
	333	.read = arm_sysctl_read,
	334	.write = arm_sysctl_write,
	335	.endianness = DEVICE_NATIVE_ENDIAN,
e69954b9 PB	336	};
e69954b9 PB	337
b50ff6f5 PM	338	static void arm_sysctl_gpio_set(void *opaque, int line, int level)
	339	{
	340	arm_sysctl_state s = (arm_sysctl_state )opaque;
	341	switch (line) {
	342	case ARM_SYSCTL_GPIO_MMC_WPROT:
	343	{
	344	/* For PB926 and EB write-protect is bit 2 of SYS_MCI;
	345	* for all later boards it is bit 1.
	346	*/
	347	int bit = 2;
	348	if ((board_id(s) == BOARD_ID_PB926) \|\| (board_id(s) == BOARD_ID_EB)) {
	349	bit = 4;
	350	}
	351	s->sys_mci &= ~bit;
	352	if (level) {
	353	s->sys_mci \|= bit;
	354	}
	355	break;
	356	}
	357	case ARM_SYSCTL_GPIO_MMC_CARDIN:
	358	s->sys_mci &= ~1;
	359	if (level) {
	360	s->sys_mci \|= 1;
	361	}
	362	break;
	363	}
	364	}
	365
81a322d4	366	static int arm_sysctl_init1(SysBusDevice *dev)
e69954b9	367	{
82634c2d	368	arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
e69954b9	369
460d7c53 AK	370	memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
460d7c53 AK	371	sysbus_init_mmio_region(dev, &s->iomem);
b50ff6f5	372	qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
242ea2c6	373	qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1);
81a322d4	374	return 0;
e69954b9	375	}
82634c2d PB	376
82634c2d PB	377	/* Legacy helper function. */
26e92f65	378	void arm_sysctl_init(uint32_t base, uint32_t sys_id, uint32_t proc_id)
82634c2d PB	379	{
	380	DeviceState *dev;
	381
	382	dev = qdev_create(NULL, "realview_sysctl");
ee6847d1	383	qdev_prop_set_uint32(dev, "sys_id", sys_id);
e23a1b33	384	qdev_init_nofail(dev);
26e92f65	385	qdev_prop_set_uint32(dev, "proc_id", proc_id);
82634c2d PB	386	sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
	387	}
	388
ee6847d1 GH	389	static SysBusDeviceInfo arm_sysctl_info = {
	390	.init = arm_sysctl_init1,
	391	.qdev.name = "realview_sysctl",
	392	.qdev.size = sizeof(arm_sysctl_state),
b5ad0ae7	393	.qdev.vmsd = &vmstate_arm_sysctl,
be0f204a	394	.qdev.reset = arm_sysctl_reset,
ee6847d1	395	.qdev.props = (Property[]) {
e325775b	396	DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
26e92f65	397	DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
e325775b	398	DEFINE_PROP_END_OF_LIST(),
ee6847d1 GH	399	}
	400	};
	401
82634c2d PB	402	static void arm_sysctl_register_devices(void)
82634c2d PB	403	{
ee6847d1	404	sysbus_register_withprop(&arm_sysctl_info);
82634c2d PB	405	}
	406
	407	device_init(arm_sysctl_register_devices)