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25a8bb96 MW |
1 | /* |
2 | * QEMU model of the Milkymist System Controller. | |
3 | * | |
4 | * Copyright (c) 2010 Michael Walle <michael@walle.cc> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | * | |
19 | * | |
20 | * Specification available at: | |
6dbbe243 | 21 | * http://milkymist.walle.cc/socdoc/ac97.pdf |
25a8bb96 MW |
22 | */ |
23 | ||
6086a565 | 24 | #include "qemu/osdep.h" |
83c9f4ca PB |
25 | #include "hw/hw.h" |
26 | #include "hw/sysbus.h" | |
25a8bb96 MW |
27 | #include "trace.h" |
28 | #include "audio/audio.h" | |
1de7afc9 | 29 | #include "qemu/error-report.h" |
0b8fa32f | 30 | #include "qemu/module.h" |
25a8bb96 MW |
31 | |
32 | enum { | |
33 | R_AC97_CTRL = 0, | |
34 | R_AC97_ADDR, | |
35 | R_AC97_DATAOUT, | |
36 | R_AC97_DATAIN, | |
37 | R_D_CTRL, | |
38 | R_D_ADDR, | |
39 | R_D_REMAINING, | |
40 | R_RESERVED, | |
41 | R_U_CTRL, | |
42 | R_U_ADDR, | |
43 | R_U_REMAINING, | |
44 | R_MAX | |
45 | }; | |
46 | ||
47 | enum { | |
48 | AC97_CTRL_RQEN = (1<<0), | |
49 | AC97_CTRL_WRITE = (1<<1), | |
50 | }; | |
51 | ||
52 | enum { | |
53 | CTRL_EN = (1<<0), | |
54 | }; | |
55 | ||
922cc601 AF |
56 | #define TYPE_MILKYMIST_AC97 "milkymist-ac97" |
57 | #define MILKYMIST_AC97(obj) \ | |
58 | OBJECT_CHECK(MilkymistAC97State, (obj), TYPE_MILKYMIST_AC97) | |
59 | ||
25a8bb96 | 60 | struct MilkymistAC97State { |
922cc601 AF |
61 | SysBusDevice parent_obj; |
62 | ||
9496e1c3 | 63 | MemoryRegion regs_region; |
25a8bb96 MW |
64 | |
65 | QEMUSoundCard card; | |
66 | SWVoiceIn *voice_in; | |
67 | SWVoiceOut *voice_out; | |
68 | ||
69 | uint32_t regs[R_MAX]; | |
70 | ||
71 | qemu_irq crrequest_irq; | |
72 | qemu_irq crreply_irq; | |
73 | qemu_irq dmar_irq; | |
74 | qemu_irq dmaw_irq; | |
75 | }; | |
76 | typedef struct MilkymistAC97State MilkymistAC97State; | |
77 | ||
78 | static void update_voices(MilkymistAC97State *s) | |
79 | { | |
80 | if (s->regs[R_D_CTRL] & CTRL_EN) { | |
81 | AUD_set_active_out(s->voice_out, 1); | |
82 | } else { | |
83 | AUD_set_active_out(s->voice_out, 0); | |
84 | } | |
85 | ||
86 | if (s->regs[R_U_CTRL] & CTRL_EN) { | |
87 | AUD_set_active_in(s->voice_in, 1); | |
88 | } else { | |
89 | AUD_set_active_in(s->voice_in, 0); | |
90 | } | |
91 | } | |
92 | ||
a8170e5e | 93 | static uint64_t ac97_read(void *opaque, hwaddr addr, |
9496e1c3 | 94 | unsigned size) |
25a8bb96 MW |
95 | { |
96 | MilkymistAC97State *s = opaque; | |
97 | uint32_t r = 0; | |
98 | ||
99 | addr >>= 2; | |
100 | switch (addr) { | |
101 | case R_AC97_CTRL: | |
102 | case R_AC97_ADDR: | |
103 | case R_AC97_DATAOUT: | |
104 | case R_AC97_DATAIN: | |
105 | case R_D_CTRL: | |
106 | case R_D_ADDR: | |
107 | case R_D_REMAINING: | |
108 | case R_U_CTRL: | |
109 | case R_U_ADDR: | |
110 | case R_U_REMAINING: | |
111 | r = s->regs[addr]; | |
112 | break; | |
113 | ||
114 | default: | |
dd3d6775 | 115 | error_report("milkymist_ac97: read access to unknown register 0x" |
25a8bb96 MW |
116 | TARGET_FMT_plx, addr << 2); |
117 | break; | |
118 | } | |
119 | ||
120 | trace_milkymist_ac97_memory_read(addr << 2, r); | |
121 | ||
122 | return r; | |
123 | } | |
124 | ||
a8170e5e | 125 | static void ac97_write(void *opaque, hwaddr addr, uint64_t value, |
9496e1c3 | 126 | unsigned size) |
25a8bb96 MW |
127 | { |
128 | MilkymistAC97State *s = opaque; | |
129 | ||
130 | trace_milkymist_ac97_memory_write(addr, value); | |
131 | ||
132 | addr >>= 2; | |
133 | switch (addr) { | |
134 | case R_AC97_CTRL: | |
135 | /* always raise an IRQ according to the direction */ | |
136 | if (value & AC97_CTRL_RQEN) { | |
137 | if (value & AC97_CTRL_WRITE) { | |
138 | trace_milkymist_ac97_pulse_irq_crrequest(); | |
139 | qemu_irq_pulse(s->crrequest_irq); | |
140 | } else { | |
141 | trace_milkymist_ac97_pulse_irq_crreply(); | |
142 | qemu_irq_pulse(s->crreply_irq); | |
143 | } | |
144 | } | |
145 | ||
146 | /* RQEN is self clearing */ | |
147 | s->regs[addr] = value & ~AC97_CTRL_RQEN; | |
148 | break; | |
149 | case R_D_CTRL: | |
150 | case R_U_CTRL: | |
151 | s->regs[addr] = value; | |
152 | update_voices(s); | |
153 | break; | |
154 | case R_AC97_ADDR: | |
155 | case R_AC97_DATAOUT: | |
156 | case R_AC97_DATAIN: | |
157 | case R_D_ADDR: | |
158 | case R_D_REMAINING: | |
159 | case R_U_ADDR: | |
160 | case R_U_REMAINING: | |
161 | s->regs[addr] = value; | |
162 | break; | |
163 | ||
164 | default: | |
dd3d6775 | 165 | error_report("milkymist_ac97: write access to unknown register 0x" |
25a8bb96 MW |
166 | TARGET_FMT_plx, addr); |
167 | break; | |
168 | } | |
169 | ||
170 | } | |
171 | ||
9496e1c3 MW |
172 | static const MemoryRegionOps ac97_mmio_ops = { |
173 | .read = ac97_read, | |
174 | .write = ac97_write, | |
175 | .valid = { | |
176 | .min_access_size = 4, | |
177 | .max_access_size = 4, | |
178 | }, | |
179 | .endianness = DEVICE_NATIVE_ENDIAN, | |
25a8bb96 MW |
180 | }; |
181 | ||
182 | static void ac97_in_cb(void *opaque, int avail_b) | |
183 | { | |
184 | MilkymistAC97State *s = opaque; | |
185 | uint8_t buf[4096]; | |
186 | uint32_t remaining = s->regs[R_U_REMAINING]; | |
187 | int temp = audio_MIN(remaining, avail_b); | |
188 | uint32_t addr = s->regs[R_U_ADDR]; | |
189 | int transferred = 0; | |
190 | ||
191 | trace_milkymist_ac97_in_cb(avail_b, remaining); | |
192 | ||
193 | /* prevent from raising an IRQ */ | |
194 | if (temp == 0) { | |
195 | return; | |
196 | } | |
197 | ||
198 | while (temp) { | |
199 | int acquired, to_copy; | |
200 | ||
201 | to_copy = audio_MIN(temp, sizeof(buf)); | |
202 | acquired = AUD_read(s->voice_in, buf, to_copy); | |
203 | if (!acquired) { | |
204 | break; | |
205 | } | |
206 | ||
207 | cpu_physical_memory_write(addr, buf, acquired); | |
208 | ||
209 | temp -= acquired; | |
210 | addr += acquired; | |
211 | transferred += acquired; | |
212 | } | |
213 | ||
214 | trace_milkymist_ac97_in_cb_transferred(transferred); | |
215 | ||
216 | s->regs[R_U_ADDR] = addr; | |
217 | s->regs[R_U_REMAINING] -= transferred; | |
218 | ||
219 | if ((s->regs[R_U_CTRL] & CTRL_EN) && (s->regs[R_U_REMAINING] == 0)) { | |
220 | trace_milkymist_ac97_pulse_irq_dmaw(); | |
221 | qemu_irq_pulse(s->dmaw_irq); | |
222 | } | |
223 | } | |
224 | ||
225 | static void ac97_out_cb(void *opaque, int free_b) | |
226 | { | |
227 | MilkymistAC97State *s = opaque; | |
228 | uint8_t buf[4096]; | |
229 | uint32_t remaining = s->regs[R_D_REMAINING]; | |
230 | int temp = audio_MIN(remaining, free_b); | |
231 | uint32_t addr = s->regs[R_D_ADDR]; | |
232 | int transferred = 0; | |
233 | ||
234 | trace_milkymist_ac97_out_cb(free_b, remaining); | |
235 | ||
236 | /* prevent from raising an IRQ */ | |
237 | if (temp == 0) { | |
238 | return; | |
239 | } | |
240 | ||
241 | while (temp) { | |
242 | int copied, to_copy; | |
243 | ||
244 | to_copy = audio_MIN(temp, sizeof(buf)); | |
245 | cpu_physical_memory_read(addr, buf, to_copy); | |
246 | copied = AUD_write(s->voice_out, buf, to_copy); | |
247 | if (!copied) { | |
248 | break; | |
249 | } | |
250 | temp -= copied; | |
251 | addr += copied; | |
252 | transferred += copied; | |
253 | } | |
254 | ||
255 | trace_milkymist_ac97_out_cb_transferred(transferred); | |
256 | ||
257 | s->regs[R_D_ADDR] = addr; | |
258 | s->regs[R_D_REMAINING] -= transferred; | |
259 | ||
260 | if ((s->regs[R_D_CTRL] & CTRL_EN) && (s->regs[R_D_REMAINING] == 0)) { | |
261 | trace_milkymist_ac97_pulse_irq_dmar(); | |
262 | qemu_irq_pulse(s->dmar_irq); | |
263 | } | |
264 | } | |
265 | ||
266 | static void milkymist_ac97_reset(DeviceState *d) | |
267 | { | |
922cc601 | 268 | MilkymistAC97State *s = MILKYMIST_AC97(d); |
25a8bb96 MW |
269 | int i; |
270 | ||
271 | for (i = 0; i < R_MAX; i++) { | |
272 | s->regs[i] = 0; | |
273 | } | |
274 | ||
275 | AUD_set_active_in(s->voice_in, 0); | |
276 | AUD_set_active_out(s->voice_out, 0); | |
277 | } | |
278 | ||
279 | static int ac97_post_load(void *opaque, int version_id) | |
280 | { | |
281 | MilkymistAC97State *s = opaque; | |
282 | ||
283 | update_voices(s); | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
07b9098d | 288 | static void milkymist_ac97_init(Object *obj) |
25a8bb96 | 289 | { |
07b9098d XZ |
290 | MilkymistAC97State *s = MILKYMIST_AC97(obj); |
291 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
25a8bb96 | 292 | |
25a8bb96 MW |
293 | sysbus_init_irq(dev, &s->crrequest_irq); |
294 | sysbus_init_irq(dev, &s->crreply_irq); | |
295 | sysbus_init_irq(dev, &s->dmar_irq); | |
296 | sysbus_init_irq(dev, &s->dmaw_irq); | |
297 | ||
07b9098d XZ |
298 | memory_region_init_io(&s->regs_region, obj, &ac97_mmio_ops, s, |
299 | "milkymist-ac97", R_MAX * 4); | |
300 | sysbus_init_mmio(dev, &s->regs_region); | |
301 | } | |
302 | ||
303 | static void milkymist_ac97_realize(DeviceState *dev, Error **errp) | |
304 | { | |
305 | MilkymistAC97State *s = MILKYMIST_AC97(dev); | |
306 | struct audsettings as; | |
307 | ||
25a8bb96 MW |
308 | AUD_register_card("Milkymist AC'97", &s->card); |
309 | ||
310 | as.freq = 48000; | |
311 | as.nchannels = 2; | |
85bc5852 | 312 | as.fmt = AUDIO_FORMAT_S16; |
25a8bb96 MW |
313 | as.endianness = 1; |
314 | ||
315 | s->voice_in = AUD_open_in(&s->card, s->voice_in, | |
316 | "mm_ac97.in", s, ac97_in_cb, &as); | |
317 | s->voice_out = AUD_open_out(&s->card, s->voice_out, | |
318 | "mm_ac97.out", s, ac97_out_cb, &as); | |
25a8bb96 MW |
319 | } |
320 | ||
321 | static const VMStateDescription vmstate_milkymist_ac97 = { | |
322 | .name = "milkymist-ac97", | |
323 | .version_id = 1, | |
324 | .minimum_version_id = 1, | |
25a8bb96 | 325 | .post_load = ac97_post_load, |
35d08458 | 326 | .fields = (VMStateField[]) { |
25a8bb96 MW |
327 | VMSTATE_UINT32_ARRAY(regs, MilkymistAC97State, R_MAX), |
328 | VMSTATE_END_OF_LIST() | |
329 | } | |
330 | }; | |
331 | ||
999e12bb AL |
332 | static void milkymist_ac97_class_init(ObjectClass *klass, void *data) |
333 | { | |
39bffca2 | 334 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 335 | |
07b9098d | 336 | dc->realize = milkymist_ac97_realize; |
39bffca2 AL |
337 | dc->reset = milkymist_ac97_reset; |
338 | dc->vmsd = &vmstate_milkymist_ac97; | |
999e12bb AL |
339 | } |
340 | ||
8c43a6f0 | 341 | static const TypeInfo milkymist_ac97_info = { |
922cc601 | 342 | .name = TYPE_MILKYMIST_AC97, |
39bffca2 AL |
343 | .parent = TYPE_SYS_BUS_DEVICE, |
344 | .instance_size = sizeof(MilkymistAC97State), | |
07b9098d | 345 | .instance_init = milkymist_ac97_init, |
39bffca2 | 346 | .class_init = milkymist_ac97_class_init, |
25a8bb96 MW |
347 | }; |
348 | ||
83f7d43a | 349 | static void milkymist_ac97_register_types(void) |
25a8bb96 | 350 | { |
39bffca2 | 351 | type_register_static(&milkymist_ac97_info); |
25a8bb96 MW |
352 | } |
353 | ||
83f7d43a | 354 | type_init(milkymist_ac97_register_types) |