]>
Commit | Line | Data |
---|---|---|
83fa1010 TS |
1 | /* |
2 | * QEMU ETRAX System Emulator | |
3 | * | |
4 | * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
0430891c | 25 | #include "qemu/osdep.h" |
64552b6b | 26 | #include "hw/irq.h" |
a27bd6c7 | 27 | #include "hw/qdev-properties.h" |
83c9f4ca | 28 | #include "hw/sysbus.h" |
4d43a603 | 29 | #include "chardev/char-fe.h" |
1de7afc9 | 30 | #include "qemu/log.h" |
0b8fa32f | 31 | #include "qemu/module.h" |
83fa1010 | 32 | |
bbaf29c7 EI |
33 | #define D(x) |
34 | ||
72af9170 EI |
35 | #define RW_TR_CTRL (0x00 / 4) |
36 | #define RW_TR_DMA_EN (0x04 / 4) | |
37 | #define RW_REC_CTRL (0x08 / 4) | |
38 | #define RW_DOUT (0x1c / 4) | |
39 | #define RS_STAT_DIN (0x20 / 4) | |
40 | #define R_STAT_DIN (0x24 / 4) | |
41 | #define RW_INTR_MASK (0x2c / 4) | |
42 | #define RW_ACK_INTR (0x30 / 4) | |
43 | #define R_INTR (0x34 / 4) | |
44 | #define R_MASKED_INTR (0x38 / 4) | |
45 | #define R_MAX (0x3c / 4) | |
83fa1010 | 46 | |
f062058f EI |
47 | #define STAT_DAV 16 |
48 | #define STAT_TR_IDLE 22 | |
49 | #define STAT_TR_RDY 24 | |
50 | ||
b85423fe AF |
51 | #define TYPE_ETRAX_FS_SERIAL "etraxfs,serial" |
52 | #define ETRAX_SERIAL(obj) \ | |
53 | OBJECT_CHECK(ETRAXSerial, (obj), TYPE_ETRAX_FS_SERIAL) | |
54 | ||
55 | typedef struct ETRAXSerial { | |
56 | SysBusDevice parent_obj; | |
57 | ||
dbfb57f3 | 58 | MemoryRegion mmio; |
becdfa00 | 59 | CharBackend chr; |
2a9859e7 | 60 | qemu_irq irq; |
f062058f | 61 | |
2a9859e7 | 62 | int pending_tx; |
f062058f | 63 | |
f2fcffbb EI |
64 | uint8_t rx_fifo[16]; |
65 | unsigned int rx_fifo_pos; | |
66 | unsigned int rx_fifo_len; | |
67 | ||
2a9859e7 EI |
68 | /* Control registers. */ |
69 | uint32_t regs[R_MAX]; | |
b85423fe | 70 | } ETRAXSerial; |
f062058f | 71 | |
b85423fe | 72 | static void ser_update_irq(ETRAXSerial *s) |
f062058f | 73 | { |
72af9170 | 74 | |
f2fcffbb EI |
75 | if (s->rx_fifo_len) { |
76 | s->regs[R_INTR] |= 8; | |
77 | } else { | |
78 | s->regs[R_INTR] &= ~8; | |
79 | } | |
80 | ||
81 | s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK]; | |
2a9859e7 | 82 | qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]); |
83fa1010 | 83 | } |
f062058f | 84 | |
dbfb57f3 | 85 | static uint64_t |
a8170e5e | 86 | ser_read(void *opaque, hwaddr addr, unsigned int size) |
83fa1010 | 87 | { |
b85423fe | 88 | ETRAXSerial *s = opaque; |
2a9859e7 EI |
89 | uint32_t r = 0; |
90 | ||
91 | addr >>= 2; | |
92 | switch (addr) | |
93 | { | |
94 | case R_STAT_DIN: | |
f2fcffbb EI |
95 | r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15]; |
96 | if (s->rx_fifo_len) { | |
97 | r |= 1 << STAT_DAV; | |
98 | } | |
99 | r |= 1 << STAT_TR_RDY; | |
100 | r |= 1 << STAT_TR_IDLE; | |
2a9859e7 EI |
101 | break; |
102 | case RS_STAT_DIN: | |
f2fcffbb EI |
103 | r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15]; |
104 | if (s->rx_fifo_len) { | |
105 | r |= 1 << STAT_DAV; | |
106 | s->rx_fifo_len--; | |
107 | } | |
108 | r |= 1 << STAT_TR_RDY; | |
109 | r |= 1 << STAT_TR_IDLE; | |
2a9859e7 EI |
110 | break; |
111 | default: | |
112 | r = s->regs[addr]; | |
8cc7c395 | 113 | D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r)); |
2a9859e7 EI |
114 | break; |
115 | } | |
116 | return r; | |
83fa1010 TS |
117 | } |
118 | ||
83fa1010 | 119 | static void |
a8170e5e | 120 | ser_write(void *opaque, hwaddr addr, |
dbfb57f3 | 121 | uint64_t val64, unsigned int size) |
83fa1010 | 122 | { |
b85423fe | 123 | ETRAXSerial *s = opaque; |
dbfb57f3 EI |
124 | uint32_t value = val64; |
125 | unsigned char ch = val64; | |
2a9859e7 | 126 | |
8cc7c395 | 127 | D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value)); |
2a9859e7 EI |
128 | addr >>= 2; |
129 | switch (addr) | |
130 | { | |
131 | case RW_DOUT: | |
6ab3fc32 DB |
132 | /* XXX this blocks entire thread. Rewrite to use |
133 | * qemu_chr_fe_write and background I/O callbacks */ | |
5345fdb4 | 134 | qemu_chr_fe_write_all(&s->chr, &ch, 1); |
f2fcffbb | 135 | s->regs[R_INTR] |= 3; |
2a9859e7 EI |
136 | s->pending_tx = 1; |
137 | s->regs[addr] = value; | |
138 | break; | |
139 | case RW_ACK_INTR: | |
f2fcffbb EI |
140 | if (s->pending_tx) { |
141 | value &= ~1; | |
2a9859e7 | 142 | s->pending_tx = 0; |
8cc7c395 EI |
143 | D(qemu_log("fixedup value=%x r_intr=%x\n", |
144 | value, s->regs[R_INTR])); | |
2a9859e7 | 145 | } |
f2fcffbb EI |
146 | s->regs[addr] = value; |
147 | s->regs[R_INTR] &= ~value; | |
148 | D(printf("r_intr=%x\n", s->regs[R_INTR])); | |
2a9859e7 EI |
149 | break; |
150 | default: | |
151 | s->regs[addr] = value; | |
152 | break; | |
153 | } | |
154 | ser_update_irq(s); | |
83fa1010 TS |
155 | } |
156 | ||
dbfb57f3 EI |
157 | static const MemoryRegionOps ser_ops = { |
158 | .read = ser_read, | |
159 | .write = ser_write, | |
160 | .endianness = DEVICE_NATIVE_ENDIAN, | |
161 | .valid = { | |
162 | .min_access_size = 4, | |
163 | .max_access_size = 4 | |
164 | } | |
83fa1010 TS |
165 | }; |
166 | ||
8290de92 XZ |
167 | static Property etraxfs_ser_properties[] = { |
168 | DEFINE_PROP_CHR("chardev", ETRAXSerial, chr), | |
169 | DEFINE_PROP_END_OF_LIST(), | |
170 | }; | |
171 | ||
f062058f | 172 | static void serial_receive(void *opaque, const uint8_t *buf, int size) |
83fa1010 | 173 | { |
b85423fe | 174 | ETRAXSerial *s = opaque; |
f2fcffbb EI |
175 | int i; |
176 | ||
177 | /* Got a byte. */ | |
178 | if (s->rx_fifo_len >= 16) { | |
79e8ed35 | 179 | D(qemu_log("WARNING: UART dropped char.\n")); |
f2fcffbb EI |
180 | return; |
181 | } | |
182 | ||
183 | for (i = 0; i < size; i++) { | |
184 | s->rx_fifo[s->rx_fifo_pos] = buf[i]; | |
185 | s->rx_fifo_pos++; | |
186 | s->rx_fifo_pos &= 15; | |
187 | s->rx_fifo_len++; | |
188 | } | |
f062058f | 189 | |
2a9859e7 | 190 | ser_update_irq(s); |
f062058f EI |
191 | } |
192 | ||
193 | static int serial_can_receive(void *opaque) | |
194 | { | |
b85423fe | 195 | ETRAXSerial *s = opaque; |
f062058f | 196 | |
2a9859e7 | 197 | /* Is the receiver enabled? */ |
f2fcffbb EI |
198 | if (!(s->regs[RW_REC_CTRL] & (1 << 3))) { |
199 | return 0; | |
200 | } | |
f062058f | 201 | |
65cb2a14 | 202 | return sizeof(s->rx_fifo) - s->rx_fifo_len; |
f062058f EI |
203 | } |
204 | ||
205 | static void serial_event(void *opaque, int event) | |
206 | { | |
207 | ||
208 | } | |
209 | ||
20be39de | 210 | static void etraxfs_ser_reset(DeviceState *d) |
f062058f | 211 | { |
b85423fe | 212 | ETRAXSerial *s = ETRAX_SERIAL(d); |
2a9859e7 EI |
213 | |
214 | /* transmitter begins ready and idle. */ | |
215 | s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY); | |
216 | s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE); | |
217 | ||
20be39de EI |
218 | s->regs[RW_REC_CTRL] = 0x10000; |
219 | ||
220 | } | |
221 | ||
8290de92 | 222 | static void etraxfs_ser_init(Object *obj) |
20be39de | 223 | { |
8290de92 XZ |
224 | ETRAXSerial *s = ETRAX_SERIAL(obj); |
225 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
20be39de | 226 | |
2a9859e7 | 227 | sysbus_init_irq(dev, &s->irq); |
8290de92 | 228 | memory_region_init_io(&s->mmio, obj, &ser_ops, s, |
300b1fc6 | 229 | "etraxfs-serial", R_MAX * 4); |
750ecd44 | 230 | sysbus_init_mmio(dev, &s->mmio); |
8290de92 XZ |
231 | } |
232 | ||
233 | static void etraxfs_ser_realize(DeviceState *dev, Error **errp) | |
234 | { | |
235 | ETRAXSerial *s = ETRAX_SERIAL(dev); | |
dbfb57f3 | 236 | |
fa394ed6 MAL |
237 | qemu_chr_fe_set_handlers(&s->chr, |
238 | serial_can_receive, serial_receive, | |
81517ba3 | 239 | serial_event, NULL, s, NULL, true); |
83fa1010 | 240 | } |
4b816985 | 241 | |
999e12bb AL |
242 | static void etraxfs_ser_class_init(ObjectClass *klass, void *data) |
243 | { | |
39bffca2 | 244 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 245 | |
39bffca2 | 246 | dc->reset = etraxfs_ser_reset; |
8290de92 XZ |
247 | dc->props = etraxfs_ser_properties; |
248 | dc->realize = etraxfs_ser_realize; | |
999e12bb AL |
249 | } |
250 | ||
8c43a6f0 | 251 | static const TypeInfo etraxfs_ser_info = { |
b85423fe | 252 | .name = TYPE_ETRAX_FS_SERIAL, |
39bffca2 | 253 | .parent = TYPE_SYS_BUS_DEVICE, |
b85423fe | 254 | .instance_size = sizeof(ETRAXSerial), |
8290de92 | 255 | .instance_init = etraxfs_ser_init, |
39bffca2 | 256 | .class_init = etraxfs_ser_class_init, |
20be39de EI |
257 | }; |
258 | ||
83f7d43a | 259 | static void etraxfs_serial_register_types(void) |
4b816985 | 260 | { |
39bffca2 | 261 | type_register_static(&etraxfs_ser_info); |
4b816985 EI |
262 | } |
263 | ||
83f7d43a | 264 | type_init(etraxfs_serial_register_types) |