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Commit | Line | Data |
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e6e5ad80 | 1 | /* |
aeb3c85f | 2 | * QEMU Cirrus CLGD 54xx VGA Emulator. |
5fafdf24 | 3 | * |
e6e5ad80 | 4 | * Copyright (c) 2004 Fabrice Bellard |
aeb3c85f | 5 | * Copyright (c) 2004 Makoto Suzuki (suzu) |
5fafdf24 | 6 | * |
e6e5ad80 FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
aeb3c85f FB |
25 | /* |
26 | * Reference: Finn Thogersons' VGADOC4b | |
27 | * available at http://home.worldonline.dk/~finth/ | |
28 | */ | |
87ecb68b PB |
29 | #include "hw.h" |
30 | #include "pc.h" | |
31 | #include "pci.h" | |
32 | #include "console.h" | |
e6e5ad80 | 33 | #include "vga_int.h" |
2bec46dc | 34 | #include "kvm.h" |
e6e5ad80 | 35 | |
a5082316 FB |
36 | /* |
37 | * TODO: | |
ad81218e | 38 | * - destination write mask support not complete (bits 5..7) |
a5082316 FB |
39 | * - optimize linear mappings |
40 | * - optimize bitblt functions | |
41 | */ | |
42 | ||
e36f36e1 | 43 | //#define DEBUG_CIRRUS |
a21ae81d | 44 | //#define DEBUG_BITBLT |
e36f36e1 | 45 | |
e6e5ad80 FB |
46 | /*************************************** |
47 | * | |
48 | * definitions | |
49 | * | |
50 | ***************************************/ | |
51 | ||
e6e5ad80 FB |
52 | // ID |
53 | #define CIRRUS_ID_CLGD5422 (0x23<<2) | |
54 | #define CIRRUS_ID_CLGD5426 (0x24<<2) | |
55 | #define CIRRUS_ID_CLGD5424 (0x25<<2) | |
56 | #define CIRRUS_ID_CLGD5428 (0x26<<2) | |
57 | #define CIRRUS_ID_CLGD5430 (0x28<<2) | |
58 | #define CIRRUS_ID_CLGD5434 (0x2A<<2) | |
a21ae81d | 59 | #define CIRRUS_ID_CLGD5436 (0x2B<<2) |
e6e5ad80 FB |
60 | #define CIRRUS_ID_CLGD5446 (0x2E<<2) |
61 | ||
62 | // sequencer 0x07 | |
63 | #define CIRRUS_SR7_BPP_VGA 0x00 | |
64 | #define CIRRUS_SR7_BPP_SVGA 0x01 | |
65 | #define CIRRUS_SR7_BPP_MASK 0x0e | |
66 | #define CIRRUS_SR7_BPP_8 0x00 | |
67 | #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02 | |
68 | #define CIRRUS_SR7_BPP_24 0x04 | |
69 | #define CIRRUS_SR7_BPP_16 0x06 | |
70 | #define CIRRUS_SR7_BPP_32 0x08 | |
71 | #define CIRRUS_SR7_ISAADDR_MASK 0xe0 | |
72 | ||
73 | // sequencer 0x0f | |
74 | #define CIRRUS_MEMSIZE_512k 0x08 | |
75 | #define CIRRUS_MEMSIZE_1M 0x10 | |
76 | #define CIRRUS_MEMSIZE_2M 0x18 | |
77 | #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled. | |
78 | ||
79 | // sequencer 0x12 | |
80 | #define CIRRUS_CURSOR_SHOW 0x01 | |
81 | #define CIRRUS_CURSOR_HIDDENPEL 0x02 | |
82 | #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear | |
83 | ||
84 | // sequencer 0x17 | |
85 | #define CIRRUS_BUSTYPE_VLBFAST 0x10 | |
86 | #define CIRRUS_BUSTYPE_PCI 0x20 | |
87 | #define CIRRUS_BUSTYPE_VLBSLOW 0x30 | |
88 | #define CIRRUS_BUSTYPE_ISA 0x38 | |
89 | #define CIRRUS_MMIO_ENABLE 0x04 | |
90 | #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared. | |
91 | #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80 | |
92 | ||
93 | // control 0x0b | |
94 | #define CIRRUS_BANKING_DUAL 0x01 | |
95 | #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k | |
96 | ||
97 | // control 0x30 | |
98 | #define CIRRUS_BLTMODE_BACKWARDS 0x01 | |
99 | #define CIRRUS_BLTMODE_MEMSYSDEST 0x02 | |
100 | #define CIRRUS_BLTMODE_MEMSYSSRC 0x04 | |
101 | #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08 | |
102 | #define CIRRUS_BLTMODE_PATTERNCOPY 0x40 | |
103 | #define CIRRUS_BLTMODE_COLOREXPAND 0x80 | |
104 | #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30 | |
105 | #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00 | |
106 | #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10 | |
107 | #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20 | |
108 | #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30 | |
109 | ||
110 | // control 0x31 | |
111 | #define CIRRUS_BLT_BUSY 0x01 | |
112 | #define CIRRUS_BLT_START 0x02 | |
113 | #define CIRRUS_BLT_RESET 0x04 | |
114 | #define CIRRUS_BLT_FIFOUSED 0x10 | |
a5082316 | 115 | #define CIRRUS_BLT_AUTOSTART 0x80 |
e6e5ad80 FB |
116 | |
117 | // control 0x32 | |
118 | #define CIRRUS_ROP_0 0x00 | |
119 | #define CIRRUS_ROP_SRC_AND_DST 0x05 | |
120 | #define CIRRUS_ROP_NOP 0x06 | |
121 | #define CIRRUS_ROP_SRC_AND_NOTDST 0x09 | |
122 | #define CIRRUS_ROP_NOTDST 0x0b | |
123 | #define CIRRUS_ROP_SRC 0x0d | |
124 | #define CIRRUS_ROP_1 0x0e | |
125 | #define CIRRUS_ROP_NOTSRC_AND_DST 0x50 | |
126 | #define CIRRUS_ROP_SRC_XOR_DST 0x59 | |
127 | #define CIRRUS_ROP_SRC_OR_DST 0x6d | |
128 | #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90 | |
129 | #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95 | |
130 | #define CIRRUS_ROP_SRC_OR_NOTDST 0xad | |
131 | #define CIRRUS_ROP_NOTSRC 0xd0 | |
132 | #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6 | |
133 | #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda | |
134 | ||
a5082316 FB |
135 | #define CIRRUS_ROP_NOP_INDEX 2 |
136 | #define CIRRUS_ROP_SRC_INDEX 5 | |
137 | ||
a21ae81d | 138 | // control 0x33 |
a5082316 | 139 | #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04 |
4c8732d7 | 140 | #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02 |
a5082316 | 141 | #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01 |
a21ae81d | 142 | |
e6e5ad80 FB |
143 | // memory-mapped IO |
144 | #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword | |
145 | #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword | |
146 | #define CIRRUS_MMIO_BLTWIDTH 0x08 // word | |
147 | #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word | |
148 | #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word | |
149 | #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word | |
150 | #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword | |
151 | #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword | |
152 | #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte | |
153 | #define CIRRUS_MMIO_BLTMODE 0x18 // byte | |
154 | #define CIRRUS_MMIO_BLTROP 0x1a // byte | |
155 | #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte | |
156 | #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word? | |
157 | #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word? | |
158 | #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word | |
159 | #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word | |
160 | #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word | |
161 | #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word | |
162 | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte | |
163 | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte | |
164 | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte | |
165 | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte | |
166 | #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word | |
167 | #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word | |
168 | #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word | |
169 | #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word | |
170 | #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte | |
171 | #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte | |
172 | #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte | |
173 | ||
e6e5ad80 FB |
174 | // PCI 0x04: command(word), 0x06(word): status |
175 | #define PCI_COMMAND_IOACCESS 0x0001 | |
176 | #define PCI_COMMAND_MEMACCESS 0x0002 | |
177 | #define PCI_COMMAND_BUSMASTER 0x0004 | |
178 | #define PCI_COMMAND_SPECIALCYCLE 0x0008 | |
179 | #define PCI_COMMAND_MEMWRITEINVALID 0x0010 | |
180 | #define PCI_COMMAND_PALETTESNOOPING 0x0020 | |
181 | #define PCI_COMMAND_PARITYDETECTION 0x0040 | |
182 | #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080 | |
183 | #define PCI_COMMAND_SERR 0x0100 | |
184 | #define PCI_COMMAND_BACKTOBACKTRANS 0x0200 | |
185 | // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev) | |
186 | #define PCI_CLASS_BASE_DISPLAY 0x03 | |
187 | // PCI 0x08, 0x00ff0000 | |
188 | #define PCI_CLASS_SUB_VGA 0x00 | |
189 | // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test) | |
e6e5ad80 FB |
190 | // 0x10-0x3f (headertype 00h) |
191 | // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers | |
192 | // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x) | |
193 | #define PCI_MAP_MEM 0x0 | |
194 | #define PCI_MAP_IO 0x1 | |
195 | #define PCI_MAP_MEM_ADDR_MASK (~0xf) | |
196 | #define PCI_MAP_IO_ADDR_MASK (~0x3) | |
197 | #define PCI_MAP_MEMFLAGS_32BIT 0x0 | |
198 | #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1 | |
199 | #define PCI_MAP_MEMFLAGS_64BIT 0x4 | |
200 | #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8 | |
201 | // PCI 0x28: cardbus CIS pointer | |
202 | // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id | |
203 | // PCI 0x30: expansion ROM base address | |
204 | #define PCI_ROMBIOS_ENABLED 0x1 | |
205 | // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer | |
206 | // PCI 0x38: reserved | |
207 | // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat | |
208 | ||
a21ae81d | 209 | #define CIRRUS_PNPMMIO_SIZE 0x1000 |
e6e5ad80 FB |
210 | |
211 | ||
212 | /* I/O and memory hook */ | |
213 | #define CIRRUS_HOOK_NOT_HANDLED 0 | |
214 | #define CIRRUS_HOOK_HANDLED 1 | |
215 | ||
b2b183c2 AL |
216 | #define ABS(a) ((signed)(a) > 0 ? a : -a) |
217 | ||
b2eb849d AJ |
218 | #define BLTUNSAFE(s) \ |
219 | ( \ | |
220 | ( /* check dst is within bounds */ \ | |
b2b183c2 | 221 | (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \ |
b2eb849d | 222 | + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \ |
4e12cd94 | 223 | (s)->vga.vram_size \ |
b2eb849d AJ |
224 | ) || \ |
225 | ( /* check src is within bounds */ \ | |
b2b183c2 | 226 | (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \ |
b2eb849d | 227 | + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \ |
4e12cd94 | 228 | (s)->vga.vram_size \ |
b2eb849d AJ |
229 | ) \ |
230 | ) | |
231 | ||
a5082316 FB |
232 | struct CirrusVGAState; |
233 | typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s, | |
234 | uint8_t * dst, const uint8_t * src, | |
e6e5ad80 FB |
235 | int dstpitch, int srcpitch, |
236 | int bltwidth, int bltheight); | |
a5082316 FB |
237 | typedef void (*cirrus_fill_t)(struct CirrusVGAState *s, |
238 | uint8_t *dst, int dst_pitch, int width, int height); | |
e6e5ad80 FB |
239 | |
240 | typedef struct CirrusVGAState { | |
4e12cd94 | 241 | VGACommonState vga; |
e6e5ad80 FB |
242 | |
243 | int cirrus_linear_io_addr; | |
a5082316 | 244 | int cirrus_linear_bitblt_io_addr; |
e6e5ad80 FB |
245 | int cirrus_mmio_io_addr; |
246 | uint32_t cirrus_addr_mask; | |
78e127ef | 247 | uint32_t linear_mmio_mask; |
e6e5ad80 FB |
248 | uint8_t cirrus_shadow_gr0; |
249 | uint8_t cirrus_shadow_gr1; | |
250 | uint8_t cirrus_hidden_dac_lockindex; | |
251 | uint8_t cirrus_hidden_dac_data; | |
252 | uint32_t cirrus_bank_base[2]; | |
253 | uint32_t cirrus_bank_limit[2]; | |
254 | uint8_t cirrus_hidden_palette[48]; | |
a5082316 FB |
255 | uint32_t hw_cursor_x; |
256 | uint32_t hw_cursor_y; | |
e6e5ad80 FB |
257 | int cirrus_blt_pixelwidth; |
258 | int cirrus_blt_width; | |
259 | int cirrus_blt_height; | |
260 | int cirrus_blt_dstpitch; | |
261 | int cirrus_blt_srcpitch; | |
a5082316 FB |
262 | uint32_t cirrus_blt_fgcol; |
263 | uint32_t cirrus_blt_bgcol; | |
e6e5ad80 FB |
264 | uint32_t cirrus_blt_dstaddr; |
265 | uint32_t cirrus_blt_srcaddr; | |
266 | uint8_t cirrus_blt_mode; | |
a5082316 | 267 | uint8_t cirrus_blt_modeext; |
e6e5ad80 | 268 | cirrus_bitblt_rop_t cirrus_rop; |
a5082316 | 269 | #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */ |
e6e5ad80 FB |
270 | uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE]; |
271 | uint8_t *cirrus_srcptr; | |
272 | uint8_t *cirrus_srcptr_end; | |
273 | uint32_t cirrus_srccounter; | |
a5082316 FB |
274 | /* hwcursor display state */ |
275 | int last_hw_cursor_size; | |
276 | int last_hw_cursor_x; | |
277 | int last_hw_cursor_y; | |
278 | int last_hw_cursor_y_start; | |
279 | int last_hw_cursor_y_end; | |
78e127ef | 280 | int real_vram_size; /* XXX: suppress that */ |
4abc796d BS |
281 | int device_id; |
282 | int bustype; | |
e6e5ad80 FB |
283 | } CirrusVGAState; |
284 | ||
285 | typedef struct PCICirrusVGAState { | |
286 | PCIDevice dev; | |
287 | CirrusVGAState cirrus_vga; | |
288 | } PCICirrusVGAState; | |
289 | ||
a5082316 | 290 | static uint8_t rop_to_index[256]; |
3b46e624 | 291 | |
e6e5ad80 FB |
292 | /*************************************** |
293 | * | |
294 | * prototypes. | |
295 | * | |
296 | ***************************************/ | |
297 | ||
298 | ||
8926b517 FB |
299 | static void cirrus_bitblt_reset(CirrusVGAState *s); |
300 | static void cirrus_update_memory_access(CirrusVGAState *s); | |
e6e5ad80 FB |
301 | |
302 | /*************************************** | |
303 | * | |
304 | * raster operations | |
305 | * | |
306 | ***************************************/ | |
307 | ||
a5082316 FB |
308 | static void cirrus_bitblt_rop_nop(CirrusVGAState *s, |
309 | uint8_t *dst,const uint8_t *src, | |
310 | int dstpitch,int srcpitch, | |
311 | int bltwidth,int bltheight) | |
312 | { | |
e6e5ad80 FB |
313 | } |
314 | ||
a5082316 FB |
315 | static void cirrus_bitblt_fill_nop(CirrusVGAState *s, |
316 | uint8_t *dst, | |
317 | int dstpitch, int bltwidth,int bltheight) | |
e6e5ad80 | 318 | { |
a5082316 | 319 | } |
e6e5ad80 | 320 | |
a5082316 FB |
321 | #define ROP_NAME 0 |
322 | #define ROP_OP(d, s) d = 0 | |
323 | #include "cirrus_vga_rop.h" | |
e6e5ad80 | 324 | |
a5082316 FB |
325 | #define ROP_NAME src_and_dst |
326 | #define ROP_OP(d, s) d = (s) & (d) | |
327 | #include "cirrus_vga_rop.h" | |
e6e5ad80 | 328 | |
a5082316 FB |
329 | #define ROP_NAME src_and_notdst |
330 | #define ROP_OP(d, s) d = (s) & (~(d)) | |
331 | #include "cirrus_vga_rop.h" | |
e6e5ad80 | 332 | |
a5082316 FB |
333 | #define ROP_NAME notdst |
334 | #define ROP_OP(d, s) d = ~(d) | |
335 | #include "cirrus_vga_rop.h" | |
e6e5ad80 | 336 | |
a5082316 FB |
337 | #define ROP_NAME src |
338 | #define ROP_OP(d, s) d = s | |
339 | #include "cirrus_vga_rop.h" | |
e6e5ad80 | 340 | |
a5082316 | 341 | #define ROP_NAME 1 |
4c8732d7 | 342 | #define ROP_OP(d, s) d = ~0 |
a5082316 FB |
343 | #include "cirrus_vga_rop.h" |
344 | ||
345 | #define ROP_NAME notsrc_and_dst | |
346 | #define ROP_OP(d, s) d = (~(s)) & (d) | |
347 | #include "cirrus_vga_rop.h" | |
348 | ||
349 | #define ROP_NAME src_xor_dst | |
350 | #define ROP_OP(d, s) d = (s) ^ (d) | |
351 | #include "cirrus_vga_rop.h" | |
352 | ||
353 | #define ROP_NAME src_or_dst | |
354 | #define ROP_OP(d, s) d = (s) | (d) | |
355 | #include "cirrus_vga_rop.h" | |
356 | ||
357 | #define ROP_NAME notsrc_or_notdst | |
358 | #define ROP_OP(d, s) d = (~(s)) | (~(d)) | |
359 | #include "cirrus_vga_rop.h" | |
360 | ||
361 | #define ROP_NAME src_notxor_dst | |
362 | #define ROP_OP(d, s) d = ~((s) ^ (d)) | |
363 | #include "cirrus_vga_rop.h" | |
e6e5ad80 | 364 | |
a5082316 FB |
365 | #define ROP_NAME src_or_notdst |
366 | #define ROP_OP(d, s) d = (s) | (~(d)) | |
367 | #include "cirrus_vga_rop.h" | |
368 | ||
369 | #define ROP_NAME notsrc | |
370 | #define ROP_OP(d, s) d = (~(s)) | |
371 | #include "cirrus_vga_rop.h" | |
372 | ||
373 | #define ROP_NAME notsrc_or_dst | |
374 | #define ROP_OP(d, s) d = (~(s)) | (d) | |
375 | #include "cirrus_vga_rop.h" | |
376 | ||
377 | #define ROP_NAME notsrc_and_notdst | |
378 | #define ROP_OP(d, s) d = (~(s)) & (~(d)) | |
379 | #include "cirrus_vga_rop.h" | |
380 | ||
381 | static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = { | |
382 | cirrus_bitblt_rop_fwd_0, | |
383 | cirrus_bitblt_rop_fwd_src_and_dst, | |
384 | cirrus_bitblt_rop_nop, | |
385 | cirrus_bitblt_rop_fwd_src_and_notdst, | |
386 | cirrus_bitblt_rop_fwd_notdst, | |
387 | cirrus_bitblt_rop_fwd_src, | |
388 | cirrus_bitblt_rop_fwd_1, | |
389 | cirrus_bitblt_rop_fwd_notsrc_and_dst, | |
390 | cirrus_bitblt_rop_fwd_src_xor_dst, | |
391 | cirrus_bitblt_rop_fwd_src_or_dst, | |
392 | cirrus_bitblt_rop_fwd_notsrc_or_notdst, | |
393 | cirrus_bitblt_rop_fwd_src_notxor_dst, | |
394 | cirrus_bitblt_rop_fwd_src_or_notdst, | |
395 | cirrus_bitblt_rop_fwd_notsrc, | |
396 | cirrus_bitblt_rop_fwd_notsrc_or_dst, | |
397 | cirrus_bitblt_rop_fwd_notsrc_and_notdst, | |
398 | }; | |
399 | ||
400 | static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = { | |
401 | cirrus_bitblt_rop_bkwd_0, | |
402 | cirrus_bitblt_rop_bkwd_src_and_dst, | |
403 | cirrus_bitblt_rop_nop, | |
404 | cirrus_bitblt_rop_bkwd_src_and_notdst, | |
405 | cirrus_bitblt_rop_bkwd_notdst, | |
406 | cirrus_bitblt_rop_bkwd_src, | |
407 | cirrus_bitblt_rop_bkwd_1, | |
408 | cirrus_bitblt_rop_bkwd_notsrc_and_dst, | |
409 | cirrus_bitblt_rop_bkwd_src_xor_dst, | |
410 | cirrus_bitblt_rop_bkwd_src_or_dst, | |
411 | cirrus_bitblt_rop_bkwd_notsrc_or_notdst, | |
412 | cirrus_bitblt_rop_bkwd_src_notxor_dst, | |
413 | cirrus_bitblt_rop_bkwd_src_or_notdst, | |
414 | cirrus_bitblt_rop_bkwd_notsrc, | |
415 | cirrus_bitblt_rop_bkwd_notsrc_or_dst, | |
416 | cirrus_bitblt_rop_bkwd_notsrc_and_notdst, | |
417 | }; | |
96cf2df8 TS |
418 | |
419 | #define TRANSP_ROP(name) {\ | |
420 | name ## _8,\ | |
421 | name ## _16,\ | |
422 | } | |
423 | #define TRANSP_NOP(func) {\ | |
424 | func,\ | |
425 | func,\ | |
426 | } | |
427 | ||
428 | static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = { | |
429 | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0), | |
430 | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst), | |
431 | TRANSP_NOP(cirrus_bitblt_rop_nop), | |
432 | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst), | |
433 | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst), | |
434 | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src), | |
435 | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1), | |
436 | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst), | |
437 | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst), | |
438 | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst), | |
439 | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst), | |
440 | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst), | |
441 | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst), | |
442 | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc), | |
443 | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst), | |
444 | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst), | |
445 | }; | |
446 | ||
447 | static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = { | |
448 | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0), | |
449 | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst), | |
450 | TRANSP_NOP(cirrus_bitblt_rop_nop), | |
451 | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst), | |
452 | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst), | |
453 | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src), | |
454 | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1), | |
455 | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst), | |
456 | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst), | |
457 | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst), | |
458 | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst), | |
459 | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst), | |
460 | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst), | |
461 | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc), | |
462 | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst), | |
463 | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst), | |
464 | }; | |
465 | ||
a5082316 FB |
466 | #define ROP2(name) {\ |
467 | name ## _8,\ | |
468 | name ## _16,\ | |
469 | name ## _24,\ | |
470 | name ## _32,\ | |
471 | } | |
472 | ||
473 | #define ROP_NOP2(func) {\ | |
474 | func,\ | |
475 | func,\ | |
476 | func,\ | |
477 | func,\ | |
478 | } | |
479 | ||
e69390ce FB |
480 | static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = { |
481 | ROP2(cirrus_patternfill_0), | |
482 | ROP2(cirrus_patternfill_src_and_dst), | |
483 | ROP_NOP2(cirrus_bitblt_rop_nop), | |
484 | ROP2(cirrus_patternfill_src_and_notdst), | |
485 | ROP2(cirrus_patternfill_notdst), | |
486 | ROP2(cirrus_patternfill_src), | |
487 | ROP2(cirrus_patternfill_1), | |
488 | ROP2(cirrus_patternfill_notsrc_and_dst), | |
489 | ROP2(cirrus_patternfill_src_xor_dst), | |
490 | ROP2(cirrus_patternfill_src_or_dst), | |
491 | ROP2(cirrus_patternfill_notsrc_or_notdst), | |
492 | ROP2(cirrus_patternfill_src_notxor_dst), | |
493 | ROP2(cirrus_patternfill_src_or_notdst), | |
494 | ROP2(cirrus_patternfill_notsrc), | |
495 | ROP2(cirrus_patternfill_notsrc_or_dst), | |
496 | ROP2(cirrus_patternfill_notsrc_and_notdst), | |
497 | }; | |
498 | ||
a5082316 FB |
499 | static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = { |
500 | ROP2(cirrus_colorexpand_transp_0), | |
501 | ROP2(cirrus_colorexpand_transp_src_and_dst), | |
502 | ROP_NOP2(cirrus_bitblt_rop_nop), | |
503 | ROP2(cirrus_colorexpand_transp_src_and_notdst), | |
504 | ROP2(cirrus_colorexpand_transp_notdst), | |
505 | ROP2(cirrus_colorexpand_transp_src), | |
506 | ROP2(cirrus_colorexpand_transp_1), | |
507 | ROP2(cirrus_colorexpand_transp_notsrc_and_dst), | |
508 | ROP2(cirrus_colorexpand_transp_src_xor_dst), | |
509 | ROP2(cirrus_colorexpand_transp_src_or_dst), | |
510 | ROP2(cirrus_colorexpand_transp_notsrc_or_notdst), | |
511 | ROP2(cirrus_colorexpand_transp_src_notxor_dst), | |
512 | ROP2(cirrus_colorexpand_transp_src_or_notdst), | |
513 | ROP2(cirrus_colorexpand_transp_notsrc), | |
514 | ROP2(cirrus_colorexpand_transp_notsrc_or_dst), | |
515 | ROP2(cirrus_colorexpand_transp_notsrc_and_notdst), | |
516 | }; | |
517 | ||
518 | static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = { | |
519 | ROP2(cirrus_colorexpand_0), | |
520 | ROP2(cirrus_colorexpand_src_and_dst), | |
521 | ROP_NOP2(cirrus_bitblt_rop_nop), | |
522 | ROP2(cirrus_colorexpand_src_and_notdst), | |
523 | ROP2(cirrus_colorexpand_notdst), | |
524 | ROP2(cirrus_colorexpand_src), | |
525 | ROP2(cirrus_colorexpand_1), | |
526 | ROP2(cirrus_colorexpand_notsrc_and_dst), | |
527 | ROP2(cirrus_colorexpand_src_xor_dst), | |
528 | ROP2(cirrus_colorexpand_src_or_dst), | |
529 | ROP2(cirrus_colorexpand_notsrc_or_notdst), | |
530 | ROP2(cirrus_colorexpand_src_notxor_dst), | |
531 | ROP2(cirrus_colorexpand_src_or_notdst), | |
532 | ROP2(cirrus_colorexpand_notsrc), | |
533 | ROP2(cirrus_colorexpand_notsrc_or_dst), | |
534 | ROP2(cirrus_colorexpand_notsrc_and_notdst), | |
535 | }; | |
536 | ||
b30d4608 FB |
537 | static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = { |
538 | ROP2(cirrus_colorexpand_pattern_transp_0), | |
539 | ROP2(cirrus_colorexpand_pattern_transp_src_and_dst), | |
540 | ROP_NOP2(cirrus_bitblt_rop_nop), | |
541 | ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst), | |
542 | ROP2(cirrus_colorexpand_pattern_transp_notdst), | |
543 | ROP2(cirrus_colorexpand_pattern_transp_src), | |
544 | ROP2(cirrus_colorexpand_pattern_transp_1), | |
545 | ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst), | |
546 | ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst), | |
547 | ROP2(cirrus_colorexpand_pattern_transp_src_or_dst), | |
548 | ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst), | |
549 | ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst), | |
550 | ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst), | |
551 | ROP2(cirrus_colorexpand_pattern_transp_notsrc), | |
552 | ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst), | |
553 | ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst), | |
554 | }; | |
555 | ||
556 | static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = { | |
557 | ROP2(cirrus_colorexpand_pattern_0), | |
558 | ROP2(cirrus_colorexpand_pattern_src_and_dst), | |
559 | ROP_NOP2(cirrus_bitblt_rop_nop), | |
560 | ROP2(cirrus_colorexpand_pattern_src_and_notdst), | |
561 | ROP2(cirrus_colorexpand_pattern_notdst), | |
562 | ROP2(cirrus_colorexpand_pattern_src), | |
563 | ROP2(cirrus_colorexpand_pattern_1), | |
564 | ROP2(cirrus_colorexpand_pattern_notsrc_and_dst), | |
565 | ROP2(cirrus_colorexpand_pattern_src_xor_dst), | |
566 | ROP2(cirrus_colorexpand_pattern_src_or_dst), | |
567 | ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst), | |
568 | ROP2(cirrus_colorexpand_pattern_src_notxor_dst), | |
569 | ROP2(cirrus_colorexpand_pattern_src_or_notdst), | |
570 | ROP2(cirrus_colorexpand_pattern_notsrc), | |
571 | ROP2(cirrus_colorexpand_pattern_notsrc_or_dst), | |
572 | ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst), | |
573 | }; | |
574 | ||
a5082316 FB |
575 | static const cirrus_fill_t cirrus_fill[16][4] = { |
576 | ROP2(cirrus_fill_0), | |
577 | ROP2(cirrus_fill_src_and_dst), | |
578 | ROP_NOP2(cirrus_bitblt_fill_nop), | |
579 | ROP2(cirrus_fill_src_and_notdst), | |
580 | ROP2(cirrus_fill_notdst), | |
581 | ROP2(cirrus_fill_src), | |
582 | ROP2(cirrus_fill_1), | |
583 | ROP2(cirrus_fill_notsrc_and_dst), | |
584 | ROP2(cirrus_fill_src_xor_dst), | |
585 | ROP2(cirrus_fill_src_or_dst), | |
586 | ROP2(cirrus_fill_notsrc_or_notdst), | |
587 | ROP2(cirrus_fill_src_notxor_dst), | |
588 | ROP2(cirrus_fill_src_or_notdst), | |
589 | ROP2(cirrus_fill_notsrc), | |
590 | ROP2(cirrus_fill_notsrc_or_dst), | |
591 | ROP2(cirrus_fill_notsrc_and_notdst), | |
592 | }; | |
593 | ||
594 | static inline void cirrus_bitblt_fgcol(CirrusVGAState *s) | |
e6e5ad80 | 595 | { |
a5082316 FB |
596 | unsigned int color; |
597 | switch (s->cirrus_blt_pixelwidth) { | |
598 | case 1: | |
599 | s->cirrus_blt_fgcol = s->cirrus_shadow_gr1; | |
600 | break; | |
601 | case 2: | |
4e12cd94 | 602 | color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8); |
a5082316 FB |
603 | s->cirrus_blt_fgcol = le16_to_cpu(color); |
604 | break; | |
605 | case 3: | |
5fafdf24 | 606 | s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 | |
4e12cd94 | 607 | (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16); |
a5082316 FB |
608 | break; |
609 | default: | |
610 | case 4: | |
4e12cd94 AK |
611 | color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) | |
612 | (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24); | |
a5082316 FB |
613 | s->cirrus_blt_fgcol = le32_to_cpu(color); |
614 | break; | |
e6e5ad80 FB |
615 | } |
616 | } | |
617 | ||
a5082316 | 618 | static inline void cirrus_bitblt_bgcol(CirrusVGAState *s) |
e6e5ad80 | 619 | { |
a5082316 | 620 | unsigned int color; |
e6e5ad80 FB |
621 | switch (s->cirrus_blt_pixelwidth) { |
622 | case 1: | |
a5082316 FB |
623 | s->cirrus_blt_bgcol = s->cirrus_shadow_gr0; |
624 | break; | |
e6e5ad80 | 625 | case 2: |
4e12cd94 | 626 | color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8); |
a5082316 FB |
627 | s->cirrus_blt_bgcol = le16_to_cpu(color); |
628 | break; | |
e6e5ad80 | 629 | case 3: |
5fafdf24 | 630 | s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 | |
4e12cd94 | 631 | (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16); |
a5082316 | 632 | break; |
e6e5ad80 | 633 | default: |
a5082316 | 634 | case 4: |
4e12cd94 AK |
635 | color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) | |
636 | (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24); | |
a5082316 FB |
637 | s->cirrus_blt_bgcol = le32_to_cpu(color); |
638 | break; | |
e6e5ad80 FB |
639 | } |
640 | } | |
641 | ||
642 | static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin, | |
643 | int off_pitch, int bytesperline, | |
644 | int lines) | |
645 | { | |
646 | int y; | |
647 | int off_cur; | |
648 | int off_cur_end; | |
649 | ||
650 | for (y = 0; y < lines; y++) { | |
651 | off_cur = off_begin; | |
b2eb849d | 652 | off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask; |
e6e5ad80 FB |
653 | off_cur &= TARGET_PAGE_MASK; |
654 | while (off_cur < off_cur_end) { | |
4e12cd94 | 655 | cpu_physical_memory_set_dirty(s->vga.vram_offset + off_cur); |
e6e5ad80 FB |
656 | off_cur += TARGET_PAGE_SIZE; |
657 | } | |
658 | off_begin += off_pitch; | |
659 | } | |
660 | } | |
661 | ||
e6e5ad80 FB |
662 | static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s, |
663 | const uint8_t * src) | |
664 | { | |
e6e5ad80 | 665 | uint8_t *dst; |
e6e5ad80 | 666 | |
4e12cd94 | 667 | dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask); |
b2eb849d AJ |
668 | |
669 | if (BLTUNSAFE(s)) | |
670 | return 0; | |
671 | ||
e69390ce | 672 | (*s->cirrus_rop) (s, dst, src, |
5fafdf24 | 673 | s->cirrus_blt_dstpitch, 0, |
e69390ce | 674 | s->cirrus_blt_width, s->cirrus_blt_height); |
e6e5ad80 | 675 | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
e69390ce FB |
676 | s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
677 | s->cirrus_blt_height); | |
e6e5ad80 FB |
678 | return 1; |
679 | } | |
680 | ||
a21ae81d FB |
681 | /* fill */ |
682 | ||
a5082316 | 683 | static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop) |
a21ae81d | 684 | { |
a5082316 | 685 | cirrus_fill_t rop_func; |
a21ae81d | 686 | |
b2eb849d AJ |
687 | if (BLTUNSAFE(s)) |
688 | return 0; | |
a5082316 | 689 | rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; |
4e12cd94 | 690 | rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), |
a5082316 FB |
691 | s->cirrus_blt_dstpitch, |
692 | s->cirrus_blt_width, s->cirrus_blt_height); | |
a21ae81d FB |
693 | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
694 | s->cirrus_blt_dstpitch, s->cirrus_blt_width, | |
695 | s->cirrus_blt_height); | |
696 | cirrus_bitblt_reset(s); | |
697 | return 1; | |
698 | } | |
699 | ||
e6e5ad80 FB |
700 | /*************************************** |
701 | * | |
702 | * bitblt (video-to-video) | |
703 | * | |
704 | ***************************************/ | |
705 | ||
706 | static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s) | |
707 | { | |
708 | return cirrus_bitblt_common_patterncopy(s, | |
4e12cd94 | 709 | s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) & |
b2eb849d | 710 | s->cirrus_addr_mask)); |
e6e5ad80 FB |
711 | } |
712 | ||
24236869 | 713 | static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h) |
e6e5ad80 | 714 | { |
24236869 FB |
715 | int sx, sy; |
716 | int dx, dy; | |
717 | int width, height; | |
718 | int depth; | |
719 | int notify = 0; | |
720 | ||
4e12cd94 AK |
721 | depth = s->vga.get_bpp(&s->vga) / 8; |
722 | s->vga.get_resolution(&s->vga, &width, &height); | |
24236869 FB |
723 | |
724 | /* extra x, y */ | |
d85d0d38 AL |
725 | sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth; |
726 | sy = (src / ABS(s->cirrus_blt_srcpitch)); | |
727 | dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth; | |
728 | dy = (dst / ABS(s->cirrus_blt_dstpitch)); | |
24236869 FB |
729 | |
730 | /* normalize width */ | |
731 | w /= depth; | |
732 | ||
733 | /* if we're doing a backward copy, we have to adjust | |
734 | our x/y to be the upper left corner (instead of the lower | |
735 | right corner) */ | |
736 | if (s->cirrus_blt_dstpitch < 0) { | |
737 | sx -= (s->cirrus_blt_width / depth) - 1; | |
738 | dx -= (s->cirrus_blt_width / depth) - 1; | |
739 | sy -= s->cirrus_blt_height - 1; | |
740 | dy -= s->cirrus_blt_height - 1; | |
741 | } | |
742 | ||
743 | /* are we in the visible portion of memory? */ | |
744 | if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 && | |
745 | (sx + w) <= width && (sy + h) <= height && | |
746 | (dx + w) <= width && (dy + h) <= height) { | |
747 | notify = 1; | |
748 | } | |
749 | ||
750 | /* make to sure only copy if it's a plain copy ROP */ | |
751 | if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src && | |
752 | *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src) | |
753 | notify = 0; | |
754 | ||
755 | /* we have to flush all pending changes so that the copy | |
756 | is generated at the appropriate moment in time */ | |
757 | if (notify) | |
758 | vga_hw_update(); | |
759 | ||
4e12cd94 | 760 | (*s->cirrus_rop) (s, s->vga.vram_ptr + |
b2eb849d | 761 | (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), |
4e12cd94 | 762 | s->vga.vram_ptr + |
b2eb849d | 763 | (s->cirrus_blt_srcaddr & s->cirrus_addr_mask), |
e6e5ad80 FB |
764 | s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch, |
765 | s->cirrus_blt_width, s->cirrus_blt_height); | |
24236869 FB |
766 | |
767 | if (notify) | |
4e12cd94 | 768 | qemu_console_copy(s->vga.ds, |
38334f76 AZ |
769 | sx, sy, dx, dy, |
770 | s->cirrus_blt_width / depth, | |
771 | s->cirrus_blt_height); | |
24236869 FB |
772 | |
773 | /* we don't have to notify the display that this portion has | |
38334f76 | 774 | changed since qemu_console_copy implies this */ |
24236869 | 775 | |
31c05501 AL |
776 | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
777 | s->cirrus_blt_dstpitch, s->cirrus_blt_width, | |
778 | s->cirrus_blt_height); | |
24236869 FB |
779 | } |
780 | ||
781 | static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s) | |
782 | { | |
65d35a09 AJ |
783 | if (BLTUNSAFE(s)) |
784 | return 0; | |
785 | ||
4e12cd94 AK |
786 | cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr, |
787 | s->cirrus_blt_srcaddr - s->vga.start_addr, | |
7d957bd8 | 788 | s->cirrus_blt_width, s->cirrus_blt_height); |
24236869 | 789 | |
e6e5ad80 FB |
790 | return 1; |
791 | } | |
792 | ||
793 | /*************************************** | |
794 | * | |
795 | * bitblt (cpu-to-video) | |
796 | * | |
797 | ***************************************/ | |
798 | ||
e6e5ad80 FB |
799 | static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s) |
800 | { | |
801 | int copy_count; | |
a5082316 | 802 | uint8_t *end_ptr; |
3b46e624 | 803 | |
e6e5ad80 | 804 | if (s->cirrus_srccounter > 0) { |
a5082316 FB |
805 | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { |
806 | cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf); | |
807 | the_end: | |
808 | s->cirrus_srccounter = 0; | |
809 | cirrus_bitblt_reset(s); | |
810 | } else { | |
811 | /* at least one scan line */ | |
812 | do { | |
4e12cd94 | 813 | (*s->cirrus_rop)(s, s->vga.vram_ptr + |
b2eb849d AJ |
814 | (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), |
815 | s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1); | |
a5082316 FB |
816 | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0, |
817 | s->cirrus_blt_width, 1); | |
818 | s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch; | |
819 | s->cirrus_srccounter -= s->cirrus_blt_srcpitch; | |
820 | if (s->cirrus_srccounter <= 0) | |
821 | goto the_end; | |
822 | /* more bytes than needed can be transfered because of | |
823 | word alignment, so we keep them for the next line */ | |
824 | /* XXX: keep alignment to speed up transfer */ | |
825 | end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; | |
826 | copy_count = s->cirrus_srcptr_end - end_ptr; | |
827 | memmove(s->cirrus_bltbuf, end_ptr, copy_count); | |
828 | s->cirrus_srcptr = s->cirrus_bltbuf + copy_count; | |
829 | s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; | |
830 | } while (s->cirrus_srcptr >= s->cirrus_srcptr_end); | |
831 | } | |
e6e5ad80 FB |
832 | } |
833 | } | |
834 | ||
835 | /*************************************** | |
836 | * | |
837 | * bitblt wrapper | |
838 | * | |
839 | ***************************************/ | |
840 | ||
841 | static void cirrus_bitblt_reset(CirrusVGAState * s) | |
842 | { | |
f8b237af AL |
843 | int need_update; |
844 | ||
4e12cd94 | 845 | s->vga.gr[0x31] &= |
e6e5ad80 | 846 | ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED); |
f8b237af AL |
847 | need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0] |
848 | || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0]; | |
e6e5ad80 FB |
849 | s->cirrus_srcptr = &s->cirrus_bltbuf[0]; |
850 | s->cirrus_srcptr_end = &s->cirrus_bltbuf[0]; | |
851 | s->cirrus_srccounter = 0; | |
f8b237af AL |
852 | if (!need_update) |
853 | return; | |
8926b517 | 854 | cirrus_update_memory_access(s); |
e6e5ad80 FB |
855 | } |
856 | ||
857 | static int cirrus_bitblt_cputovideo(CirrusVGAState * s) | |
858 | { | |
a5082316 FB |
859 | int w; |
860 | ||
e6e5ad80 FB |
861 | s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC; |
862 | s->cirrus_srcptr = &s->cirrus_bltbuf[0]; | |
863 | s->cirrus_srcptr_end = &s->cirrus_bltbuf[0]; | |
864 | ||
865 | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { | |
866 | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) { | |
a5082316 | 867 | s->cirrus_blt_srcpitch = 8; |
e6e5ad80 | 868 | } else { |
b30d4608 | 869 | /* XXX: check for 24 bpp */ |
a5082316 | 870 | s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth; |
e6e5ad80 | 871 | } |
a5082316 | 872 | s->cirrus_srccounter = s->cirrus_blt_srcpitch; |
e6e5ad80 FB |
873 | } else { |
874 | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) { | |
a5082316 | 875 | w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth; |
5fafdf24 | 876 | if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY) |
a5082316 FB |
877 | s->cirrus_blt_srcpitch = ((w + 31) >> 5); |
878 | else | |
879 | s->cirrus_blt_srcpitch = ((w + 7) >> 3); | |
e6e5ad80 | 880 | } else { |
c9c0eae8 FB |
881 | /* always align input size to 32 bits */ |
882 | s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3; | |
e6e5ad80 | 883 | } |
a5082316 | 884 | s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height; |
e6e5ad80 | 885 | } |
a5082316 FB |
886 | s->cirrus_srcptr = s->cirrus_bltbuf; |
887 | s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; | |
8926b517 | 888 | cirrus_update_memory_access(s); |
e6e5ad80 FB |
889 | return 1; |
890 | } | |
891 | ||
892 | static int cirrus_bitblt_videotocpu(CirrusVGAState * s) | |
893 | { | |
894 | /* XXX */ | |
a5082316 | 895 | #ifdef DEBUG_BITBLT |
e6e5ad80 FB |
896 | printf("cirrus: bitblt (video to cpu) is not implemented yet\n"); |
897 | #endif | |
898 | return 0; | |
899 | } | |
900 | ||
901 | static int cirrus_bitblt_videotovideo(CirrusVGAState * s) | |
902 | { | |
903 | int ret; | |
904 | ||
905 | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { | |
906 | ret = cirrus_bitblt_videotovideo_patterncopy(s); | |
907 | } else { | |
908 | ret = cirrus_bitblt_videotovideo_copy(s); | |
909 | } | |
e6e5ad80 FB |
910 | if (ret) |
911 | cirrus_bitblt_reset(s); | |
912 | return ret; | |
913 | } | |
914 | ||
915 | static void cirrus_bitblt_start(CirrusVGAState * s) | |
916 | { | |
917 | uint8_t blt_rop; | |
918 | ||
4e12cd94 | 919 | s->vga.gr[0x31] |= CIRRUS_BLT_BUSY; |
a5082316 | 920 | |
4e12cd94 AK |
921 | s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1; |
922 | s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1; | |
923 | s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8)); | |
924 | s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8)); | |
e6e5ad80 | 925 | s->cirrus_blt_dstaddr = |
4e12cd94 | 926 | (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16)); |
e6e5ad80 | 927 | s->cirrus_blt_srcaddr = |
4e12cd94 AK |
928 | (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16)); |
929 | s->cirrus_blt_mode = s->vga.gr[0x30]; | |
930 | s->cirrus_blt_modeext = s->vga.gr[0x33]; | |
931 | blt_rop = s->vga.gr[0x32]; | |
e6e5ad80 | 932 | |
a21ae81d | 933 | #ifdef DEBUG_BITBLT |
0b74ed78 | 934 | printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n", |
5fafdf24 | 935 | blt_rop, |
a21ae81d | 936 | s->cirrus_blt_mode, |
a5082316 | 937 | s->cirrus_blt_modeext, |
a21ae81d FB |
938 | s->cirrus_blt_width, |
939 | s->cirrus_blt_height, | |
940 | s->cirrus_blt_dstpitch, | |
941 | s->cirrus_blt_srcpitch, | |
942 | s->cirrus_blt_dstaddr, | |
a5082316 | 943 | s->cirrus_blt_srcaddr, |
4e12cd94 | 944 | s->vga.gr[0x2f]); |
a21ae81d FB |
945 | #endif |
946 | ||
e6e5ad80 FB |
947 | switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) { |
948 | case CIRRUS_BLTMODE_PIXELWIDTH8: | |
949 | s->cirrus_blt_pixelwidth = 1; | |
950 | break; | |
951 | case CIRRUS_BLTMODE_PIXELWIDTH16: | |
952 | s->cirrus_blt_pixelwidth = 2; | |
953 | break; | |
954 | case CIRRUS_BLTMODE_PIXELWIDTH24: | |
955 | s->cirrus_blt_pixelwidth = 3; | |
956 | break; | |
957 | case CIRRUS_BLTMODE_PIXELWIDTH32: | |
958 | s->cirrus_blt_pixelwidth = 4; | |
959 | break; | |
960 | default: | |
a5082316 | 961 | #ifdef DEBUG_BITBLT |
e6e5ad80 FB |
962 | printf("cirrus: bitblt - pixel width is unknown\n"); |
963 | #endif | |
964 | goto bitblt_ignore; | |
965 | } | |
966 | s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK; | |
967 | ||
968 | if ((s-> | |
969 | cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC | | |
970 | CIRRUS_BLTMODE_MEMSYSDEST)) | |
971 | == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) { | |
a5082316 | 972 | #ifdef DEBUG_BITBLT |
e6e5ad80 FB |
973 | printf("cirrus: bitblt - memory-to-memory copy is requested\n"); |
974 | #endif | |
975 | goto bitblt_ignore; | |
976 | } | |
977 | ||
a5082316 | 978 | if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) && |
5fafdf24 | 979 | (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST | |
a21ae81d | 980 | CIRRUS_BLTMODE_TRANSPARENTCOMP | |
5fafdf24 TS |
981 | CIRRUS_BLTMODE_PATTERNCOPY | |
982 | CIRRUS_BLTMODE_COLOREXPAND)) == | |
a21ae81d | 983 | (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) { |
a5082316 FB |
984 | cirrus_bitblt_fgcol(s); |
985 | cirrus_bitblt_solidfill(s, blt_rop); | |
e6e5ad80 | 986 | } else { |
5fafdf24 TS |
987 | if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND | |
988 | CIRRUS_BLTMODE_PATTERNCOPY)) == | |
a5082316 FB |
989 | CIRRUS_BLTMODE_COLOREXPAND) { |
990 | ||
991 | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) { | |
b30d4608 | 992 | if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) |
4c8732d7 | 993 | cirrus_bitblt_bgcol(s); |
b30d4608 | 994 | else |
4c8732d7 | 995 | cirrus_bitblt_fgcol(s); |
b30d4608 | 996 | s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; |
a5082316 FB |
997 | } else { |
998 | cirrus_bitblt_fgcol(s); | |
999 | cirrus_bitblt_bgcol(s); | |
1000 | s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; | |
1001 | } | |
e69390ce | 1002 | } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { |
b30d4608 FB |
1003 | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) { |
1004 | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) { | |
1005 | if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) | |
1006 | cirrus_bitblt_bgcol(s); | |
1007 | else | |
1008 | cirrus_bitblt_fgcol(s); | |
1009 | s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; | |
1010 | } else { | |
1011 | cirrus_bitblt_fgcol(s); | |
1012 | cirrus_bitblt_bgcol(s); | |
1013 | s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; | |
1014 | } | |
1015 | } else { | |
1016 | s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; | |
1017 | } | |
a21ae81d | 1018 | } else { |
96cf2df8 TS |
1019 | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) { |
1020 | if (s->cirrus_blt_pixelwidth > 2) { | |
1021 | printf("src transparent without colorexpand must be 8bpp or 16bpp\n"); | |
1022 | goto bitblt_ignore; | |
1023 | } | |
1024 | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) { | |
1025 | s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; | |
1026 | s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; | |
1027 | s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; | |
1028 | } else { | |
1029 | s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; | |
1030 | } | |
1031 | } else { | |
1032 | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) { | |
1033 | s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; | |
1034 | s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; | |
1035 | s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]]; | |
1036 | } else { | |
1037 | s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]]; | |
1038 | } | |
1039 | } | |
1040 | } | |
a21ae81d FB |
1041 | // setup bitblt engine. |
1042 | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) { | |
1043 | if (!cirrus_bitblt_cputovideo(s)) | |
1044 | goto bitblt_ignore; | |
1045 | } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) { | |
1046 | if (!cirrus_bitblt_videotocpu(s)) | |
1047 | goto bitblt_ignore; | |
1048 | } else { | |
1049 | if (!cirrus_bitblt_videotovideo(s)) | |
1050 | goto bitblt_ignore; | |
1051 | } | |
e6e5ad80 | 1052 | } |
e6e5ad80 FB |
1053 | return; |
1054 | bitblt_ignore:; | |
1055 | cirrus_bitblt_reset(s); | |
1056 | } | |
1057 | ||
1058 | static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value) | |
1059 | { | |
1060 | unsigned old_value; | |
1061 | ||
4e12cd94 AK |
1062 | old_value = s->vga.gr[0x31]; |
1063 | s->vga.gr[0x31] = reg_value; | |
e6e5ad80 FB |
1064 | |
1065 | if (((old_value & CIRRUS_BLT_RESET) != 0) && | |
1066 | ((reg_value & CIRRUS_BLT_RESET) == 0)) { | |
1067 | cirrus_bitblt_reset(s); | |
1068 | } else if (((old_value & CIRRUS_BLT_START) == 0) && | |
1069 | ((reg_value & CIRRUS_BLT_START) != 0)) { | |
e6e5ad80 FB |
1070 | cirrus_bitblt_start(s); |
1071 | } | |
1072 | } | |
1073 | ||
1074 | ||
1075 | /*************************************** | |
1076 | * | |
1077 | * basic parameters | |
1078 | * | |
1079 | ***************************************/ | |
1080 | ||
a4a2f59c | 1081 | static void cirrus_get_offsets(VGACommonState *s1, |
83acc96b FB |
1082 | uint32_t *pline_offset, |
1083 | uint32_t *pstart_addr, | |
1084 | uint32_t *pline_compare) | |
e6e5ad80 | 1085 | { |
4e12cd94 | 1086 | CirrusVGAState * s = container_of(s1, CirrusVGAState, vga); |
83acc96b | 1087 | uint32_t start_addr, line_offset, line_compare; |
e6e5ad80 | 1088 | |
4e12cd94 AK |
1089 | line_offset = s->vga.cr[0x13] |
1090 | | ((s->vga.cr[0x1b] & 0x10) << 4); | |
e6e5ad80 FB |
1091 | line_offset <<= 3; |
1092 | *pline_offset = line_offset; | |
1093 | ||
4e12cd94 AK |
1094 | start_addr = (s->vga.cr[0x0c] << 8) |
1095 | | s->vga.cr[0x0d] | |
1096 | | ((s->vga.cr[0x1b] & 0x01) << 16) | |
1097 | | ((s->vga.cr[0x1b] & 0x0c) << 15) | |
1098 | | ((s->vga.cr[0x1d] & 0x80) << 12); | |
e6e5ad80 | 1099 | *pstart_addr = start_addr; |
83acc96b | 1100 | |
4e12cd94 AK |
1101 | line_compare = s->vga.cr[0x18] | |
1102 | ((s->vga.cr[0x07] & 0x10) << 4) | | |
1103 | ((s->vga.cr[0x09] & 0x40) << 3); | |
83acc96b | 1104 | *pline_compare = line_compare; |
e6e5ad80 FB |
1105 | } |
1106 | ||
1107 | static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s) | |
1108 | { | |
1109 | uint32_t ret = 16; | |
1110 | ||
1111 | switch (s->cirrus_hidden_dac_data & 0xf) { | |
1112 | case 0: | |
1113 | ret = 15; | |
1114 | break; /* Sierra HiColor */ | |
1115 | case 1: | |
1116 | ret = 16; | |
1117 | break; /* XGA HiColor */ | |
1118 | default: | |
1119 | #ifdef DEBUG_CIRRUS | |
1120 | printf("cirrus: invalid DAC value %x in 16bpp\n", | |
1121 | (s->cirrus_hidden_dac_data & 0xf)); | |
1122 | #endif | |
1123 | ret = 15; /* XXX */ | |
1124 | break; | |
1125 | } | |
1126 | return ret; | |
1127 | } | |
1128 | ||
a4a2f59c | 1129 | static int cirrus_get_bpp(VGACommonState *s1) |
e6e5ad80 | 1130 | { |
4e12cd94 | 1131 | CirrusVGAState * s = container_of(s1, CirrusVGAState, vga); |
e6e5ad80 FB |
1132 | uint32_t ret = 8; |
1133 | ||
4e12cd94 | 1134 | if ((s->vga.sr[0x07] & 0x01) != 0) { |
e6e5ad80 | 1135 | /* Cirrus SVGA */ |
4e12cd94 | 1136 | switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) { |
e6e5ad80 FB |
1137 | case CIRRUS_SR7_BPP_8: |
1138 | ret = 8; | |
1139 | break; | |
1140 | case CIRRUS_SR7_BPP_16_DOUBLEVCLK: | |
1141 | ret = cirrus_get_bpp16_depth(s); | |
1142 | break; | |
1143 | case CIRRUS_SR7_BPP_24: | |
1144 | ret = 24; | |
1145 | break; | |
1146 | case CIRRUS_SR7_BPP_16: | |
1147 | ret = cirrus_get_bpp16_depth(s); | |
1148 | break; | |
1149 | case CIRRUS_SR7_BPP_32: | |
1150 | ret = 32; | |
1151 | break; | |
1152 | default: | |
1153 | #ifdef DEBUG_CIRRUS | |
4e12cd94 | 1154 | printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]); |
e6e5ad80 FB |
1155 | #endif |
1156 | ret = 8; | |
1157 | break; | |
1158 | } | |
1159 | } else { | |
1160 | /* VGA */ | |
aeb3c85f | 1161 | ret = 0; |
e6e5ad80 FB |
1162 | } |
1163 | ||
1164 | return ret; | |
1165 | } | |
1166 | ||
a4a2f59c | 1167 | static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight) |
78e127ef FB |
1168 | { |
1169 | int width, height; | |
3b46e624 | 1170 | |
78e127ef | 1171 | width = (s->cr[0x01] + 1) * 8; |
5fafdf24 TS |
1172 | height = s->cr[0x12] | |
1173 | ((s->cr[0x07] & 0x02) << 7) | | |
78e127ef FB |
1174 | ((s->cr[0x07] & 0x40) << 3); |
1175 | height = (height + 1); | |
1176 | /* interlace support */ | |
1177 | if (s->cr[0x1a] & 0x01) | |
1178 | height = height * 2; | |
1179 | *pwidth = width; | |
1180 | *pheight = height; | |
1181 | } | |
1182 | ||
e6e5ad80 FB |
1183 | /*************************************** |
1184 | * | |
1185 | * bank memory | |
1186 | * | |
1187 | ***************************************/ | |
1188 | ||
1189 | static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index) | |
1190 | { | |
1191 | unsigned offset; | |
1192 | unsigned limit; | |
1193 | ||
4e12cd94 AK |
1194 | if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */ |
1195 | offset = s->vga.gr[0x09 + bank_index]; | |
e6e5ad80 | 1196 | else /* single bank */ |
4e12cd94 | 1197 | offset = s->vga.gr[0x09]; |
e6e5ad80 | 1198 | |
4e12cd94 | 1199 | if ((s->vga.gr[0x0b] & 0x20) != 0) |
e6e5ad80 FB |
1200 | offset <<= 14; |
1201 | else | |
1202 | offset <<= 12; | |
1203 | ||
e3a4e4b6 | 1204 | if (s->real_vram_size <= offset) |
e6e5ad80 FB |
1205 | limit = 0; |
1206 | else | |
e3a4e4b6 | 1207 | limit = s->real_vram_size - offset; |
e6e5ad80 | 1208 | |
4e12cd94 | 1209 | if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) { |
e6e5ad80 FB |
1210 | if (limit > 0x8000) { |
1211 | offset += 0x8000; | |
1212 | limit -= 0x8000; | |
1213 | } else { | |
1214 | limit = 0; | |
1215 | } | |
1216 | } | |
1217 | ||
1218 | if (limit > 0) { | |
2bec46dc AL |
1219 | /* Thinking about changing bank base? First, drop the dirty bitmap information |
1220 | * on the current location, otherwise we lose this pointer forever */ | |
4e12cd94 | 1221 | if (s->vga.lfb_vram_mapped) { |
2bec46dc AL |
1222 | target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000; |
1223 | cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000); | |
1224 | } | |
e6e5ad80 FB |
1225 | s->cirrus_bank_base[bank_index] = offset; |
1226 | s->cirrus_bank_limit[bank_index] = limit; | |
1227 | } else { | |
1228 | s->cirrus_bank_base[bank_index] = 0; | |
1229 | s->cirrus_bank_limit[bank_index] = 0; | |
1230 | } | |
1231 | } | |
1232 | ||
1233 | /*************************************** | |
1234 | * | |
1235 | * I/O access between 0x3c4-0x3c5 | |
1236 | * | |
1237 | ***************************************/ | |
1238 | ||
8a82c322 | 1239 | static int cirrus_vga_read_sr(CirrusVGAState * s) |
e6e5ad80 | 1240 | { |
8a82c322 | 1241 | switch (s->vga.sr_index) { |
e6e5ad80 FB |
1242 | case 0x00: // Standard VGA |
1243 | case 0x01: // Standard VGA | |
1244 | case 0x02: // Standard VGA | |
1245 | case 0x03: // Standard VGA | |
1246 | case 0x04: // Standard VGA | |
8a82c322 | 1247 | return s->vga.sr[s->vga.sr_index]; |
e6e5ad80 | 1248 | case 0x06: // Unlock Cirrus extensions |
8a82c322 | 1249 | return s->vga.sr[s->vga.sr_index]; |
e6e5ad80 FB |
1250 | case 0x10: |
1251 | case 0x30: | |
1252 | case 0x50: | |
1253 | case 0x70: // Graphics Cursor X | |
1254 | case 0x90: | |
1255 | case 0xb0: | |
1256 | case 0xd0: | |
1257 | case 0xf0: // Graphics Cursor X | |
8a82c322 | 1258 | return s->vga.sr[0x10]; |
e6e5ad80 FB |
1259 | case 0x11: |
1260 | case 0x31: | |
1261 | case 0x51: | |
1262 | case 0x71: // Graphics Cursor Y | |
1263 | case 0x91: | |
1264 | case 0xb1: | |
1265 | case 0xd1: | |
a5082316 | 1266 | case 0xf1: // Graphics Cursor Y |
8a82c322 | 1267 | return s->vga.sr[0x11]; |
aeb3c85f FB |
1268 | case 0x05: // ??? |
1269 | case 0x07: // Extended Sequencer Mode | |
1270 | case 0x08: // EEPROM Control | |
1271 | case 0x09: // Scratch Register 0 | |
1272 | case 0x0a: // Scratch Register 1 | |
1273 | case 0x0b: // VCLK 0 | |
1274 | case 0x0c: // VCLK 1 | |
1275 | case 0x0d: // VCLK 2 | |
1276 | case 0x0e: // VCLK 3 | |
1277 | case 0x0f: // DRAM Control | |
e6e5ad80 FB |
1278 | case 0x12: // Graphics Cursor Attribute |
1279 | case 0x13: // Graphics Cursor Pattern Address | |
1280 | case 0x14: // Scratch Register 2 | |
1281 | case 0x15: // Scratch Register 3 | |
1282 | case 0x16: // Performance Tuning Register | |
1283 | case 0x17: // Configuration Readback and Extended Control | |
1284 | case 0x18: // Signature Generator Control | |
1285 | case 0x19: // Signal Generator Result | |
1286 | case 0x1a: // Signal Generator Result | |
1287 | case 0x1b: // VCLK 0 Denominator & Post | |
1288 | case 0x1c: // VCLK 1 Denominator & Post | |
1289 | case 0x1d: // VCLK 2 Denominator & Post | |
1290 | case 0x1e: // VCLK 3 Denominator & Post | |
1291 | case 0x1f: // BIOS Write Enable and MCLK select | |
1292 | #ifdef DEBUG_CIRRUS | |
8a82c322 | 1293 | printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index); |
e6e5ad80 | 1294 | #endif |
8a82c322 | 1295 | return s->vga.sr[s->vga.sr_index]; |
e6e5ad80 FB |
1296 | default: |
1297 | #ifdef DEBUG_CIRRUS | |
8a82c322 | 1298 | printf("cirrus: inport sr_index %02x\n", s->vga.sr_index); |
e6e5ad80 | 1299 | #endif |
8a82c322 | 1300 | return 0xff; |
e6e5ad80 FB |
1301 | break; |
1302 | } | |
e6e5ad80 FB |
1303 | } |
1304 | ||
31c63201 | 1305 | static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val) |
e6e5ad80 | 1306 | { |
31c63201 | 1307 | switch (s->vga.sr_index) { |
e6e5ad80 FB |
1308 | case 0x00: // Standard VGA |
1309 | case 0x01: // Standard VGA | |
1310 | case 0x02: // Standard VGA | |
1311 | case 0x03: // Standard VGA | |
1312 | case 0x04: // Standard VGA | |
31c63201 JQ |
1313 | s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index]; |
1314 | if (s->vga.sr_index == 1) | |
1315 | s->vga.update_retrace_info(&s->vga); | |
1316 | break; | |
e6e5ad80 | 1317 | case 0x06: // Unlock Cirrus extensions |
31c63201 JQ |
1318 | val &= 0x17; |
1319 | if (val == 0x12) { | |
1320 | s->vga.sr[s->vga.sr_index] = 0x12; | |
e6e5ad80 | 1321 | } else { |
31c63201 | 1322 | s->vga.sr[s->vga.sr_index] = 0x0f; |
e6e5ad80 FB |
1323 | } |
1324 | break; | |
1325 | case 0x10: | |
1326 | case 0x30: | |
1327 | case 0x50: | |
1328 | case 0x70: // Graphics Cursor X | |
1329 | case 0x90: | |
1330 | case 0xb0: | |
1331 | case 0xd0: | |
1332 | case 0xf0: // Graphics Cursor X | |
31c63201 JQ |
1333 | s->vga.sr[0x10] = val; |
1334 | s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5); | |
e6e5ad80 FB |
1335 | break; |
1336 | case 0x11: | |
1337 | case 0x31: | |
1338 | case 0x51: | |
1339 | case 0x71: // Graphics Cursor Y | |
1340 | case 0x91: | |
1341 | case 0xb1: | |
1342 | case 0xd1: | |
1343 | case 0xf1: // Graphics Cursor Y | |
31c63201 JQ |
1344 | s->vga.sr[0x11] = val; |
1345 | s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5); | |
e6e5ad80 FB |
1346 | break; |
1347 | case 0x07: // Extended Sequencer Mode | |
2bec46dc | 1348 | cirrus_update_memory_access(s); |
e6e5ad80 FB |
1349 | case 0x08: // EEPROM Control |
1350 | case 0x09: // Scratch Register 0 | |
1351 | case 0x0a: // Scratch Register 1 | |
1352 | case 0x0b: // VCLK 0 | |
1353 | case 0x0c: // VCLK 1 | |
1354 | case 0x0d: // VCLK 2 | |
1355 | case 0x0e: // VCLK 3 | |
1356 | case 0x0f: // DRAM Control | |
1357 | case 0x12: // Graphics Cursor Attribute | |
1358 | case 0x13: // Graphics Cursor Pattern Address | |
1359 | case 0x14: // Scratch Register 2 | |
1360 | case 0x15: // Scratch Register 3 | |
1361 | case 0x16: // Performance Tuning Register | |
e6e5ad80 FB |
1362 | case 0x18: // Signature Generator Control |
1363 | case 0x19: // Signature Generator Result | |
1364 | case 0x1a: // Signature Generator Result | |
1365 | case 0x1b: // VCLK 0 Denominator & Post | |
1366 | case 0x1c: // VCLK 1 Denominator & Post | |
1367 | case 0x1d: // VCLK 2 Denominator & Post | |
1368 | case 0x1e: // VCLK 3 Denominator & Post | |
1369 | case 0x1f: // BIOS Write Enable and MCLK select | |
31c63201 | 1370 | s->vga.sr[s->vga.sr_index] = val; |
e6e5ad80 FB |
1371 | #ifdef DEBUG_CIRRUS |
1372 | printf("cirrus: handled outport sr_index %02x, sr_value %02x\n", | |
31c63201 | 1373 | s->vga.sr_index, val); |
e6e5ad80 FB |
1374 | #endif |
1375 | break; | |
8926b517 | 1376 | case 0x17: // Configuration Readback and Extended Control |
31c63201 JQ |
1377 | s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38) |
1378 | | (val & 0xc7); | |
8926b517 FB |
1379 | cirrus_update_memory_access(s); |
1380 | break; | |
e6e5ad80 FB |
1381 | default: |
1382 | #ifdef DEBUG_CIRRUS | |
31c63201 JQ |
1383 | printf("cirrus: outport sr_index %02x, sr_value %02x\n", |
1384 | s->vga.sr_index, val); | |
e6e5ad80 FB |
1385 | #endif |
1386 | break; | |
1387 | } | |
e6e5ad80 FB |
1388 | } |
1389 | ||
1390 | /*************************************** | |
1391 | * | |
1392 | * I/O access at 0x3c6 | |
1393 | * | |
1394 | ***************************************/ | |
1395 | ||
957c9db5 | 1396 | static int cirrus_read_hidden_dac(CirrusVGAState * s) |
e6e5ad80 | 1397 | { |
a21ae81d | 1398 | if (++s->cirrus_hidden_dac_lockindex == 5) { |
957c9db5 JQ |
1399 | s->cirrus_hidden_dac_lockindex = 0; |
1400 | return s->cirrus_hidden_dac_data; | |
e6e5ad80 | 1401 | } |
957c9db5 | 1402 | return 0xff; |
e6e5ad80 FB |
1403 | } |
1404 | ||
1405 | static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value) | |
1406 | { | |
1407 | if (s->cirrus_hidden_dac_lockindex == 4) { | |
1408 | s->cirrus_hidden_dac_data = reg_value; | |
a21ae81d | 1409 | #if defined(DEBUG_CIRRUS) |
e6e5ad80 FB |
1410 | printf("cirrus: outport hidden DAC, value %02x\n", reg_value); |
1411 | #endif | |
1412 | } | |
1413 | s->cirrus_hidden_dac_lockindex = 0; | |
1414 | } | |
1415 | ||
1416 | /*************************************** | |
1417 | * | |
1418 | * I/O access at 0x3c9 | |
1419 | * | |
1420 | ***************************************/ | |
1421 | ||
5deaeee3 | 1422 | static int cirrus_vga_read_palette(CirrusVGAState * s) |
e6e5ad80 | 1423 | { |
5deaeee3 JQ |
1424 | int val; |
1425 | ||
1426 | if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) { | |
1427 | val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 + | |
1428 | s->vga.dac_sub_index]; | |
1429 | } else { | |
1430 | val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index]; | |
1431 | } | |
4e12cd94 AK |
1432 | if (++s->vga.dac_sub_index == 3) { |
1433 | s->vga.dac_sub_index = 0; | |
1434 | s->vga.dac_read_index++; | |
e6e5ad80 | 1435 | } |
5deaeee3 | 1436 | return val; |
e6e5ad80 FB |
1437 | } |
1438 | ||
1439 | static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value) | |
1440 | { | |
4e12cd94 | 1441 | if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) |
e6e5ad80 | 1442 | return CIRRUS_HOOK_NOT_HANDLED; |
4e12cd94 AK |
1443 | s->vga.dac_cache[s->vga.dac_sub_index] = reg_value; |
1444 | if (++s->vga.dac_sub_index == 3) { | |
1445 | memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3], | |
1446 | s->vga.dac_cache, 3); | |
a5082316 | 1447 | /* XXX update cursor */ |
4e12cd94 AK |
1448 | s->vga.dac_sub_index = 0; |
1449 | s->vga.dac_write_index++; | |
e6e5ad80 FB |
1450 | } |
1451 | return CIRRUS_HOOK_HANDLED; | |
1452 | } | |
1453 | ||
1454 | /*************************************** | |
1455 | * | |
1456 | * I/O access between 0x3ce-0x3cf | |
1457 | * | |
1458 | ***************************************/ | |
1459 | ||
1460 | static int | |
1461 | cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value) | |
1462 | { | |
1463 | switch (reg_index) { | |
aeb3c85f FB |
1464 | case 0x00: // Standard VGA, BGCOLOR 0x000000ff |
1465 | *reg_value = s->cirrus_shadow_gr0; | |
1466 | return CIRRUS_HOOK_HANDLED; | |
1467 | case 0x01: // Standard VGA, FGCOLOR 0x000000ff | |
1468 | *reg_value = s->cirrus_shadow_gr1; | |
1469 | return CIRRUS_HOOK_HANDLED; | |
e6e5ad80 FB |
1470 | case 0x02: // Standard VGA |
1471 | case 0x03: // Standard VGA | |
1472 | case 0x04: // Standard VGA | |
1473 | case 0x06: // Standard VGA | |
1474 | case 0x07: // Standard VGA | |
1475 | case 0x08: // Standard VGA | |
1476 | return CIRRUS_HOOK_NOT_HANDLED; | |
1477 | case 0x05: // Standard VGA, Cirrus extended mode | |
1478 | default: | |
1479 | break; | |
1480 | } | |
1481 | ||
1482 | if (reg_index < 0x3a) { | |
4e12cd94 | 1483 | *reg_value = s->vga.gr[reg_index]; |
e6e5ad80 FB |
1484 | } else { |
1485 | #ifdef DEBUG_CIRRUS | |
1486 | printf("cirrus: inport gr_index %02x\n", reg_index); | |
1487 | #endif | |
1488 | *reg_value = 0xff; | |
1489 | } | |
1490 | ||
1491 | return CIRRUS_HOOK_HANDLED; | |
1492 | } | |
1493 | ||
1494 | static int | |
1495 | cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value) | |
1496 | { | |
a5082316 FB |
1497 | #if defined(DEBUG_BITBLT) && 0 |
1498 | printf("gr%02x: %02x\n", reg_index, reg_value); | |
1499 | #endif | |
e6e5ad80 FB |
1500 | switch (reg_index) { |
1501 | case 0x00: // Standard VGA, BGCOLOR 0x000000ff | |
aeb3c85f | 1502 | s->cirrus_shadow_gr0 = reg_value; |
e6e5ad80 FB |
1503 | return CIRRUS_HOOK_NOT_HANDLED; |
1504 | case 0x01: // Standard VGA, FGCOLOR 0x000000ff | |
aeb3c85f | 1505 | s->cirrus_shadow_gr1 = reg_value; |
e6e5ad80 FB |
1506 | return CIRRUS_HOOK_NOT_HANDLED; |
1507 | case 0x02: // Standard VGA | |
1508 | case 0x03: // Standard VGA | |
1509 | case 0x04: // Standard VGA | |
1510 | case 0x06: // Standard VGA | |
1511 | case 0x07: // Standard VGA | |
1512 | case 0x08: // Standard VGA | |
1513 | return CIRRUS_HOOK_NOT_HANDLED; | |
1514 | case 0x05: // Standard VGA, Cirrus extended mode | |
4e12cd94 | 1515 | s->vga.gr[reg_index] = reg_value & 0x7f; |
8926b517 | 1516 | cirrus_update_memory_access(s); |
e6e5ad80 FB |
1517 | break; |
1518 | case 0x09: // bank offset #0 | |
1519 | case 0x0A: // bank offset #1 | |
4e12cd94 | 1520 | s->vga.gr[reg_index] = reg_value; |
8926b517 FB |
1521 | cirrus_update_bank_ptr(s, 0); |
1522 | cirrus_update_bank_ptr(s, 1); | |
2bec46dc | 1523 | cirrus_update_memory_access(s); |
8926b517 | 1524 | break; |
e6e5ad80 | 1525 | case 0x0B: |
4e12cd94 | 1526 | s->vga.gr[reg_index] = reg_value; |
e6e5ad80 FB |
1527 | cirrus_update_bank_ptr(s, 0); |
1528 | cirrus_update_bank_ptr(s, 1); | |
8926b517 | 1529 | cirrus_update_memory_access(s); |
e6e5ad80 FB |
1530 | break; |
1531 | case 0x10: // BGCOLOR 0x0000ff00 | |
1532 | case 0x11: // FGCOLOR 0x0000ff00 | |
1533 | case 0x12: // BGCOLOR 0x00ff0000 | |
1534 | case 0x13: // FGCOLOR 0x00ff0000 | |
1535 | case 0x14: // BGCOLOR 0xff000000 | |
1536 | case 0x15: // FGCOLOR 0xff000000 | |
1537 | case 0x20: // BLT WIDTH 0x0000ff | |
1538 | case 0x22: // BLT HEIGHT 0x0000ff | |
1539 | case 0x24: // BLT DEST PITCH 0x0000ff | |
1540 | case 0x26: // BLT SRC PITCH 0x0000ff | |
1541 | case 0x28: // BLT DEST ADDR 0x0000ff | |
1542 | case 0x29: // BLT DEST ADDR 0x00ff00 | |
1543 | case 0x2c: // BLT SRC ADDR 0x0000ff | |
1544 | case 0x2d: // BLT SRC ADDR 0x00ff00 | |
a5082316 | 1545 | case 0x2f: // BLT WRITEMASK |
e6e5ad80 FB |
1546 | case 0x30: // BLT MODE |
1547 | case 0x32: // RASTER OP | |
a21ae81d | 1548 | case 0x33: // BLT MODEEXT |
e6e5ad80 FB |
1549 | case 0x34: // BLT TRANSPARENT COLOR 0x00ff |
1550 | case 0x35: // BLT TRANSPARENT COLOR 0xff00 | |
1551 | case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff | |
1552 | case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00 | |
4e12cd94 | 1553 | s->vga.gr[reg_index] = reg_value; |
e6e5ad80 FB |
1554 | break; |
1555 | case 0x21: // BLT WIDTH 0x001f00 | |
1556 | case 0x23: // BLT HEIGHT 0x001f00 | |
1557 | case 0x25: // BLT DEST PITCH 0x001f00 | |
1558 | case 0x27: // BLT SRC PITCH 0x001f00 | |
4e12cd94 | 1559 | s->vga.gr[reg_index] = reg_value & 0x1f; |
e6e5ad80 FB |
1560 | break; |
1561 | case 0x2a: // BLT DEST ADDR 0x3f0000 | |
4e12cd94 | 1562 | s->vga.gr[reg_index] = reg_value & 0x3f; |
a5082316 | 1563 | /* if auto start mode, starts bit blt now */ |
4e12cd94 | 1564 | if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) { |
a5082316 FB |
1565 | cirrus_bitblt_start(s); |
1566 | } | |
1567 | break; | |
e6e5ad80 | 1568 | case 0x2e: // BLT SRC ADDR 0x3f0000 |
4e12cd94 | 1569 | s->vga.gr[reg_index] = reg_value & 0x3f; |
e6e5ad80 FB |
1570 | break; |
1571 | case 0x31: // BLT STATUS/START | |
1572 | cirrus_write_bitblt(s, reg_value); | |
1573 | break; | |
1574 | default: | |
1575 | #ifdef DEBUG_CIRRUS | |
1576 | printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index, | |
1577 | reg_value); | |
1578 | #endif | |
1579 | break; | |
1580 | } | |
1581 | ||
1582 | return CIRRUS_HOOK_HANDLED; | |
1583 | } | |
1584 | ||
1585 | /*************************************** | |
1586 | * | |
1587 | * I/O access between 0x3d4-0x3d5 | |
1588 | * | |
1589 | ***************************************/ | |
1590 | ||
1591 | static int | |
1592 | cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value) | |
1593 | { | |
1594 | switch (reg_index) { | |
1595 | case 0x00: // Standard VGA | |
1596 | case 0x01: // Standard VGA | |
1597 | case 0x02: // Standard VGA | |
1598 | case 0x03: // Standard VGA | |
1599 | case 0x04: // Standard VGA | |
1600 | case 0x05: // Standard VGA | |
1601 | case 0x06: // Standard VGA | |
1602 | case 0x07: // Standard VGA | |
1603 | case 0x08: // Standard VGA | |
1604 | case 0x09: // Standard VGA | |
1605 | case 0x0a: // Standard VGA | |
1606 | case 0x0b: // Standard VGA | |
1607 | case 0x0c: // Standard VGA | |
1608 | case 0x0d: // Standard VGA | |
1609 | case 0x0e: // Standard VGA | |
1610 | case 0x0f: // Standard VGA | |
1611 | case 0x10: // Standard VGA | |
1612 | case 0x11: // Standard VGA | |
1613 | case 0x12: // Standard VGA | |
1614 | case 0x13: // Standard VGA | |
1615 | case 0x14: // Standard VGA | |
1616 | case 0x15: // Standard VGA | |
1617 | case 0x16: // Standard VGA | |
1618 | case 0x17: // Standard VGA | |
1619 | case 0x18: // Standard VGA | |
1620 | return CIRRUS_HOOK_NOT_HANDLED; | |
ca896ef3 | 1621 | case 0x24: // Attribute Controller Toggle Readback (R) |
4e12cd94 | 1622 | *reg_value = (s->vga.ar_flip_flop << 7); |
ca896ef3 | 1623 | break; |
e6e5ad80 FB |
1624 | case 0x19: // Interlace End |
1625 | case 0x1a: // Miscellaneous Control | |
1626 | case 0x1b: // Extended Display Control | |
1627 | case 0x1c: // Sync Adjust and Genlock | |
1628 | case 0x1d: // Overlay Extended Control | |
1629 | case 0x22: // Graphics Data Latches Readback (R) | |
e6e5ad80 FB |
1630 | case 0x25: // Part Status |
1631 | case 0x27: // Part ID (R) | |
4e12cd94 | 1632 | *reg_value = s->vga.cr[reg_index]; |
e6e5ad80 FB |
1633 | break; |
1634 | case 0x26: // Attribute Controller Index Readback (R) | |
4e12cd94 | 1635 | *reg_value = s->vga.ar_index & 0x3f; |
e6e5ad80 FB |
1636 | break; |
1637 | default: | |
1638 | #ifdef DEBUG_CIRRUS | |
1639 | printf("cirrus: inport cr_index %02x\n", reg_index); | |
1640 | *reg_value = 0xff; | |
1641 | #endif | |
1642 | break; | |
1643 | } | |
1644 | ||
1645 | return CIRRUS_HOOK_HANDLED; | |
1646 | } | |
1647 | ||
1648 | static int | |
1649 | cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value) | |
1650 | { | |
1651 | switch (reg_index) { | |
1652 | case 0x00: // Standard VGA | |
1653 | case 0x01: // Standard VGA | |
1654 | case 0x02: // Standard VGA | |
1655 | case 0x03: // Standard VGA | |
1656 | case 0x04: // Standard VGA | |
1657 | case 0x05: // Standard VGA | |
1658 | case 0x06: // Standard VGA | |
1659 | case 0x07: // Standard VGA | |
1660 | case 0x08: // Standard VGA | |
1661 | case 0x09: // Standard VGA | |
1662 | case 0x0a: // Standard VGA | |
1663 | case 0x0b: // Standard VGA | |
1664 | case 0x0c: // Standard VGA | |
1665 | case 0x0d: // Standard VGA | |
1666 | case 0x0e: // Standard VGA | |
1667 | case 0x0f: // Standard VGA | |
1668 | case 0x10: // Standard VGA | |
1669 | case 0x11: // Standard VGA | |
1670 | case 0x12: // Standard VGA | |
1671 | case 0x13: // Standard VGA | |
1672 | case 0x14: // Standard VGA | |
1673 | case 0x15: // Standard VGA | |
1674 | case 0x16: // Standard VGA | |
1675 | case 0x17: // Standard VGA | |
1676 | case 0x18: // Standard VGA | |
1677 | return CIRRUS_HOOK_NOT_HANDLED; | |
1678 | case 0x19: // Interlace End | |
1679 | case 0x1a: // Miscellaneous Control | |
1680 | case 0x1b: // Extended Display Control | |
1681 | case 0x1c: // Sync Adjust and Genlock | |
ae184e4a | 1682 | case 0x1d: // Overlay Extended Control |
4e12cd94 | 1683 | s->vga.cr[reg_index] = reg_value; |
e6e5ad80 FB |
1684 | #ifdef DEBUG_CIRRUS |
1685 | printf("cirrus: handled outport cr_index %02x, cr_value %02x\n", | |
1686 | reg_index, reg_value); | |
1687 | #endif | |
1688 | break; | |
1689 | case 0x22: // Graphics Data Latches Readback (R) | |
1690 | case 0x24: // Attribute Controller Toggle Readback (R) | |
1691 | case 0x26: // Attribute Controller Index Readback (R) | |
1692 | case 0x27: // Part ID (R) | |
1693 | break; | |
e6e5ad80 FB |
1694 | case 0x25: // Part Status |
1695 | default: | |
1696 | #ifdef DEBUG_CIRRUS | |
1697 | printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index, | |
1698 | reg_value); | |
1699 | #endif | |
1700 | break; | |
1701 | } | |
1702 | ||
1703 | return CIRRUS_HOOK_HANDLED; | |
1704 | } | |
1705 | ||
1706 | /*************************************** | |
1707 | * | |
1708 | * memory-mapped I/O (bitblt) | |
1709 | * | |
1710 | ***************************************/ | |
1711 | ||
1712 | static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address) | |
1713 | { | |
1714 | int value = 0xff; | |
1715 | ||
1716 | switch (address) { | |
1717 | case (CIRRUS_MMIO_BLTBGCOLOR + 0): | |
1718 | cirrus_hook_read_gr(s, 0x00, &value); | |
1719 | break; | |
1720 | case (CIRRUS_MMIO_BLTBGCOLOR + 1): | |
1721 | cirrus_hook_read_gr(s, 0x10, &value); | |
1722 | break; | |
1723 | case (CIRRUS_MMIO_BLTBGCOLOR + 2): | |
1724 | cirrus_hook_read_gr(s, 0x12, &value); | |
1725 | break; | |
1726 | case (CIRRUS_MMIO_BLTBGCOLOR + 3): | |
1727 | cirrus_hook_read_gr(s, 0x14, &value); | |
1728 | break; | |
1729 | case (CIRRUS_MMIO_BLTFGCOLOR + 0): | |
1730 | cirrus_hook_read_gr(s, 0x01, &value); | |
1731 | break; | |
1732 | case (CIRRUS_MMIO_BLTFGCOLOR + 1): | |
1733 | cirrus_hook_read_gr(s, 0x11, &value); | |
1734 | break; | |
1735 | case (CIRRUS_MMIO_BLTFGCOLOR + 2): | |
1736 | cirrus_hook_read_gr(s, 0x13, &value); | |
1737 | break; | |
1738 | case (CIRRUS_MMIO_BLTFGCOLOR + 3): | |
1739 | cirrus_hook_read_gr(s, 0x15, &value); | |
1740 | break; | |
1741 | case (CIRRUS_MMIO_BLTWIDTH + 0): | |
1742 | cirrus_hook_read_gr(s, 0x20, &value); | |
1743 | break; | |
1744 | case (CIRRUS_MMIO_BLTWIDTH + 1): | |
1745 | cirrus_hook_read_gr(s, 0x21, &value); | |
1746 | break; | |
1747 | case (CIRRUS_MMIO_BLTHEIGHT + 0): | |
1748 | cirrus_hook_read_gr(s, 0x22, &value); | |
1749 | break; | |
1750 | case (CIRRUS_MMIO_BLTHEIGHT + 1): | |
1751 | cirrus_hook_read_gr(s, 0x23, &value); | |
1752 | break; | |
1753 | case (CIRRUS_MMIO_BLTDESTPITCH + 0): | |
1754 | cirrus_hook_read_gr(s, 0x24, &value); | |
1755 | break; | |
1756 | case (CIRRUS_MMIO_BLTDESTPITCH + 1): | |
1757 | cirrus_hook_read_gr(s, 0x25, &value); | |
1758 | break; | |
1759 | case (CIRRUS_MMIO_BLTSRCPITCH + 0): | |
1760 | cirrus_hook_read_gr(s, 0x26, &value); | |
1761 | break; | |
1762 | case (CIRRUS_MMIO_BLTSRCPITCH + 1): | |
1763 | cirrus_hook_read_gr(s, 0x27, &value); | |
1764 | break; | |
1765 | case (CIRRUS_MMIO_BLTDESTADDR + 0): | |
1766 | cirrus_hook_read_gr(s, 0x28, &value); | |
1767 | break; | |
1768 | case (CIRRUS_MMIO_BLTDESTADDR + 1): | |
1769 | cirrus_hook_read_gr(s, 0x29, &value); | |
1770 | break; | |
1771 | case (CIRRUS_MMIO_BLTDESTADDR + 2): | |
1772 | cirrus_hook_read_gr(s, 0x2a, &value); | |
1773 | break; | |
1774 | case (CIRRUS_MMIO_BLTSRCADDR + 0): | |
1775 | cirrus_hook_read_gr(s, 0x2c, &value); | |
1776 | break; | |
1777 | case (CIRRUS_MMIO_BLTSRCADDR + 1): | |
1778 | cirrus_hook_read_gr(s, 0x2d, &value); | |
1779 | break; | |
1780 | case (CIRRUS_MMIO_BLTSRCADDR + 2): | |
1781 | cirrus_hook_read_gr(s, 0x2e, &value); | |
1782 | break; | |
1783 | case CIRRUS_MMIO_BLTWRITEMASK: | |
1784 | cirrus_hook_read_gr(s, 0x2f, &value); | |
1785 | break; | |
1786 | case CIRRUS_MMIO_BLTMODE: | |
1787 | cirrus_hook_read_gr(s, 0x30, &value); | |
1788 | break; | |
1789 | case CIRRUS_MMIO_BLTROP: | |
1790 | cirrus_hook_read_gr(s, 0x32, &value); | |
1791 | break; | |
a21ae81d FB |
1792 | case CIRRUS_MMIO_BLTMODEEXT: |
1793 | cirrus_hook_read_gr(s, 0x33, &value); | |
1794 | break; | |
e6e5ad80 FB |
1795 | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): |
1796 | cirrus_hook_read_gr(s, 0x34, &value); | |
1797 | break; | |
1798 | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): | |
1799 | cirrus_hook_read_gr(s, 0x35, &value); | |
1800 | break; | |
1801 | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): | |
1802 | cirrus_hook_read_gr(s, 0x38, &value); | |
1803 | break; | |
1804 | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): | |
1805 | cirrus_hook_read_gr(s, 0x39, &value); | |
1806 | break; | |
1807 | case CIRRUS_MMIO_BLTSTATUS: | |
1808 | cirrus_hook_read_gr(s, 0x31, &value); | |
1809 | break; | |
1810 | default: | |
1811 | #ifdef DEBUG_CIRRUS | |
1812 | printf("cirrus: mmio read - address 0x%04x\n", address); | |
1813 | #endif | |
1814 | break; | |
1815 | } | |
1816 | ||
1817 | return (uint8_t) value; | |
1818 | } | |
1819 | ||
1820 | static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address, | |
1821 | uint8_t value) | |
1822 | { | |
1823 | switch (address) { | |
1824 | case (CIRRUS_MMIO_BLTBGCOLOR + 0): | |
1825 | cirrus_hook_write_gr(s, 0x00, value); | |
1826 | break; | |
1827 | case (CIRRUS_MMIO_BLTBGCOLOR + 1): | |
1828 | cirrus_hook_write_gr(s, 0x10, value); | |
1829 | break; | |
1830 | case (CIRRUS_MMIO_BLTBGCOLOR + 2): | |
1831 | cirrus_hook_write_gr(s, 0x12, value); | |
1832 | break; | |
1833 | case (CIRRUS_MMIO_BLTBGCOLOR + 3): | |
1834 | cirrus_hook_write_gr(s, 0x14, value); | |
1835 | break; | |
1836 | case (CIRRUS_MMIO_BLTFGCOLOR + 0): | |
1837 | cirrus_hook_write_gr(s, 0x01, value); | |
1838 | break; | |
1839 | case (CIRRUS_MMIO_BLTFGCOLOR + 1): | |
1840 | cirrus_hook_write_gr(s, 0x11, value); | |
1841 | break; | |
1842 | case (CIRRUS_MMIO_BLTFGCOLOR + 2): | |
1843 | cirrus_hook_write_gr(s, 0x13, value); | |
1844 | break; | |
1845 | case (CIRRUS_MMIO_BLTFGCOLOR + 3): | |
1846 | cirrus_hook_write_gr(s, 0x15, value); | |
1847 | break; | |
1848 | case (CIRRUS_MMIO_BLTWIDTH + 0): | |
1849 | cirrus_hook_write_gr(s, 0x20, value); | |
1850 | break; | |
1851 | case (CIRRUS_MMIO_BLTWIDTH + 1): | |
1852 | cirrus_hook_write_gr(s, 0x21, value); | |
1853 | break; | |
1854 | case (CIRRUS_MMIO_BLTHEIGHT + 0): | |
1855 | cirrus_hook_write_gr(s, 0x22, value); | |
1856 | break; | |
1857 | case (CIRRUS_MMIO_BLTHEIGHT + 1): | |
1858 | cirrus_hook_write_gr(s, 0x23, value); | |
1859 | break; | |
1860 | case (CIRRUS_MMIO_BLTDESTPITCH + 0): | |
1861 | cirrus_hook_write_gr(s, 0x24, value); | |
1862 | break; | |
1863 | case (CIRRUS_MMIO_BLTDESTPITCH + 1): | |
1864 | cirrus_hook_write_gr(s, 0x25, value); | |
1865 | break; | |
1866 | case (CIRRUS_MMIO_BLTSRCPITCH + 0): | |
1867 | cirrus_hook_write_gr(s, 0x26, value); | |
1868 | break; | |
1869 | case (CIRRUS_MMIO_BLTSRCPITCH + 1): | |
1870 | cirrus_hook_write_gr(s, 0x27, value); | |
1871 | break; | |
1872 | case (CIRRUS_MMIO_BLTDESTADDR + 0): | |
1873 | cirrus_hook_write_gr(s, 0x28, value); | |
1874 | break; | |
1875 | case (CIRRUS_MMIO_BLTDESTADDR + 1): | |
1876 | cirrus_hook_write_gr(s, 0x29, value); | |
1877 | break; | |
1878 | case (CIRRUS_MMIO_BLTDESTADDR + 2): | |
1879 | cirrus_hook_write_gr(s, 0x2a, value); | |
1880 | break; | |
1881 | case (CIRRUS_MMIO_BLTDESTADDR + 3): | |
1882 | /* ignored */ | |
1883 | break; | |
1884 | case (CIRRUS_MMIO_BLTSRCADDR + 0): | |
1885 | cirrus_hook_write_gr(s, 0x2c, value); | |
1886 | break; | |
1887 | case (CIRRUS_MMIO_BLTSRCADDR + 1): | |
1888 | cirrus_hook_write_gr(s, 0x2d, value); | |
1889 | break; | |
1890 | case (CIRRUS_MMIO_BLTSRCADDR + 2): | |
1891 | cirrus_hook_write_gr(s, 0x2e, value); | |
1892 | break; | |
1893 | case CIRRUS_MMIO_BLTWRITEMASK: | |
1894 | cirrus_hook_write_gr(s, 0x2f, value); | |
1895 | break; | |
1896 | case CIRRUS_MMIO_BLTMODE: | |
1897 | cirrus_hook_write_gr(s, 0x30, value); | |
1898 | break; | |
1899 | case CIRRUS_MMIO_BLTROP: | |
1900 | cirrus_hook_write_gr(s, 0x32, value); | |
1901 | break; | |
a21ae81d FB |
1902 | case CIRRUS_MMIO_BLTMODEEXT: |
1903 | cirrus_hook_write_gr(s, 0x33, value); | |
1904 | break; | |
e6e5ad80 FB |
1905 | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): |
1906 | cirrus_hook_write_gr(s, 0x34, value); | |
1907 | break; | |
1908 | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): | |
1909 | cirrus_hook_write_gr(s, 0x35, value); | |
1910 | break; | |
1911 | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): | |
1912 | cirrus_hook_write_gr(s, 0x38, value); | |
1913 | break; | |
1914 | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): | |
1915 | cirrus_hook_write_gr(s, 0x39, value); | |
1916 | break; | |
1917 | case CIRRUS_MMIO_BLTSTATUS: | |
1918 | cirrus_hook_write_gr(s, 0x31, value); | |
1919 | break; | |
1920 | default: | |
1921 | #ifdef DEBUG_CIRRUS | |
1922 | printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n", | |
1923 | address, value); | |
1924 | #endif | |
1925 | break; | |
1926 | } | |
1927 | } | |
1928 | ||
e6e5ad80 FB |
1929 | /*************************************** |
1930 | * | |
1931 | * write mode 4/5 | |
1932 | * | |
1933 | * assume TARGET_PAGE_SIZE >= 16 | |
1934 | * | |
1935 | ***************************************/ | |
1936 | ||
1937 | static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s, | |
1938 | unsigned mode, | |
1939 | unsigned offset, | |
1940 | uint32_t mem_value) | |
1941 | { | |
1942 | int x; | |
1943 | unsigned val = mem_value; | |
1944 | uint8_t *dst; | |
1945 | ||
4e12cd94 | 1946 | dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask); |
e6e5ad80 FB |
1947 | for (x = 0; x < 8; x++) { |
1948 | if (val & 0x80) { | |
0b74ed78 | 1949 | *dst = s->cirrus_shadow_gr1; |
e6e5ad80 | 1950 | } else if (mode == 5) { |
0b74ed78 | 1951 | *dst = s->cirrus_shadow_gr0; |
e6e5ad80 FB |
1952 | } |
1953 | val <<= 1; | |
0b74ed78 | 1954 | dst++; |
e6e5ad80 | 1955 | } |
4e12cd94 AK |
1956 | cpu_physical_memory_set_dirty(s->vga.vram_offset + offset); |
1957 | cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 7); | |
e6e5ad80 FB |
1958 | } |
1959 | ||
1960 | static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, | |
1961 | unsigned mode, | |
1962 | unsigned offset, | |
1963 | uint32_t mem_value) | |
1964 | { | |
1965 | int x; | |
1966 | unsigned val = mem_value; | |
1967 | uint8_t *dst; | |
1968 | ||
4e12cd94 | 1969 | dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask); |
e6e5ad80 FB |
1970 | for (x = 0; x < 8; x++) { |
1971 | if (val & 0x80) { | |
0b74ed78 | 1972 | *dst = s->cirrus_shadow_gr1; |
4e12cd94 | 1973 | *(dst + 1) = s->vga.gr[0x11]; |
e6e5ad80 | 1974 | } else if (mode == 5) { |
0b74ed78 | 1975 | *dst = s->cirrus_shadow_gr0; |
4e12cd94 | 1976 | *(dst + 1) = s->vga.gr[0x10]; |
e6e5ad80 FB |
1977 | } |
1978 | val <<= 1; | |
0b74ed78 | 1979 | dst += 2; |
e6e5ad80 | 1980 | } |
4e12cd94 AK |
1981 | cpu_physical_memory_set_dirty(s->vga.vram_offset + offset); |
1982 | cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 15); | |
e6e5ad80 FB |
1983 | } |
1984 | ||
1985 | /*************************************** | |
1986 | * | |
1987 | * memory access between 0xa0000-0xbffff | |
1988 | * | |
1989 | ***************************************/ | |
1990 | ||
1991 | static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr) | |
1992 | { | |
1993 | CirrusVGAState *s = opaque; | |
1994 | unsigned bank_index; | |
1995 | unsigned bank_offset; | |
1996 | uint32_t val; | |
1997 | ||
4e12cd94 | 1998 | if ((s->vga.sr[0x07] & 0x01) == 0) { |
e6e5ad80 FB |
1999 | return vga_mem_readb(s, addr); |
2000 | } | |
2001 | ||
aeb3c85f FB |
2002 | addr &= 0x1ffff; |
2003 | ||
e6e5ad80 FB |
2004 | if (addr < 0x10000) { |
2005 | /* XXX handle bitblt */ | |
2006 | /* video memory */ | |
2007 | bank_index = addr >> 15; | |
2008 | bank_offset = addr & 0x7fff; | |
2009 | if (bank_offset < s->cirrus_bank_limit[bank_index]) { | |
2010 | bank_offset += s->cirrus_bank_base[bank_index]; | |
4e12cd94 | 2011 | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
e6e5ad80 | 2012 | bank_offset <<= 4; |
4e12cd94 | 2013 | } else if (s->vga.gr[0x0B] & 0x02) { |
e6e5ad80 FB |
2014 | bank_offset <<= 3; |
2015 | } | |
2016 | bank_offset &= s->cirrus_addr_mask; | |
4e12cd94 | 2017 | val = *(s->vga.vram_ptr + bank_offset); |
e6e5ad80 FB |
2018 | } else |
2019 | val = 0xff; | |
2020 | } else if (addr >= 0x18000 && addr < 0x18100) { | |
2021 | /* memory-mapped I/O */ | |
2022 | val = 0xff; | |
4e12cd94 | 2023 | if ((s->vga.sr[0x17] & 0x44) == 0x04) { |
e6e5ad80 FB |
2024 | val = cirrus_mmio_blt_read(s, addr & 0xff); |
2025 | } | |
2026 | } else { | |
2027 | val = 0xff; | |
2028 | #ifdef DEBUG_CIRRUS | |
0bf9e31a | 2029 | printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr); |
e6e5ad80 FB |
2030 | #endif |
2031 | } | |
2032 | return val; | |
2033 | } | |
2034 | ||
2035 | static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr) | |
2036 | { | |
2037 | uint32_t v; | |
2038 | #ifdef TARGET_WORDS_BIGENDIAN | |
2039 | v = cirrus_vga_mem_readb(opaque, addr) << 8; | |
2040 | v |= cirrus_vga_mem_readb(opaque, addr + 1); | |
2041 | #else | |
2042 | v = cirrus_vga_mem_readb(opaque, addr); | |
2043 | v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8; | |
2044 | #endif | |
2045 | return v; | |
2046 | } | |
2047 | ||
2048 | static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr) | |
2049 | { | |
2050 | uint32_t v; | |
2051 | #ifdef TARGET_WORDS_BIGENDIAN | |
2052 | v = cirrus_vga_mem_readb(opaque, addr) << 24; | |
2053 | v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16; | |
2054 | v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8; | |
2055 | v |= cirrus_vga_mem_readb(opaque, addr + 3); | |
2056 | #else | |
2057 | v = cirrus_vga_mem_readb(opaque, addr); | |
2058 | v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8; | |
2059 | v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16; | |
2060 | v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24; | |
2061 | #endif | |
2062 | return v; | |
2063 | } | |
2064 | ||
5fafdf24 | 2065 | static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr, |
e6e5ad80 FB |
2066 | uint32_t mem_value) |
2067 | { | |
2068 | CirrusVGAState *s = opaque; | |
2069 | unsigned bank_index; | |
2070 | unsigned bank_offset; | |
2071 | unsigned mode; | |
2072 | ||
4e12cd94 | 2073 | if ((s->vga.sr[0x07] & 0x01) == 0) { |
e6e5ad80 FB |
2074 | vga_mem_writeb(s, addr, mem_value); |
2075 | return; | |
2076 | } | |
2077 | ||
aeb3c85f FB |
2078 | addr &= 0x1ffff; |
2079 | ||
e6e5ad80 FB |
2080 | if (addr < 0x10000) { |
2081 | if (s->cirrus_srcptr != s->cirrus_srcptr_end) { | |
2082 | /* bitblt */ | |
2083 | *s->cirrus_srcptr++ = (uint8_t) mem_value; | |
a5082316 | 2084 | if (s->cirrus_srcptr >= s->cirrus_srcptr_end) { |
e6e5ad80 FB |
2085 | cirrus_bitblt_cputovideo_next(s); |
2086 | } | |
2087 | } else { | |
2088 | /* video memory */ | |
2089 | bank_index = addr >> 15; | |
2090 | bank_offset = addr & 0x7fff; | |
2091 | if (bank_offset < s->cirrus_bank_limit[bank_index]) { | |
2092 | bank_offset += s->cirrus_bank_base[bank_index]; | |
4e12cd94 | 2093 | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
e6e5ad80 | 2094 | bank_offset <<= 4; |
4e12cd94 | 2095 | } else if (s->vga.gr[0x0B] & 0x02) { |
e6e5ad80 FB |
2096 | bank_offset <<= 3; |
2097 | } | |
2098 | bank_offset &= s->cirrus_addr_mask; | |
4e12cd94 AK |
2099 | mode = s->vga.gr[0x05] & 0x7; |
2100 | if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { | |
2101 | *(s->vga.vram_ptr + bank_offset) = mem_value; | |
2102 | cpu_physical_memory_set_dirty(s->vga.vram_offset + | |
e6e5ad80 FB |
2103 | bank_offset); |
2104 | } else { | |
4e12cd94 | 2105 | if ((s->vga.gr[0x0B] & 0x14) != 0x14) { |
e6e5ad80 FB |
2106 | cirrus_mem_writeb_mode4and5_8bpp(s, mode, |
2107 | bank_offset, | |
2108 | mem_value); | |
2109 | } else { | |
2110 | cirrus_mem_writeb_mode4and5_16bpp(s, mode, | |
2111 | bank_offset, | |
2112 | mem_value); | |
2113 | } | |
2114 | } | |
2115 | } | |
2116 | } | |
2117 | } else if (addr >= 0x18000 && addr < 0x18100) { | |
2118 | /* memory-mapped I/O */ | |
4e12cd94 | 2119 | if ((s->vga.sr[0x17] & 0x44) == 0x04) { |
e6e5ad80 FB |
2120 | cirrus_mmio_blt_write(s, addr & 0xff, mem_value); |
2121 | } | |
2122 | } else { | |
2123 | #ifdef DEBUG_CIRRUS | |
0bf9e31a BS |
2124 | printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr, |
2125 | mem_value); | |
e6e5ad80 FB |
2126 | #endif |
2127 | } | |
2128 | } | |
2129 | ||
2130 | static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) | |
2131 | { | |
2132 | #ifdef TARGET_WORDS_BIGENDIAN | |
2133 | cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff); | |
2134 | cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff); | |
2135 | #else | |
2136 | cirrus_vga_mem_writeb(opaque, addr, val & 0xff); | |
2137 | cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); | |
2138 | #endif | |
2139 | } | |
2140 | ||
2141 | static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) | |
2142 | { | |
2143 | #ifdef TARGET_WORDS_BIGENDIAN | |
2144 | cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff); | |
2145 | cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff); | |
2146 | cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff); | |
2147 | cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff); | |
2148 | #else | |
2149 | cirrus_vga_mem_writeb(opaque, addr, val & 0xff); | |
2150 | cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); | |
2151 | cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff); | |
2152 | cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff); | |
2153 | #endif | |
2154 | } | |
2155 | ||
d60efc6b | 2156 | static CPUReadMemoryFunc * const cirrus_vga_mem_read[3] = { |
e6e5ad80 FB |
2157 | cirrus_vga_mem_readb, |
2158 | cirrus_vga_mem_readw, | |
2159 | cirrus_vga_mem_readl, | |
2160 | }; | |
2161 | ||
d60efc6b | 2162 | static CPUWriteMemoryFunc * const cirrus_vga_mem_write[3] = { |
e6e5ad80 FB |
2163 | cirrus_vga_mem_writeb, |
2164 | cirrus_vga_mem_writew, | |
2165 | cirrus_vga_mem_writel, | |
2166 | }; | |
2167 | ||
a5082316 FB |
2168 | /*************************************** |
2169 | * | |
2170 | * hardware cursor | |
2171 | * | |
2172 | ***************************************/ | |
2173 | ||
2174 | static inline void invalidate_cursor1(CirrusVGAState *s) | |
2175 | { | |
2176 | if (s->last_hw_cursor_size) { | |
4e12cd94 | 2177 | vga_invalidate_scanlines(&s->vga, |
a5082316 FB |
2178 | s->last_hw_cursor_y + s->last_hw_cursor_y_start, |
2179 | s->last_hw_cursor_y + s->last_hw_cursor_y_end); | |
2180 | } | |
2181 | } | |
2182 | ||
2183 | static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s) | |
2184 | { | |
2185 | const uint8_t *src; | |
2186 | uint32_t content; | |
2187 | int y, y_min, y_max; | |
2188 | ||
4e12cd94 AK |
2189 | src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024; |
2190 | if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { | |
2191 | src += (s->vga.sr[0x13] & 0x3c) * 256; | |
a5082316 FB |
2192 | y_min = 64; |
2193 | y_max = -1; | |
2194 | for(y = 0; y < 64; y++) { | |
2195 | content = ((uint32_t *)src)[0] | | |
2196 | ((uint32_t *)src)[1] | | |
2197 | ((uint32_t *)src)[2] | | |
2198 | ((uint32_t *)src)[3]; | |
2199 | if (content) { | |
2200 | if (y < y_min) | |
2201 | y_min = y; | |
2202 | if (y > y_max) | |
2203 | y_max = y; | |
2204 | } | |
2205 | src += 16; | |
2206 | } | |
2207 | } else { | |
4e12cd94 | 2208 | src += (s->vga.sr[0x13] & 0x3f) * 256; |
a5082316 FB |
2209 | y_min = 32; |
2210 | y_max = -1; | |
2211 | for(y = 0; y < 32; y++) { | |
2212 | content = ((uint32_t *)src)[0] | | |
2213 | ((uint32_t *)(src + 128))[0]; | |
2214 | if (content) { | |
2215 | if (y < y_min) | |
2216 | y_min = y; | |
2217 | if (y > y_max) | |
2218 | y_max = y; | |
2219 | } | |
2220 | src += 4; | |
2221 | } | |
2222 | } | |
2223 | if (y_min > y_max) { | |
2224 | s->last_hw_cursor_y_start = 0; | |
2225 | s->last_hw_cursor_y_end = 0; | |
2226 | } else { | |
2227 | s->last_hw_cursor_y_start = y_min; | |
2228 | s->last_hw_cursor_y_end = y_max + 1; | |
2229 | } | |
2230 | } | |
2231 | ||
2232 | /* NOTE: we do not currently handle the cursor bitmap change, so we | |
2233 | update the cursor only if it moves. */ | |
a4a2f59c | 2234 | static void cirrus_cursor_invalidate(VGACommonState *s1) |
a5082316 | 2235 | { |
4e12cd94 | 2236 | CirrusVGAState *s = container_of(s1, CirrusVGAState, vga); |
a5082316 FB |
2237 | int size; |
2238 | ||
4e12cd94 | 2239 | if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) { |
a5082316 FB |
2240 | size = 0; |
2241 | } else { | |
4e12cd94 | 2242 | if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) |
a5082316 FB |
2243 | size = 64; |
2244 | else | |
2245 | size = 32; | |
2246 | } | |
2247 | /* invalidate last cursor and new cursor if any change */ | |
2248 | if (s->last_hw_cursor_size != size || | |
2249 | s->last_hw_cursor_x != s->hw_cursor_x || | |
2250 | s->last_hw_cursor_y != s->hw_cursor_y) { | |
2251 | ||
2252 | invalidate_cursor1(s); | |
3b46e624 | 2253 | |
a5082316 FB |
2254 | s->last_hw_cursor_size = size; |
2255 | s->last_hw_cursor_x = s->hw_cursor_x; | |
2256 | s->last_hw_cursor_y = s->hw_cursor_y; | |
2257 | /* compute the real cursor min and max y */ | |
2258 | cirrus_cursor_compute_yrange(s); | |
2259 | invalidate_cursor1(s); | |
2260 | } | |
2261 | } | |
2262 | ||
a4a2f59c | 2263 | static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y) |
a5082316 | 2264 | { |
4e12cd94 | 2265 | CirrusVGAState *s = container_of(s1, CirrusVGAState, vga); |
a5082316 FB |
2266 | int w, h, bpp, x1, x2, poffset; |
2267 | unsigned int color0, color1; | |
2268 | const uint8_t *palette, *src; | |
2269 | uint32_t content; | |
3b46e624 | 2270 | |
4e12cd94 | 2271 | if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) |
a5082316 FB |
2272 | return; |
2273 | /* fast test to see if the cursor intersects with the scan line */ | |
4e12cd94 | 2274 | if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { |
a5082316 FB |
2275 | h = 64; |
2276 | } else { | |
2277 | h = 32; | |
2278 | } | |
2279 | if (scr_y < s->hw_cursor_y || | |
2280 | scr_y >= (s->hw_cursor_y + h)) | |
2281 | return; | |
3b46e624 | 2282 | |
4e12cd94 AK |
2283 | src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024; |
2284 | if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { | |
2285 | src += (s->vga.sr[0x13] & 0x3c) * 256; | |
a5082316 FB |
2286 | src += (scr_y - s->hw_cursor_y) * 16; |
2287 | poffset = 8; | |
2288 | content = ((uint32_t *)src)[0] | | |
2289 | ((uint32_t *)src)[1] | | |
2290 | ((uint32_t *)src)[2] | | |
2291 | ((uint32_t *)src)[3]; | |
2292 | } else { | |
4e12cd94 | 2293 | src += (s->vga.sr[0x13] & 0x3f) * 256; |
a5082316 FB |
2294 | src += (scr_y - s->hw_cursor_y) * 4; |
2295 | poffset = 128; | |
2296 | content = ((uint32_t *)src)[0] | | |
2297 | ((uint32_t *)(src + 128))[0]; | |
2298 | } | |
2299 | /* if nothing to draw, no need to continue */ | |
2300 | if (!content) | |
2301 | return; | |
2302 | w = h; | |
2303 | ||
2304 | x1 = s->hw_cursor_x; | |
4e12cd94 | 2305 | if (x1 >= s->vga.last_scr_width) |
a5082316 FB |
2306 | return; |
2307 | x2 = s->hw_cursor_x + w; | |
4e12cd94 AK |
2308 | if (x2 > s->vga.last_scr_width) |
2309 | x2 = s->vga.last_scr_width; | |
a5082316 FB |
2310 | w = x2 - x1; |
2311 | palette = s->cirrus_hidden_palette; | |
4e12cd94 AK |
2312 | color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]), |
2313 | c6_to_8(palette[0x0 * 3 + 1]), | |
2314 | c6_to_8(palette[0x0 * 3 + 2])); | |
2315 | color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]), | |
2316 | c6_to_8(palette[0xf * 3 + 1]), | |
2317 | c6_to_8(palette[0xf * 3 + 2])); | |
2318 | bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3); | |
a5082316 | 2319 | d1 += x1 * bpp; |
4e12cd94 | 2320 | switch(ds_get_bits_per_pixel(s->vga.ds)) { |
a5082316 FB |
2321 | default: |
2322 | break; | |
2323 | case 8: | |
2324 | vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff); | |
2325 | break; | |
2326 | case 15: | |
2327 | vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff); | |
2328 | break; | |
2329 | case 16: | |
2330 | vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff); | |
2331 | break; | |
2332 | case 32: | |
2333 | vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff); | |
2334 | break; | |
2335 | } | |
2336 | } | |
2337 | ||
e6e5ad80 FB |
2338 | /*************************************** |
2339 | * | |
2340 | * LFB memory access | |
2341 | * | |
2342 | ***************************************/ | |
2343 | ||
2344 | static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr) | |
2345 | { | |
e05587e8 | 2346 | CirrusVGAState *s = opaque; |
e6e5ad80 FB |
2347 | uint32_t ret; |
2348 | ||
e6e5ad80 FB |
2349 | addr &= s->cirrus_addr_mask; |
2350 | ||
4e12cd94 | 2351 | if (((s->vga.sr[0x17] & 0x44) == 0x44) && |
78e127ef | 2352 | ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { |
e6e5ad80 FB |
2353 | /* memory-mapped I/O */ |
2354 | ret = cirrus_mmio_blt_read(s, addr & 0xff); | |
2355 | } else if (0) { | |
2356 | /* XXX handle bitblt */ | |
2357 | ret = 0xff; | |
2358 | } else { | |
2359 | /* video memory */ | |
4e12cd94 | 2360 | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
e6e5ad80 | 2361 | addr <<= 4; |
4e12cd94 | 2362 | } else if (s->vga.gr[0x0B] & 0x02) { |
e6e5ad80 FB |
2363 | addr <<= 3; |
2364 | } | |
2365 | addr &= s->cirrus_addr_mask; | |
4e12cd94 | 2366 | ret = *(s->vga.vram_ptr + addr); |
e6e5ad80 FB |
2367 | } |
2368 | ||
2369 | return ret; | |
2370 | } | |
2371 | ||
2372 | static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr) | |
2373 | { | |
2374 | uint32_t v; | |
2375 | #ifdef TARGET_WORDS_BIGENDIAN | |
2376 | v = cirrus_linear_readb(opaque, addr) << 8; | |
2377 | v |= cirrus_linear_readb(opaque, addr + 1); | |
2378 | #else | |
2379 | v = cirrus_linear_readb(opaque, addr); | |
2380 | v |= cirrus_linear_readb(opaque, addr + 1) << 8; | |
2381 | #endif | |
2382 | return v; | |
2383 | } | |
2384 | ||
2385 | static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr) | |
2386 | { | |
2387 | uint32_t v; | |
2388 | #ifdef TARGET_WORDS_BIGENDIAN | |
2389 | v = cirrus_linear_readb(opaque, addr) << 24; | |
2390 | v |= cirrus_linear_readb(opaque, addr + 1) << 16; | |
2391 | v |= cirrus_linear_readb(opaque, addr + 2) << 8; | |
2392 | v |= cirrus_linear_readb(opaque, addr + 3); | |
2393 | #else | |
2394 | v = cirrus_linear_readb(opaque, addr); | |
2395 | v |= cirrus_linear_readb(opaque, addr + 1) << 8; | |
2396 | v |= cirrus_linear_readb(opaque, addr + 2) << 16; | |
2397 | v |= cirrus_linear_readb(opaque, addr + 3) << 24; | |
2398 | #endif | |
2399 | return v; | |
2400 | } | |
2401 | ||
2402 | static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr, | |
2403 | uint32_t val) | |
2404 | { | |
e05587e8 | 2405 | CirrusVGAState *s = opaque; |
e6e5ad80 FB |
2406 | unsigned mode; |
2407 | ||
2408 | addr &= s->cirrus_addr_mask; | |
3b46e624 | 2409 | |
4e12cd94 | 2410 | if (((s->vga.sr[0x17] & 0x44) == 0x44) && |
78e127ef | 2411 | ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { |
e6e5ad80 FB |
2412 | /* memory-mapped I/O */ |
2413 | cirrus_mmio_blt_write(s, addr & 0xff, val); | |
2414 | } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { | |
2415 | /* bitblt */ | |
2416 | *s->cirrus_srcptr++ = (uint8_t) val; | |
a5082316 | 2417 | if (s->cirrus_srcptr >= s->cirrus_srcptr_end) { |
e6e5ad80 FB |
2418 | cirrus_bitblt_cputovideo_next(s); |
2419 | } | |
2420 | } else { | |
2421 | /* video memory */ | |
4e12cd94 | 2422 | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
e6e5ad80 | 2423 | addr <<= 4; |
4e12cd94 | 2424 | } else if (s->vga.gr[0x0B] & 0x02) { |
e6e5ad80 FB |
2425 | addr <<= 3; |
2426 | } | |
2427 | addr &= s->cirrus_addr_mask; | |
2428 | ||
4e12cd94 AK |
2429 | mode = s->vga.gr[0x05] & 0x7; |
2430 | if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { | |
2431 | *(s->vga.vram_ptr + addr) = (uint8_t) val; | |
2432 | cpu_physical_memory_set_dirty(s->vga.vram_offset + addr); | |
e6e5ad80 | 2433 | } else { |
4e12cd94 | 2434 | if ((s->vga.gr[0x0B] & 0x14) != 0x14) { |
e6e5ad80 FB |
2435 | cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val); |
2436 | } else { | |
2437 | cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val); | |
2438 | } | |
2439 | } | |
2440 | } | |
2441 | } | |
2442 | ||
2443 | static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr, | |
2444 | uint32_t val) | |
2445 | { | |
2446 | #ifdef TARGET_WORDS_BIGENDIAN | |
2447 | cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff); | |
2448 | cirrus_linear_writeb(opaque, addr + 1, val & 0xff); | |
2449 | #else | |
2450 | cirrus_linear_writeb(opaque, addr, val & 0xff); | |
2451 | cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff); | |
2452 | #endif | |
2453 | } | |
2454 | ||
2455 | static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr, | |
2456 | uint32_t val) | |
2457 | { | |
2458 | #ifdef TARGET_WORDS_BIGENDIAN | |
2459 | cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff); | |
2460 | cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff); | |
2461 | cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff); | |
2462 | cirrus_linear_writeb(opaque, addr + 3, val & 0xff); | |
2463 | #else | |
2464 | cirrus_linear_writeb(opaque, addr, val & 0xff); | |
2465 | cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff); | |
2466 | cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff); | |
2467 | cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff); | |
2468 | #endif | |
2469 | } | |
2470 | ||
2471 | ||
d60efc6b | 2472 | static CPUReadMemoryFunc * const cirrus_linear_read[3] = { |
e6e5ad80 FB |
2473 | cirrus_linear_readb, |
2474 | cirrus_linear_readw, | |
2475 | cirrus_linear_readl, | |
2476 | }; | |
2477 | ||
d60efc6b | 2478 | static CPUWriteMemoryFunc * const cirrus_linear_write[3] = { |
e6e5ad80 FB |
2479 | cirrus_linear_writeb, |
2480 | cirrus_linear_writew, | |
2481 | cirrus_linear_writel, | |
2482 | }; | |
2483 | ||
a5082316 FB |
2484 | /*************************************** |
2485 | * | |
2486 | * system to screen memory access | |
2487 | * | |
2488 | ***************************************/ | |
2489 | ||
2490 | ||
2491 | static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr) | |
2492 | { | |
2493 | uint32_t ret; | |
2494 | ||
2495 | /* XXX handle bitblt */ | |
2496 | ret = 0xff; | |
2497 | return ret; | |
2498 | } | |
2499 | ||
2500 | static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr) | |
2501 | { | |
2502 | uint32_t v; | |
2503 | #ifdef TARGET_WORDS_BIGENDIAN | |
2504 | v = cirrus_linear_bitblt_readb(opaque, addr) << 8; | |
2505 | v |= cirrus_linear_bitblt_readb(opaque, addr + 1); | |
2506 | #else | |
2507 | v = cirrus_linear_bitblt_readb(opaque, addr); | |
2508 | v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8; | |
2509 | #endif | |
2510 | return v; | |
2511 | } | |
2512 | ||
2513 | static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr) | |
2514 | { | |
2515 | uint32_t v; | |
2516 | #ifdef TARGET_WORDS_BIGENDIAN | |
2517 | v = cirrus_linear_bitblt_readb(opaque, addr) << 24; | |
2518 | v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16; | |
2519 | v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8; | |
2520 | v |= cirrus_linear_bitblt_readb(opaque, addr + 3); | |
2521 | #else | |
2522 | v = cirrus_linear_bitblt_readb(opaque, addr); | |
2523 | v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8; | |
2524 | v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16; | |
2525 | v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24; | |
2526 | #endif | |
2527 | return v; | |
2528 | } | |
2529 | ||
2530 | static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr, | |
2531 | uint32_t val) | |
2532 | { | |
e05587e8 | 2533 | CirrusVGAState *s = opaque; |
a5082316 FB |
2534 | |
2535 | if (s->cirrus_srcptr != s->cirrus_srcptr_end) { | |
2536 | /* bitblt */ | |
2537 | *s->cirrus_srcptr++ = (uint8_t) val; | |
2538 | if (s->cirrus_srcptr >= s->cirrus_srcptr_end) { | |
2539 | cirrus_bitblt_cputovideo_next(s); | |
2540 | } | |
2541 | } | |
2542 | } | |
2543 | ||
2544 | static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr, | |
2545 | uint32_t val) | |
2546 | { | |
2547 | #ifdef TARGET_WORDS_BIGENDIAN | |
2548 | cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff); | |
2549 | cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff); | |
2550 | #else | |
2551 | cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff); | |
2552 | cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff); | |
2553 | #endif | |
2554 | } | |
2555 | ||
2556 | static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr, | |
2557 | uint32_t val) | |
2558 | { | |
2559 | #ifdef TARGET_WORDS_BIGENDIAN | |
2560 | cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff); | |
2561 | cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff); | |
2562 | cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff); | |
2563 | cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff); | |
2564 | #else | |
2565 | cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff); | |
2566 | cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff); | |
2567 | cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff); | |
2568 | cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff); | |
2569 | #endif | |
2570 | } | |
2571 | ||
2572 | ||
d60efc6b | 2573 | static CPUReadMemoryFunc * const cirrus_linear_bitblt_read[3] = { |
a5082316 FB |
2574 | cirrus_linear_bitblt_readb, |
2575 | cirrus_linear_bitblt_readw, | |
2576 | cirrus_linear_bitblt_readl, | |
2577 | }; | |
2578 | ||
d60efc6b | 2579 | static CPUWriteMemoryFunc * const cirrus_linear_bitblt_write[3] = { |
a5082316 FB |
2580 | cirrus_linear_bitblt_writeb, |
2581 | cirrus_linear_bitblt_writew, | |
2582 | cirrus_linear_bitblt_writel, | |
2583 | }; | |
2584 | ||
2bec46dc AL |
2585 | static void map_linear_vram(CirrusVGAState *s) |
2586 | { | |
4e12cd94 AK |
2587 | if (!s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) { |
2588 | s->vga.map_addr = s->vga.lfb_addr; | |
2589 | s->vga.map_end = s->vga.lfb_end; | |
2590 | cpu_register_physical_memory(s->vga.map_addr, s->vga.map_end - s->vga.map_addr, s->vga.vram_offset); | |
2bec46dc AL |
2591 | } |
2592 | ||
4e12cd94 | 2593 | if (!s->vga.map_addr) |
2bec46dc AL |
2594 | return; |
2595 | ||
4e12cd94 | 2596 | s->vga.lfb_vram_mapped = 0; |
2bec46dc AL |
2597 | |
2598 | if (!(s->cirrus_srcptr != s->cirrus_srcptr_end) | |
4e12cd94 AK |
2599 | && !((s->vga.sr[0x07] & 0x01) == 0) |
2600 | && !((s->vga.gr[0x0B] & 0x14) == 0x14) | |
2601 | && !(s->vga.gr[0x0B] & 0x02)) { | |
2bec46dc AL |
2602 | |
2603 | cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000, | |
4e12cd94 | 2604 | (s->vga.vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM); |
2bec46dc | 2605 | cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000, |
4e12cd94 | 2606 | (s->vga.vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM); |
2bec46dc | 2607 | |
4e12cd94 | 2608 | s->vga.lfb_vram_mapped = 1; |
2bec46dc AL |
2609 | } |
2610 | else { | |
7cff316e | 2611 | cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000, |
4e12cd94 | 2612 | s->vga.vga_io_memory); |
2bec46dc AL |
2613 | } |
2614 | ||
4e12cd94 | 2615 | vga_dirty_log_start(&s->vga); |
2bec46dc AL |
2616 | } |
2617 | ||
2618 | static void unmap_linear_vram(CirrusVGAState *s) | |
2619 | { | |
4e12cd94 AK |
2620 | if (s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) |
2621 | s->vga.map_addr = s->vga.map_end = 0; | |
2bec46dc AL |
2622 | |
2623 | cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000, | |
4e12cd94 | 2624 | s->vga.vga_io_memory); |
2bec46dc AL |
2625 | } |
2626 | ||
8926b517 FB |
2627 | /* Compute the memory access functions */ |
2628 | static void cirrus_update_memory_access(CirrusVGAState *s) | |
2629 | { | |
2630 | unsigned mode; | |
2631 | ||
4e12cd94 | 2632 | if ((s->vga.sr[0x17] & 0x44) == 0x44) { |
8926b517 FB |
2633 | goto generic_io; |
2634 | } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { | |
2635 | goto generic_io; | |
2636 | } else { | |
4e12cd94 | 2637 | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
8926b517 | 2638 | goto generic_io; |
4e12cd94 | 2639 | } else if (s->vga.gr[0x0B] & 0x02) { |
8926b517 FB |
2640 | goto generic_io; |
2641 | } | |
3b46e624 | 2642 | |
4e12cd94 AK |
2643 | mode = s->vga.gr[0x05] & 0x7; |
2644 | if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { | |
2bec46dc | 2645 | map_linear_vram(s); |
8926b517 FB |
2646 | } else { |
2647 | generic_io: | |
2bec46dc | 2648 | unmap_linear_vram(s); |
8926b517 FB |
2649 | } |
2650 | } | |
2651 | } | |
2652 | ||
2653 | ||
e6e5ad80 FB |
2654 | /* I/O ports */ |
2655 | ||
0ceac75b | 2656 | static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr) |
e6e5ad80 | 2657 | { |
b6343073 JQ |
2658 | CirrusVGAState *c = opaque; |
2659 | VGACommonState *s = &c->vga; | |
e6e5ad80 FB |
2660 | int val, index; |
2661 | ||
b6343073 | 2662 | if (vga_ioport_invalid(s, addr)) { |
e6e5ad80 FB |
2663 | val = 0xff; |
2664 | } else { | |
2665 | switch (addr) { | |
2666 | case 0x3c0: | |
b6343073 JQ |
2667 | if (s->ar_flip_flop == 0) { |
2668 | val = s->ar_index; | |
e6e5ad80 FB |
2669 | } else { |
2670 | val = 0; | |
2671 | } | |
2672 | break; | |
2673 | case 0x3c1: | |
b6343073 | 2674 | index = s->ar_index & 0x1f; |
e6e5ad80 | 2675 | if (index < 21) |
b6343073 | 2676 | val = s->ar[index]; |
e6e5ad80 FB |
2677 | else |
2678 | val = 0; | |
2679 | break; | |
2680 | case 0x3c2: | |
b6343073 | 2681 | val = s->st00; |
e6e5ad80 FB |
2682 | break; |
2683 | case 0x3c4: | |
b6343073 | 2684 | val = s->sr_index; |
e6e5ad80 FB |
2685 | break; |
2686 | case 0x3c5: | |
8a82c322 JQ |
2687 | val = cirrus_vga_read_sr(c); |
2688 | break; | |
e6e5ad80 | 2689 | #ifdef DEBUG_VGA_REG |
b6343073 | 2690 | printf("vga: read SR%x = 0x%02x\n", s->sr_index, val); |
e6e5ad80 FB |
2691 | #endif |
2692 | break; | |
2693 | case 0x3c6: | |
957c9db5 | 2694 | val = cirrus_read_hidden_dac(c); |
e6e5ad80 FB |
2695 | break; |
2696 | case 0x3c7: | |
b6343073 | 2697 | val = s->dac_state; |
e6e5ad80 | 2698 | break; |
ae184e4a | 2699 | case 0x3c8: |
b6343073 JQ |
2700 | val = s->dac_write_index; |
2701 | c->cirrus_hidden_dac_lockindex = 0; | |
ae184e4a FB |
2702 | break; |
2703 | case 0x3c9: | |
5deaeee3 JQ |
2704 | val = cirrus_vga_read_palette(c); |
2705 | break; | |
e6e5ad80 | 2706 | case 0x3ca: |
b6343073 | 2707 | val = s->fcr; |
e6e5ad80 FB |
2708 | break; |
2709 | case 0x3cc: | |
b6343073 | 2710 | val = s->msr; |
e6e5ad80 FB |
2711 | break; |
2712 | case 0x3ce: | |
b6343073 | 2713 | val = s->gr_index; |
e6e5ad80 FB |
2714 | break; |
2715 | case 0x3cf: | |
b6343073 | 2716 | if (cirrus_hook_read_gr(c, s->gr_index, &val)) |
e6e5ad80 | 2717 | break; |
b6343073 | 2718 | val = s->gr[s->gr_index]; |
e6e5ad80 | 2719 | #ifdef DEBUG_VGA_REG |
b6343073 | 2720 | printf("vga: read GR%x = 0x%02x\n", s->gr_index, val); |
e6e5ad80 FB |
2721 | #endif |
2722 | break; | |
2723 | case 0x3b4: | |
2724 | case 0x3d4: | |
b6343073 | 2725 | val = s->cr_index; |
e6e5ad80 FB |
2726 | break; |
2727 | case 0x3b5: | |
2728 | case 0x3d5: | |
b6343073 | 2729 | if (cirrus_hook_read_cr(c, s->cr_index, &val)) |
e6e5ad80 | 2730 | break; |
b6343073 | 2731 | val = s->cr[s->cr_index]; |
e6e5ad80 | 2732 | #ifdef DEBUG_VGA_REG |
b6343073 | 2733 | printf("vga: read CR%x = 0x%02x\n", s->cr_index, val); |
e6e5ad80 FB |
2734 | #endif |
2735 | break; | |
2736 | case 0x3ba: | |
2737 | case 0x3da: | |
2738 | /* just toggle to fool polling */ | |
b6343073 JQ |
2739 | val = s->st01 = s->retrace(s); |
2740 | s->ar_flip_flop = 0; | |
e6e5ad80 FB |
2741 | break; |
2742 | default: | |
2743 | val = 0x00; | |
2744 | break; | |
2745 | } | |
2746 | } | |
2747 | #if defined(DEBUG_VGA) | |
2748 | printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val); | |
2749 | #endif | |
2750 | return val; | |
2751 | } | |
2752 | ||
0ceac75b | 2753 | static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
e6e5ad80 | 2754 | { |
b6343073 JQ |
2755 | CirrusVGAState *c = opaque; |
2756 | VGACommonState *s = &c->vga; | |
e6e5ad80 FB |
2757 | int index; |
2758 | ||
2759 | /* check port range access depending on color/monochrome mode */ | |
b6343073 | 2760 | if (vga_ioport_invalid(s, addr)) { |
e6e5ad80 | 2761 | return; |
25a18cbd | 2762 | } |
e6e5ad80 FB |
2763 | #ifdef DEBUG_VGA |
2764 | printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val); | |
2765 | #endif | |
2766 | ||
2767 | switch (addr) { | |
2768 | case 0x3c0: | |
b6343073 | 2769 | if (s->ar_flip_flop == 0) { |
e6e5ad80 | 2770 | val &= 0x3f; |
b6343073 | 2771 | s->ar_index = val; |
e6e5ad80 | 2772 | } else { |
b6343073 | 2773 | index = s->ar_index & 0x1f; |
e6e5ad80 FB |
2774 | switch (index) { |
2775 | case 0x00 ... 0x0f: | |
b6343073 | 2776 | s->ar[index] = val & 0x3f; |
e6e5ad80 FB |
2777 | break; |
2778 | case 0x10: | |
b6343073 | 2779 | s->ar[index] = val & ~0x10; |
e6e5ad80 FB |
2780 | break; |
2781 | case 0x11: | |
b6343073 | 2782 | s->ar[index] = val; |
e6e5ad80 FB |
2783 | break; |
2784 | case 0x12: | |
b6343073 | 2785 | s->ar[index] = val & ~0xc0; |
e6e5ad80 FB |
2786 | break; |
2787 | case 0x13: | |
b6343073 | 2788 | s->ar[index] = val & ~0xf0; |
e6e5ad80 FB |
2789 | break; |
2790 | case 0x14: | |
b6343073 | 2791 | s->ar[index] = val & ~0xf0; |
e6e5ad80 FB |
2792 | break; |
2793 | default: | |
2794 | break; | |
2795 | } | |
2796 | } | |
b6343073 | 2797 | s->ar_flip_flop ^= 1; |
e6e5ad80 FB |
2798 | break; |
2799 | case 0x3c2: | |
b6343073 JQ |
2800 | s->msr = val & ~0x10; |
2801 | s->update_retrace_info(s); | |
e6e5ad80 FB |
2802 | break; |
2803 | case 0x3c4: | |
b6343073 | 2804 | s->sr_index = val; |
e6e5ad80 FB |
2805 | break; |
2806 | case 0x3c5: | |
e6e5ad80 | 2807 | #ifdef DEBUG_VGA_REG |
b6343073 | 2808 | printf("vga: write SR%x = 0x%02x\n", s->sr_index, val); |
e6e5ad80 | 2809 | #endif |
31c63201 JQ |
2810 | cirrus_vga_write_sr(c, val); |
2811 | break; | |
e6e5ad80 FB |
2812 | break; |
2813 | case 0x3c6: | |
b6343073 | 2814 | cirrus_write_hidden_dac(c, val); |
e6e5ad80 FB |
2815 | break; |
2816 | case 0x3c7: | |
b6343073 JQ |
2817 | s->dac_read_index = val; |
2818 | s->dac_sub_index = 0; | |
2819 | s->dac_state = 3; | |
e6e5ad80 FB |
2820 | break; |
2821 | case 0x3c8: | |
b6343073 JQ |
2822 | s->dac_write_index = val; |
2823 | s->dac_sub_index = 0; | |
2824 | s->dac_state = 0; | |
e6e5ad80 FB |
2825 | break; |
2826 | case 0x3c9: | |
b6343073 | 2827 | if (cirrus_hook_write_palette(c, val)) |
e6e5ad80 | 2828 | break; |
b6343073 JQ |
2829 | s->dac_cache[s->dac_sub_index] = val; |
2830 | if (++s->dac_sub_index == 3) { | |
2831 | memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3); | |
2832 | s->dac_sub_index = 0; | |
2833 | s->dac_write_index++; | |
e6e5ad80 FB |
2834 | } |
2835 | break; | |
2836 | case 0x3ce: | |
b6343073 | 2837 | s->gr_index = val; |
e6e5ad80 FB |
2838 | break; |
2839 | case 0x3cf: | |
b6343073 | 2840 | if (cirrus_hook_write_gr(c, s->gr_index, val)) |
e6e5ad80 FB |
2841 | break; |
2842 | #ifdef DEBUG_VGA_REG | |
b6343073 | 2843 | printf("vga: write GR%x = 0x%02x\n", s->gr_index, val); |
e6e5ad80 | 2844 | #endif |
b6343073 | 2845 | s->gr[s->gr_index] = val & gr_mask[s->gr_index]; |
e6e5ad80 FB |
2846 | break; |
2847 | case 0x3b4: | |
2848 | case 0x3d4: | |
b6343073 | 2849 | s->cr_index = val; |
e6e5ad80 FB |
2850 | break; |
2851 | case 0x3b5: | |
2852 | case 0x3d5: | |
b6343073 | 2853 | if (cirrus_hook_write_cr(c, s->cr_index, val)) |
e6e5ad80 FB |
2854 | break; |
2855 | #ifdef DEBUG_VGA_REG | |
b6343073 | 2856 | printf("vga: write CR%x = 0x%02x\n", s->cr_index, val); |
e6e5ad80 FB |
2857 | #endif |
2858 | /* handle CR0-7 protection */ | |
b6343073 | 2859 | if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) { |
e6e5ad80 | 2860 | /* can always write bit 4 of CR7 */ |
b6343073 JQ |
2861 | if (s->cr_index == 7) |
2862 | s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10); | |
e6e5ad80 FB |
2863 | return; |
2864 | } | |
a46007a0 | 2865 | s->cr[s->cr_index] = val; |
cb5a7aa8 | 2866 | |
b6343073 | 2867 | switch(s->cr_index) { |
cb5a7aa8 | 2868 | case 0x00: |
2869 | case 0x04: | |
2870 | case 0x05: | |
2871 | case 0x06: | |
2872 | case 0x07: | |
2873 | case 0x11: | |
2874 | case 0x17: | |
b6343073 | 2875 | s->update_retrace_info(s); |
cb5a7aa8 | 2876 | break; |
2877 | } | |
e6e5ad80 FB |
2878 | break; |
2879 | case 0x3ba: | |
2880 | case 0x3da: | |
b6343073 | 2881 | s->fcr = val & 0x10; |
e6e5ad80 FB |
2882 | break; |
2883 | } | |
2884 | } | |
2885 | ||
e36f36e1 FB |
2886 | /*************************************** |
2887 | * | |
2888 | * memory-mapped I/O access | |
2889 | * | |
2890 | ***************************************/ | |
2891 | ||
2892 | static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr) | |
2893 | { | |
e05587e8 | 2894 | CirrusVGAState *s = opaque; |
e36f36e1 FB |
2895 | |
2896 | addr &= CIRRUS_PNPMMIO_SIZE - 1; | |
2897 | ||
2898 | if (addr >= 0x100) { | |
2899 | return cirrus_mmio_blt_read(s, addr - 0x100); | |
2900 | } else { | |
0ceac75b | 2901 | return cirrus_vga_ioport_read(s, addr + 0x3c0); |
e36f36e1 FB |
2902 | } |
2903 | } | |
2904 | ||
2905 | static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr) | |
2906 | { | |
2907 | uint32_t v; | |
2908 | #ifdef TARGET_WORDS_BIGENDIAN | |
2909 | v = cirrus_mmio_readb(opaque, addr) << 8; | |
2910 | v |= cirrus_mmio_readb(opaque, addr + 1); | |
2911 | #else | |
2912 | v = cirrus_mmio_readb(opaque, addr); | |
2913 | v |= cirrus_mmio_readb(opaque, addr + 1) << 8; | |
2914 | #endif | |
2915 | return v; | |
2916 | } | |
2917 | ||
2918 | static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr) | |
2919 | { | |
2920 | uint32_t v; | |
2921 | #ifdef TARGET_WORDS_BIGENDIAN | |
2922 | v = cirrus_mmio_readb(opaque, addr) << 24; | |
2923 | v |= cirrus_mmio_readb(opaque, addr + 1) << 16; | |
2924 | v |= cirrus_mmio_readb(opaque, addr + 2) << 8; | |
2925 | v |= cirrus_mmio_readb(opaque, addr + 3); | |
2926 | #else | |
2927 | v = cirrus_mmio_readb(opaque, addr); | |
2928 | v |= cirrus_mmio_readb(opaque, addr + 1) << 8; | |
2929 | v |= cirrus_mmio_readb(opaque, addr + 2) << 16; | |
2930 | v |= cirrus_mmio_readb(opaque, addr + 3) << 24; | |
2931 | #endif | |
2932 | return v; | |
2933 | } | |
2934 | ||
2935 | static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr, | |
2936 | uint32_t val) | |
2937 | { | |
e05587e8 | 2938 | CirrusVGAState *s = opaque; |
e36f36e1 FB |
2939 | |
2940 | addr &= CIRRUS_PNPMMIO_SIZE - 1; | |
2941 | ||
2942 | if (addr >= 0x100) { | |
2943 | cirrus_mmio_blt_write(s, addr - 0x100, val); | |
2944 | } else { | |
0ceac75b | 2945 | cirrus_vga_ioport_write(s, addr + 0x3c0, val); |
e36f36e1 FB |
2946 | } |
2947 | } | |
2948 | ||
2949 | static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr, | |
2950 | uint32_t val) | |
2951 | { | |
2952 | #ifdef TARGET_WORDS_BIGENDIAN | |
2953 | cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff); | |
2954 | cirrus_mmio_writeb(opaque, addr + 1, val & 0xff); | |
2955 | #else | |
2956 | cirrus_mmio_writeb(opaque, addr, val & 0xff); | |
2957 | cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); | |
2958 | #endif | |
2959 | } | |
2960 | ||
2961 | static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr, | |
2962 | uint32_t val) | |
2963 | { | |
2964 | #ifdef TARGET_WORDS_BIGENDIAN | |
2965 | cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff); | |
2966 | cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff); | |
2967 | cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff); | |
2968 | cirrus_mmio_writeb(opaque, addr + 3, val & 0xff); | |
2969 | #else | |
2970 | cirrus_mmio_writeb(opaque, addr, val & 0xff); | |
2971 | cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); | |
2972 | cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff); | |
2973 | cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff); | |
2974 | #endif | |
2975 | } | |
2976 | ||
2977 | ||
d60efc6b | 2978 | static CPUReadMemoryFunc * const cirrus_mmio_read[3] = { |
e36f36e1 FB |
2979 | cirrus_mmio_readb, |
2980 | cirrus_mmio_readw, | |
2981 | cirrus_mmio_readl, | |
2982 | }; | |
2983 | ||
d60efc6b | 2984 | static CPUWriteMemoryFunc * const cirrus_mmio_write[3] = { |
e36f36e1 FB |
2985 | cirrus_mmio_writeb, |
2986 | cirrus_mmio_writew, | |
2987 | cirrus_mmio_writel, | |
2988 | }; | |
2989 | ||
2c6ab832 FB |
2990 | /* load/save state */ |
2991 | ||
2992 | static void cirrus_vga_save(QEMUFile *f, void *opaque) | |
2993 | { | |
2994 | CirrusVGAState *s = opaque; | |
2995 | ||
4e12cd94 AK |
2996 | qemu_put_be32s(f, &s->vga.latch); |
2997 | qemu_put_8s(f, &s->vga.sr_index); | |
2998 | qemu_put_buffer(f, s->vga.sr, 256); | |
2999 | qemu_put_8s(f, &s->vga.gr_index); | |
2c6ab832 FB |
3000 | qemu_put_8s(f, &s->cirrus_shadow_gr0); |
3001 | qemu_put_8s(f, &s->cirrus_shadow_gr1); | |
4e12cd94 AK |
3002 | qemu_put_buffer(f, s->vga.gr + 2, 254); |
3003 | qemu_put_8s(f, &s->vga.ar_index); | |
3004 | qemu_put_buffer(f, s->vga.ar, 21); | |
3005 | qemu_put_be32(f, s->vga.ar_flip_flop); | |
3006 | qemu_put_8s(f, &s->vga.cr_index); | |
3007 | qemu_put_buffer(f, s->vga.cr, 256); | |
3008 | qemu_put_8s(f, &s->vga.msr); | |
3009 | qemu_put_8s(f, &s->vga.fcr); | |
3010 | qemu_put_8s(f, &s->vga.st00); | |
3011 | qemu_put_8s(f, &s->vga.st01); | |
3012 | ||
3013 | qemu_put_8s(f, &s->vga.dac_state); | |
3014 | qemu_put_8s(f, &s->vga.dac_sub_index); | |
3015 | qemu_put_8s(f, &s->vga.dac_read_index); | |
3016 | qemu_put_8s(f, &s->vga.dac_write_index); | |
3017 | qemu_put_buffer(f, s->vga.dac_cache, 3); | |
3018 | qemu_put_buffer(f, s->vga.palette, 768); | |
3019 | ||
3020 | qemu_put_be32(f, s->vga.bank_offset); | |
2c6ab832 FB |
3021 | |
3022 | qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex); | |
3023 | qemu_put_8s(f, &s->cirrus_hidden_dac_data); | |
3024 | ||
3025 | qemu_put_be32s(f, &s->hw_cursor_x); | |
3026 | qemu_put_be32s(f, &s->hw_cursor_y); | |
3027 | /* XXX: we do not save the bitblt state - we assume we do not save | |
3028 | the state when the blitter is active */ | |
3029 | } | |
3030 | ||
3031 | static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id) | |
3032 | { | |
3033 | CirrusVGAState *s = opaque; | |
3034 | ||
d2269f6f | 3035 | if (version_id > 2) |
2c6ab832 FB |
3036 | return -EINVAL; |
3037 | ||
4e12cd94 AK |
3038 | qemu_get_be32s(f, &s->vga.latch); |
3039 | qemu_get_8s(f, &s->vga.sr_index); | |
3040 | qemu_get_buffer(f, s->vga.sr, 256); | |
3041 | qemu_get_8s(f, &s->vga.gr_index); | |
2c6ab832 FB |
3042 | qemu_get_8s(f, &s->cirrus_shadow_gr0); |
3043 | qemu_get_8s(f, &s->cirrus_shadow_gr1); | |
4e12cd94 AK |
3044 | s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f; |
3045 | s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f; | |
3046 | qemu_get_buffer(f, s->vga.gr + 2, 254); | |
3047 | qemu_get_8s(f, &s->vga.ar_index); | |
3048 | qemu_get_buffer(f, s->vga.ar, 21); | |
3049 | s->vga.ar_flip_flop=qemu_get_be32(f); | |
3050 | qemu_get_8s(f, &s->vga.cr_index); | |
3051 | qemu_get_buffer(f, s->vga.cr, 256); | |
3052 | qemu_get_8s(f, &s->vga.msr); | |
3053 | qemu_get_8s(f, &s->vga.fcr); | |
3054 | qemu_get_8s(f, &s->vga.st00); | |
3055 | qemu_get_8s(f, &s->vga.st01); | |
3056 | ||
3057 | qemu_get_8s(f, &s->vga.dac_state); | |
3058 | qemu_get_8s(f, &s->vga.dac_sub_index); | |
3059 | qemu_get_8s(f, &s->vga.dac_read_index); | |
3060 | qemu_get_8s(f, &s->vga.dac_write_index); | |
3061 | qemu_get_buffer(f, s->vga.dac_cache, 3); | |
3062 | qemu_get_buffer(f, s->vga.palette, 768); | |
3063 | ||
3064 | s->vga.bank_offset = qemu_get_be32(f); | |
2c6ab832 FB |
3065 | |
3066 | qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex); | |
3067 | qemu_get_8s(f, &s->cirrus_hidden_dac_data); | |
3068 | ||
3069 | qemu_get_be32s(f, &s->hw_cursor_x); | |
3070 | qemu_get_be32s(f, &s->hw_cursor_y); | |
3071 | ||
2bec46dc | 3072 | cirrus_update_memory_access(s); |
2c6ab832 | 3073 | /* force refresh */ |
4e12cd94 | 3074 | s->vga.graphic_mode = -1; |
2c6ab832 FB |
3075 | cirrus_update_bank_ptr(s, 0); |
3076 | cirrus_update_bank_ptr(s, 1); | |
3077 | return 0; | |
3078 | } | |
3079 | ||
4f335feb JQ |
3080 | static void pci_cirrus_vga_save(QEMUFile *f, void *opaque) |
3081 | { | |
3082 | PCICirrusVGAState *s = opaque; | |
3083 | ||
3084 | pci_device_save(&s->dev, f); | |
3085 | cirrus_vga_save(f, &s->cirrus_vga); | |
3086 | } | |
3087 | ||
3088 | static int pci_cirrus_vga_load(QEMUFile *f, void *opaque, int version_id) | |
3089 | { | |
3090 | PCICirrusVGAState *s = opaque; | |
3091 | int ret; | |
3092 | ||
3093 | if (version_id > 2) | |
3094 | return -EINVAL; | |
3095 | ||
3096 | if (version_id >= 2) { | |
3097 | ret = pci_device_load(&s->dev, f); | |
3098 | if (ret < 0) | |
3099 | return ret; | |
3100 | } | |
3101 | ||
3102 | return cirrus_vga_load(f, &s->cirrus_vga, version_id); | |
3103 | } | |
3104 | ||
e6e5ad80 FB |
3105 | /*************************************** |
3106 | * | |
3107 | * initialize | |
3108 | * | |
3109 | ***************************************/ | |
3110 | ||
4abc796d | 3111 | static void cirrus_reset(void *opaque) |
e6e5ad80 | 3112 | { |
4abc796d | 3113 | CirrusVGAState *s = opaque; |
e6e5ad80 | 3114 | |
03a3e7ba | 3115 | vga_common_reset(&s->vga); |
ee50c6bc | 3116 | unmap_linear_vram(s); |
4e12cd94 | 3117 | s->vga.sr[0x06] = 0x0f; |
4abc796d | 3118 | if (s->device_id == CIRRUS_ID_CLGD5446) { |
78e127ef | 3119 | /* 4MB 64 bit memory config, always PCI */ |
4e12cd94 AK |
3120 | s->vga.sr[0x1F] = 0x2d; // MemClock |
3121 | s->vga.gr[0x18] = 0x0f; // fastest memory configuration | |
3122 | s->vga.sr[0x0f] = 0x98; | |
3123 | s->vga.sr[0x17] = 0x20; | |
3124 | s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */ | |
78e127ef | 3125 | } else { |
4e12cd94 AK |
3126 | s->vga.sr[0x1F] = 0x22; // MemClock |
3127 | s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M; | |
3128 | s->vga.sr[0x17] = s->bustype; | |
3129 | s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */ | |
78e127ef | 3130 | } |
4e12cd94 | 3131 | s->vga.cr[0x27] = s->device_id; |
e6e5ad80 | 3132 | |
78e127ef FB |
3133 | /* Win2K seems to assume that the pattern buffer is at 0xff |
3134 | initially ! */ | |
4e12cd94 | 3135 | memset(s->vga.vram_ptr, 0xff, s->real_vram_size); |
78e127ef | 3136 | |
e6e5ad80 FB |
3137 | s->cirrus_hidden_dac_lockindex = 5; |
3138 | s->cirrus_hidden_dac_data = 0; | |
4abc796d BS |
3139 | } |
3140 | ||
3141 | static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci) | |
3142 | { | |
3143 | int i; | |
3144 | static int inited; | |
3145 | ||
3146 | if (!inited) { | |
3147 | inited = 1; | |
3148 | for(i = 0;i < 256; i++) | |
3149 | rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */ | |
3150 | rop_to_index[CIRRUS_ROP_0] = 0; | |
3151 | rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1; | |
3152 | rop_to_index[CIRRUS_ROP_NOP] = 2; | |
3153 | rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3; | |
3154 | rop_to_index[CIRRUS_ROP_NOTDST] = 4; | |
3155 | rop_to_index[CIRRUS_ROP_SRC] = 5; | |
3156 | rop_to_index[CIRRUS_ROP_1] = 6; | |
3157 | rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7; | |
3158 | rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8; | |
3159 | rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9; | |
3160 | rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10; | |
3161 | rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11; | |
3162 | rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12; | |
3163 | rop_to_index[CIRRUS_ROP_NOTSRC] = 13; | |
3164 | rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14; | |
3165 | rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15; | |
3166 | s->device_id = device_id; | |
3167 | if (is_pci) | |
3168 | s->bustype = CIRRUS_BUSTYPE_PCI; | |
3169 | else | |
3170 | s->bustype = CIRRUS_BUSTYPE_ISA; | |
3171 | } | |
3172 | ||
0ceac75b | 3173 | register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s); |
4abc796d | 3174 | |
0ceac75b JQ |
3175 | register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s); |
3176 | register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s); | |
3177 | register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s); | |
3178 | register_ioport_write(0x3da, 1, 1, cirrus_vga_ioport_write, s); | |
4abc796d | 3179 | |
0ceac75b | 3180 | register_ioport_read(0x3c0, 16, 1, cirrus_vga_ioport_read, s); |
4abc796d | 3181 | |
0ceac75b JQ |
3182 | register_ioport_read(0x3b4, 2, 1, cirrus_vga_ioport_read, s); |
3183 | register_ioport_read(0x3d4, 2, 1, cirrus_vga_ioport_read, s); | |
3184 | register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read, s); | |
3185 | register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s); | |
4abc796d | 3186 | |
1eed09cb | 3187 | s->vga.vga_io_memory = cpu_register_io_memory(cirrus_vga_mem_read, |
4e12cd94 | 3188 | cirrus_vga_mem_write, s); |
4abc796d | 3189 | cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000, |
4e12cd94 | 3190 | s->vga.vga_io_memory); |
4abc796d | 3191 | qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000); |
2c6ab832 | 3192 | |
fefe54e3 AL |
3193 | /* I/O handler for LFB */ |
3194 | s->cirrus_linear_io_addr = | |
1eed09cb | 3195 | cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s); |
fefe54e3 AL |
3196 | |
3197 | /* I/O handler for LFB */ | |
3198 | s->cirrus_linear_bitblt_io_addr = | |
1eed09cb | 3199 | cpu_register_io_memory(cirrus_linear_bitblt_read, |
fefe54e3 AL |
3200 | cirrus_linear_bitblt_write, s); |
3201 | ||
3202 | /* I/O handler for memory-mapped I/O */ | |
3203 | s->cirrus_mmio_io_addr = | |
1eed09cb | 3204 | cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s); |
fefe54e3 AL |
3205 | |
3206 | s->real_vram_size = | |
3207 | (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024; | |
3208 | ||
4e12cd94 | 3209 | /* XXX: s->vga.vram_size must be a power of two */ |
fefe54e3 AL |
3210 | s->cirrus_addr_mask = s->real_vram_size - 1; |
3211 | s->linear_mmio_mask = s->real_vram_size - 256; | |
3212 | ||
4e12cd94 AK |
3213 | s->vga.get_bpp = cirrus_get_bpp; |
3214 | s->vga.get_offsets = cirrus_get_offsets; | |
3215 | s->vga.get_resolution = cirrus_get_resolution; | |
3216 | s->vga.cursor_invalidate = cirrus_cursor_invalidate; | |
3217 | s->vga.cursor_draw_line = cirrus_cursor_draw_line; | |
fefe54e3 | 3218 | |
a08d4367 | 3219 | qemu_register_reset(cirrus_reset, s); |
4abc796d | 3220 | cirrus_reset(s); |
e6e5ad80 FB |
3221 | } |
3222 | ||
3223 | /*************************************** | |
3224 | * | |
3225 | * ISA bus support | |
3226 | * | |
3227 | ***************************************/ | |
3228 | ||
fbe1b595 | 3229 | void isa_cirrus_vga_init(void) |
e6e5ad80 FB |
3230 | { |
3231 | CirrusVGAState *s; | |
3232 | ||
3233 | s = qemu_mallocz(sizeof(CirrusVGAState)); | |
3b46e624 | 3234 | |
fbe1b595 | 3235 | vga_common_init(&s->vga, VGA_RAM_SIZE); |
78e127ef | 3236 | cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0); |
4e12cd94 AK |
3237 | s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate, |
3238 | s->vga.screen_dump, s->vga.text_update, | |
3239 | &s->vga); | |
4f335feb | 3240 | register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s); |
e6e5ad80 FB |
3241 | /* XXX ISA-LFB support */ |
3242 | } | |
3243 | ||
3244 | /*************************************** | |
3245 | * | |
3246 | * PCI bus support | |
3247 | * | |
3248 | ***************************************/ | |
3249 | ||
3250 | static void cirrus_pci_lfb_map(PCIDevice *d, int region_num, | |
3251 | uint32_t addr, uint32_t size, int type) | |
3252 | { | |
f3566bf9 | 3253 | CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga; |
e6e5ad80 | 3254 | |
a5082316 | 3255 | /* XXX: add byte swapping apertures */ |
4e12cd94 | 3256 | cpu_register_physical_memory(addr, s->vga.vram_size, |
e6e5ad80 | 3257 | s->cirrus_linear_io_addr); |
a5082316 FB |
3258 | cpu_register_physical_memory(addr + 0x1000000, 0x400000, |
3259 | s->cirrus_linear_bitblt_io_addr); | |
2bec46dc | 3260 | |
4e12cd94 AK |
3261 | s->vga.map_addr = s->vga.map_end = 0; |
3262 | s->vga.lfb_addr = addr & TARGET_PAGE_MASK; | |
3263 | s->vga.lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; | |
2bec46dc | 3264 | /* account for overflow */ |
4e12cd94 AK |
3265 | if (s->vga.lfb_end < addr + VGA_RAM_SIZE) |
3266 | s->vga.lfb_end = addr + VGA_RAM_SIZE; | |
ba7349cd | 3267 | |
4e12cd94 | 3268 | vga_dirty_log_start(&s->vga); |
e6e5ad80 FB |
3269 | } |
3270 | ||
3271 | static void cirrus_pci_mmio_map(PCIDevice *d, int region_num, | |
3272 | uint32_t addr, uint32_t size, int type) | |
3273 | { | |
f3566bf9 | 3274 | CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga; |
e6e5ad80 FB |
3275 | |
3276 | cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE, | |
3277 | s->cirrus_mmio_io_addr); | |
3278 | } | |
3279 | ||
ba7349cd AL |
3280 | static void pci_cirrus_write_config(PCIDevice *d, |
3281 | uint32_t address, uint32_t val, int len) | |
3282 | { | |
f3566bf9 | 3283 | PCICirrusVGAState *pvs = DO_UPCAST(PCICirrusVGAState, dev, d); |
ba7349cd AL |
3284 | CirrusVGAState *s = &pvs->cirrus_vga; |
3285 | ||
ba7349cd | 3286 | pci_default_write_config(d, address, val, len); |
f3566bf9 | 3287 | if (s->vga.map_addr && d->io_regions[0].addr == -1) |
4e12cd94 | 3288 | s->vga.map_addr = 0; |
ba7349cd | 3289 | cirrus_update_memory_access(s); |
ba7349cd AL |
3290 | } |
3291 | ||
81a322d4 | 3292 | static int pci_cirrus_vga_initfn(PCIDevice *dev) |
a414c306 GH |
3293 | { |
3294 | PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev); | |
3295 | CirrusVGAState *s = &d->cirrus_vga; | |
3296 | uint8_t *pci_conf = d->dev.config; | |
3297 | int device_id = CIRRUS_ID_CLGD5446; | |
3298 | ||
3299 | /* setup VGA */ | |
3300 | vga_common_init(&s->vga, VGA_RAM_SIZE); | |
3301 | cirrus_init_common(s, device_id, 1); | |
a414c306 GH |
3302 | s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate, |
3303 | s->vga.screen_dump, s->vga.text_update, | |
3304 | &s->vga); | |
3305 | ||
3306 | /* setup PCI */ | |
3307 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS); | |
3308 | pci_config_set_device_id(pci_conf, device_id); | |
3309 | pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS; | |
3310 | pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA); | |
3311 | pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; | |
3312 | ||
3313 | /* setup memory space */ | |
3314 | /* memory #0 LFB */ | |
3315 | /* memory #1 memory-mapped I/O */ | |
3316 | /* XXX: s->vga.vram_size must be a power of two */ | |
3317 | pci_register_bar((PCIDevice *)d, 0, 0x2000000, | |
3318 | PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map); | |
3319 | if (device_id == CIRRUS_ID_CLGD5446) { | |
3320 | pci_register_bar((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE, | |
3321 | PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map); | |
3322 | } | |
4f335feb | 3323 | register_savevm("cirrus_vga", 0, 2, pci_cirrus_vga_save, pci_cirrus_vga_load, d); |
a414c306 | 3324 | /* XXX: ROM BIOS */ |
81a322d4 | 3325 | return 0; |
a414c306 GH |
3326 | } |
3327 | ||
fbe1b595 | 3328 | void pci_cirrus_vga_init(PCIBus *bus) |
e6e5ad80 | 3329 | { |
a414c306 GH |
3330 | pci_create_simple(bus, -1, "Cirrus VGA"); |
3331 | } | |
d34cab9f | 3332 | |
a414c306 GH |
3333 | static PCIDeviceInfo cirrus_vga_info = { |
3334 | .qdev.name = "Cirrus VGA", | |
3335 | .qdev.size = sizeof(PCICirrusVGAState), | |
3336 | .init = pci_cirrus_vga_initfn, | |
3337 | .config_write = pci_cirrus_write_config, | |
3338 | }; | |
e6e5ad80 | 3339 | |
a414c306 GH |
3340 | static void cirrus_vga_register(void) |
3341 | { | |
3342 | pci_qdev_register(&cirrus_vga_info); | |
e6e5ad80 | 3343 | } |
a414c306 | 3344 | device_init(cirrus_vga_register); |