[mirror_qemu.git] / hw / cxl / cxl-component-utils.c

/*
 * CXL Utility library for components
 *
 * Copyright(C) 2020 Intel Corporation.
 *
 * This work is licensed under the terms of the GNU GPL, version 2. See the
 * COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qapi/error.h"
#include "hw/pci/pci.h"
#include "hw/cxl/cxl.h"

static uint64_t cxl_cache_mem_read_reg(void *opaque, hwaddr offset,
                                       unsigned size)
{
    CXLComponentState *cxl_cstate = opaque;
    ComponentRegisters *cregs = &cxl_cstate->crb;

    if (size == 8) {
        qemu_log_mask(LOG_UNIMP,
                      "CXL 8 byte cache mem registers not implemented\n");
        return 0;
    }

    if (cregs->special_ops && cregs->special_ops->read) {
        return cregs->special_ops->read(cxl_cstate, offset, size);
    } else {
        return cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)];
    }
}

static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset,
                             uint32_t value)
{
    ComponentRegisters *cregs = &cxl_cstate->crb;
    uint32_t *cache_mem = cregs->cache_mem_registers;
    bool should_commit = false;

    switch (offset) {
    case A_CXL_HDM_DECODER0_CTRL:
        should_commit = FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT);
        break;
    default:
        break;
    }

    memory_region_transaction_begin();
    stl_le_p((uint8_t *)cache_mem + offset, value);
    if (should_commit) {
        ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0);
        ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERR, 0);
        ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
    }
    memory_region_transaction_commit();
}

static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value,
                                    unsigned size)
{
    CXLComponentState *cxl_cstate = opaque;
    ComponentRegisters *cregs = &cxl_cstate->crb;
    uint32_t mask;

    if (size == 8) {
        qemu_log_mask(LOG_UNIMP,
                      "CXL 8 byte cache mem registers not implemented\n");
        return;
    }
    mask = cregs->cache_mem_regs_write_mask[offset / sizeof(*cregs->cache_mem_regs_write_mask)];
    value &= mask;
    /* RO bits should remain constant. Done by reading existing value */
    value |= ~mask & cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)];
    if (cregs->special_ops && cregs->special_ops->write) {
        cregs->special_ops->write(cxl_cstate, offset, value, size);
        return;
    }

    if (offset >= A_CXL_HDM_DECODER_CAPABILITY &&
        offset <= A_CXL_HDM_DECODER0_TARGET_LIST_HI) {
        dumb_hdm_handler(cxl_cstate, offset, value);
    } else {
        cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)] = value;
    }
}

/*
 * 8.2.3
 *   The access restrictions specified in Section 8.2.2 also apply to CXL 2.0
 *   Component Registers.
 *
 * 8.2.2
 *   • A 32 bit register shall be accessed as a 4 Bytes quantity. Partial
 *   reads are not permitted.
 *   • A 64 bit register shall be accessed as a 8 Bytes quantity. Partial
 *   reads are not permitted.
 *
 * As of the spec defined today, only 4 byte registers exist.
 */
static const MemoryRegionOps cache_mem_ops = {
    .read = cxl_cache_mem_read_reg,
    .write = cxl_cache_mem_write_reg,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 8,
        .unaligned = false,
    },
    .impl = {
        .min_access_size = 4,
        .max_access_size = 8,
    },
};

void cxl_component_register_block_init(Object *obj,
                                       CXLComponentState *cxl_cstate,
                                       const char *type)
{
    ComponentRegisters *cregs = &cxl_cstate->crb;

    memory_region_init(&cregs->component_registers, obj, type,
                       CXL2_COMPONENT_BLOCK_SIZE);

    /* io registers controls link which we don't care about in QEMU */
    memory_region_init_io(&cregs->io, obj, NULL, cregs, ".io",
                          CXL2_COMPONENT_IO_REGION_SIZE);
    memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs,
                          ".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE);

    memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io);
    memory_region_add_subregion(&cregs->component_registers,
                                CXL2_COMPONENT_IO_REGION_SIZE,
                                &cregs->cache_mem);
}

static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk)
{
    /*
     * Error status is RW1C but given bits are not yet set, it can
     * be handled as RO.
     */
    reg_state[R_CXL_RAS_UNC_ERR_STATUS] = 0;
    /* Bits 12-13 and 17-31 reserved in CXL 2.0 */
    reg_state[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff;
    write_msk[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff;
    reg_state[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff;
    write_msk[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff;
    reg_state[R_CXL_RAS_COR_ERR_STATUS] = 0;
    reg_state[R_CXL_RAS_COR_ERR_MASK] = 0x7f;
    write_msk[R_CXL_RAS_COR_ERR_MASK] = 0x7f;
    /* CXL switches and devices must set */
    reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00;
}

static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk)
{
    int decoder_count = 1;
    int i;

    ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT,
                     cxl_decoder_count_enc(decoder_count));
    ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 1);
    ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 1);
    ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 1);
    ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 0);
    ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL,
                     HDM_DECODER_ENABLE, 0);
    write_msk[R_CXL_HDM_DECODER_GLOBAL_CONTROL] = 0x3;
    for (i = 0; i < decoder_count; i++) {
        write_msk[R_CXL_HDM_DECODER0_BASE_LO + i * 0x20] = 0xf0000000;
        write_msk[R_CXL_HDM_DECODER0_BASE_HI + i * 0x20] = 0xffffffff;
        write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000;
        write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff;
        write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff;
    }
}

void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk,
                                        enum reg_type type)
{
    int caps = 0;

    /*
     * In CXL 2.0 the capabilities required for each CXL component are such that,
     * with the ordering chosen here, a single number can be used to define
     * which capabilities should be provided.
     */
    switch (type) {
    case CXL2_DOWNSTREAM_PORT:
    case CXL2_DEVICE:
        /* RAS, Link */
        caps = 2;
        break;
    case CXL2_UPSTREAM_PORT:
    case CXL2_TYPE3_DEVICE:
    case CXL2_LOGICAL_DEVICE:
        /* + HDM */
        caps = 3;
        break;
    case CXL2_ROOT_PORT:
        /* + Extended Security, + Snoop */
        caps = 5;
        break;
    default:
        abort();
    }

    memset(reg_state, 0, CXL2_COMPONENT_CM_REGION_SIZE);

    /* CXL Capability Header Register */
    ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ID, 1);
    ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, VERSION, 1);
    ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 1);
    ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ARRAY_SIZE, caps);

#define init_cap_reg(reg, id, version)                                        \
    QEMU_BUILD_BUG_ON(CXL_##reg##_REGISTERS_OFFSET == 0);                     \
    do {                                                                      \
        int which = R_CXL_##reg##_CAPABILITY_HEADER;                          \
        reg_state[which] = FIELD_DP32(reg_state[which],                       \
                                      CXL_##reg##_CAPABILITY_HEADER, ID, id); \
        reg_state[which] =                                                    \
            FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER,       \
                       VERSION, version);                                     \
        reg_state[which] =                                                    \
            FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, PTR,  \
                       CXL_##reg##_REGISTERS_OFFSET);                         \
    } while (0)

    init_cap_reg(RAS, 2, 2);
    ras_init_common(reg_state, write_msk);

    init_cap_reg(LINK, 4, 2);

    if (caps < 3) {
        return;
    }

    init_cap_reg(HDM, 5, 1);
    hdm_init_common(reg_state, write_msk);

    if (caps < 5) {
        return;
    }

    init_cap_reg(EXTSEC, 6, 1);
    init_cap_reg(SNOOP, 8, 1);

#undef init_cap_reg
}

/*
 * Helper to creates a DVSEC header for a CXL entity. The caller is responsible
 * for tracking the valid offset.
 *
 * This function will build the DVSEC header on behalf of the caller and then
 * copy in the remaining data for the vendor specific bits.
 * It will also set up appropriate write masks.
 */
void cxl_component_create_dvsec(CXLComponentState *cxl,
                                enum reg_type cxl_dev_type, uint16_t length,
                                uint16_t type, uint8_t rev, uint8_t *body)
{
    PCIDevice *pdev = cxl->pdev;
    uint16_t offset = cxl->dvsec_offset;
    uint8_t *wmask = pdev->wmask;

    assert(offset >= PCI_CFG_SPACE_SIZE &&
           ((offset + length) < PCI_CFG_SPACE_EXP_SIZE));
    assert((length & 0xf000) == 0);
    assert((rev & ~0xf) == 0);

    /* Create the DVSEC in the MCFG space */
    pcie_add_capability(pdev, PCI_EXT_CAP_ID_DVSEC, 1, offset, length);
    pci_set_long(pdev->config + offset + PCIE_DVSEC_HEADER1_OFFSET,
                 (length << 20) | (rev << 16) | CXL_VENDOR_ID);
    pci_set_word(pdev->config + offset + PCIE_DVSEC_ID_OFFSET, type);
    memcpy(pdev->config + offset + sizeof(DVSECHeader),
           body + sizeof(DVSECHeader),
           length - sizeof(DVSECHeader));

    /* Configure write masks */
    switch (type) {
    case PCIE_CXL_DEVICE_DVSEC:
        /* Cntrl RW Lock - so needs explicit blocking when lock is set */
        wmask[offset + offsetof(CXLDVSECDevice, ctrl)] = 0xFD;
        wmask[offset + offsetof(CXLDVSECDevice, ctrl) + 1] = 0x4F;
        /* Status is RW1CS */
        wmask[offset + offsetof(CXLDVSECDevice, ctrl2)] = 0x0F;
       /* Lock is RW Once */
        wmask[offset + offsetof(CXLDVSECDevice, lock)] = 0x01;
        /* range1/2_base_high/low is RW Lock */
        wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi)] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 2] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 3] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDevice, range1_base_lo) + 3] = 0xF0;
        wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi)] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 2] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 3] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDevice, range2_base_lo) + 3] = 0xF0;
        break;
    case NON_CXL_FUNCTION_MAP_DVSEC:
        break; /* Not yet implemented */
    case EXTENSIONS_PORT_DVSEC:
        wmask[offset + offsetof(CXLDVSECPortExtensions, control)] = 0x0F;
        wmask[offset + offsetof(CXLDVSECPortExtensions, control) + 1] = 0x40;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_base)] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_limit)] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base)] = 0xF0;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit)] = 0xF0;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base)] = 0xF0;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit)] = 0xF0;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high)] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 2] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 3] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high)] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 2] = 0xFF;
        wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 3] = 0xFF;
        break;
    case GPF_PORT_DVSEC:
        wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl)] = 0x0F;
        wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl) + 1] = 0x0F;
        wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl)] = 0x0F;
        wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl) + 1] = 0x0F;
        break;
    case GPF_DEVICE_DVSEC:
        wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration)] = 0x0F;
        wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration) + 1] = 0x0F;
        wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power)] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 1] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 2] = 0xFF;
        wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 3] = 0xFF;
        break;
    case PCIE_FLEXBUS_PORT_DVSEC:
        switch (cxl_dev_type) {
        case CXL2_ROOT_PORT:
            /* No MLD */
            wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xbd;
            break;
        case CXL2_DOWNSTREAM_PORT:
            wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xfd;
            break;
        default: /* Registers are RO for other component types */
            break;
        }
        /* There are rw1cs bits in the status register but never set currently */
        break;
    }

    /* Update state for future DVSEC additions */
    range_init_nofail(&cxl->dvsecs[type], cxl->dvsec_offset, length);
    cxl->dvsec_offset += length;
}

uint8_t cxl_interleave_ways_enc(int iw, Error **errp)
{
    switch (iw) {
    case 1: return 0x0;
    case 2: return 0x1;
    case 4: return 0x2;
    case 8: return 0x3;
    case 16: return 0x4;
    case 3: return 0x8;
    case 6: return 0x9;
    case 12: return 0xa;
    default:
        error_setg(errp, "Interleave ways: %d not supported", iw);
        return 0;
    }
}

uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp)
{
    switch (gran) {
    case 256: return 0;
    case 512: return 1;
    case 1024: return 2;
    case 2048: return 3;
    case 4096: return 4;
    case 8192: return 5;
    case 16384: return 6;
    default:
        error_setg(errp, "Interleave granularity: %" PRIu64 " invalid", gran);
        return 0;
    }
}
Commit	Line	Data
9e58f52d BW	1	/*
	2	* CXL Utility library for components
	3	*
	4	* Copyright(C) 2020 Intel Corporation.
	5	*
	6	* This work is licensed under the terms of the GNU GPL, version 2. See the
	7	* COPYING file in the top-level directory.
	8	*/
	9
	10	#include "qemu/osdep.h"
	11	#include "qemu/log.h"
829de299	12	#include "qapi/error.h"
9e58f52d BW	13	#include "hw/pci/pci.h"
	14	#include "hw/cxl/cxl.h"
	15
	16	static uint64_t cxl_cache_mem_read_reg(void *opaque, hwaddr offset,
	17	unsigned size)
	18	{
	19	CXLComponentState *cxl_cstate = opaque;
	20	ComponentRegisters *cregs = &cxl_cstate->crb;
	21
	22	if (size == 8) {
	23	qemu_log_mask(LOG_UNIMP,
	24	"CXL 8 byte cache mem registers not implemented\n");
	25	return 0;
	26	}
	27
	28	if (cregs->special_ops && cregs->special_ops->read) {
	29	return cregs->special_ops->read(cxl_cstate, offset, size);
	30	} else {
	31	return cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)];
	32	}
	33	}
	34
3540bf56 BW	35	static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset,
	36	uint32_t value)
	37	{
	38	ComponentRegisters *cregs = &cxl_cstate->crb;
	39	uint32_t *cache_mem = cregs->cache_mem_registers;
	40	bool should_commit = false;
	41
	42	switch (offset) {
	43	case A_CXL_HDM_DECODER0_CTRL:
	44	should_commit = FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT);
	45	break;
	46	default:
	47	break;
	48	}
	49
	50	memory_region_transaction_begin();
	51	stl_le_p((uint8_t *)cache_mem + offset, value);
	52	if (should_commit) {
	53	ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0);
	54	ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERR, 0);
	55	ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
	56	}
	57	memory_region_transaction_commit();
	58	}
	59
9e58f52d BW	60	static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value,
	61	unsigned size)
	62	{
	63	CXLComponentState *cxl_cstate = opaque;
	64	ComponentRegisters *cregs = &cxl_cstate->crb;
	65	uint32_t mask;
	66
	67	if (size == 8) {
	68	qemu_log_mask(LOG_UNIMP,
	69	"CXL 8 byte cache mem registers not implemented\n");
	70	return;
	71	}
	72	mask = cregs->cache_mem_regs_write_mask[offset / sizeof(*cregs->cache_mem_regs_write_mask)];
	73	value &= mask;
	74	/* RO bits should remain constant. Done by reading existing value */
	75	value \|= ~mask & cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)];
	76	if (cregs->special_ops && cregs->special_ops->write) {
	77	cregs->special_ops->write(cxl_cstate, offset, value, size);
3540bf56 BW	78	return;
	79	}
	80
	81	if (offset >= A_CXL_HDM_DECODER_CAPABILITY &&
	82	offset <= A_CXL_HDM_DECODER0_TARGET_LIST_HI) {
	83	dumb_hdm_handler(cxl_cstate, offset, value);
9e58f52d BW	84	} else {
	85	cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)] = value;
	86	}
	87	}
	88
	89	/*
	90	* 8.2.3
	91	* The access restrictions specified in Section 8.2.2 also apply to CXL 2.0
	92	* Component Registers.
	93	*
	94	* 8.2.2
	95	* • A 32 bit register shall be accessed as a 4 Bytes quantity. Partial
	96	* reads are not permitted.
	97	* • A 64 bit register shall be accessed as a 8 Bytes quantity. Partial
	98	* reads are not permitted.
	99	*
	100	* As of the spec defined today, only 4 byte registers exist.
	101	*/
	102	static const MemoryRegionOps cache_mem_ops = {
	103	.read = cxl_cache_mem_read_reg,
	104	.write = cxl_cache_mem_write_reg,
	105	.endianness = DEVICE_LITTLE_ENDIAN,
	106	.valid = {
	107	.min_access_size = 4,
	108	.max_access_size = 8,
	109	.unaligned = false,
	110	},
	111	.impl = {
	112	.min_access_size = 4,
	113	.max_access_size = 8,
	114	},
	115	};
	116
	117	void cxl_component_register_block_init(Object *obj,
	118	CXLComponentState *cxl_cstate,
	119	const char *type)
	120	{
	121	ComponentRegisters *cregs = &cxl_cstate->crb;
	122
	123	memory_region_init(&cregs->component_registers, obj, type,
	124	CXL2_COMPONENT_BLOCK_SIZE);
	125
	126	/* io registers controls link which we don't care about in QEMU */
	127	memory_region_init_io(&cregs->io, obj, NULL, cregs, ".io",
	128	CXL2_COMPONENT_IO_REGION_SIZE);
	129	memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs,
	130	".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE);
	131
	132	memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io);
	133	memory_region_add_subregion(&cregs->component_registers,
	134	CXL2_COMPONENT_IO_REGION_SIZE,
	135	&cregs->cache_mem);
	136	}
	137
	138	static void ras_init_common(uint32_t reg_state, uint32_t write_msk)
	139	{
	140	/*
	141	* Error status is RW1C but given bits are not yet set, it can
	142	* be handled as RO.
	143	*/
	144	reg_state[R_CXL_RAS_UNC_ERR_STATUS] = 0;
	145	/* Bits 12-13 and 17-31 reserved in CXL 2.0 */
	146	reg_state[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff;
	147	write_msk[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff;
148	reg_state[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff;
149	write_msk[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff;
150	reg_state[R_CXL_RAS_COR_ERR_STATUS] = 0;
151	reg_state[R_CXL_RAS_COR_ERR_MASK] = 0x7f;
152	write_msk[R_CXL_RAS_COR_ERR_MASK] = 0x7f;
153	/* CXL switches and devices must set */
154	reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00;
155	}
156
157	static void hdm_init_common(uint32_t reg_state, uint32_t write_msk)
158	{
159	int decoder_count = 1;
160	int i;
161
162	ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT,
163	cxl_decoder_count_enc(decoder_count));
164	ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 1);
165	ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 1);
166	ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 1);
167	ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 0);
168	ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL,
169	HDM_DECODER_ENABLE, 0);
170	write_msk[R_CXL_HDM_DECODER_GLOBAL_CONTROL] = 0x3;
171	for (i = 0; i < decoder_count; i++) {
172	write_msk[R_CXL_HDM_DECODER0_BASE_LO + i * 0x20] = 0xf0000000;
173	write_msk[R_CXL_HDM_DECODER0_BASE_HI + i * 0x20] = 0xffffffff;
174	write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000;
175	write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff;
176	write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff;
177	}
178	}
179
180	void cxl_component_register_init_common(uint32_t reg_state, uint32_t write_msk,
181	enum reg_type type)
182	{
183	int caps = 0;
184
185	/*
186	* In CXL 2.0 the capabilities required for each CXL component are such that,
187	* with the ordering chosen here, a single number can be used to define
188	* which capabilities should be provided.
189	*/
190	switch (type) {
191	case CXL2_DOWNSTREAM_PORT:
192	case CXL2_DEVICE:
193	/* RAS, Link */
194	caps = 2;
195	break;
196	case CXL2_UPSTREAM_PORT:
197	case CXL2_TYPE3_DEVICE:
198	case CXL2_LOGICAL_DEVICE:
199	/* + HDM */
200	caps = 3;
201	break;
202	case CXL2_ROOT_PORT:
203	/* + Extended Security, + Snoop */
204	caps = 5;
205	break;
206	default:
207	abort();
208	}
209
210	memset(reg_state, 0, CXL2_COMPONENT_CM_REGION_SIZE);
211
212	/* CXL Capability Header Register */
213	ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ID, 1);
214	ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, VERSION, 1);
215	ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 1);
216	ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ARRAY_SIZE, caps);
217
218	#define init_cap_reg(reg, id, version) \
219	QEMU_BUILD_BUG_ON(CXL_##reg##_REGISTERS_OFFSET == 0); \
220	do { \
221	int which = R_CXL_##reg##_CAPABILITY_HEADER; \
222	reg_state[which] = FIELD_DP32(reg_state[which], \
223	CXL_##reg##_CAPABILITY_HEADER, ID, id); \
224	reg_state[which] = \
225	FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, \
226	VERSION, version); \
227	reg_state[which] = \
228	FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, PTR, \
229	CXL_##reg##_REGISTERS_OFFSET); \
230	} while (0)
231
232	init_cap_reg(RAS, 2, 2);
233	ras_init_common(reg_state, write_msk);
234
235	init_cap_reg(LINK, 4, 2);
236
237	if (caps < 3) {
238	return;
239	}
240
241	init_cap_reg(HDM, 5, 1);
242	hdm_init_common(reg_state, write_msk);
243
244	if (caps < 5) {
245	return;
246	}
247
248	init_cap_reg(EXTSEC, 6, 1);
249	init_cap_reg(SNOOP, 8, 1);
250
251	#undef init_cap_reg
252	}
253
254	/*
255	* Helper to creates a DVSEC header for a CXL entity. The caller is responsible
256	* for tracking the valid offset.
257	*
258	* This function will build the DVSEC header on behalf of the caller and then
259	* copy in the remaining data for the vendor specific bits.
260	* It will also set up appropriate write masks.
261	*/
262	void cxl_component_create_dvsec(CXLComponentState *cxl,
263	enum reg_type cxl_dev_type, uint16_t length,
264	uint16_t type, uint8_t rev, uint8_t *body)
265	{
266	PCIDevice *pdev = cxl->pdev;
267	uint16_t offset = cxl->dvsec_offset;
268	uint8_t *wmask = pdev->wmask;
269
270	assert(offset >= PCI_CFG_SPACE_SIZE &&
271	((offset + length) < PCI_CFG_SPACE_EXP_SIZE));
272	assert((length & 0xf000) == 0);
273	assert((rev & ~0xf) == 0);
274
275	/* Create the DVSEC in the MCFG space */
276	pcie_add_capability(pdev, PCI_EXT_CAP_ID_DVSEC, 1, offset, length);
277	pci_set_long(pdev->config + offset + PCIE_DVSEC_HEADER1_OFFSET,
278	(length << 20) \| (rev << 16) \| CXL_VENDOR_ID);
279	pci_set_word(pdev->config + offset + PCIE_DVSEC_ID_OFFSET, type);
280	memcpy(pdev->config + offset + sizeof(DVSECHeader),
281	body + sizeof(DVSECHeader),
282	length - sizeof(DVSECHeader));
283
284	/* Configure write masks */
285	switch (type) {
286	case PCIE_CXL_DEVICE_DVSEC:
e1706ea8 BW	287	/* Cntrl RW Lock - so needs explicit blocking when lock is set */
	288	wmask[offset + offsetof(CXLDVSECDevice, ctrl)] = 0xFD;
	289	wmask[offset + offsetof(CXLDVSECDevice, ctrl) + 1] = 0x4F;
	290	/* Status is RW1CS */
	291	wmask[offset + offsetof(CXLDVSECDevice, ctrl2)] = 0x0F;
	292	/* Lock is RW Once */
	293	wmask[offset + offsetof(CXLDVSECDevice, lock)] = 0x01;
	294	/* range1/2_base_high/low is RW Lock */
	295	wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi)] = 0xFF;
	296	wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 1] = 0xFF;
	297	wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 2] = 0xFF;
	298	wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 3] = 0xFF;
	299	wmask[offset + offsetof(CXLDVSECDevice, range1_base_lo) + 3] = 0xF0;
	300	wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi)] = 0xFF;
	301	wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 1] = 0xFF;
	302	wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 2] = 0xFF;
	303	wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 3] = 0xFF;
	304	wmask[offset + offsetof(CXLDVSECDevice, range2_base_lo) + 3] = 0xF0;
9e58f52d BW	305	break;
	306	case NON_CXL_FUNCTION_MAP_DVSEC:
	307	break; /* Not yet implemented */
	308	case EXTENSIONS_PORT_DVSEC:
	309	wmask[offset + offsetof(CXLDVSECPortExtensions, control)] = 0x0F;
	310	wmask[offset + offsetof(CXLDVSECPortExtensions, control) + 1] = 0x40;
	311	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_base)] = 0xFF;
	312	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_limit)] = 0xFF;
	313	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base)] = 0xF0;
	314	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base) + 1] = 0xFF;
	315	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit)] = 0xF0;
	316	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit) + 1] = 0xFF;
	317	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base)] = 0xF0;
	318	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base) + 1] = 0xFF;
	319	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit)] = 0xF0;
	320	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit) + 1] = 0xFF;
	321	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high)] = 0xFF;
	322	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 1] = 0xFF;
	323	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 2] = 0xFF;
	324	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 3] = 0xFF;
	325	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high)] = 0xFF;
	326	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 1] = 0xFF;
	327	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 2] = 0xFF;
	328	wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 3] = 0xFF;
	329	break;
	330	case GPF_PORT_DVSEC:
	331	wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl)] = 0x0F;
	332	wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl) + 1] = 0x0F;
	333	wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl)] = 0x0F;
	334	wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl) + 1] = 0x0F;
	335	break;
	336	case GPF_DEVICE_DVSEC:
	337	wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration)] = 0x0F;
	338	wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration) + 1] = 0x0F;
	339	wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power)] = 0xFF;
	340	wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 1] = 0xFF;
	341	wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 2] = 0xFF;
	342	wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 3] = 0xFF;
	343	break;
	344	case PCIE_FLEXBUS_PORT_DVSEC:
	345	switch (cxl_dev_type) {
	346	case CXL2_ROOT_PORT:
	347	/* No MLD */
	348	wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xbd;
	349	break;
	350	case CXL2_DOWNSTREAM_PORT:
	351	wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xfd;
	352	break;
	353	default: /* Registers are RO for other component types */
	354	break;
	355	}
	356	/* There are rw1cs bits in the status register but never set currently */
	357	break;
	358	}
	359
	360	/* Update state for future DVSEC additions */
	361	range_init_nofail(&cxl->dvsecs[type], cxl->dvsec_offset, length);
	362	cxl->dvsec_offset += length;
	363	}
829de299 JC	364
	365	uint8_t cxl_interleave_ways_enc(int iw, Error **errp)
	366	{
	367	switch (iw) {
	368	case 1: return 0x0;
	369	case 2: return 0x1;
	370	case 4: return 0x2;
	371	case 8: return 0x3;
	372	case 16: return 0x4;
	373	case 3: return 0x8;
	374	case 6: return 0x9;
	375	case 12: return 0xa;
	376	default:
	377	error_setg(errp, "Interleave ways: %d not supported", iw);
	378	return 0;
	379	}
	380	}
	381
	382	uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp)
	383	{
	384	switch (gran) {
	385	case 256: return 0;
	386	case 512: return 1;
	387	case 1024: return 2;
	388	case 2048: return 3;
	389	case 4096: return 4;
	390	case 8192: return 5;
	391	case 16384: return 6;
	392	default:
	393	error_setg(errp, "Interleave granularity: %" PRIu64 " invalid", gran);
	394	return 0;
	395	}
	396	}