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Commit | Line | Data |
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9e58f52d BW |
1 | /* |
2 | * CXL Utility library for components | |
3 | * | |
4 | * Copyright(C) 2020 Intel Corporation. | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2. See the | |
7 | * COPYING file in the top-level directory. | |
8 | */ | |
9 | ||
10 | #include "qemu/osdep.h" | |
11 | #include "qemu/log.h" | |
829de299 | 12 | #include "qapi/error.h" |
9e58f52d BW |
13 | #include "hw/pci/pci.h" |
14 | #include "hw/cxl/cxl.h" | |
15 | ||
8700ee15 | 16 | /* CXL r3.1 Section 8.2.4.20.1 CXL HDM Decoder Capability Register */ |
f5a4e1a6 JC |
17 | int cxl_decoder_count_enc(int count) |
18 | { | |
19 | switch (count) { | |
87de174a JC |
20 | case 1: return 0x0; |
21 | case 2: return 0x1; | |
22 | case 4: return 0x2; | |
23 | case 6: return 0x3; | |
24 | case 8: return 0x4; | |
25 | case 10: return 0x5; | |
26 | /* Switches and Host Bridges may have more than 10 decoders */ | |
27 | case 12: return 0x6; | |
28 | case 14: return 0x7; | |
29 | case 16: return 0x8; | |
30 | case 20: return 0x9; | |
31 | case 24: return 0xa; | |
32 | case 28: return 0xb; | |
33 | case 32: return 0xc; | |
34 | } | |
35 | return 0; | |
36 | } | |
37 | ||
38 | int cxl_decoder_count_dec(int enc_cnt) | |
39 | { | |
40 | switch (enc_cnt) { | |
41 | case 0x0: return 1; | |
42 | case 0x1: return 2; | |
43 | case 0x2: return 4; | |
44 | case 0x3: return 6; | |
45 | case 0x4: return 8; | |
46 | case 0x5: return 10; | |
47 | /* Switches and Host Bridges may have more than 10 decoders */ | |
48 | case 0x6: return 12; | |
49 | case 0x7: return 14; | |
50 | case 0x8: return 16; | |
51 | case 0x9: return 20; | |
52 | case 0xa: return 24; | |
53 | case 0xb: return 28; | |
54 | case 0xc: return 32; | |
f5a4e1a6 JC |
55 | } |
56 | return 0; | |
57 | } | |
58 | ||
59 | hwaddr cxl_decode_ig(int ig) | |
60 | { | |
61 | return 1ULL << (ig + 8); | |
62 | } | |
63 | ||
9e58f52d BW |
64 | static uint64_t cxl_cache_mem_read_reg(void *opaque, hwaddr offset, |
65 | unsigned size) | |
66 | { | |
67 | CXLComponentState *cxl_cstate = opaque; | |
68 | ComponentRegisters *cregs = &cxl_cstate->crb; | |
69 | ||
388d6b57 JC |
70 | switch (size) { |
71 | case 4: | |
72 | if (cregs->special_ops && cregs->special_ops->read) { | |
73 | return cregs->special_ops->read(cxl_cstate, offset, 4); | |
74 | } else { | |
75 | QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_registers) != 4); | |
76 | return cregs->cache_mem_registers[offset / 4]; | |
77 | } | |
78 | case 8: | |
9e58f52d BW |
79 | qemu_log_mask(LOG_UNIMP, |
80 | "CXL 8 byte cache mem registers not implemented\n"); | |
81 | return 0; | |
388d6b57 JC |
82 | default: |
83 | /* | |
487152fa | 84 | * In line with specification limitaions on access sizes, this |
388d6b57 JC |
85 | * routine is not called with other sizes. |
86 | */ | |
87 | g_assert_not_reached(); | |
9e58f52d BW |
88 | } |
89 | } | |
90 | ||
3540bf56 BW |
91 | static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset, |
92 | uint32_t value) | |
93 | { | |
94 | ComponentRegisters *cregs = &cxl_cstate->crb; | |
95 | uint32_t *cache_mem = cregs->cache_mem_registers; | |
96 | bool should_commit = false; | |
823371a6 | 97 | bool should_uncommit = false; |
3540bf56 BW |
98 | |
99 | switch (offset) { | |
100 | case A_CXL_HDM_DECODER0_CTRL: | |
e967413f JC |
101 | case A_CXL_HDM_DECODER1_CTRL: |
102 | case A_CXL_HDM_DECODER2_CTRL: | |
103 | case A_CXL_HDM_DECODER3_CTRL: | |
3540bf56 | 104 | should_commit = FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT); |
823371a6 | 105 | should_uncommit = !should_commit; |
3540bf56 BW |
106 | break; |
107 | default: | |
108 | break; | |
109 | } | |
110 | ||
3540bf56 | 111 | if (should_commit) { |
92ff7cab JC |
112 | value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0); |
113 | value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); | |
823371a6 JC |
114 | } else if (should_uncommit) { |
115 | value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0); | |
116 | value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 0); | |
3540bf56 | 117 | } |
92ff7cab | 118 | stl_le_p((uint8_t *)cache_mem + offset, value); |
3540bf56 BW |
119 | } |
120 | ||
9e58f52d BW |
121 | static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value, |
122 | unsigned size) | |
123 | { | |
124 | CXLComponentState *cxl_cstate = opaque; | |
125 | ComponentRegisters *cregs = &cxl_cstate->crb; | |
126 | uint32_t mask; | |
127 | ||
388d6b57 JC |
128 | switch (size) { |
129 | case 4: { | |
130 | QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_regs_write_mask) != 4); | |
131 | QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_registers) != 4); | |
132 | mask = cregs->cache_mem_regs_write_mask[offset / 4]; | |
133 | value &= mask; | |
134 | /* RO bits should remain constant. Done by reading existing value */ | |
135 | value |= ~mask & cregs->cache_mem_registers[offset / 4]; | |
136 | if (cregs->special_ops && cregs->special_ops->write) { | |
137 | cregs->special_ops->write(cxl_cstate, offset, value, size); | |
138 | return; | |
139 | } | |
140 | ||
141 | if (offset >= A_CXL_HDM_DECODER_CAPABILITY && | |
142 | offset <= A_CXL_HDM_DECODER3_TARGET_LIST_HI) { | |
143 | dumb_hdm_handler(cxl_cstate, offset, value); | |
144 | } else { | |
145 | cregs->cache_mem_registers[offset / 4] = value; | |
146 | } | |
9e58f52d BW |
147 | return; |
148 | } | |
388d6b57 JC |
149 | case 8: |
150 | qemu_log_mask(LOG_UNIMP, | |
151 | "CXL 8 byte cache mem registers not implemented\n"); | |
3540bf56 | 152 | return; |
388d6b57 JC |
153 | default: |
154 | /* | |
487152fa | 155 | * In line with specification limitaions on access sizes, this |
388d6b57 JC |
156 | * routine is not called with other sizes. |
157 | */ | |
158 | g_assert_not_reached(); | |
9e58f52d BW |
159 | } |
160 | } | |
161 | ||
162 | /* | |
8700ee15 | 163 | * CXL r3.1 Section 8.2.3: Component Register Layout and Definition |
9e58f52d BW |
164 | * The access restrictions specified in Section 8.2.2 also apply to CXL 2.0 |
165 | * Component Registers. | |
166 | * | |
8700ee15 | 167 | * CXL r3.1 Section 8.2.2: Accessing Component Registers |
9e58f52d BW |
168 | * • A 32 bit register shall be accessed as a 4 Bytes quantity. Partial |
169 | * reads are not permitted. | |
170 | * • A 64 bit register shall be accessed as a 8 Bytes quantity. Partial | |
171 | * reads are not permitted. | |
172 | * | |
173 | * As of the spec defined today, only 4 byte registers exist. | |
174 | */ | |
175 | static const MemoryRegionOps cache_mem_ops = { | |
176 | .read = cxl_cache_mem_read_reg, | |
177 | .write = cxl_cache_mem_write_reg, | |
178 | .endianness = DEVICE_LITTLE_ENDIAN, | |
179 | .valid = { | |
180 | .min_access_size = 4, | |
181 | .max_access_size = 8, | |
182 | .unaligned = false, | |
183 | }, | |
184 | .impl = { | |
185 | .min_access_size = 4, | |
186 | .max_access_size = 8, | |
187 | }, | |
188 | }; | |
189 | ||
190 | void cxl_component_register_block_init(Object *obj, | |
191 | CXLComponentState *cxl_cstate, | |
192 | const char *type) | |
193 | { | |
194 | ComponentRegisters *cregs = &cxl_cstate->crb; | |
195 | ||
196 | memory_region_init(&cregs->component_registers, obj, type, | |
197 | CXL2_COMPONENT_BLOCK_SIZE); | |
198 | ||
199 | /* io registers controls link which we don't care about in QEMU */ | |
f8b02dd6 | 200 | memory_region_init_io(&cregs->io, obj, NULL, NULL, ".io", |
9e58f52d | 201 | CXL2_COMPONENT_IO_REGION_SIZE); |
729d45a6 | 202 | memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cxl_cstate, |
9e58f52d BW |
203 | ".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE); |
204 | ||
205 | memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io); | |
206 | memory_region_add_subregion(&cregs->component_registers, | |
207 | CXL2_COMPONENT_IO_REGION_SIZE, | |
208 | &cregs->cache_mem); | |
209 | } | |
210 | ||
211 | static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk) | |
212 | { | |
213 | /* | |
214 | * Error status is RW1C but given bits are not yet set, it can | |
215 | * be handled as RO. | |
216 | */ | |
cb4e642c | 217 | stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0); |
415442a1 | 218 | stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_STATUS, 0x1cfff); |
9e58f52d | 219 | /* Bits 12-13 and 17-31 reserved in CXL 2.0 */ |
cb4e642c JC |
220 | stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); |
221 | stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); | |
222 | stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); | |
223 | stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); | |
224 | stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0); | |
415442a1 | 225 | stl_le_p(write_msk + R_CXL_RAS_COR_ERR_STATUS, 0x7f); |
cb4e642c JC |
226 | stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f); |
227 | stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f); | |
9e58f52d | 228 | /* CXL switches and devices must set */ |
415442a1 | 229 | stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x200); |
9e58f52d BW |
230 | } |
231 | ||
f824f529 JC |
232 | static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, |
233 | enum reg_type type) | |
9e58f52d | 234 | { |
e967413f | 235 | int decoder_count = CXL_HDM_DECODER_COUNT; |
61c44bcf | 236 | int hdm_inc = R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_LO; |
9e58f52d BW |
237 | int i; |
238 | ||
239 | ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT, | |
240 | cxl_decoder_count_enc(decoder_count)); | |
241 | ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 1); | |
242 | ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 1); | |
243 | ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 1); | |
b342489a JC |
244 | ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, |
245 | POISON_ON_ERR_CAP, 0); | |
ae243dbf JC |
246 | ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY, 0); |
247 | ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 16_WAY, 0); | |
248 | ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, UIO, 0); | |
249 | ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, | |
250 | UIO_DECODER_COUNT, 0); | |
251 | ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, MEMDATA_NXM_CAP, 0); | |
252 | ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, | |
253 | SUPPORTED_COHERENCY_MODEL, 0); /* Unknown */ | |
9e58f52d BW |
254 | ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL, |
255 | HDM_DECODER_ENABLE, 0); | |
256 | write_msk[R_CXL_HDM_DECODER_GLOBAL_CONTROL] = 0x3; | |
257 | for (i = 0; i < decoder_count; i++) { | |
61c44bcf JC |
258 | write_msk[R_CXL_HDM_DECODER0_BASE_LO + i * hdm_inc] = 0xf0000000; |
259 | write_msk[R_CXL_HDM_DECODER0_BASE_HI + i * hdm_inc] = 0xffffffff; | |
260 | write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * hdm_inc] = 0xf0000000; | |
261 | write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * hdm_inc] = 0xffffffff; | |
262 | write_msk[R_CXL_HDM_DECODER0_CTRL + i * hdm_inc] = 0x13ff; | |
f824f529 JC |
263 | if (type == CXL2_DEVICE || |
264 | type == CXL2_TYPE3_DEVICE || | |
265 | type == CXL2_LOGICAL_DEVICE) { | |
61c44bcf JC |
266 | write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * hdm_inc] = |
267 | 0xf0000000; | |
f824f529 | 268 | } else { |
61c44bcf JC |
269 | write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * hdm_inc] = |
270 | 0xffffffff; | |
f824f529 | 271 | } |
61c44bcf | 272 | write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * hdm_inc] = 0xffffffff; |
9e58f52d BW |
273 | } |
274 | } | |
275 | ||
b342489a JC |
276 | void cxl_component_register_init_common(uint32_t *reg_state, |
277 | uint32_t *write_msk, | |
9e58f52d BW |
278 | enum reg_type type) |
279 | { | |
280 | int caps = 0; | |
281 | ||
282 | /* | |
b342489a JC |
283 | * In CXL 2.0 the capabilities required for each CXL component are such |
284 | * that, with the ordering chosen here, a single number can be used to | |
285 | * define which capabilities should be provided. | |
9e58f52d BW |
286 | */ |
287 | switch (type) { | |
288 | case CXL2_DOWNSTREAM_PORT: | |
289 | case CXL2_DEVICE: | |
290 | /* RAS, Link */ | |
291 | caps = 2; | |
292 | break; | |
293 | case CXL2_UPSTREAM_PORT: | |
294 | case CXL2_TYPE3_DEVICE: | |
295 | case CXL2_LOGICAL_DEVICE: | |
296 | /* + HDM */ | |
297 | caps = 3; | |
298 | break; | |
299 | case CXL2_ROOT_PORT: | |
3a95f572 | 300 | case CXL2_RC: |
9e58f52d BW |
301 | /* + Extended Security, + Snoop */ |
302 | caps = 5; | |
303 | break; | |
304 | default: | |
305 | abort(); | |
306 | } | |
307 | ||
308 | memset(reg_state, 0, CXL2_COMPONENT_CM_REGION_SIZE); | |
309 | ||
310 | /* CXL Capability Header Register */ | |
311 | ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ID, 1); | |
8700ee15 JC |
312 | ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, VERSION, |
313 | CXL_CAPABILITY_VERSION); | |
9e58f52d BW |
314 | ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 1); |
315 | ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ARRAY_SIZE, caps); | |
316 | ||
317 | #define init_cap_reg(reg, id, version) \ | |
9e58f52d BW |
318 | do { \ |
319 | int which = R_CXL_##reg##_CAPABILITY_HEADER; \ | |
320 | reg_state[which] = FIELD_DP32(reg_state[which], \ | |
321 | CXL_##reg##_CAPABILITY_HEADER, ID, id); \ | |
322 | reg_state[which] = \ | |
323 | FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, \ | |
324 | VERSION, version); \ | |
325 | reg_state[which] = \ | |
326 | FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, PTR, \ | |
327 | CXL_##reg##_REGISTERS_OFFSET); \ | |
328 | } while (0) | |
329 | ||
3a95f572 JC |
330 | switch (type) { |
331 | case CXL2_DEVICE: | |
332 | case CXL2_TYPE3_DEVICE: | |
333 | case CXL2_LOGICAL_DEVICE: | |
334 | case CXL2_ROOT_PORT: | |
335 | case CXL2_UPSTREAM_PORT: | |
336 | case CXL2_DOWNSTREAM_PORT: | |
a185ff05 | 337 | init_cap_reg(RAS, 2, CXL_RAS_CAPABILITY_VERSION); |
3a95f572 JC |
338 | ras_init_common(reg_state, write_msk); |
339 | break; | |
340 | default: | |
341 | break; | |
342 | } | |
9e58f52d | 343 | |
8700ee15 | 344 | init_cap_reg(LINK, 4, CXL_LINK_CAPABILITY_VERSION); |
9e58f52d BW |
345 | |
346 | if (caps < 3) { | |
347 | return; | |
348 | } | |
349 | ||
3a95f572 JC |
350 | if (type != CXL2_ROOT_PORT) { |
351 | init_cap_reg(HDM, 5, CXL_HDM_CAPABILITY_VERSION); | |
352 | hdm_init_common(reg_state, write_msk, type); | |
353 | } | |
9e58f52d BW |
354 | if (caps < 5) { |
355 | return; | |
356 | } | |
357 | ||
8700ee15 JC |
358 | init_cap_reg(EXTSEC, 6, CXL_EXTSEC_CAP_VERSION); |
359 | init_cap_reg(SNOOP, 8, CXL_SNOOP_CAP_VERSION); | |
9e58f52d BW |
360 | |
361 | #undef init_cap_reg | |
362 | } | |
363 | ||
364 | /* | |
365 | * Helper to creates a DVSEC header for a CXL entity. The caller is responsible | |
366 | * for tracking the valid offset. | |
367 | * | |
368 | * This function will build the DVSEC header on behalf of the caller and then | |
369 | * copy in the remaining data for the vendor specific bits. | |
370 | * It will also set up appropriate write masks. | |
371 | */ | |
372 | void cxl_component_create_dvsec(CXLComponentState *cxl, | |
373 | enum reg_type cxl_dev_type, uint16_t length, | |
374 | uint16_t type, uint8_t rev, uint8_t *body) | |
375 | { | |
376 | PCIDevice *pdev = cxl->pdev; | |
377 | uint16_t offset = cxl->dvsec_offset; | |
378 | uint8_t *wmask = pdev->wmask; | |
379 | ||
380 | assert(offset >= PCI_CFG_SPACE_SIZE && | |
381 | ((offset + length) < PCI_CFG_SPACE_EXP_SIZE)); | |
382 | assert((length & 0xf000) == 0); | |
383 | assert((rev & ~0xf) == 0); | |
384 | ||
385 | /* Create the DVSEC in the MCFG space */ | |
386 | pcie_add_capability(pdev, PCI_EXT_CAP_ID_DVSEC, 1, offset, length); | |
387 | pci_set_long(pdev->config + offset + PCIE_DVSEC_HEADER1_OFFSET, | |
388 | (length << 20) | (rev << 16) | CXL_VENDOR_ID); | |
389 | pci_set_word(pdev->config + offset + PCIE_DVSEC_ID_OFFSET, type); | |
390 | memcpy(pdev->config + offset + sizeof(DVSECHeader), | |
391 | body + sizeof(DVSECHeader), | |
392 | length - sizeof(DVSECHeader)); | |
393 | ||
394 | /* Configure write masks */ | |
395 | switch (type) { | |
396 | case PCIE_CXL_DEVICE_DVSEC: | |
e1706ea8 BW |
397 | /* Cntrl RW Lock - so needs explicit blocking when lock is set */ |
398 | wmask[offset + offsetof(CXLDVSECDevice, ctrl)] = 0xFD; | |
399 | wmask[offset + offsetof(CXLDVSECDevice, ctrl) + 1] = 0x4F; | |
400 | /* Status is RW1CS */ | |
401 | wmask[offset + offsetof(CXLDVSECDevice, ctrl2)] = 0x0F; | |
402 | /* Lock is RW Once */ | |
403 | wmask[offset + offsetof(CXLDVSECDevice, lock)] = 0x01; | |
404 | /* range1/2_base_high/low is RW Lock */ | |
405 | wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi)] = 0xFF; | |
406 | wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 1] = 0xFF; | |
407 | wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 2] = 0xFF; | |
408 | wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 3] = 0xFF; | |
409 | wmask[offset + offsetof(CXLDVSECDevice, range1_base_lo) + 3] = 0xF0; | |
410 | wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi)] = 0xFF; | |
411 | wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 1] = 0xFF; | |
412 | wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 2] = 0xFF; | |
413 | wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 3] = 0xFF; | |
414 | wmask[offset + offsetof(CXLDVSECDevice, range2_base_lo) + 3] = 0xF0; | |
9e58f52d BW |
415 | break; |
416 | case NON_CXL_FUNCTION_MAP_DVSEC: | |
417 | break; /* Not yet implemented */ | |
418 | case EXTENSIONS_PORT_DVSEC: | |
b34ae3c9 JC |
419 | wmask[offset + offsetof(CXLDVSECPortExt, control)] = 0x0F; |
420 | wmask[offset + offsetof(CXLDVSECPortExt, control) + 1] = 0x40; | |
421 | wmask[offset + offsetof(CXLDVSECPortExt, alt_bus_base)] = 0xFF; | |
422 | wmask[offset + offsetof(CXLDVSECPortExt, alt_bus_limit)] = 0xFF; | |
423 | wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_base)] = 0xF0; | |
424 | wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_base) + 1] = 0xFF; | |
425 | wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_limit)] = 0xF0; | |
426 | wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_limit) + 1] = 0xFF; | |
427 | wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base)] = 0xF0; | |
428 | wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base) + 1] = 0xFF; | |
429 | wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit)] = 0xF0; | |
430 | wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit) + 1] = | |
431 | 0xFF; | |
432 | wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base_high)] = | |
433 | 0xFF; | |
434 | wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base_high) + 1] = | |
435 | 0xFF; | |
436 | wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base_high) + 2] = | |
437 | 0xFF; | |
438 | wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base_high) + 3] = | |
439 | 0xFF; | |
440 | wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit_high)] = | |
441 | 0xFF; | |
442 | wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit_high) + 1] = | |
443 | 0xFF; | |
444 | wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit_high) + 2] = | |
445 | 0xFF; | |
446 | wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit_high) + 3] = | |
447 | 0xFF; | |
9e58f52d BW |
448 | break; |
449 | case GPF_PORT_DVSEC: | |
450 | wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl)] = 0x0F; | |
451 | wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl) + 1] = 0x0F; | |
452 | wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl)] = 0x0F; | |
453 | wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl) + 1] = 0x0F; | |
454 | break; | |
455 | case GPF_DEVICE_DVSEC: | |
456 | wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration)] = 0x0F; | |
457 | wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration) + 1] = 0x0F; | |
458 | wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power)] = 0xFF; | |
459 | wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 1] = 0xFF; | |
460 | wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 2] = 0xFF; | |
461 | wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 3] = 0xFF; | |
462 | break; | |
463 | case PCIE_FLEXBUS_PORT_DVSEC: | |
464 | switch (cxl_dev_type) { | |
465 | case CXL2_ROOT_PORT: | |
466 | /* No MLD */ | |
467 | wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xbd; | |
468 | break; | |
469 | case CXL2_DOWNSTREAM_PORT: | |
470 | wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xfd; | |
471 | break; | |
472 | default: /* Registers are RO for other component types */ | |
473 | break; | |
474 | } | |
b342489a | 475 | /* There are rw1cs bits in the status register but never set */ |
9e58f52d BW |
476 | break; |
477 | } | |
478 | ||
479 | /* Update state for future DVSEC additions */ | |
480 | range_init_nofail(&cxl->dvsecs[type], cxl->dvsec_offset, length); | |
481 | cxl->dvsec_offset += length; | |
482 | } | |
829de299 | 483 | |
8700ee15 | 484 | /* CXL r3.1 Section 8.2.4.20.7 CXL HDM Decoder n Control Register */ |
829de299 JC |
485 | uint8_t cxl_interleave_ways_enc(int iw, Error **errp) |
486 | { | |
487 | switch (iw) { | |
488 | case 1: return 0x0; | |
489 | case 2: return 0x1; | |
490 | case 4: return 0x2; | |
491 | case 8: return 0x3; | |
492 | case 16: return 0x4; | |
493 | case 3: return 0x8; | |
494 | case 6: return 0x9; | |
495 | case 12: return 0xa; | |
496 | default: | |
497 | error_setg(errp, "Interleave ways: %d not supported", iw); | |
498 | return 0; | |
499 | } | |
500 | } | |
501 | ||
87de174a JC |
502 | int cxl_interleave_ways_dec(uint8_t iw_enc, Error **errp) |
503 | { | |
504 | switch (iw_enc) { | |
505 | case 0x0: return 1; | |
506 | case 0x1: return 2; | |
507 | case 0x2: return 4; | |
508 | case 0x3: return 8; | |
509 | case 0x4: return 16; | |
510 | case 0x8: return 3; | |
511 | case 0x9: return 6; | |
512 | case 0xa: return 12; | |
513 | default: | |
514 | error_setg(errp, "Encoded interleave ways: %d not supported", iw_enc); | |
515 | return 0; | |
516 | } | |
517 | } | |
518 | ||
829de299 JC |
519 | uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp) |
520 | { | |
521 | switch (gran) { | |
522 | case 256: return 0; | |
523 | case 512: return 1; | |
524 | case 1024: return 2; | |
525 | case 2048: return 3; | |
526 | case 4096: return 4; | |
527 | case 8192: return 5; | |
528 | case 16384: return 6; | |
529 | default: | |
530 | error_setg(errp, "Interleave granularity: %" PRIu64 " invalid", gran); | |
531 | return 0; | |
532 | } | |
533 | } |