[mirror_qemu.git] / hw / dma / pl080.c

/*
 * Arm PrimeCell PL080/PL081 DMA controller
 *
 * Copyright (c) 2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "exec/address-spaces.h"
#include "qemu/log.h"
#include "hw/dma/pl080.h"

#define PL080_CONF_E    0x1
#define PL080_CONF_M1   0x2
#define PL080_CONF_M2   0x4

#define PL080_CCONF_H   0x40000
#define PL080_CCONF_A   0x20000
#define PL080_CCONF_L   0x10000
#define PL080_CCONF_ITC 0x08000
#define PL080_CCONF_IE  0x04000
#define PL080_CCONF_E   0x00001

#define PL080_CCTRL_I   0x80000000
#define PL080_CCTRL_DI  0x08000000
#define PL080_CCTRL_SI  0x04000000
#define PL080_CCTRL_D   0x02000000
#define PL080_CCTRL_S   0x01000000

static const VMStateDescription vmstate_pl080_channel = {
    .name = "pl080_channel",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(src, pl080_channel),
        VMSTATE_UINT32(dest, pl080_channel),
        VMSTATE_UINT32(lli, pl080_channel),
        VMSTATE_UINT32(ctrl, pl080_channel),
        VMSTATE_UINT32(conf, pl080_channel),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pl080 = {
    .name = "pl080",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_mask, PL080State),
        VMSTATE_UINT8(err_int, PL080State),
        VMSTATE_UINT8(err_mask, PL080State),
        VMSTATE_UINT32(conf, PL080State),
        VMSTATE_UINT32(sync, PL080State),
        VMSTATE_UINT32(req_single, PL080State),
        VMSTATE_UINT32(req_burst, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS,
                             1, vmstate_pl080_channel, pl080_channel),
        VMSTATE_INT32(running, PL080State),
        VMSTATE_END_OF_LIST()
    }
};

static const unsigned char pl080_id[] =
{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };

static const unsigned char pl081_id[] =
{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };

static void pl080_update(PL080State *s)
{
    bool tclevel = (s->tc_int & s->tc_mask);
    bool errlevel = (s->err_int & s->err_mask);

    qemu_set_irq(s->interr, errlevel);
    qemu_set_irq(s->inttc, tclevel);
    qemu_set_irq(s->irq, errlevel || tclevel);
}

static void pl080_run(PL080State *s)
{
    int c;
    int flow;
    pl080_channel *ch;
    int swidth;
    int dwidth;
    int xsize;
    int n;
    int src_id;
    int dest_id;
    int size;
    uint8_t buff[4];
    uint32_t req;

    s->tc_mask = 0;
    for (c = 0; c < s->nchannels; c++) {
        if (s->chan[c].conf & PL080_CCONF_ITC)
            s->tc_mask |= 1 << c;
        if (s->chan[c].conf & PL080_CCONF_IE)
            s->err_mask |= 1 << c;
    }

    if ((s->conf & PL080_CONF_E) == 0)
        return;

hw_error("DMA active\n");
    /* If we are already in the middle of a DMA operation then indicate that
       there may be new DMA requests and return immediately.  */
    if (s->running) {
        s->running++;
        return;
    }
    s->running = 1;
    while (s->running) {
        for (c = 0; c < s->nchannels; c++) {
            ch = &s->chan[c];
again:
            /* Test if thiws channel has any pending DMA requests.  */
            if ((ch->conf & (PL080_CCONF_H | PL080_CCONF_E))
                    != PL080_CCONF_E)
                continue;
            flow = (ch->conf >> 11) & 7;
            if (flow >= 4) {
                hw_error(
                    "pl080_run: Peripheral flow control not implemented\n");
            }
            src_id = (ch->conf >> 1) & 0x1f;
            dest_id = (ch->conf >> 6) & 0x1f;
            size = ch->ctrl & 0xfff;
            req = s->req_single | s->req_burst;
            switch (flow) {
            case 0:
                break;
            case 1:
                if ((req & (1u << dest_id)) == 0)
                    size = 0;
                break;
            case 2:
                if ((req & (1u << src_id)) == 0)
                    size = 0;
                break;
            case 3:
                if ((req & (1u << src_id)) == 0
                        || (req & (1u << dest_id)) == 0)
                    size = 0;
                break;
            }
            if (!size)
                continue;

            /* Transfer one element.  */
            /* ??? Should transfer multiple elements for a burst request.  */
            /* ??? Unclear what the proper behavior is when source and
               destination widths are different.  */
            swidth = 1 << ((ch->ctrl >> 18) & 7);
            dwidth = 1 << ((ch->ctrl >> 21) & 7);
            for (n = 0; n < dwidth; n+= swidth) {
                cpu_physical_memory_read(ch->src, buff + n, swidth);
                if (ch->ctrl & PL080_CCTRL_SI)
                    ch->src += swidth;
            }
            xsize = (dwidth < swidth) ? swidth : dwidth;
            /* ??? This may pad the value incorrectly for dwidth < 32.  */
            for (n = 0; n < xsize; n += dwidth) {
                cpu_physical_memory_write(ch->dest + n, buff + n, dwidth);
                if (ch->ctrl & PL080_CCTRL_DI)
                    ch->dest += swidth;
            }

            size--;
            ch->ctrl = (ch->ctrl & 0xfffff000) | size;
            if (size == 0) {
                /* Transfer complete.  */
                if (ch->lli) {
                    ch->src = address_space_ldl_le(&address_space_memory,
                                                   ch->lli,
                                                   MEMTXATTRS_UNSPECIFIED,
                                                   NULL);
                    ch->dest = address_space_ldl_le(&address_space_memory,
                                                    ch->lli + 4,
                                                    MEMTXATTRS_UNSPECIFIED,
                                                    NULL);
                    ch->ctrl = address_space_ldl_le(&address_space_memory,
                                                    ch->lli + 12,
                                                    MEMTXATTRS_UNSPECIFIED,
                                                    NULL);
                    ch->lli = address_space_ldl_le(&address_space_memory,
                                                   ch->lli + 8,
                                                   MEMTXATTRS_UNSPECIFIED,
                                                   NULL);
                } else {
                    ch->conf &= ~PL080_CCONF_E;
                }
                if (ch->ctrl & PL080_CCTRL_I) {
                    s->tc_int |= 1 << c;
                }
            }
            goto again;
        }
        if (--s->running)
            s->running = 1;
    }
}

static uint64_t pl080_read(void *opaque, hwaddr offset,
                           unsigned size)
{
    PL080State *s = (PL080State *)opaque;
    uint32_t i;
    uint32_t mask;

    if (offset >= 0xfe0 && offset < 0x1000) {
        if (s->nchannels == 8) {
            return pl080_id[(offset - 0xfe0) >> 2];
        } else {
            return pl081_id[(offset - 0xfe0) >> 2];
        }
    }
    if (offset >= 0x100 && offset < 0x200) {
        i = (offset & 0xe0) >> 5;
        if (i >= s->nchannels)
            goto bad_offset;
        switch (offset >> 2) {
        case 0: /* SrcAddr */
            return s->chan[i].src;
        case 1: /* DestAddr */
            return s->chan[i].dest;
        case 2: /* LLI */
            return s->chan[i].lli;
        case 3: /* Control */
            return s->chan[i].ctrl;
        case 4: /* Configuration */
            return s->chan[i].conf;
        default:
            goto bad_offset;
        }
    }
    switch (offset >> 2) {
    case 0: /* IntStatus */
        return (s->tc_int & s->tc_mask) | (s->err_int & s->err_mask);
    case 1: /* IntTCStatus */
        return (s->tc_int & s->tc_mask);
    case 3: /* IntErrorStatus */
        return (s->err_int & s->err_mask);
    case 5: /* RawIntTCStatus */
        return s->tc_int;
    case 6: /* RawIntErrorStatus */
        return s->err_int;
    case 7: /* EnbldChns */
        mask = 0;
        for (i = 0; i < s->nchannels; i++) {
            if (s->chan[i].conf & PL080_CCONF_E)
                mask |= 1 << i;
        }
        return mask;
    case 8: /* SoftBReq */
    case 9: /* SoftSReq */
    case 10: /* SoftLBReq */
    case 11: /* SoftLSReq */
        /* ??? Implement these. */
        return 0;
    case 12: /* Configuration */
        return s->conf;
    case 13: /* Sync */
        return s->sync;
    default:
    bad_offset:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl080_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl080_write(void *opaque, hwaddr offset,
                        uint64_t value, unsigned size)
{
    PL080State *s = (PL080State *)opaque;
    int i;

    if (offset >= 0x100 && offset < 0x200) {
        i = (offset & 0xe0) >> 5;
        if (i >= s->nchannels)
            goto bad_offset;
        switch (offset >> 2) {
        case 0: /* SrcAddr */
            s->chan[i].src = value;
            break;
        case 1: /* DestAddr */
            s->chan[i].dest = value;
            break;
        case 2: /* LLI */
            s->chan[i].lli = value;
            break;
        case 3: /* Control */
            s->chan[i].ctrl = value;
            break;
        case 4: /* Configuration */
            s->chan[i].conf = value;
            pl080_run(s);
            break;
        }
    }
    switch (offset >> 2) {
    case 2: /* IntTCClear */
        s->tc_int &= ~value;
        break;
    case 4: /* IntErrorClear */
        s->err_int &= ~value;
        break;
    case 8: /* SoftBReq */
    case 9: /* SoftSReq */
    case 10: /* SoftLBReq */
    case 11: /* SoftLSReq */
        /* ??? Implement these.  */
        qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n");
        break;
    case 12: /* Configuration */
        s->conf = value;
        if (s->conf & (PL080_CONF_M1 | PL080_CONF_M2)) {
            qemu_log_mask(LOG_UNIMP,
                          "pl080_write: Big-endian DMA not implemented\n");
        }
        pl080_run(s);
        break;
    case 13: /* Sync */
        s->sync = value;
        break;
    default:
    bad_offset:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl080_write: Bad offset %x\n", (int)offset);
    }
    pl080_update(s);
}

static const MemoryRegionOps pl080_ops = {
    .read = pl080_read,
    .write = pl080_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pl080_init(Object *obj)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    PL080State *s = PL080(obj);

    memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
    sysbus_init_irq(sbd, &s->interr);
    sysbus_init_irq(sbd, &s->inttc);
    s->nchannels = 8;
}

static void pl081_init(Object *obj)
{
    PL080State *s = PL080(obj);

    s->nchannels = 2;
}

static void pl080_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->vmsd = &vmstate_pl080;
}

static const TypeInfo pl080_info = {
    .name          = TYPE_PL080,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PL080State),
    .instance_init = pl080_init,
    .class_init    = pl080_class_init,
};

static const TypeInfo pl081_info = {
    .name          = TYPE_PL081,
    .parent        = TYPE_PL080,
    .instance_init = pl081_init,
};

/* The PL080 and PL081 are the same except for the number of channels
   they implement (8 and 2 respectively).  */
static void pl080_register_types(void)
{
    type_register_static(&pl080_info);
    type_register_static(&pl081_info);
}

type_init(pl080_register_types)
Commit	Line	Data
5fafdf24	1	/*
e69954b9	2	* Arm PrimeCell PL080/PL081 DMA controller
cdbdb648 PB	3	*
	4	* Copyright (c) 2006 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
cdbdb648 PB	8	*/
cdbdb648 PB	9
8ef94f0b	10	#include "qemu/osdep.h"
83c9f4ca	11	#include "hw/sysbus.h"
fdfba1a2	12	#include "exec/address-spaces.h"
03dd024f	13	#include "qemu/log.h"
aa74e355	14	#include "hw/dma/pl080.h"
cdbdb648	15
cdbdb648 PB	16	#define PL080_CONF_E 0x1
	17	#define PL080_CONF_M1 0x2
	18	#define PL080_CONF_M2 0x4
	19
	20	#define PL080_CCONF_H 0x40000
	21	#define PL080_CCONF_A 0x20000
	22	#define PL080_CCONF_L 0x10000
	23	#define PL080_CCONF_ITC 0x08000
	24	#define PL080_CCONF_IE 0x04000
	25	#define PL080_CCONF_E 0x00001
	26
	27	#define PL080_CCTRL_I 0x80000000
	28	#define PL080_CCTRL_DI 0x08000000
	29	#define PL080_CCTRL_SI 0x04000000
	30	#define PL080_CCTRL_D 0x02000000
	31	#define PL080_CCTRL_S 0x01000000
	32
ff175853 PM	33	static const VMStateDescription vmstate_pl080_channel = {
	34	.name = "pl080_channel",
	35	.version_id = 1,
	36	.minimum_version_id = 1,
	37	.fields = (VMStateField[]) {
	38	VMSTATE_UINT32(src, pl080_channel),
	39	VMSTATE_UINT32(dest, pl080_channel),
	40	VMSTATE_UINT32(lli, pl080_channel),
	41	VMSTATE_UINT32(ctrl, pl080_channel),
	42	VMSTATE_UINT32(conf, pl080_channel),
	43	VMSTATE_END_OF_LIST()
	44	}
	45	};
	46
	47	static const VMStateDescription vmstate_pl080 = {
	48	.name = "pl080",
	49	.version_id = 1,
	50	.minimum_version_id = 1,
	51	.fields = (VMStateField[]) {
d7ba0a62 AF	52	VMSTATE_UINT8(tc_int, PL080State),
	53	VMSTATE_UINT8(tc_mask, PL080State),
	54	VMSTATE_UINT8(err_int, PL080State),
	55	VMSTATE_UINT8(err_mask, PL080State),
	56	VMSTATE_UINT32(conf, PL080State),
	57	VMSTATE_UINT32(sync, PL080State),
	58	VMSTATE_UINT32(req_single, PL080State),
	59	VMSTATE_UINT32(req_burst, PL080State),
	60	VMSTATE_UINT8(tc_int, PL080State),
	61	VMSTATE_UINT8(tc_int, PL080State),
	62	VMSTATE_UINT8(tc_int, PL080State),
	63	VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS,
ff175853	64	1, vmstate_pl080_channel, pl080_channel),
d7ba0a62	65	VMSTATE_INT32(running, PL080State),
ff175853 PM	66	VMSTATE_END_OF_LIST()
	67	}
	68	};
	69
cdbdb648 PB	70	static const unsigned char pl080_id[] =
	71	{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
	72
e69954b9 PB	73	static const unsigned char pl081_id[] =
	74	{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
	75
d7ba0a62	76	static void pl080_update(PL080State *s)
cdbdb648	77	{
6d0ed6ba PM	78	bool tclevel = (s->tc_int & s->tc_mask);
	79	bool errlevel = (s->err_int & s->err_mask);
	80
	81	qemu_set_irq(s->interr, errlevel);
	82	qemu_set_irq(s->inttc, tclevel);
	83	qemu_set_irq(s->irq, errlevel \|\| tclevel);
cdbdb648 PB	84	}
cdbdb648 PB	85
d7ba0a62	86	static void pl080_run(PL080State *s)
cdbdb648 PB	87	{
	88	int c;
	89	int flow;
	90	pl080_channel *ch;
	91	int swidth;
	92	int dwidth;
	93	int xsize;
	94	int n;
	95	int src_id;
	96	int dest_id;
	97	int size;
b55266b5	98	uint8_t buff[4];
cdbdb648 PB	99	uint32_t req;
	100
	101	s->tc_mask = 0;
e69954b9	102	for (c = 0; c < s->nchannels; c++) {
cdbdb648 PB	103	if (s->chan[c].conf & PL080_CCONF_ITC)
	104	s->tc_mask \|= 1 << c;
	105	if (s->chan[c].conf & PL080_CCONF_IE)
	106	s->err_mask \|= 1 << c;
	107	}
	108
	109	if ((s->conf & PL080_CONF_E) == 0)
	110	return;
	111
2ac71179	112	hw_error("DMA active\n");
cdbdb648 PB	113	/* If we are already in the middle of a DMA operation then indicate that
	114	there may be new DMA requests and return immediately. */
	115	if (s->running) {
	116	s->running++;
	117	return;
	118	}
	119	s->running = 1;
	120	while (s->running) {
e69954b9	121	for (c = 0; c < s->nchannels; c++) {
cdbdb648 PB	122	ch = &s->chan[c];
	123	again:
	124	/* Test if thiws channel has any pending DMA requests. */
	125	if ((ch->conf & (PL080_CCONF_H \| PL080_CCONF_E))
	126	!= PL080_CCONF_E)
	127	continue;
	128	flow = (ch->conf >> 11) & 7;
	129	if (flow >= 4) {
2ac71179	130	hw_error(
cdbdb648 PB	131	"pl080_run: Peripheral flow control not implemented\n");
	132	}
	133	src_id = (ch->conf >> 1) & 0x1f;
	134	dest_id = (ch->conf >> 6) & 0x1f;
	135	size = ch->ctrl & 0xfff;
	136	req = s->req_single \| s->req_burst;
	137	switch (flow) {
	138	case 0:
	139	break;
	140	case 1:
	141	if ((req & (1u << dest_id)) == 0)
	142	size = 0;
	143	break;
	144	case 2:
	145	if ((req & (1u << src_id)) == 0)
	146	size = 0;
	147	break;
	148	case 3:
	149	if ((req & (1u << src_id)) == 0
	150	\|\| (req & (1u << dest_id)) == 0)
	151	size = 0;
	152	break;
	153	}
	154	if (!size)
	155	continue;
	156
	157	/* Transfer one element. */
	158	/* ??? Should transfer multiple elements for a burst request. */
	159	/* ??? Unclear what the proper behavior is when source and
	160	destination widths are different. */
	161	swidth = 1 << ((ch->ctrl >> 18) & 7);
	162	dwidth = 1 << ((ch->ctrl >> 21) & 7);
	163	for (n = 0; n < dwidth; n+= swidth) {
	164	cpu_physical_memory_read(ch->src, buff + n, swidth);
	165	if (ch->ctrl & PL080_CCTRL_SI)
	166	ch->src += swidth;
	167	}
	168	xsize = (dwidth < swidth) ? swidth : dwidth;
	169	/* ??? This may pad the value incorrectly for dwidth < 32. */
	170	for (n = 0; n < xsize; n += dwidth) {
	171	cpu_physical_memory_write(ch->dest + n, buff + n, dwidth);
	172	if (ch->ctrl & PL080_CCTRL_DI)
	173	ch->dest += swidth;
	174	}
	175
	176	size--;
	177	ch->ctrl = (ch->ctrl & 0xfffff000) \| size;
	178	if (size == 0) {
	179	/* Transfer complete. */
	180	if (ch->lli) {
42874d3a PM	181	ch->src = address_space_ldl_le(&address_space_memory,
	182	ch->lli,
	183	MEMTXATTRS_UNSPECIFIED,
	184	NULL);
	185	ch->dest = address_space_ldl_le(&address_space_memory,
	186	ch->lli + 4,
	187	MEMTXATTRS_UNSPECIFIED,
	188	NULL);
	189	ch->ctrl = address_space_ldl_le(&address_space_memory,
	190	ch->lli + 12,
	191	MEMTXATTRS_UNSPECIFIED,
	192	NULL);
	193	ch->lli = address_space_ldl_le(&address_space_memory,
	194	ch->lli + 8,
	195	MEMTXATTRS_UNSPECIFIED,
	196	NULL);
cdbdb648 PB	197	} else {
	198	ch->conf &= ~PL080_CCONF_E;
	199	}
	200	if (ch->ctrl & PL080_CCTRL_I) {
	201	s->tc_int \|= 1 << c;
	202	}
	203	}
	204	goto again;
	205	}
	206	if (--s->running)
	207	s->running = 1;
	208	}
	209	}
	210
a8170e5e	211	static uint64_t pl080_read(void *opaque, hwaddr offset,
63b02e04	212	unsigned size)
cdbdb648	213	{
d7ba0a62	214	PL080State s = (PL080State )opaque;
cdbdb648 PB	215	uint32_t i;
	216	uint32_t mask;
	217
cdbdb648	218	if (offset >= 0xfe0 && offset < 0x1000) {
e69954b9 PB	219	if (s->nchannels == 8) {
	220	return pl080_id[(offset - 0xfe0) >> 2];
	221	} else {
	222	return pl081_id[(offset - 0xfe0) >> 2];
	223	}
cdbdb648 PB	224	}
	225	if (offset >= 0x100 && offset < 0x200) {
	226	i = (offset & 0xe0) >> 5;
e69954b9 PB	227	if (i >= s->nchannels)
e69954b9 PB	228	goto bad_offset;
cdbdb648 PB	229	switch (offset >> 2) {
	230	case 0: /* SrcAddr */
	231	return s->chan[i].src;
	232	case 1: /* DestAddr */
	233	return s->chan[i].dest;
	234	case 2: /* LLI */
	235	return s->chan[i].lli;
	236	case 3: /* Control */
	237	return s->chan[i].ctrl;
	238	case 4: /* Configuration */
	239	return s->chan[i].conf;
	240	default:
	241	goto bad_offset;
	242	}
	243	}
	244	switch (offset >> 2) {
	245	case 0: /* IntStatus */
	246	return (s->tc_int & s->tc_mask) \| (s->err_int & s->err_mask);
	247	case 1: /* IntTCStatus */
	248	return (s->tc_int & s->tc_mask);
	249	case 3: /* IntErrorStatus */
	250	return (s->err_int & s->err_mask);
	251	case 5: /* RawIntTCStatus */
	252	return s->tc_int;
	253	case 6: /* RawIntErrorStatus */
	254	return s->err_int;
	255	case 7: /* EnbldChns */
	256	mask = 0;
e69954b9	257	for (i = 0; i < s->nchannels; i++) {
cdbdb648 PB	258	if (s->chan[i].conf & PL080_CCONF_E)
	259	mask \|= 1 << i;
	260	}
	261	return mask;
	262	case 8: /* SoftBReq */
	263	case 9: /* SoftSReq */
	264	case 10: /* SoftLBReq */
	265	case 11: /* SoftLSReq */
	266	/* ??? Implement these. */
	267	return 0;
	268	case 12: /* Configuration */
	269	return s->conf;
	270	case 13: /* Sync */
	271	return s->sync;
	272	default:
	273	bad_offset:
df374162 PM	274	qemu_log_mask(LOG_GUEST_ERROR,
df374162 PM	275	"pl080_read: Bad offset %x\n", (int)offset);
cdbdb648 PB	276	return 0;
	277	}
	278	}
	279
a8170e5e	280	static void pl080_write(void *opaque, hwaddr offset,
63b02e04	281	uint64_t value, unsigned size)
cdbdb648	282	{
d7ba0a62	283	PL080State s = (PL080State )opaque;
cdbdb648 PB	284	int i;
cdbdb648 PB	285
cdbdb648 PB	286	if (offset >= 0x100 && offset < 0x200) {
cdbdb648 PB	287	i = (offset & 0xe0) >> 5;
e69954b9 PB	288	if (i >= s->nchannels)
e69954b9 PB	289	goto bad_offset;
cdbdb648 PB	290	switch (offset >> 2) {
	291	case 0: /* SrcAddr */
	292	s->chan[i].src = value;
	293	break;
	294	case 1: /* DestAddr */
	295	s->chan[i].dest = value;
	296	break;
	297	case 2: /* LLI */
	298	s->chan[i].lli = value;
	299	break;
	300	case 3: /* Control */
	301	s->chan[i].ctrl = value;
	302	break;
	303	case 4: /* Configuration */
	304	s->chan[i].conf = value;
	305	pl080_run(s);
	306	break;
	307	}
	308	}
	309	switch (offset >> 2) {
	310	case 2: /* IntTCClear */
	311	s->tc_int &= ~value;
	312	break;
	313	case 4: /* IntErrorClear */
	314	s->err_int &= ~value;
	315	break;
	316	case 8: /* SoftBReq */
	317	case 9: /* SoftSReq */
	318	case 10: /* SoftLBReq */
	319	case 11: /* SoftLSReq */
	320	/* ??? Implement these. */
df374162	321	qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n");
cdbdb648 PB	322	break;
	323	case 12: /* Configuration */
	324	s->conf = value;
04bb79d1	325	if (s->conf & (PL080_CONF_M1 \| PL080_CONF_M2)) {
df374162 PM	326	qemu_log_mask(LOG_UNIMP,
df374162 PM	327	"pl080_write: Big-endian DMA not implemented\n");
cdbdb648 PB	328	}
	329	pl080_run(s);
	330	break;
	331	case 13: /* Sync */
	332	s->sync = value;
	333	break;
	334	default:
e69954b9	335	bad_offset:
df374162 PM	336	qemu_log_mask(LOG_GUEST_ERROR,
df374162 PM	337	"pl080_write: Bad offset %x\n", (int)offset);
cdbdb648 PB	338	}
	339	pl080_update(s);
	340	}
	341
63b02e04 AK	342	static const MemoryRegionOps pl080_ops = {
	343	.read = pl080_read,
	344	.write = pl080_write,
	345	.endianness = DEVICE_NATIVE_ENDIAN,
cdbdb648 PB	346	};
cdbdb648 PB	347
4f800554	348	static void pl080_init(Object *obj)
cdbdb648	349	{
4f800554 AF	350	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
4f800554 AF	351	PL080State *s = PL080(obj);
cdbdb648	352
3eadad55	353	memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);
4f800554 AF	354	sysbus_init_mmio(sbd, &s->iomem);
4f800554 AF	355	sysbus_init_irq(sbd, &s->irq);
6d0ed6ba PM	356	sysbus_init_irq(sbd, &s->interr);
6d0ed6ba PM	357	sysbus_init_irq(sbd, &s->inttc);
4f800554	358	s->nchannels = 8;
cdbdb648	359	}
b4496b13	360
4f800554	361	static void pl081_init(Object *obj)
b4496b13	362	{
4f800554	363	PL080State *s = PL080(obj);
b4496b13	364
4f800554	365	s->nchannels = 2;
b4496b13 PB	366	}
b4496b13 PB	367
4f800554	368	static void pl080_class_init(ObjectClass oc, void data)
999e12bb	369	{
4f800554	370	DeviceClass *dc = DEVICE_CLASS(oc);
999e12bb	371
39bffca2	372	dc->vmsd = &vmstate_pl080;
999e12bb AL	373	}
999e12bb AL	374
8c43a6f0	375	static const TypeInfo pl080_info = {
4f800554	376	.name = TYPE_PL080,
39bffca2	377	.parent = TYPE_SYS_BUS_DEVICE,
d7ba0a62	378	.instance_size = sizeof(PL080State),
4f800554	379	.instance_init = pl080_init,
39bffca2	380	.class_init = pl080_class_init,
ff175853 PM	381	};
ff175853 PM	382
8c43a6f0	383	static const TypeInfo pl081_info = {
aa74e355	384	.name = TYPE_PL081,
4f800554 AF	385	.parent = TYPE_PL080,
4f800554 AF	386	.instance_init = pl081_init,
ff175853 PM	387	};
ff175853 PM	388
b4496b13 PB	389	/* The PL080 and PL081 are the same except for the number of channels
b4496b13 PB	390	they implement (8 and 2 respectively). */
83f7d43a	391	static void pl080_register_types(void)
b4496b13	392	{
39bffca2 AL	393	type_register_static(&pl080_info);
39bffca2 AL	394	type_register_static(&pl081_info);
b4496b13 PB	395	}
b4496b13 PB	396
83f7d43a	397	type_init(pl080_register_types)