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Commit | Line | Data |
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c1713132 AZ |
1 | /* |
2 | * Intel XScale PXA255/270 DMA controller. | |
3 | * | |
4 | * Copyright (c) 2006 Openedhand Ltd. | |
5 | * Copyright (c) 2006 Thorsten Zitterell | |
6 | * Written by Andrzej Zaborowski <balrog@zabor.org> | |
7 | * | |
8e31bf38 | 8 | * This code is licensed under the GPL. |
c1713132 AZ |
9 | */ |
10 | ||
8ef94f0b | 11 | #include "qemu/osdep.h" |
83c9f4ca | 12 | #include "hw/hw.h" |
64552b6b | 13 | #include "hw/irq.h" |
0d09e41a | 14 | #include "hw/arm/pxa.h" |
83c9f4ca | 15 | #include "hw/sysbus.h" |
d6454270 | 16 | #include "migration/vmstate.h" |
c9796d71 | 17 | #include "qapi/error.h" |
0b8fa32f | 18 | #include "qemu/module.h" |
2115c019 AZ |
19 | |
20 | #define PXA255_DMA_NUM_CHANNELS 16 | |
21 | #define PXA27X_DMA_NUM_CHANNELS 32 | |
22 | ||
23 | #define PXA2XX_DMA_NUM_REQUESTS 75 | |
c1713132 | 24 | |
bc24a225 | 25 | typedef struct { |
a10394e1 MI |
26 | uint32_t descr; |
27 | uint32_t src; | |
28 | uint32_t dest; | |
c1713132 AZ |
29 | uint32_t cmd; |
30 | uint32_t state; | |
31 | int request; | |
bc24a225 | 32 | } PXA2xxDMAChannel; |
c1713132 | 33 | |
358cd7ac AF |
34 | #define TYPE_PXA2XX_DMA "pxa2xx-dma" |
35 | #define PXA2XX_DMA(obj) OBJECT_CHECK(PXA2xxDMAState, (obj), TYPE_PXA2XX_DMA) | |
36 | ||
2115c019 | 37 | typedef struct PXA2xxDMAState { |
358cd7ac AF |
38 | SysBusDevice parent_obj; |
39 | ||
00049a12 | 40 | MemoryRegion iomem; |
c1713132 AZ |
41 | qemu_irq irq; |
42 | ||
43 | uint32_t stopintr; | |
44 | uint32_t eorintr; | |
45 | uint32_t rasintr; | |
46 | uint32_t startintr; | |
47 | uint32_t endintr; | |
48 | ||
49 | uint32_t align; | |
50 | uint32_t pio; | |
51 | ||
52 | int channels; | |
bc24a225 | 53 | PXA2xxDMAChannel *chan; |
c1713132 | 54 | |
2115c019 | 55 | uint8_t req[PXA2XX_DMA_NUM_REQUESTS]; |
c1713132 AZ |
56 | |
57 | /* Flag to avoid recursive DMA invocations. */ | |
58 | int running; | |
2115c019 | 59 | } PXA2xxDMAState; |
c1713132 AZ |
60 | |
61 | #define DCSR0 0x0000 /* DMA Control / Status register for Channel 0 */ | |
62 | #define DCSR31 0x007c /* DMA Control / Status register for Channel 31 */ | |
63 | #define DALGN 0x00a0 /* DMA Alignment register */ | |
64 | #define DPCSR 0x00a4 /* DMA Programmed I/O Control Status register */ | |
65 | #define DRQSR0 0x00e0 /* DMA DREQ<0> Status register */ | |
66 | #define DRQSR1 0x00e4 /* DMA DREQ<1> Status register */ | |
67 | #define DRQSR2 0x00e8 /* DMA DREQ<2> Status register */ | |
68 | #define DINT 0x00f0 /* DMA Interrupt register */ | |
69 | #define DRCMR0 0x0100 /* Request to Channel Map register 0 */ | |
70 | #define DRCMR63 0x01fc /* Request to Channel Map register 63 */ | |
71 | #define D_CH0 0x0200 /* Channel 0 Descriptor start */ | |
72 | #define DRCMR64 0x1100 /* Request to Channel Map register 64 */ | |
73 | #define DRCMR74 0x1128 /* Request to Channel Map register 74 */ | |
74 | ||
75 | /* Per-channel register */ | |
76 | #define DDADR 0x00 | |
77 | #define DSADR 0x01 | |
78 | #define DTADR 0x02 | |
79 | #define DCMD 0x03 | |
80 | ||
81 | /* Bit-field masks */ | |
82 | #define DRCMR_CHLNUM 0x1f | |
83 | #define DRCMR_MAPVLD (1 << 7) | |
84 | #define DDADR_STOP (1 << 0) | |
85 | #define DDADR_BREN (1 << 1) | |
86 | #define DCMD_LEN 0x1fff | |
87 | #define DCMD_WIDTH(x) (1 << ((((x) >> 14) & 3) - 1)) | |
88 | #define DCMD_SIZE(x) (4 << (((x) >> 16) & 3)) | |
89 | #define DCMD_FLYBYT (1 << 19) | |
90 | #define DCMD_FLYBYS (1 << 20) | |
91 | #define DCMD_ENDIRQEN (1 << 21) | |
92 | #define DCMD_STARTIRQEN (1 << 22) | |
93 | #define DCMD_CMPEN (1 << 25) | |
94 | #define DCMD_FLOWTRG (1 << 28) | |
95 | #define DCMD_FLOWSRC (1 << 29) | |
96 | #define DCMD_INCTRGADDR (1 << 30) | |
97 | #define DCMD_INCSRCADDR (1 << 31) | |
98 | #define DCSR_BUSERRINTR (1 << 0) | |
99 | #define DCSR_STARTINTR (1 << 1) | |
100 | #define DCSR_ENDINTR (1 << 2) | |
101 | #define DCSR_STOPINTR (1 << 3) | |
102 | #define DCSR_RASINTR (1 << 4) | |
103 | #define DCSR_REQPEND (1 << 8) | |
104 | #define DCSR_EORINT (1 << 9) | |
105 | #define DCSR_CMPST (1 << 10) | |
106 | #define DCSR_MASKRUN (1 << 22) | |
107 | #define DCSR_RASIRQEN (1 << 23) | |
108 | #define DCSR_CLRCMPST (1 << 24) | |
109 | #define DCSR_SETCMPST (1 << 25) | |
110 | #define DCSR_EORSTOPEN (1 << 26) | |
111 | #define DCSR_EORJMPEN (1 << 27) | |
112 | #define DCSR_EORIRQEN (1 << 28) | |
113 | #define DCSR_STOPIRQEN (1 << 29) | |
114 | #define DCSR_NODESCFETCH (1 << 30) | |
115 | #define DCSR_RUN (1 << 31) | |
116 | ||
bc24a225 | 117 | static inline void pxa2xx_dma_update(PXA2xxDMAState *s, int ch) |
c1713132 AZ |
118 | { |
119 | if (ch >= 0) { | |
120 | if ((s->chan[ch].state & DCSR_STOPIRQEN) && | |
121 | (s->chan[ch].state & DCSR_STOPINTR)) | |
122 | s->stopintr |= 1 << ch; | |
123 | else | |
124 | s->stopintr &= ~(1 << ch); | |
125 | ||
126 | if ((s->chan[ch].state & DCSR_EORIRQEN) && | |
127 | (s->chan[ch].state & DCSR_EORINT)) | |
128 | s->eorintr |= 1 << ch; | |
129 | else | |
130 | s->eorintr &= ~(1 << ch); | |
131 | ||
132 | if ((s->chan[ch].state & DCSR_RASIRQEN) && | |
133 | (s->chan[ch].state & DCSR_RASINTR)) | |
134 | s->rasintr |= 1 << ch; | |
135 | else | |
136 | s->rasintr &= ~(1 << ch); | |
137 | ||
138 | if (s->chan[ch].state & DCSR_STARTINTR) | |
139 | s->startintr |= 1 << ch; | |
140 | else | |
141 | s->startintr &= ~(1 << ch); | |
142 | ||
143 | if (s->chan[ch].state & DCSR_ENDINTR) | |
144 | s->endintr |= 1 << ch; | |
145 | else | |
146 | s->endintr &= ~(1 << ch); | |
147 | } | |
148 | ||
149 | if (s->stopintr | s->eorintr | s->rasintr | s->startintr | s->endintr) | |
150 | qemu_irq_raise(s->irq); | |
151 | else | |
152 | qemu_irq_lower(s->irq); | |
153 | } | |
154 | ||
155 | static inline void pxa2xx_dma_descriptor_fetch( | |
bc24a225 | 156 | PXA2xxDMAState *s, int ch) |
c1713132 AZ |
157 | { |
158 | uint32_t desc[4]; | |
a8170e5e | 159 | hwaddr daddr = s->chan[ch].descr & ~0xf; |
c1713132 AZ |
160 | if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST)) |
161 | daddr += 32; | |
162 | ||
e1fe50dc | 163 | cpu_physical_memory_read(daddr, desc, 16); |
c1713132 AZ |
164 | s->chan[ch].descr = desc[DDADR]; |
165 | s->chan[ch].src = desc[DSADR]; | |
166 | s->chan[ch].dest = desc[DTADR]; | |
167 | s->chan[ch].cmd = desc[DCMD]; | |
168 | ||
169 | if (s->chan[ch].cmd & DCMD_FLOWSRC) | |
170 | s->chan[ch].src &= ~3; | |
171 | if (s->chan[ch].cmd & DCMD_FLOWTRG) | |
172 | s->chan[ch].dest &= ~3; | |
173 | ||
174 | if (s->chan[ch].cmd & (DCMD_CMPEN | DCMD_FLYBYS | DCMD_FLYBYT)) | |
a89f364a | 175 | printf("%s: unsupported mode in channel %i\n", __func__, ch); |
c1713132 AZ |
176 | |
177 | if (s->chan[ch].cmd & DCMD_STARTIRQEN) | |
178 | s->chan[ch].state |= DCSR_STARTINTR; | |
179 | } | |
180 | ||
bc24a225 | 181 | static void pxa2xx_dma_run(PXA2xxDMAState *s) |
c1713132 AZ |
182 | { |
183 | int c, srcinc, destinc; | |
184 | uint32_t n, size; | |
185 | uint32_t width; | |
186 | uint32_t length; | |
b55266b5 | 187 | uint8_t buffer[32]; |
bc24a225 | 188 | PXA2xxDMAChannel *ch; |
c1713132 AZ |
189 | |
190 | if (s->running ++) | |
191 | return; | |
192 | ||
193 | while (s->running) { | |
194 | s->running = 1; | |
195 | for (c = 0; c < s->channels; c ++) { | |
196 | ch = &s->chan[c]; | |
197 | ||
198 | while ((ch->state & DCSR_RUN) && !(ch->state & DCSR_STOPINTR)) { | |
199 | /* Test for pending requests */ | |
200 | if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request) | |
201 | break; | |
202 | ||
203 | length = ch->cmd & DCMD_LEN; | |
204 | size = DCMD_SIZE(ch->cmd); | |
205 | width = DCMD_WIDTH(ch->cmd); | |
206 | ||
207 | srcinc = (ch->cmd & DCMD_INCSRCADDR) ? width : 0; | |
208 | destinc = (ch->cmd & DCMD_INCTRGADDR) ? width : 0; | |
209 | ||
210 | while (length) { | |
211 | size = MIN(length, size); | |
212 | ||
213 | for (n = 0; n < size; n += width) { | |
214 | cpu_physical_memory_read(ch->src, buffer + n, width); | |
215 | ch->src += srcinc; | |
216 | } | |
217 | ||
218 | for (n = 0; n < size; n += width) { | |
219 | cpu_physical_memory_write(ch->dest, buffer + n, width); | |
220 | ch->dest += destinc; | |
221 | } | |
222 | ||
223 | length -= size; | |
224 | ||
225 | if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && | |
226 | !ch->request) { | |
227 | ch->state |= DCSR_EORINT; | |
228 | if (ch->state & DCSR_EORSTOPEN) | |
229 | ch->state |= DCSR_STOPINTR; | |
230 | if ((ch->state & DCSR_EORJMPEN) && | |
231 | !(ch->state & DCSR_NODESCFETCH)) | |
232 | pxa2xx_dma_descriptor_fetch(s, c); | |
233 | break; | |
7d37435b | 234 | } |
c1713132 AZ |
235 | } |
236 | ||
237 | ch->cmd = (ch->cmd & ~DCMD_LEN) | length; | |
238 | ||
239 | /* Is the transfer complete now? */ | |
240 | if (!length) { | |
241 | if (ch->cmd & DCMD_ENDIRQEN) | |
242 | ch->state |= DCSR_ENDINTR; | |
243 | ||
244 | if ((ch->state & DCSR_NODESCFETCH) || | |
245 | (ch->descr & DDADR_STOP) || | |
246 | (ch->state & DCSR_EORSTOPEN)) { | |
247 | ch->state |= DCSR_STOPINTR; | |
248 | ch->state &= ~DCSR_RUN; | |
249 | ||
250 | break; | |
251 | } | |
252 | ||
253 | ch->state |= DCSR_STOPINTR; | |
254 | break; | |
255 | } | |
256 | } | |
257 | } | |
258 | ||
259 | s->running --; | |
260 | } | |
261 | } | |
262 | ||
a8170e5e | 263 | static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset, |
00049a12 | 264 | unsigned size) |
c1713132 | 265 | { |
bc24a225 | 266 | PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; |
c1713132 | 267 | unsigned int channel; |
c1713132 | 268 | |
00049a12 | 269 | if (size != 4) { |
a89f364a | 270 | hw_error("%s: Bad access width\n", __func__); |
00049a12 AK |
271 | return 5; |
272 | } | |
273 | ||
c1713132 AZ |
274 | switch (offset) { |
275 | case DRCMR64 ... DRCMR74: | |
276 | offset -= DRCMR64 - DRCMR0 - (64 << 2); | |
277 | /* Fall through */ | |
278 | case DRCMR0 ... DRCMR63: | |
279 | channel = (offset - DRCMR0) >> 2; | |
280 | return s->req[channel]; | |
281 | ||
282 | case DRQSR0: | |
283 | case DRQSR1: | |
284 | case DRQSR2: | |
285 | return 0; | |
286 | ||
287 | case DCSR0 ... DCSR31: | |
288 | channel = offset >> 2; | |
7d37435b | 289 | if (s->chan[channel].request) |
c1713132 AZ |
290 | return s->chan[channel].state | DCSR_REQPEND; |
291 | return s->chan[channel].state; | |
292 | ||
293 | case DINT: | |
294 | return s->stopintr | s->eorintr | s->rasintr | | |
295 | s->startintr | s->endintr; | |
296 | ||
297 | case DALGN: | |
298 | return s->align; | |
299 | ||
300 | case DPCSR: | |
301 | return s->pio; | |
302 | } | |
303 | ||
304 | if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) { | |
305 | channel = (offset - D_CH0) >> 4; | |
306 | switch ((offset & 0x0f) >> 2) { | |
307 | case DDADR: | |
308 | return s->chan[channel].descr; | |
309 | case DSADR: | |
310 | return s->chan[channel].src; | |
311 | case DTADR: | |
312 | return s->chan[channel].dest; | |
313 | case DCMD: | |
314 | return s->chan[channel].cmd; | |
315 | } | |
316 | } | |
317 | ||
a89f364a | 318 | hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); |
c1713132 AZ |
319 | return 7; |
320 | } | |
321 | ||
a8170e5e | 322 | static void pxa2xx_dma_write(void *opaque, hwaddr offset, |
00049a12 | 323 | uint64_t value, unsigned size) |
c1713132 | 324 | { |
bc24a225 | 325 | PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; |
c1713132 | 326 | unsigned int channel; |
c1713132 | 327 | |
00049a12 | 328 | if (size != 4) { |
a89f364a | 329 | hw_error("%s: Bad access width\n", __func__); |
00049a12 AK |
330 | return; |
331 | } | |
332 | ||
c1713132 AZ |
333 | switch (offset) { |
334 | case DRCMR64 ... DRCMR74: | |
335 | offset -= DRCMR64 - DRCMR0 - (64 << 2); | |
336 | /* Fall through */ | |
337 | case DRCMR0 ... DRCMR63: | |
338 | channel = (offset - DRCMR0) >> 2; | |
339 | ||
340 | if (value & DRCMR_MAPVLD) | |
341 | if ((value & DRCMR_CHLNUM) > s->channels) | |
2ac71179 | 342 | hw_error("%s: Bad DMA channel %i\n", |
a89f364a | 343 | __func__, (unsigned)value & DRCMR_CHLNUM); |
c1713132 AZ |
344 | |
345 | s->req[channel] = value; | |
346 | break; | |
347 | ||
348 | case DRQSR0: | |
349 | case DRQSR1: | |
350 | case DRQSR2: | |
351 | /* Nothing to do */ | |
352 | break; | |
353 | ||
354 | case DCSR0 ... DCSR31: | |
355 | channel = offset >> 2; | |
356 | s->chan[channel].state &= 0x0000071f & ~(value & | |
357 | (DCSR_EORINT | DCSR_ENDINTR | | |
358 | DCSR_STARTINTR | DCSR_BUSERRINTR)); | |
359 | s->chan[channel].state |= value & 0xfc800000; | |
360 | ||
361 | if (s->chan[channel].state & DCSR_STOPIRQEN) | |
362 | s->chan[channel].state &= ~DCSR_STOPINTR; | |
363 | ||
364 | if (value & DCSR_NODESCFETCH) { | |
365 | /* No-descriptor-fetch mode */ | |
e1dad5a6 AZ |
366 | if (value & DCSR_RUN) { |
367 | s->chan[channel].state &= ~DCSR_STOPINTR; | |
c1713132 | 368 | pxa2xx_dma_run(s); |
e1dad5a6 | 369 | } |
c1713132 AZ |
370 | } else { |
371 | /* Descriptor-fetch mode */ | |
372 | if (value & DCSR_RUN) { | |
373 | s->chan[channel].state &= ~DCSR_STOPINTR; | |
374 | pxa2xx_dma_descriptor_fetch(s, channel); | |
375 | pxa2xx_dma_run(s); | |
376 | } | |
377 | } | |
378 | ||
379 | /* Shouldn't matter as our DMA is synchronous. */ | |
380 | if (!(value & (DCSR_RUN | DCSR_MASKRUN))) | |
381 | s->chan[channel].state |= DCSR_STOPINTR; | |
382 | ||
383 | if (value & DCSR_CLRCMPST) | |
384 | s->chan[channel].state &= ~DCSR_CMPST; | |
385 | if (value & DCSR_SETCMPST) | |
386 | s->chan[channel].state |= DCSR_CMPST; | |
387 | ||
388 | pxa2xx_dma_update(s, channel); | |
389 | break; | |
390 | ||
391 | case DALGN: | |
392 | s->align = value; | |
393 | break; | |
394 | ||
395 | case DPCSR: | |
396 | s->pio = value & 0x80000001; | |
397 | break; | |
398 | ||
399 | default: | |
400 | if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) { | |
401 | channel = (offset - D_CH0) >> 4; | |
402 | switch ((offset & 0x0f) >> 2) { | |
403 | case DDADR: | |
404 | s->chan[channel].descr = value; | |
405 | break; | |
406 | case DSADR: | |
407 | s->chan[channel].src = value; | |
408 | break; | |
409 | case DTADR: | |
410 | s->chan[channel].dest = value; | |
411 | break; | |
412 | case DCMD: | |
413 | s->chan[channel].cmd = value; | |
414 | break; | |
415 | default: | |
416 | goto fail; | |
417 | } | |
418 | ||
419 | break; | |
420 | } | |
421 | fail: | |
a89f364a | 422 | hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __func__, offset); |
c1713132 AZ |
423 | } |
424 | } | |
425 | ||
00049a12 AK |
426 | static const MemoryRegionOps pxa2xx_dma_ops = { |
427 | .read = pxa2xx_dma_read, | |
428 | .write = pxa2xx_dma_write, | |
429 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c1713132 AZ |
430 | }; |
431 | ||
f114c826 AZ |
432 | static void pxa2xx_dma_request(void *opaque, int req_num, int on) |
433 | { | |
434 | PXA2xxDMAState *s = opaque; | |
435 | int ch; | |
436 | if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS) | |
a89f364a | 437 | hw_error("%s: Bad DMA request %i\n", __func__, req_num); |
f114c826 AZ |
438 | |
439 | if (!(s->req[req_num] & DRCMR_MAPVLD)) | |
440 | return; | |
441 | ch = s->req[req_num] & DRCMR_CHLNUM; | |
442 | ||
443 | if (!s->chan[ch].request && on) | |
444 | s->chan[ch].state |= DCSR_RASINTR; | |
445 | else | |
446 | s->chan[ch].state &= ~DCSR_RASINTR; | |
447 | if (s->chan[ch].request && !on) | |
448 | s->chan[ch].state |= DCSR_EORINT; | |
449 | ||
450 | s->chan[ch].request = on; | |
451 | if (on) { | |
452 | pxa2xx_dma_run(s); | |
453 | pxa2xx_dma_update(s, ch); | |
454 | } | |
455 | } | |
aa941b94 | 456 | |
c9796d71 XZ |
457 | static void pxa2xx_dma_init(Object *obj) |
458 | { | |
459 | DeviceState *dev = DEVICE(obj); | |
460 | PXA2xxDMAState *s = PXA2XX_DMA(obj); | |
461 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
462 | ||
463 | memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS); | |
464 | ||
465 | qdev_init_gpio_in(dev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS); | |
466 | ||
467 | memory_region_init_io(&s->iomem, obj, &pxa2xx_dma_ops, s, | |
468 | "pxa2xx.dma", 0x00010000); | |
469 | sysbus_init_mmio(sbd, &s->iomem); | |
470 | sysbus_init_irq(sbd, &s->irq); | |
471 | } | |
472 | ||
473 | static void pxa2xx_dma_realize(DeviceState *dev, Error **errp) | |
c1713132 | 474 | { |
358cd7ac | 475 | PXA2xxDMAState *s = PXA2XX_DMA(dev); |
00049a12 | 476 | int i; |
2115c019 AZ |
477 | |
478 | if (s->channels <= 0) { | |
c9796d71 XZ |
479 | error_setg(errp, "channels value invalid"); |
480 | return; | |
2115c019 | 481 | } |
c1713132 | 482 | |
1a13b272 | 483 | s->chan = g_new0(PXA2xxDMAChannel, s->channels); |
c1713132 | 484 | |
c1713132 AZ |
485 | for (i = 0; i < s->channels; i ++) |
486 | s->chan[i].state = DCSR_STOPINTR; | |
c1713132 AZ |
487 | } |
488 | ||
a8170e5e | 489 | DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq) |
c1713132 | 490 | { |
2115c019 AZ |
491 | DeviceState *dev; |
492 | ||
493 | dev = qdev_create(NULL, "pxa2xx-dma"); | |
494 | qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS); | |
495 | qdev_init_nofail(dev); | |
496 | ||
1356b98d AF |
497 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
498 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); | |
2115c019 AZ |
499 | |
500 | return dev; | |
c1713132 AZ |
501 | } |
502 | ||
a8170e5e | 503 | DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq) |
c1713132 | 504 | { |
2115c019 AZ |
505 | DeviceState *dev; |
506 | ||
507 | dev = qdev_create(NULL, "pxa2xx-dma"); | |
508 | qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS); | |
509 | qdev_init_nofail(dev); | |
510 | ||
1356b98d AF |
511 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
512 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); | |
2115c019 AZ |
513 | |
514 | return dev; | |
c1713132 AZ |
515 | } |
516 | ||
2115c019 AZ |
517 | static bool is_version_0(void *opaque, int version_id) |
518 | { | |
519 | return version_id == 0; | |
520 | } | |
521 | ||
522 | static VMStateDescription vmstate_pxa2xx_dma_chan = { | |
523 | .name = "pxa2xx_dma_chan", | |
524 | .version_id = 1, | |
525 | .minimum_version_id = 1, | |
2115c019 | 526 | .fields = (VMStateField[]) { |
a10394e1 MI |
527 | VMSTATE_UINT32(descr, PXA2xxDMAChannel), |
528 | VMSTATE_UINT32(src, PXA2xxDMAChannel), | |
529 | VMSTATE_UINT32(dest, PXA2xxDMAChannel), | |
2115c019 AZ |
530 | VMSTATE_UINT32(cmd, PXA2xxDMAChannel), |
531 | VMSTATE_UINT32(state, PXA2xxDMAChannel), | |
532 | VMSTATE_INT32(request, PXA2xxDMAChannel), | |
533 | VMSTATE_END_OF_LIST(), | |
534 | }, | |
535 | }; | |
536 | ||
537 | static VMStateDescription vmstate_pxa2xx_dma = { | |
538 | .name = "pxa2xx_dma", | |
539 | .version_id = 1, | |
540 | .minimum_version_id = 0, | |
2115c019 AZ |
541 | .fields = (VMStateField[]) { |
542 | VMSTATE_UNUSED_TEST(is_version_0, 4), | |
543 | VMSTATE_UINT32(stopintr, PXA2xxDMAState), | |
544 | VMSTATE_UINT32(eorintr, PXA2xxDMAState), | |
545 | VMSTATE_UINT32(rasintr, PXA2xxDMAState), | |
546 | VMSTATE_UINT32(startintr, PXA2xxDMAState), | |
547 | VMSTATE_UINT32(endintr, PXA2xxDMAState), | |
548 | VMSTATE_UINT32(align, PXA2xxDMAState), | |
549 | VMSTATE_UINT32(pio, PXA2xxDMAState), | |
550 | VMSTATE_BUFFER(req, PXA2xxDMAState), | |
551 | VMSTATE_STRUCT_VARRAY_POINTER_INT32(chan, PXA2xxDMAState, channels, | |
552 | vmstate_pxa2xx_dma_chan, PXA2xxDMAChannel), | |
553 | VMSTATE_END_OF_LIST(), | |
554 | }, | |
555 | }; | |
556 | ||
999e12bb AL |
557 | static Property pxa2xx_dma_properties[] = { |
558 | DEFINE_PROP_INT32("channels", PXA2xxDMAState, channels, -1), | |
559 | DEFINE_PROP_END_OF_LIST(), | |
560 | }; | |
561 | ||
562 | static void pxa2xx_dma_class_init(ObjectClass *klass, void *data) | |
563 | { | |
39bffca2 | 564 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 565 | |
39bffca2 AL |
566 | dc->desc = "PXA2xx DMA controller"; |
567 | dc->vmsd = &vmstate_pxa2xx_dma; | |
568 | dc->props = pxa2xx_dma_properties; | |
c9796d71 | 569 | dc->realize = pxa2xx_dma_realize; |
999e12bb AL |
570 | } |
571 | ||
8c43a6f0 | 572 | static const TypeInfo pxa2xx_dma_info = { |
358cd7ac | 573 | .name = TYPE_PXA2XX_DMA, |
39bffca2 AL |
574 | .parent = TYPE_SYS_BUS_DEVICE, |
575 | .instance_size = sizeof(PXA2xxDMAState), | |
c9796d71 | 576 | .instance_init = pxa2xx_dma_init, |
39bffca2 | 577 | .class_init = pxa2xx_dma_class_init, |
2115c019 AZ |
578 | }; |
579 | ||
83f7d43a | 580 | static void pxa2xx_dma_register_types(void) |
2115c019 | 581 | { |
39bffca2 | 582 | type_register_static(&pxa2xx_dma_info); |
2115c019 | 583 | } |
83f7d43a AF |
584 | |
585 | type_init(pxa2xx_dma_register_types) |