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7eb0c8e8 BS |
1 | /* |
2 | * QEMU Sparc Sun4m ECC memory controller emulation | |
3 | * | |
4 | * Copyright (c) 2007 Robert Reif | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
49e66373 | 24 | |
7eb0c8e8 | 25 | #include "sun4m.h" |
49e66373 | 26 | #include "sysbus.h" |
7eb0c8e8 BS |
27 | |
28 | //#define DEBUG_ECC | |
29 | ||
30 | #ifdef DEBUG_ECC | |
001faf32 BS |
31 | #define DPRINTF(fmt, ...) \ |
32 | do { printf("ECC: " fmt , ## __VA_ARGS__); } while (0) | |
7eb0c8e8 | 33 | #else |
001faf32 | 34 | #define DPRINTF(fmt, ...) |
7eb0c8e8 BS |
35 | #endif |
36 | ||
37 | /* There are 3 versions of this chip used in SMP sun4m systems: | |
38 | * MCC (version 0, implementation 0) SS-600MP | |
39 | * EMC (version 0, implementation 1) SS-10 | |
40 | * SMC (version 0, implementation 2) SS-10SX and SS-20 | |
41 | */ | |
42 | ||
0bb3602c BS |
43 | #define ECC_MCC 0x00000000 |
44 | #define ECC_EMC 0x10000000 | |
45 | #define ECC_SMC 0x20000000 | |
46 | ||
8f2ad0a3 BS |
47 | /* Register indexes */ |
48 | #define ECC_MER 0 /* Memory Enable Register */ | |
49 | #define ECC_MDR 1 /* Memory Delay Register */ | |
50 | #define ECC_MFSR 2 /* Memory Fault Status Register */ | |
51 | #define ECC_VCR 3 /* Video Configuration Register */ | |
52 | #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */ | |
53 | #define ECC_MFAR1 5 /* Memory Fault Address Register 1 */ | |
54 | #define ECC_DR 6 /* Diagnostic Register */ | |
55 | #define ECC_ECR0 7 /* Event Count Register 0 */ | |
56 | #define ECC_ECR1 8 /* Event Count Register 1 */ | |
7eb0c8e8 BS |
57 | |
58 | /* ECC fault control register */ | |
dd53ded3 | 59 | #define ECC_MER_EE 0x00000001 /* Enable ECC checking */ |
77f193da BS |
60 | #define ECC_MER_EI 0x00000002 /* Enable Interrupts on |
61 | correctable errors */ | |
dd53ded3 BS |
62 | #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */ |
63 | #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */ | |
64 | #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */ | |
65 | #define ECC_MER_MRR3 0x00000020 /* SIMM 3 */ | |
66 | #define ECC_MER_MRR4 0x00000040 /* SIMM 4 */ | |
67 | #define ECC_MER_MRR5 0x00000080 /* SIMM 5 */ | |
68 | #define ECC_MER_MRR6 0x00000100 /* SIMM 6 */ | |
69 | #define ECC_MER_MRR7 0x00000200 /* SIMM 7 */ | |
0bb3602c | 70 | #define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */ |
dd53ded3 | 71 | #define ECC_MER_MRR 0x000003fc /* MRR mask */ |
0bb3602c | 72 | #define ECC_MER_A 0x00000400 /* Memory controller addr map select */ |
77f193da | 73 | #define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */ |
dd53ded3 BS |
74 | #define ECC_MER_VER 0x0f000000 /* Version */ |
75 | #define ECC_MER_IMPL 0xf0000000 /* Implementation */ | |
0bb3602c BS |
76 | #define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */ |
77 | #define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */ | |
78 | #define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */ | |
dd53ded3 BS |
79 | |
80 | /* ECC memory delay register */ | |
81 | #define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */ | |
82 | #define ECC_MDR_MI 0x00001c00 /* MIH Delay */ | |
83 | #define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */ | |
84 | #define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */ | |
85 | #define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */ | |
86 | #define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */ | |
87 | #define ECC_MDR_RSC 0x80000000 /* Refresh load control */ | |
88 | #define ECC_MDR_MASK 0x7fffffff | |
7eb0c8e8 BS |
89 | |
90 | /* ECC fault status register */ | |
dd53ded3 BS |
91 | #define ECC_MFSR_CE 0x00000001 /* Correctable error */ |
92 | #define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */ | |
93 | #define ECC_MFSR_TO 0x00000004 /* Timeout on write */ | |
94 | #define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */ | |
95 | #define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */ | |
96 | #define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */ | |
97 | #define ECC_MFSR_ME 0x00010000 /* Multiple errors */ | |
98 | #define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */ | |
7eb0c8e8 BS |
99 | |
100 | /* ECC fault address register 0 */ | |
dd53ded3 BS |
101 | #define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */ |
102 | #define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */ | |
103 | #define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */ | |
104 | #define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */ | |
105 | #define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */ | |
106 | #define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */ | |
107 | #define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */ | |
108 | #define ECC_MFAR0_S 0x08000000 /* Supervisor mode */ | |
109 | #define ECC_MFARO_MID 0xf0000000 /* Module ID */ | |
7eb0c8e8 BS |
110 | |
111 | /* ECC diagnostic register */ | |
dd53ded3 BS |
112 | #define ECC_DR_CBX 0x00000001 |
113 | #define ECC_DR_CB0 0x00000002 | |
114 | #define ECC_DR_CB1 0x00000004 | |
115 | #define ECC_DR_CB2 0x00000008 | |
116 | #define ECC_DR_CB4 0x00000010 | |
117 | #define ECC_DR_CB8 0x00000020 | |
118 | #define ECC_DR_CB16 0x00000040 | |
119 | #define ECC_DR_CB32 0x00000080 | |
120 | #define ECC_DR_DMODE 0x00000c00 | |
121 | ||
122 | #define ECC_NREGS 9 | |
7eb0c8e8 | 123 | #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t)) |
dd53ded3 BS |
124 | |
125 | #define ECC_DIAG_SIZE 4 | |
126 | #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1) | |
7eb0c8e8 BS |
127 | |
128 | typedef struct ECCState { | |
49e66373 | 129 | SysBusDevice busdev; |
e42c20b4 | 130 | qemu_irq irq; |
7eb0c8e8 | 131 | uint32_t regs[ECC_NREGS]; |
dd53ded3 | 132 | uint8_t diag[ECC_DIAG_SIZE]; |
0bb3602c | 133 | uint32_t version; |
7eb0c8e8 BS |
134 | } ECCState; |
135 | ||
c227f099 | 136 | static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
7eb0c8e8 BS |
137 | { |
138 | ECCState *s = opaque; | |
139 | ||
e64d7d59 | 140 | switch (addr >> 2) { |
dd53ded3 | 141 | case ECC_MER: |
0bb3602c BS |
142 | if (s->version == ECC_MCC) |
143 | s->regs[ECC_MER] = (val & ECC_MER_MASK_0); | |
144 | else if (s->version == ECC_EMC) | |
145 | s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1); | |
146 | else if (s->version == ECC_SMC) | |
147 | s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2); | |
dd53ded3 | 148 | DPRINTF("Write memory enable %08x\n", val); |
7eb0c8e8 | 149 | break; |
dd53ded3 | 150 | case ECC_MDR: |
8f2ad0a3 | 151 | s->regs[ECC_MDR] = val & ECC_MDR_MASK; |
dd53ded3 | 152 | DPRINTF("Write memory delay %08x\n", val); |
7eb0c8e8 | 153 | break; |
dd53ded3 | 154 | case ECC_MFSR: |
8f2ad0a3 | 155 | s->regs[ECC_MFSR] = val; |
0bb3602c | 156 | qemu_irq_lower(s->irq); |
dd53ded3 | 157 | DPRINTF("Write memory fault status %08x\n", val); |
7eb0c8e8 | 158 | break; |
dd53ded3 | 159 | case ECC_VCR: |
8f2ad0a3 | 160 | s->regs[ECC_VCR] = val; |
dd53ded3 | 161 | DPRINTF("Write slot configuration %08x\n", val); |
7eb0c8e8 | 162 | break; |
dd53ded3 | 163 | case ECC_DR: |
8f2ad0a3 | 164 | s->regs[ECC_DR] = val; |
0bb3602c | 165 | DPRINTF("Write diagnostic %08x\n", val); |
dd53ded3 BS |
166 | break; |
167 | case ECC_ECR0: | |
8f2ad0a3 | 168 | s->regs[ECC_ECR0] = val; |
dd53ded3 | 169 | DPRINTF("Write event count 1 %08x\n", val); |
7eb0c8e8 | 170 | break; |
dd53ded3 | 171 | case ECC_ECR1: |
8f2ad0a3 | 172 | s->regs[ECC_ECR0] = val; |
dd53ded3 | 173 | DPRINTF("Write event count 2 %08x\n", val); |
7eb0c8e8 BS |
174 | break; |
175 | } | |
176 | } | |
177 | ||
c227f099 | 178 | static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr) |
7eb0c8e8 BS |
179 | { |
180 | ECCState *s = opaque; | |
181 | uint32_t ret = 0; | |
182 | ||
e64d7d59 | 183 | switch (addr >> 2) { |
dd53ded3 | 184 | case ECC_MER: |
8f2ad0a3 | 185 | ret = s->regs[ECC_MER]; |
dd53ded3 | 186 | DPRINTF("Read memory enable %08x\n", ret); |
7eb0c8e8 | 187 | break; |
dd53ded3 | 188 | case ECC_MDR: |
8f2ad0a3 | 189 | ret = s->regs[ECC_MDR]; |
dd53ded3 | 190 | DPRINTF("Read memory delay %08x\n", ret); |
7eb0c8e8 | 191 | break; |
dd53ded3 | 192 | case ECC_MFSR: |
8f2ad0a3 | 193 | ret = s->regs[ECC_MFSR]; |
dd53ded3 | 194 | DPRINTF("Read memory fault status %08x\n", ret); |
7eb0c8e8 | 195 | break; |
dd53ded3 | 196 | case ECC_VCR: |
8f2ad0a3 | 197 | ret = s->regs[ECC_VCR]; |
dd53ded3 | 198 | DPRINTF("Read slot configuration %08x\n", ret); |
7eb0c8e8 | 199 | break; |
dd53ded3 | 200 | case ECC_MFAR0: |
8f2ad0a3 | 201 | ret = s->regs[ECC_MFAR0]; |
dd53ded3 | 202 | DPRINTF("Read memory fault address 0 %08x\n", ret); |
7eb0c8e8 | 203 | break; |
dd53ded3 | 204 | case ECC_MFAR1: |
8f2ad0a3 | 205 | ret = s->regs[ECC_MFAR1]; |
dd53ded3 | 206 | DPRINTF("Read memory fault address 1 %08x\n", ret); |
7eb0c8e8 | 207 | break; |
dd53ded3 | 208 | case ECC_DR: |
8f2ad0a3 | 209 | ret = s->regs[ECC_DR]; |
dd53ded3 | 210 | DPRINTF("Read diagnostic %08x\n", ret); |
7eb0c8e8 | 211 | break; |
dd53ded3 | 212 | case ECC_ECR0: |
8f2ad0a3 | 213 | ret = s->regs[ECC_ECR0]; |
dd53ded3 BS |
214 | DPRINTF("Read event count 1 %08x\n", ret); |
215 | break; | |
216 | case ECC_ECR1: | |
8f2ad0a3 | 217 | ret = s->regs[ECC_ECR0]; |
dd53ded3 | 218 | DPRINTF("Read event count 2 %08x\n", ret); |
7eb0c8e8 BS |
219 | break; |
220 | } | |
221 | return ret; | |
222 | } | |
223 | ||
d60efc6b | 224 | static CPUReadMemoryFunc * const ecc_mem_read[3] = { |
7c560456 BS |
225 | NULL, |
226 | NULL, | |
7eb0c8e8 BS |
227 | ecc_mem_readl, |
228 | }; | |
229 | ||
d60efc6b | 230 | static CPUWriteMemoryFunc * const ecc_mem_write[3] = { |
7c560456 BS |
231 | NULL, |
232 | NULL, | |
7eb0c8e8 BS |
233 | ecc_mem_writel, |
234 | }; | |
235 | ||
c227f099 | 236 | static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr, |
dd53ded3 BS |
237 | uint32_t val) |
238 | { | |
239 | ECCState *s = opaque; | |
240 | ||
e64d7d59 | 241 | DPRINTF("Write diagnostic[%d] = %02x\n", (int)addr, val); |
dd53ded3 BS |
242 | s->diag[addr & ECC_DIAG_MASK] = val; |
243 | } | |
244 | ||
c227f099 | 245 | static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr) |
dd53ded3 BS |
246 | { |
247 | ECCState *s = opaque; | |
e64d7d59 BS |
248 | uint32_t ret = s->diag[(int)addr]; |
249 | ||
250 | DPRINTF("Read diagnostic[%d] = %02x\n", (int)addr, ret); | |
dd53ded3 BS |
251 | return ret; |
252 | } | |
253 | ||
d60efc6b | 254 | static CPUReadMemoryFunc * const ecc_diag_mem_read[3] = { |
dd53ded3 BS |
255 | ecc_diag_mem_readb, |
256 | NULL, | |
257 | NULL, | |
258 | }; | |
259 | ||
d60efc6b | 260 | static CPUWriteMemoryFunc * const ecc_diag_mem_write[3] = { |
dd53ded3 BS |
261 | ecc_diag_mem_writeb, |
262 | NULL, | |
263 | NULL, | |
264 | }; | |
265 | ||
c21011a9 BS |
266 | static const VMStateDescription vmstate_ecc = { |
267 | .name ="ECC", | |
268 | .version_id = 3, | |
269 | .minimum_version_id = 3, | |
270 | .minimum_version_id_old = 3, | |
271 | .fields = (VMStateField []) { | |
272 | VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS), | |
273 | VMSTATE_BUFFER(diag, ECCState), | |
274 | VMSTATE_UINT32(version, ECCState), | |
275 | VMSTATE_END_OF_LIST() | |
276 | } | |
277 | }; | |
7eb0c8e8 BS |
278 | |
279 | static void ecc_reset(void *opaque) | |
280 | { | |
281 | ECCState *s = opaque; | |
7eb0c8e8 | 282 | |
0bb3602c BS |
283 | if (s->version == ECC_MCC) |
284 | s->regs[ECC_MER] &= ECC_MER_REU; | |
285 | else | |
286 | s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR | | |
287 | ECC_MER_DCI); | |
dd53ded3 BS |
288 | s->regs[ECC_MDR] = 0x20; |
289 | s->regs[ECC_MFSR] = 0; | |
290 | s->regs[ECC_VCR] = 0; | |
291 | s->regs[ECC_MFAR0] = 0x07c00000; | |
292 | s->regs[ECC_MFAR1] = 0; | |
293 | s->regs[ECC_DR] = 0; | |
294 | s->regs[ECC_ECR0] = 0; | |
295 | s->regs[ECC_ECR1] = 0; | |
7eb0c8e8 BS |
296 | } |
297 | ||
81a322d4 | 298 | static int ecc_init1(SysBusDevice *dev) |
7eb0c8e8 BS |
299 | { |
300 | int ecc_io_memory; | |
49e66373 | 301 | ECCState *s = FROM_SYSBUS(ECCState, dev); |
7eb0c8e8 | 302 | |
49e66373 | 303 | sysbus_init_irq(dev, &s->irq); |
49e66373 | 304 | s->regs[0] = s->version; |
1eed09cb | 305 | ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s); |
49e66373 BS |
306 | sysbus_init_mmio(dev, ECC_SIZE, ecc_io_memory); |
307 | ||
308 | if (s->version == ECC_MCC) { // SS-600MP only | |
1eed09cb | 309 | ecc_io_memory = cpu_register_io_memory(ecc_diag_mem_read, |
dd53ded3 | 310 | ecc_diag_mem_write, s); |
49e66373 | 311 | sysbus_init_mmio(dev, ECC_DIAG_SIZE, ecc_io_memory); |
dd53ded3 | 312 | } |
c21011a9 | 313 | vmstate_register(-1, &vmstate_ecc, s); |
a08d4367 | 314 | qemu_register_reset(ecc_reset, s); |
7eb0c8e8 | 315 | ecc_reset(s); |
81a322d4 | 316 | return 0; |
7eb0c8e8 | 317 | } |
49e66373 | 318 | |
ee6847d1 GH |
319 | static SysBusDeviceInfo ecc_info = { |
320 | .init = ecc_init1, | |
321 | .qdev.name = "eccmemctl", | |
322 | .qdev.size = sizeof(ECCState), | |
323 | .qdev.props = (Property[]) { | |
d210a1b4 GH |
324 | DEFINE_PROP_HEX32("version", ECCState, version, -1), |
325 | DEFINE_PROP_END_OF_LIST(), | |
ee6847d1 GH |
326 | } |
327 | }; | |
328 | ||
329 | ||
49e66373 BS |
330 | static void ecc_register_devices(void) |
331 | { | |
ee6847d1 | 332 | sysbus_register_withprop(&ecc_info); |
49e66373 BS |
333 | } |
334 | ||
335 | device_init(ecc_register_devices) |