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Commit | Line | Data |
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663e8e51 TS |
1 | /* |
2 | * QEMU i8255x (PRO100) emulation | |
3 | * | |
1b4f97d6 | 4 | * Copyright (C) 2006-2011 Stefan Weil |
663e8e51 TS |
5 | * |
6 | * Portions of the code are copies from grub / etherboot eepro100.c | |
7 | * and linux e100.c. | |
8 | * | |
230a167c | 9 | * This program is free software: you can redistribute it and/or modify |
663e8e51 | 10 | * it under the terms of the GNU General Public License as published by |
230a167c SW |
11 | * the Free Software Foundation, either version 2 of the License, or |
12 | * (at your option) version 3 or any later version. | |
663e8e51 TS |
13 | * |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
230a167c | 20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
663e8e51 TS |
21 | * |
22 | * Tested features (i82559): | |
e5e23ab8 | 23 | * PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok |
663e8e51 TS |
24 | * Linux networking (i386) ok |
25 | * | |
26 | * Untested: | |
663e8e51 TS |
27 | * Windows networking |
28 | * | |
29 | * References: | |
30 | * | |
31 | * Intel 8255x 10/100 Mbps Ethernet Controller Family | |
32 | * Open Source Software Developer Manual | |
ba19f2de SW |
33 | * |
34 | * TODO: | |
35 | * * PHY emulation should be separated from nic emulation. | |
36 | * Most nic emulations could share the same phy code. | |
37 | * * i82550 is untested. It is programmed like the i82559. | |
38 | * * i82562 is untested. It is programmed like the i82559. | |
39 | * * Power management (i82558 and later) is not implemented. | |
40 | * * Wake-on-LAN is not implemented. | |
663e8e51 TS |
41 | */ |
42 | ||
663e8e51 | 43 | #include <stddef.h> /* offsetof */ |
87ecb68b PB |
44 | #include "hw.h" |
45 | #include "pci.h" | |
46 | #include "net.h" | |
663e8e51 | 47 | #include "eeprom93xx.h" |
1ca4d09a | 48 | #include "sysemu.h" |
663e8e51 | 49 | |
792f1d63 SW |
50 | /* QEMU sends frames smaller than 60 bytes to ethernet nics. |
51 | * Such frames are rejected by real nics and their emulations. | |
52 | * To avoid this behaviour, other nic emulations pad received | |
53 | * frames. The following definition enables this padding for | |
54 | * eepro100, too. We keep the define around in case it might | |
55 | * become useful the future if the core networking is ever | |
56 | * changed to pad short packets itself. */ | |
57 | #define CONFIG_PAD_RECEIVED_FRAMES | |
58 | ||
663e8e51 TS |
59 | #define KiB 1024 |
60 | ||
aac443e6 | 61 | /* Debug EEPRO100 card. */ |
ce0e58b3 SW |
62 | #if 0 |
63 | # define DEBUG_EEPRO100 | |
64 | #endif | |
663e8e51 TS |
65 | |
66 | #ifdef DEBUG_EEPRO100 | |
001faf32 | 67 | #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__) |
663e8e51 | 68 | #else |
001faf32 | 69 | #define logout(fmt, ...) ((void)0) |
663e8e51 TS |
70 | #endif |
71 | ||
72 | /* Set flags to 0 to disable debug output. */ | |
aac443e6 SW |
73 | #define INT 1 /* interrupt related actions */ |
74 | #define MDI 1 /* mdi related actions */ | |
75 | #define OTHER 1 | |
76 | #define RXTX 1 | |
77 | #define EEPROM 1 /* eeprom related actions */ | |
663e8e51 TS |
78 | |
79 | #define TRACE(flag, command) ((flag) ? (command) : (void)0) | |
80 | ||
7f1e9d4e | 81 | #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n") |
663e8e51 TS |
82 | |
83 | #define MAX_ETH_FRAME_SIZE 1514 | |
84 | ||
85 | /* This driver supports several different devices which are declared here. */ | |
c4c270e2 | 86 | #define i82550 0x82550 |
663e8e51 | 87 | #define i82551 0x82551 |
c4c270e2 | 88 | #define i82557A 0x82557a |
663e8e51 TS |
89 | #define i82557B 0x82557b |
90 | #define i82557C 0x82557c | |
c4c270e2 | 91 | #define i82558A 0x82558a |
663e8e51 | 92 | #define i82558B 0x82558b |
c4c270e2 SW |
93 | #define i82559A 0x82559a |
94 | #define i82559B 0x82559b | |
663e8e51 TS |
95 | #define i82559C 0x82559c |
96 | #define i82559ER 0x82559e | |
97 | #define i82562 0x82562 | |
db667a12 | 98 | #define i82801 0x82801 |
663e8e51 | 99 | |
aac443e6 | 100 | /* Use 64 word EEPROM. TODO: could be a runtime option. */ |
663e8e51 TS |
101 | #define EEPROM_SIZE 64 |
102 | ||
103 | #define PCI_MEM_SIZE (4 * KiB) | |
104 | #define PCI_IO_SIZE 64 | |
105 | #define PCI_FLASH_SIZE (128 * KiB) | |
106 | ||
107 | #define BIT(n) (1 << (n)) | |
108 | #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) | |
109 | ||
110 | /* The SCB accepts the following controls for the Tx and Rx units: */ | |
111 | #define CU_NOP 0x0000 /* No operation. */ | |
112 | #define CU_START 0x0010 /* CU start. */ | |
113 | #define CU_RESUME 0x0020 /* CU resume. */ | |
114 | #define CU_STATSADDR 0x0040 /* Load dump counters address. */ | |
115 | #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */ | |
116 | #define CU_CMD_BASE 0x0060 /* Load CU base address. */ | |
117 | #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */ | |
118 | #define CU_SRESUME 0x00a0 /* CU static resume. */ | |
119 | ||
120 | #define RU_NOP 0x0000 | |
121 | #define RX_START 0x0001 | |
122 | #define RX_RESUME 0x0002 | |
e824012b | 123 | #define RU_ABORT 0x0004 |
663e8e51 TS |
124 | #define RX_ADDR_LOAD 0x0006 |
125 | #define RX_RESUMENR 0x0007 | |
126 | #define INT_MASK 0x0100 | |
127 | #define DRVR_INT 0x0200 /* Driver generated interrupt. */ | |
128 | ||
558c8634 SW |
129 | typedef struct { |
130 | PCIDeviceInfo pci; | |
131 | uint32_t device; | |
132 | uint16_t device_id; | |
133 | uint8_t revision; | |
134 | uint8_t stats_size; | |
135 | bool has_extended_tcb_support; | |
136 | bool power_management; | |
137 | } E100PCIDeviceInfo; | |
138 | ||
663e8e51 TS |
139 | /* Offsets to the various registers. |
140 | All accesses need not be longword aligned. */ | |
e5e23ab8 | 141 | typedef enum { |
0908bba1 | 142 | SCBStatus = 0, /* Status Word. */ |
663e8e51 TS |
143 | SCBAck = 1, |
144 | SCBCmd = 2, /* Rx/Command Unit command and status. */ | |
145 | SCBIntmask = 3, | |
146 | SCBPointer = 4, /* General purpose pointer. */ | |
147 | SCBPort = 8, /* Misc. commands and operands. */ | |
0908bba1 SW |
148 | SCBflash = 12, /* Flash memory control. */ |
149 | SCBeeprom = 14, /* EEPROM control. */ | |
663e8e51 TS |
150 | SCBCtrlMDI = 16, /* MDI interface control. */ |
151 | SCBEarlyRx = 20, /* Early receive byte count. */ | |
0908bba1 SW |
152 | SCBFlow = 24, /* Flow Control. */ |
153 | SCBpmdr = 27, /* Power Management Driver. */ | |
154 | SCBgctrl = 28, /* General Control. */ | |
155 | SCBgstat = 29, /* General Status. */ | |
e5e23ab8 | 156 | } E100RegisterOffset; |
663e8e51 TS |
157 | |
158 | /* A speedo3 transmit buffer descriptor with two buffers... */ | |
159 | typedef struct { | |
160 | uint16_t status; | |
161 | uint16_t command; | |
162 | uint32_t link; /* void * */ | |
7b8737de | 163 | uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */ |
663e8e51 TS |
164 | uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */ |
165 | uint8_t tx_threshold; /* transmit threshold */ | |
166 | uint8_t tbd_count; /* TBD number */ | |
e7493b25 SW |
167 | #if 0 |
168 | /* This constitutes two "TBD" entries: hdr and data */ | |
169 | uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */ | |
170 | int32_t tx_buf_size0; /* Length of Tx hdr. */ | |
171 | uint32_t tx_buf_addr1; /* void *, data to be transmitted. */ | |
172 | int32_t tx_buf_size1; /* Length of Tx data. */ | |
173 | #endif | |
c227f099 | 174 | } eepro100_tx_t; |
663e8e51 TS |
175 | |
176 | /* Receive frame descriptor. */ | |
177 | typedef struct { | |
178 | int16_t status; | |
179 | uint16_t command; | |
180 | uint32_t link; /* struct RxFD * */ | |
181 | uint32_t rx_buf_addr; /* void * */ | |
182 | uint16_t count; | |
183 | uint16_t size; | |
27112f18 | 184 | /* Ethernet frame data follows. */ |
c227f099 | 185 | } eepro100_rx_t; |
663e8e51 | 186 | |
ced5296a SW |
187 | typedef enum { |
188 | COMMAND_EL = BIT(15), | |
189 | COMMAND_S = BIT(14), | |
190 | COMMAND_I = BIT(13), | |
191 | COMMAND_NC = BIT(4), | |
192 | COMMAND_SF = BIT(3), | |
193 | COMMAND_CMD = BITS(2, 0), | |
194 | } scb_command_bit; | |
195 | ||
196 | typedef enum { | |
197 | STATUS_C = BIT(15), | |
198 | STATUS_OK = BIT(13), | |
199 | } scb_status_bit; | |
200 | ||
663e8e51 TS |
201 | typedef struct { |
202 | uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, | |
cc02c66c SW |
203 | tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, |
204 | tx_multiple_collisions, tx_total_collisions; | |
663e8e51 | 205 | uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors, |
cc02c66c SW |
206 | rx_resource_errors, rx_overrun_errors, rx_cdt_errors, |
207 | rx_short_frame_errors; | |
663e8e51 TS |
208 | uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; |
209 | uint16_t xmt_tco_frames, rcv_tco_frames; | |
ba42b646 SW |
210 | /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */ |
211 | uint32_t reserved[4]; | |
c227f099 | 212 | } eepro100_stats_t; |
663e8e51 TS |
213 | |
214 | typedef enum { | |
215 | cu_idle = 0, | |
216 | cu_suspended = 1, | |
217 | cu_active = 2, | |
218 | cu_lpq_active = 2, | |
219 | cu_hqp_active = 3 | |
c227f099 | 220 | } cu_state_t; |
663e8e51 TS |
221 | |
222 | typedef enum { | |
223 | ru_idle = 0, | |
224 | ru_suspended = 1, | |
225 | ru_no_resources = 2, | |
226 | ru_ready = 4 | |
c227f099 | 227 | } ru_state_t; |
663e8e51 | 228 | |
663e8e51 | 229 | typedef struct { |
273a2142 | 230 | PCIDevice dev; |
010ec629 SW |
231 | /* Hash register (multicast mask array, multiple individual addresses). */ |
232 | uint8_t mult[8]; | |
663e8e51 | 233 | int mmio_index; |
e00e365e | 234 | NICState *nic; |
508ef936 | 235 | NICConf conf; |
663e8e51 TS |
236 | uint8_t scb_stat; /* SCB stat/ack byte */ |
237 | uint8_t int_stat; /* PCI interrupt status */ | |
3706c43f | 238 | /* region must not be saved by nic_save. */ |
22ec6093 | 239 | uint32_t region1; /* PCI region 1 address */ |
663e8e51 | 240 | uint16_t mdimem[32]; |
c227f099 | 241 | eeprom_t *eeprom; |
663e8e51 | 242 | uint32_t device; /* device variant */ |
663e8e51 TS |
243 | /* (cu_base + cu_offset) address the next command block in the command block list. */ |
244 | uint32_t cu_base; /* CU base address */ | |
245 | uint32_t cu_offset; /* CU address offset */ | |
246 | /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */ | |
247 | uint32_t ru_base; /* RU base address */ | |
248 | uint32_t ru_offset; /* RU address offset */ | |
c227f099 | 249 | uint32_t statsaddr; /* pointer to eepro100_stats_t */ |
ba42b646 | 250 | |
f3a52e50 SW |
251 | /* Temporary status information (no need to save these values), |
252 | * used while processing CU commands. */ | |
253 | eepro100_tx_t tx; /* transmit buffer descriptor */ | |
254 | uint32_t cb_address; /* = cu_base + cu_offset */ | |
255 | ||
ba42b646 SW |
256 | /* Statistical counters. Also used for wake-up packet (i82559). */ |
257 | eepro100_stats_t statistics; | |
258 | ||
e5e23ab8 SW |
259 | /* Data in mem is always in the byte order of the controller (le). |
260 | * It must be dword aligned to allow direct access to 32 bit values. */ | |
261 | uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));; | |
262 | ||
663e8e51 TS |
263 | /* Configuration bytes. */ |
264 | uint8_t configuration[22]; | |
265 | ||
151b2986 JQ |
266 | /* vmstate for each particular nic */ |
267 | VMStateDescription *vmstate; | |
ba42b646 SW |
268 | |
269 | /* Quasi static device properties (no need to save them). */ | |
270 | uint16_t stats_size; | |
271 | bool has_extended_tcb_support; | |
663e8e51 TS |
272 | } EEPRO100State; |
273 | ||
6cded3a4 SW |
274 | /* Word indices in EEPROM. */ |
275 | typedef enum { | |
276 | EEPROM_CNFG_MDIX = 0x03, | |
277 | EEPROM_ID = 0x05, | |
278 | EEPROM_PHY_ID = 0x06, | |
279 | EEPROM_VENDOR_ID = 0x0c, | |
280 | EEPROM_CONFIG_ASF = 0x0d, | |
281 | EEPROM_DEVICE_ID = 0x23, | |
282 | EEPROM_SMBUS_ADDR = 0x90, | |
283 | } EEPROMOffset; | |
284 | ||
b1e87018 SW |
285 | /* Bit values for EEPROM ID word. */ |
286 | typedef enum { | |
287 | EEPROM_ID_MDM = BIT(0), /* Modem */ | |
288 | EEPROM_ID_STB = BIT(1), /* Standby Enable */ | |
289 | EEPROM_ID_WMR = BIT(2), /* ??? */ | |
290 | EEPROM_ID_WOL = BIT(5), /* Wake on LAN */ | |
291 | EEPROM_ID_DPD = BIT(6), /* Deep Power Down */ | |
292 | EEPROM_ID_ALT = BIT(7), /* */ | |
293 | /* BITS(10, 8) device revision */ | |
294 | EEPROM_ID_BD = BIT(11), /* boot disable */ | |
295 | EEPROM_ID_ID = BIT(13), /* id bit */ | |
296 | /* BITS(15, 14) signature */ | |
297 | EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */ | |
298 | } eeprom_id_bit; | |
299 | ||
663e8e51 TS |
300 | /* Default values for MDI (PHY) registers */ |
301 | static const uint16_t eepro100_mdi_default[] = { | |
302 | /* MDI Registers 0 - 6, 7 */ | |
303 | 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000, | |
304 | /* MDI Registers 8 - 15 */ | |
305 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
306 | /* MDI Registers 16 - 31 */ | |
307 | 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
308 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
309 | }; | |
310 | ||
311 | /* Readonly mask for MDI (PHY) registers */ | |
312 | static const uint16_t eepro100_mdi_mask[] = { | |
313 | 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000, | |
314 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
315 | 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, | |
316 | 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
317 | }; | |
318 | ||
e5e23ab8 SW |
319 | /* Read a 16 bit little endian value from physical memory. */ |
320 | static uint16_t e100_ldw_le_phys(target_phys_addr_t addr) | |
321 | { | |
322 | /* Load 16 bit (little endian) word from emulated hardware. */ | |
323 | uint16_t val; | |
324 | cpu_physical_memory_read(addr, &val, sizeof(val)); | |
325 | return le16_to_cpu(val); | |
326 | } | |
327 | ||
328 | /* Read a 32 bit little endian value from physical memory. */ | |
329 | static uint32_t e100_ldl_le_phys(target_phys_addr_t addr) | |
330 | { | |
331 | /* Load 32 bit (little endian) word from emulated hardware. */ | |
332 | uint32_t val; | |
333 | cpu_physical_memory_read(addr, &val, sizeof(val)); | |
334 | return le32_to_cpu(val); | |
335 | } | |
336 | ||
337 | /* Write a 16 bit little endian value to physical memory. */ | |
338 | static void e100_stw_le_phys(target_phys_addr_t addr, uint16_t val) | |
339 | { | |
340 | val = cpu_to_le16(val); | |
341 | cpu_physical_memory_write(addr, &val, sizeof(val)); | |
342 | } | |
343 | ||
344 | /* Write a 32 bit little endian value to physical memory. */ | |
345 | static void e100_stl_le_phys(target_phys_addr_t addr, uint32_t val) | |
ba42b646 SW |
346 | { |
347 | val = cpu_to_le32(val); | |
77bee84e | 348 | cpu_physical_memory_write(addr, &val, sizeof(val)); |
ba42b646 SW |
349 | } |
350 | ||
663e8e51 TS |
351 | #define POLYNOMIAL 0x04c11db6 |
352 | ||
353 | /* From FreeBSD */ | |
354 | /* XXX: optimize */ | |
7b8737de | 355 | static unsigned compute_mcast_idx(const uint8_t * ep) |
663e8e51 TS |
356 | { |
357 | uint32_t crc; | |
358 | int carry, i, j; | |
359 | uint8_t b; | |
360 | ||
361 | crc = 0xffffffff; | |
362 | for (i = 0; i < 6; i++) { | |
363 | b = *ep++; | |
364 | for (j = 0; j < 8; j++) { | |
365 | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); | |
366 | crc <<= 1; | |
367 | b >>= 1; | |
aac443e6 | 368 | if (carry) { |
663e8e51 | 369 | crc = ((crc ^ POLYNOMIAL) | carry); |
aac443e6 | 370 | } |
663e8e51 TS |
371 | } |
372 | } | |
7b8737de | 373 | return (crc & BITS(7, 2)) >> 2; |
663e8e51 TS |
374 | } |
375 | ||
e5e23ab8 SW |
376 | /* Read a 16 bit control/status (CSR) register. */ |
377 | static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr) | |
378 | { | |
379 | assert(!((uintptr_t)&s->mem[addr] & 1)); | |
380 | return le16_to_cpup((uint16_t *)&s->mem[addr]); | |
381 | } | |
382 | ||
383 | /* Read a 32 bit control/status (CSR) register. */ | |
384 | static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr) | |
385 | { | |
386 | assert(!((uintptr_t)&s->mem[addr] & 3)); | |
387 | return le32_to_cpup((uint32_t *)&s->mem[addr]); | |
388 | } | |
389 | ||
390 | /* Write a 16 bit control/status (CSR) register. */ | |
391 | static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr, | |
392 | uint16_t val) | |
393 | { | |
394 | assert(!((uintptr_t)&s->mem[addr] & 1)); | |
395 | cpu_to_le16w((uint16_t *)&s->mem[addr], val); | |
396 | } | |
397 | ||
398 | /* Read a 32 bit control/status (CSR) register. */ | |
399 | static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr, | |
400 | uint32_t val) | |
401 | { | |
402 | assert(!((uintptr_t)&s->mem[addr] & 3)); | |
403 | cpu_to_le32w((uint32_t *)&s->mem[addr], val); | |
404 | } | |
405 | ||
663e8e51 TS |
406 | #if defined(DEBUG_EEPRO100) |
407 | static const char *nic_dump(const uint8_t * buf, unsigned size) | |
408 | { | |
409 | static char dump[3 * 16 + 1]; | |
410 | char *p = &dump[0]; | |
aac443e6 | 411 | if (size > 16) { |
663e8e51 | 412 | size = 16; |
aac443e6 | 413 | } |
663e8e51 TS |
414 | while (size-- > 0) { |
415 | p += sprintf(p, " %02x", *buf++); | |
416 | } | |
417 | return dump; | |
418 | } | |
419 | #endif /* DEBUG_EEPRO100 */ | |
420 | ||
421 | enum scb_stat_ack { | |
422 | stat_ack_not_ours = 0x00, | |
423 | stat_ack_sw_gen = 0x04, | |
424 | stat_ack_rnr = 0x10, | |
425 | stat_ack_cu_idle = 0x20, | |
426 | stat_ack_frame_rx = 0x40, | |
427 | stat_ack_cu_cmd_done = 0x80, | |
428 | stat_ack_not_present = 0xFF, | |
429 | stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx), | |
430 | stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done), | |
431 | }; | |
432 | ||
433 | static void disable_interrupt(EEPRO100State * s) | |
434 | { | |
435 | if (s->int_stat) { | |
aac443e6 | 436 | TRACE(INT, logout("interrupt disabled\n")); |
273a2142 | 437 | qemu_irq_lower(s->dev.irq[0]); |
663e8e51 TS |
438 | s->int_stat = 0; |
439 | } | |
440 | } | |
441 | ||
442 | static void enable_interrupt(EEPRO100State * s) | |
443 | { | |
444 | if (!s->int_stat) { | |
aac443e6 | 445 | TRACE(INT, logout("interrupt enabled\n")); |
273a2142 | 446 | qemu_irq_raise(s->dev.irq[0]); |
663e8e51 TS |
447 | s->int_stat = 1; |
448 | } | |
449 | } | |
450 | ||
451 | static void eepro100_acknowledge(EEPRO100State * s) | |
452 | { | |
453 | s->scb_stat &= ~s->mem[SCBAck]; | |
454 | s->mem[SCBAck] = s->scb_stat; | |
455 | if (s->scb_stat == 0) { | |
456 | disable_interrupt(s); | |
457 | } | |
458 | } | |
459 | ||
e715c8e8 | 460 | static void eepro100_interrupt(EEPRO100State * s, uint8_t status) |
663e8e51 TS |
461 | { |
462 | uint8_t mask = ~s->mem[SCBIntmask]; | |
e715c8e8 SW |
463 | s->mem[SCBAck] |= status; |
464 | status = s->scb_stat = s->mem[SCBAck]; | |
465 | status &= (mask | 0x0f); | |
e7493b25 SW |
466 | #if 0 |
467 | status &= (~s->mem[SCBIntmask] | 0x0xf); | |
468 | #endif | |
e715c8e8 | 469 | if (status && (mask & 0x01)) { |
663e8e51 TS |
470 | /* SCB mask and SCB Bit M do not disable interrupt. */ |
471 | enable_interrupt(s); | |
472 | } else if (s->int_stat) { | |
473 | disable_interrupt(s); | |
474 | } | |
475 | } | |
476 | ||
477 | static void eepro100_cx_interrupt(EEPRO100State * s) | |
478 | { | |
479 | /* CU completed action command. */ | |
480 | /* Transmit not ok (82557 only, not in emulation). */ | |
481 | eepro100_interrupt(s, 0x80); | |
482 | } | |
483 | ||
484 | static void eepro100_cna_interrupt(EEPRO100State * s) | |
485 | { | |
486 | /* CU left the active state. */ | |
487 | eepro100_interrupt(s, 0x20); | |
488 | } | |
489 | ||
490 | static void eepro100_fr_interrupt(EEPRO100State * s) | |
491 | { | |
492 | /* RU received a complete frame. */ | |
493 | eepro100_interrupt(s, 0x40); | |
494 | } | |
495 | ||
663e8e51 TS |
496 | static void eepro100_rnr_interrupt(EEPRO100State * s) |
497 | { | |
498 | /* RU is not ready. */ | |
499 | eepro100_interrupt(s, 0x10); | |
500 | } | |
663e8e51 TS |
501 | |
502 | static void eepro100_mdi_interrupt(EEPRO100State * s) | |
503 | { | |
504 | /* MDI completed read or write cycle. */ | |
505 | eepro100_interrupt(s, 0x08); | |
506 | } | |
507 | ||
508 | static void eepro100_swi_interrupt(EEPRO100State * s) | |
509 | { | |
510 | /* Software has requested an interrupt. */ | |
511 | eepro100_interrupt(s, 0x04); | |
512 | } | |
513 | ||
514 | #if 0 | |
515 | static void eepro100_fcp_interrupt(EEPRO100State * s) | |
516 | { | |
517 | /* Flow control pause interrupt (82558 and later). */ | |
518 | eepro100_interrupt(s, 0x01); | |
519 | } | |
520 | #endif | |
521 | ||
558c8634 | 522 | static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device) |
663e8e51 TS |
523 | { |
524 | uint32_t device = s->device; | |
273a2142 | 525 | uint8_t *pci_conf = s->dev.config; |
663e8e51 | 526 | |
aac443e6 | 527 | TRACE(OTHER, logout("%p\n", s)); |
663e8e51 TS |
528 | |
529 | /* PCI Vendor ID */ | |
deb54399 | 530 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
558c8634 SW |
531 | /* PCI Device ID */ |
532 | pci_config_set_device_id(pci_conf, e100_device->device_id); | |
663e8e51 | 533 | /* PCI Status */ |
ae543b49 SW |
534 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
535 | PCI_STATUS_FAST_BACK); | |
663e8e51 | 536 | /* PCI Revision ID */ |
558c8634 | 537 | pci_config_set_revision(pci_conf, e100_device->revision); |
173a543b | 538 | pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
663e8e51 | 539 | /* PCI Latency Timer */ |
15e89f59 | 540 | pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */ |
ae543b49 | 541 | /* Capability Pointer is set by PCI framework. */ |
f62719ca SW |
542 | /* Interrupt Line */ |
543 | /* Interrupt Pin */ | |
544 | pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */ | |
663e8e51 | 545 | /* Minimum Grant */ |
15e89f59 | 546 | pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08); |
663e8e51 | 547 | /* Maximum Latency */ |
15e89f59 | 548 | pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18); |
663e8e51 | 549 | |
558c8634 SW |
550 | s->stats_size = e100_device->stats_size; |
551 | s->has_extended_tcb_support = e100_device->has_extended_tcb_support; | |
552 | ||
663e8e51 | 553 | switch (device) { |
ba42b646 | 554 | case i82550: |
663e8e51 | 555 | case i82551: |
ba42b646 | 556 | case i82557A: |
663e8e51 | 557 | case i82557B: |
663e8e51 | 558 | case i82557C: |
ba42b646 | 559 | case i82558A: |
663e8e51 | 560 | case i82558B: |
ba42b646 | 561 | case i82559A: |
ba42b646 | 562 | case i82559B: |
558c8634 SW |
563 | case i82559ER: |
564 | case i82562: | |
db667a12 | 565 | case i82801: |
663e8e51 TS |
566 | break; |
567 | case i82559C: | |
ba42b646 | 568 | #if EEPROM_SIZE > 0 |
558c8634 | 569 | pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_INTEL); |
15e89f59 | 570 | pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040); |
ba42b646 | 571 | #endif |
663e8e51 | 572 | break; |
663e8e51 TS |
573 | default: |
574 | logout("Device %X is undefined!\n", device); | |
575 | } | |
576 | ||
3dec59a1 SW |
577 | /* Standard TxCB. */ |
578 | s->configuration[6] |= BIT(4); | |
579 | ||
558c8634 | 580 | /* Standard statistical counters. */ |
ba42b646 SW |
581 | s->configuration[6] |= BIT(5); |
582 | ||
583 | if (s->stats_size == 80) { | |
584 | /* TODO: check TCO Statistical Counters bit. Documentation not clear. */ | |
585 | if (s->configuration[6] & BIT(2)) { | |
586 | /* TCO statistical counters. */ | |
587 | assert(s->configuration[6] & BIT(5)); | |
588 | } else { | |
589 | if (s->configuration[6] & BIT(5)) { | |
590 | /* No extended statistical counters, i82557 compatible. */ | |
591 | s->stats_size = 64; | |
592 | } else { | |
593 | /* i82558 compatible. */ | |
594 | s->stats_size = 76; | |
595 | } | |
596 | } | |
597 | } else { | |
598 | if (s->configuration[6] & BIT(5)) { | |
599 | /* No extended statistical counters. */ | |
600 | s->stats_size = 64; | |
601 | } | |
602 | } | |
603 | assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics)); | |
604 | ||
558c8634 | 605 | if (e100_device->power_management) { |
ba42b646 | 606 | /* Power Management Capabilities */ |
8bbd1ce2 | 607 | int cfg_offset = 0xdc; |
ca77089d IY |
608 | int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM, |
609 | cfg_offset, PCI_PM_SIZEOF); | |
8bbd1ce2 MT |
610 | assert(r >= 0); |
611 | pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21); | |
ae543b49 | 612 | #if 0 /* TODO: replace dummy code for power management emulation. */ |
8bbd1ce2 MT |
613 | /* TODO: Power Management Control / Status. */ |
614 | pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000); | |
615 | /* TODO: Ethernet Power Consumption Registers (i82559 and later). */ | |
616 | pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000); | |
ae543b49 | 617 | #endif |
ba42b646 SW |
618 | } |
619 | ||
620 | #if EEPROM_SIZE > 0 | |
663e8e51 | 621 | if (device == i82557C || device == i82558B || device == i82559C) { |
e7493b25 SW |
622 | /* |
623 | TODO: get vendor id from EEPROM for i82557C or later. | |
624 | TODO: get device id from EEPROM for i82557C or later. | |
625 | TODO: status bit 4 can be disabled by EEPROM for i82558, i82559. | |
626 | TODO: header type is determined by EEPROM for i82559. | |
627 | TODO: get subsystem id from EEPROM for i82557C or later. | |
628 | TODO: get subsystem vendor id from EEPROM for i82557C or later. | |
629 | TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later. | |
630 | TODO: capability pointer depends on EEPROM for i82558. | |
631 | */ | |
663e8e51 TS |
632 | logout("Get device id and revision from EEPROM!!!\n"); |
633 | } | |
ba42b646 | 634 | #endif /* EEPROM_SIZE > 0 */ |
663e8e51 TS |
635 | } |
636 | ||
637 | static void nic_selective_reset(EEPRO100State * s) | |
638 | { | |
639 | size_t i; | |
640 | uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom); | |
e7493b25 SW |
641 | #if 0 |
642 | eeprom93xx_reset(s->eeprom); | |
643 | #endif | |
508ef936 | 644 | memcpy(eeprom_contents, s->conf.macaddr.a, 6); |
b1e87018 | 645 | eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID; |
f4e94dfe URCB |
646 | if (s->device == i82557B || s->device == i82557C) |
647 | eeprom_contents[5] = 0x0100; | |
6cded3a4 | 648 | eeprom_contents[EEPROM_PHY_ID] = 1; |
663e8e51 TS |
649 | uint16_t sum = 0; |
650 | for (i = 0; i < EEPROM_SIZE - 1; i++) { | |
651 | sum += eeprom_contents[i]; | |
652 | } | |
653 | eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum; | |
aac443e6 | 654 | TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1])); |
663e8e51 TS |
655 | |
656 | memset(s->mem, 0, sizeof(s->mem)); | |
e5e23ab8 | 657 | e100_write_reg4(s, SCBCtrlMDI, BIT(21)); |
663e8e51 TS |
658 | |
659 | assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default)); | |
660 | memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem)); | |
661 | } | |
662 | ||
663 | static void nic_reset(void *opaque) | |
664 | { | |
769cf7a5 | 665 | EEPRO100State *s = opaque; |
aac443e6 | 666 | TRACE(OTHER, logout("%p\n", s)); |
010ec629 | 667 | /* TODO: Clearing of hash register for selective reset, too? */ |
7b8737de | 668 | memset(&s->mult[0], 0, sizeof(s->mult)); |
663e8e51 TS |
669 | nic_selective_reset(s); |
670 | } | |
671 | ||
672 | #if defined(DEBUG_EEPRO100) | |
b8f6ba0d | 673 | static const char * const e100_reg[PCI_IO_SIZE / 4] = { |
663e8e51 TS |
674 | "Command/Status", |
675 | "General Pointer", | |
676 | "Port", | |
677 | "EEPROM/Flash Control", | |
678 | "MDI Control", | |
679 | "Receive DMA Byte Count", | |
b8f6ba0d | 680 | "Flow Control", |
663e8e51 TS |
681 | "General Status/Control" |
682 | }; | |
683 | ||
684 | static char *regname(uint32_t addr) | |
685 | { | |
ec169288 | 686 | static char buf[32]; |
663e8e51 | 687 | if (addr < PCI_IO_SIZE) { |
b8f6ba0d | 688 | const char *r = e100_reg[addr / 4]; |
663e8e51 | 689 | if (r != 0) { |
41cbc23c | 690 | snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4); |
663e8e51 | 691 | } else { |
41cbc23c | 692 | snprintf(buf, sizeof(buf), "0x%02x", addr); |
663e8e51 TS |
693 | } |
694 | } else { | |
41cbc23c | 695 | snprintf(buf, sizeof(buf), "??? 0x%08x", addr); |
663e8e51 TS |
696 | } |
697 | return buf; | |
698 | } | |
699 | #endif /* DEBUG_EEPRO100 */ | |
700 | ||
663e8e51 TS |
701 | /***************************************************************************** |
702 | * | |
703 | * Command emulation. | |
704 | * | |
705 | ****************************************************************************/ | |
706 | ||
707 | #if 0 | |
708 | static uint16_t eepro100_read_command(EEPRO100State * s) | |
709 | { | |
710 | uint16_t val = 0xffff; | |
e7493b25 | 711 | TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
712 | return val; |
713 | } | |
714 | #endif | |
715 | ||
716 | /* Commands that can be put in a command list entry. */ | |
717 | enum commands { | |
718 | CmdNOp = 0, | |
719 | CmdIASetup = 1, | |
720 | CmdConfigure = 2, | |
721 | CmdMulticastList = 3, | |
722 | CmdTx = 4, | |
723 | CmdTDR = 5, /* load microcode */ | |
724 | CmdDump = 6, | |
725 | CmdDiagnose = 7, | |
726 | ||
727 | /* And some extra flags: */ | |
728 | CmdSuspend = 0x4000, /* Suspend after completion. */ | |
729 | CmdIntr = 0x2000, /* Interrupt after completion. */ | |
730 | CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ | |
731 | }; | |
732 | ||
c227f099 | 733 | static cu_state_t get_cu_state(EEPRO100State * s) |
663e8e51 | 734 | { |
ced5296a | 735 | return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6); |
663e8e51 TS |
736 | } |
737 | ||
c227f099 | 738 | static void set_cu_state(EEPRO100State * s, cu_state_t state) |
663e8e51 | 739 | { |
ced5296a | 740 | s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6); |
663e8e51 TS |
741 | } |
742 | ||
c227f099 | 743 | static ru_state_t get_ru_state(EEPRO100State * s) |
663e8e51 | 744 | { |
ced5296a | 745 | return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2); |
663e8e51 TS |
746 | } |
747 | ||
c227f099 | 748 | static void set_ru_state(EEPRO100State * s, ru_state_t state) |
663e8e51 | 749 | { |
ced5296a | 750 | s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2); |
663e8e51 TS |
751 | } |
752 | ||
753 | static void dump_statistics(EEPRO100State * s) | |
754 | { | |
755 | /* Dump statistical data. Most data is never changed by the emulation | |
756 | * and always 0, so we first just copy the whole block and then those | |
757 | * values which really matter. | |
758 | * Number of data should check configuration!!! | |
759 | */ | |
77bee84e | 760 | cpu_physical_memory_write(s->statsaddr, &s->statistics, s->stats_size); |
e5e23ab8 SW |
761 | e100_stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames); |
762 | e100_stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames); | |
763 | e100_stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors); | |
764 | e100_stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors); | |
e7493b25 | 765 | #if 0 |
e5e23ab8 SW |
766 | e100_stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames); |
767 | e100_stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames); | |
e7493b25 SW |
768 | missing("CU dump statistical counters"); |
769 | #endif | |
663e8e51 TS |
770 | } |
771 | ||
3d0f4b9b SW |
772 | static void read_cb(EEPRO100State *s) |
773 | { | |
77bee84e | 774 | cpu_physical_memory_read(s->cb_address, &s->tx, sizeof(s->tx)); |
3d0f4b9b SW |
775 | s->tx.status = le16_to_cpu(s->tx.status); |
776 | s->tx.command = le16_to_cpu(s->tx.command); | |
777 | s->tx.link = le32_to_cpu(s->tx.link); | |
778 | s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr); | |
779 | s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes); | |
780 | } | |
781 | ||
f3a52e50 SW |
782 | static void tx_command(EEPRO100State *s) |
783 | { | |
7b8737de | 784 | uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr); |
f3a52e50 SW |
785 | uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff); |
786 | /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */ | |
787 | uint8_t buf[2600]; | |
788 | uint16_t size = 0; | |
789 | uint32_t tbd_address = s->cb_address + 0x10; | |
790 | TRACE(RXTX, logout | |
791 | ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n", | |
792 | tbd_array, tcb_bytes, s->tx.tbd_count)); | |
793 | ||
794 | if (tcb_bytes > 2600) { | |
795 | logout("TCB byte count too large, using 2600\n"); | |
796 | tcb_bytes = 2600; | |
797 | } | |
798 | if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) { | |
799 | logout | |
800 | ("illegal values of TBD array address and TCB byte count!\n"); | |
801 | } | |
802 | assert(tcb_bytes <= sizeof(buf)); | |
803 | while (size < tcb_bytes) { | |
e5e23ab8 SW |
804 | uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address); |
805 | uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4); | |
e7493b25 | 806 | #if 0 |
e5e23ab8 | 807 | uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6); |
e7493b25 | 808 | #endif |
f3a52e50 SW |
809 | tbd_address += 8; |
810 | TRACE(RXTX, logout | |
811 | ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n", | |
812 | tx_buffer_address, tx_buffer_size)); | |
813 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); | |
814 | cpu_physical_memory_read(tx_buffer_address, &buf[size], | |
815 | tx_buffer_size); | |
816 | size += tx_buffer_size; | |
817 | } | |
818 | if (tbd_array == 0xffffffff) { | |
819 | /* Simplified mode. Was already handled by code above. */ | |
820 | } else { | |
821 | /* Flexible mode. */ | |
822 | uint8_t tbd_count = 0; | |
823 | if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) { | |
824 | /* Extended Flexible TCB. */ | |
825 | for (; tbd_count < 2; tbd_count++) { | |
e5e23ab8 SW |
826 | uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address); |
827 | uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4); | |
828 | uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6); | |
f3a52e50 SW |
829 | tbd_address += 8; |
830 | TRACE(RXTX, logout | |
831 | ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n", | |
832 | tx_buffer_address, tx_buffer_size)); | |
833 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); | |
834 | cpu_physical_memory_read(tx_buffer_address, &buf[size], | |
835 | tx_buffer_size); | |
836 | size += tx_buffer_size; | |
837 | if (tx_buffer_el & 1) { | |
838 | break; | |
839 | } | |
840 | } | |
841 | } | |
842 | tbd_address = tbd_array; | |
843 | for (; tbd_count < s->tx.tbd_count; tbd_count++) { | |
e5e23ab8 SW |
844 | uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address); |
845 | uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4); | |
846 | uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6); | |
f3a52e50 SW |
847 | tbd_address += 8; |
848 | TRACE(RXTX, logout | |
849 | ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n", | |
850 | tx_buffer_address, tx_buffer_size)); | |
851 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); | |
852 | cpu_physical_memory_read(tx_buffer_address, &buf[size], | |
853 | tx_buffer_size); | |
854 | size += tx_buffer_size; | |
855 | if (tx_buffer_el & 1) { | |
856 | break; | |
857 | } | |
858 | } | |
859 | } | |
860 | TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size))); | |
861 | qemu_send_packet(&s->nic->nc, buf, size); | |
862 | s->statistics.tx_good_frames++; | |
863 | /* Transmit with bad status would raise an CX/TNO interrupt. | |
864 | * (82557 only). Emulation never has bad status. */ | |
e7493b25 SW |
865 | #if 0 |
866 | eepro100_cx_interrupt(s); | |
867 | #endif | |
f3a52e50 SW |
868 | } |
869 | ||
7b8737de SW |
870 | static void set_multicast_list(EEPRO100State *s) |
871 | { | |
872 | uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0); | |
873 | uint16_t i; | |
874 | memset(&s->mult[0], 0, sizeof(s->mult)); | |
875 | TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count)); | |
876 | for (i = 0; i < multicast_count; i += 6) { | |
877 | uint8_t multicast_addr[6]; | |
878 | cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6); | |
879 | TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6))); | |
880 | unsigned mcast_idx = compute_mcast_idx(multicast_addr); | |
881 | assert(mcast_idx < 64); | |
882 | s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7)); | |
883 | } | |
884 | } | |
885 | ||
5fa9a0ae | 886 | static void action_command(EEPRO100State *s) |
663e8e51 | 887 | { |
5fa9a0ae | 888 | for (;;) { |
3d0f4b9b SW |
889 | bool bit_el; |
890 | bool bit_s; | |
891 | bool bit_i; | |
892 | bool bit_nc; | |
75f5a6cc | 893 | uint16_t ok_status = STATUS_OK; |
3d0f4b9b SW |
894 | s->cb_address = s->cu_base + s->cu_offset; |
895 | read_cb(s); | |
896 | bit_el = ((s->tx.command & COMMAND_EL) != 0); | |
897 | bit_s = ((s->tx.command & COMMAND_S) != 0); | |
898 | bit_i = ((s->tx.command & COMMAND_I) != 0); | |
899 | bit_nc = ((s->tx.command & COMMAND_NC) != 0); | |
900 | #if 0 | |
901 | bool bit_sf = ((s->tx.command & COMMAND_SF) != 0); | |
902 | #endif | |
903 | s->cu_offset = s->tx.link; | |
904 | TRACE(OTHER, | |
905 | logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n", | |
906 | s->tx.status, s->tx.command, s->tx.link)); | |
907 | switch (s->tx.command & COMMAND_CMD) { | |
663e8e51 TS |
908 | case CmdNOp: |
909 | /* Do nothing. */ | |
910 | break; | |
911 | case CmdIASetup: | |
f3a52e50 | 912 | cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6); |
ce0e58b3 | 913 | TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6))); |
663e8e51 TS |
914 | break; |
915 | case CmdConfigure: | |
f3a52e50 | 916 | cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0], |
663e8e51 | 917 | sizeof(s->configuration)); |
010ec629 SW |
918 | TRACE(OTHER, logout("configuration: %s\n", |
919 | nic_dump(&s->configuration[0], 16))); | |
920 | TRACE(OTHER, logout("configuration: %s\n", | |
921 | nic_dump(&s->configuration[16], | |
922 | ARRAY_SIZE(s->configuration) - 16))); | |
923 | if (s->configuration[20] & BIT(6)) { | |
924 | TRACE(OTHER, logout("Multiple IA bit\n")); | |
925 | } | |
663e8e51 TS |
926 | break; |
927 | case CmdMulticastList: | |
7b8737de | 928 | set_multicast_list(s); |
663e8e51 TS |
929 | break; |
930 | case CmdTx: | |
7f1e9d4e KW |
931 | if (bit_nc) { |
932 | missing("CmdTx: NC = 0"); | |
75f5a6cc | 933 | ok_status = 0; |
7f1e9d4e KW |
934 | break; |
935 | } | |
f3a52e50 | 936 | tx_command(s); |
663e8e51 TS |
937 | break; |
938 | case CmdTDR: | |
aac443e6 | 939 | TRACE(OTHER, logout("load microcode\n")); |
663e8e51 TS |
940 | /* Starting with offset 8, the command contains |
941 | * 64 dwords microcode which we just ignore here. */ | |
942 | break; | |
f80a7fc3 SW |
943 | case CmdDiagnose: |
944 | TRACE(OTHER, logout("diagnose\n")); | |
945 | /* Make sure error flag is not set. */ | |
946 | s->tx.status = 0; | |
947 | break; | |
663e8e51 TS |
948 | default: |
949 | missing("undefined command"); | |
75f5a6cc | 950 | ok_status = 0; |
7f1e9d4e | 951 | break; |
663e8e51 | 952 | } |
7f1e9d4e | 953 | /* Write new status. */ |
e5e23ab8 | 954 | e100_stw_le_phys(s->cb_address, s->tx.status | ok_status | STATUS_C); |
663e8e51 TS |
955 | if (bit_i) { |
956 | /* CU completed action. */ | |
957 | eepro100_cx_interrupt(s); | |
958 | } | |
959 | if (bit_el) { | |
aac443e6 | 960 | /* CU becomes idle. Terminate command loop. */ |
663e8e51 TS |
961 | set_cu_state(s, cu_idle); |
962 | eepro100_cna_interrupt(s); | |
5fa9a0ae | 963 | break; |
663e8e51 | 964 | } else if (bit_s) { |
5fa9a0ae | 965 | /* CU becomes suspended. Terminate command loop. */ |
663e8e51 TS |
966 | set_cu_state(s, cu_suspended); |
967 | eepro100_cna_interrupt(s); | |
5fa9a0ae | 968 | break; |
663e8e51 TS |
969 | } else { |
970 | /* More entries in list. */ | |
aac443e6 | 971 | TRACE(OTHER, logout("CU list with at least one more entry\n")); |
663e8e51 | 972 | } |
5fa9a0ae SW |
973 | } |
974 | TRACE(OTHER, logout("CU list empty\n")); | |
975 | /* List is empty. Now CU is idle or suspended. */ | |
976 | } | |
977 | ||
978 | static void eepro100_cu_command(EEPRO100State * s, uint8_t val) | |
979 | { | |
cb25a3fb | 980 | cu_state_t cu_state; |
5fa9a0ae SW |
981 | switch (val) { |
982 | case CU_NOP: | |
983 | /* No operation. */ | |
984 | break; | |
985 | case CU_START: | |
cb25a3fb SW |
986 | cu_state = get_cu_state(s); |
987 | if (cu_state != cu_idle && cu_state != cu_suspended) { | |
988 | /* Intel documentation says that CU must be idle or suspended | |
989 | * for the CU start command. */ | |
990 | logout("unexpected CU state is %u\n", cu_state); | |
5fa9a0ae SW |
991 | } |
992 | set_cu_state(s, cu_active); | |
27a05006 | 993 | s->cu_offset = e100_read_reg4(s, SCBPointer); |
5fa9a0ae | 994 | action_command(s); |
663e8e51 TS |
995 | break; |
996 | case CU_RESUME: | |
997 | if (get_cu_state(s) != cu_suspended) { | |
998 | logout("bad CU resume from CU state %u\n", get_cu_state(s)); | |
999 | /* Workaround for bad Linux eepro100 driver which resumes | |
1000 | * from idle state. */ | |
e7493b25 SW |
1001 | #if 0 |
1002 | missing("cu resume"); | |
1003 | #endif | |
663e8e51 TS |
1004 | set_cu_state(s, cu_suspended); |
1005 | } | |
1006 | if (get_cu_state(s) == cu_suspended) { | |
aac443e6 | 1007 | TRACE(OTHER, logout("CU resuming\n")); |
663e8e51 | 1008 | set_cu_state(s, cu_active); |
5fa9a0ae | 1009 | action_command(s); |
663e8e51 TS |
1010 | } |
1011 | break; | |
1012 | case CU_STATSADDR: | |
1013 | /* Load dump counters address. */ | |
27a05006 | 1014 | s->statsaddr = e100_read_reg4(s, SCBPointer); |
aac443e6 | 1015 | TRACE(OTHER, logout("val=0x%02x (status address)\n", val)); |
663e8e51 TS |
1016 | break; |
1017 | case CU_SHOWSTATS: | |
1018 | /* Dump statistical counters. */ | |
aac443e6 | 1019 | TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val)); |
663e8e51 | 1020 | dump_statistics(s); |
e5e23ab8 | 1021 | e100_stl_le_phys(s->statsaddr + s->stats_size, 0xa005); |
663e8e51 TS |
1022 | break; |
1023 | case CU_CMD_BASE: | |
1024 | /* Load CU base. */ | |
aac443e6 | 1025 | TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val)); |
27a05006 | 1026 | s->cu_base = e100_read_reg4(s, SCBPointer); |
663e8e51 TS |
1027 | break; |
1028 | case CU_DUMPSTATS: | |
1029 | /* Dump and reset statistical counters. */ | |
aac443e6 | 1030 | TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val)); |
663e8e51 | 1031 | dump_statistics(s); |
e5e23ab8 | 1032 | e100_stl_le_phys(s->statsaddr + s->stats_size, 0xa007); |
663e8e51 TS |
1033 | memset(&s->statistics, 0, sizeof(s->statistics)); |
1034 | break; | |
1035 | case CU_SRESUME: | |
1036 | /* CU static resume. */ | |
1037 | missing("CU static resume"); | |
1038 | break; | |
1039 | default: | |
1040 | missing("Undefined CU command"); | |
1041 | } | |
1042 | } | |
1043 | ||
1044 | static void eepro100_ru_command(EEPRO100State * s, uint8_t val) | |
1045 | { | |
1046 | switch (val) { | |
1047 | case RU_NOP: | |
1048 | /* No operation. */ | |
1049 | break; | |
1050 | case RX_START: | |
1051 | /* RU start. */ | |
1052 | if (get_ru_state(s) != ru_idle) { | |
1053 | logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle); | |
e7493b25 SW |
1054 | #if 0 |
1055 | assert(!"wrong RU state"); | |
1056 | #endif | |
663e8e51 TS |
1057 | } |
1058 | set_ru_state(s, ru_ready); | |
27a05006 | 1059 | s->ru_offset = e100_read_reg4(s, SCBPointer); |
aac443e6 | 1060 | TRACE(OTHER, logout("val=0x%02x (rx start)\n", val)); |
663e8e51 TS |
1061 | break; |
1062 | case RX_RESUME: | |
1063 | /* Restart RU. */ | |
1064 | if (get_ru_state(s) != ru_suspended) { | |
1065 | logout("RU state is %u, should be %u\n", get_ru_state(s), | |
1066 | ru_suspended); | |
e7493b25 SW |
1067 | #if 0 |
1068 | assert(!"wrong RU state"); | |
1069 | #endif | |
663e8e51 TS |
1070 | } |
1071 | set_ru_state(s, ru_ready); | |
1072 | break; | |
e824012b SW |
1073 | case RU_ABORT: |
1074 | /* RU abort. */ | |
1075 | if (get_ru_state(s) == ru_ready) { | |
1076 | eepro100_rnr_interrupt(s); | |
1077 | } | |
1078 | set_ru_state(s, ru_idle); | |
1079 | break; | |
663e8e51 TS |
1080 | case RX_ADDR_LOAD: |
1081 | /* Load RU base. */ | |
aac443e6 | 1082 | TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val)); |
27a05006 | 1083 | s->ru_base = e100_read_reg4(s, SCBPointer); |
663e8e51 TS |
1084 | break; |
1085 | default: | |
1086 | logout("val=0x%02x (undefined RU command)\n", val); | |
1087 | missing("Undefined SU command"); | |
1088 | } | |
1089 | } | |
1090 | ||
1091 | static void eepro100_write_command(EEPRO100State * s, uint8_t val) | |
1092 | { | |
1093 | eepro100_ru_command(s, val & 0x0f); | |
1094 | eepro100_cu_command(s, val & 0xf0); | |
1095 | if ((val) == 0) { | |
aac443e6 | 1096 | TRACE(OTHER, logout("val=0x%02x\n", val)); |
663e8e51 TS |
1097 | } |
1098 | /* Clear command byte after command was accepted. */ | |
1099 | s->mem[SCBCmd] = 0; | |
1100 | } | |
1101 | ||
1102 | /***************************************************************************** | |
1103 | * | |
1104 | * EEPROM emulation. | |
1105 | * | |
1106 | ****************************************************************************/ | |
1107 | ||
1108 | #define EEPROM_CS 0x02 | |
1109 | #define EEPROM_SK 0x01 | |
1110 | #define EEPROM_DI 0x04 | |
1111 | #define EEPROM_DO 0x08 | |
1112 | ||
1113 | static uint16_t eepro100_read_eeprom(EEPRO100State * s) | |
1114 | { | |
e5e23ab8 | 1115 | uint16_t val = e100_read_reg2(s, SCBeeprom); |
663e8e51 TS |
1116 | if (eeprom93xx_read(s->eeprom)) { |
1117 | val |= EEPROM_DO; | |
1118 | } else { | |
1119 | val &= ~EEPROM_DO; | |
1120 | } | |
aac443e6 | 1121 | TRACE(EEPROM, logout("val=0x%04x\n", val)); |
663e8e51 TS |
1122 | return val; |
1123 | } | |
1124 | ||
c227f099 | 1125 | static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val) |
663e8e51 | 1126 | { |
aac443e6 | 1127 | TRACE(EEPROM, logout("val=0x%02x\n", val)); |
663e8e51 | 1128 | |
ebabb67a | 1129 | /* mask unwritable bits */ |
e7493b25 SW |
1130 | #if 0 |
1131 | val = SET_MASKED(val, 0x31, eeprom->value); | |
1132 | #endif | |
663e8e51 TS |
1133 | |
1134 | int eecs = ((val & EEPROM_CS) != 0); | |
1135 | int eesk = ((val & EEPROM_SK) != 0); | |
1136 | int eedi = ((val & EEPROM_DI) != 0); | |
1137 | eeprom93xx_write(eeprom, eecs, eesk, eedi); | |
1138 | } | |
1139 | ||
663e8e51 TS |
1140 | /***************************************************************************** |
1141 | * | |
1142 | * MDI emulation. | |
1143 | * | |
1144 | ****************************************************************************/ | |
1145 | ||
1146 | #if defined(DEBUG_EEPRO100) | |
6a0b9cc9 | 1147 | static const char * const mdi_op_name[] = { |
663e8e51 TS |
1148 | "opcode 0", |
1149 | "write", | |
1150 | "read", | |
1151 | "opcode 3" | |
1152 | }; | |
1153 | ||
6a0b9cc9 | 1154 | static const char * const mdi_reg_name[] = { |
663e8e51 TS |
1155 | "Control", |
1156 | "Status", | |
1157 | "PHY Identification (Word 1)", | |
1158 | "PHY Identification (Word 2)", | |
1159 | "Auto-Negotiation Advertisement", | |
1160 | "Auto-Negotiation Link Partner Ability", | |
1161 | "Auto-Negotiation Expansion" | |
1162 | }; | |
aac443e6 SW |
1163 | |
1164 | static const char *reg2name(uint8_t reg) | |
1165 | { | |
1166 | static char buffer[10]; | |
1167 | const char *p = buffer; | |
1168 | if (reg < ARRAY_SIZE(mdi_reg_name)) { | |
1169 | p = mdi_reg_name[reg]; | |
1170 | } else { | |
1171 | snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg); | |
1172 | } | |
1173 | return p; | |
1174 | } | |
663e8e51 TS |
1175 | #endif /* DEBUG_EEPRO100 */ |
1176 | ||
1177 | static uint32_t eepro100_read_mdi(EEPRO100State * s) | |
1178 | { | |
e5e23ab8 | 1179 | uint32_t val = e100_read_reg4(s, SCBCtrlMDI); |
663e8e51 TS |
1180 | |
1181 | #ifdef DEBUG_EEPRO100 | |
1182 | uint8_t raiseint = (val & BIT(29)) >> 29; | |
1183 | uint8_t opcode = (val & BITS(27, 26)) >> 26; | |
1184 | uint8_t phy = (val & BITS(25, 21)) >> 21; | |
1185 | uint8_t reg = (val & BITS(20, 16)) >> 16; | |
1186 | uint16_t data = (val & BITS(15, 0)); | |
1187 | #endif | |
1188 | /* Emulation takes no time to finish MDI transaction. */ | |
1189 | val |= BIT(28); | |
1190 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", | |
1191 | val, raiseint, mdi_op_name[opcode], phy, | |
aac443e6 | 1192 | reg2name(reg), data)); |
663e8e51 TS |
1193 | return val; |
1194 | } | |
1195 | ||
0113f48d | 1196 | static void eepro100_write_mdi(EEPRO100State *s) |
663e8e51 | 1197 | { |
0113f48d | 1198 | uint32_t val = e100_read_reg4(s, SCBCtrlMDI); |
663e8e51 TS |
1199 | uint8_t raiseint = (val & BIT(29)) >> 29; |
1200 | uint8_t opcode = (val & BITS(27, 26)) >> 26; | |
1201 | uint8_t phy = (val & BITS(25, 21)) >> 21; | |
1202 | uint8_t reg = (val & BITS(20, 16)) >> 16; | |
1203 | uint16_t data = (val & BITS(15, 0)); | |
aac443e6 SW |
1204 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", |
1205 | val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data)); | |
663e8e51 TS |
1206 | if (phy != 1) { |
1207 | /* Unsupported PHY address. */ | |
e7493b25 SW |
1208 | #if 0 |
1209 | logout("phy must be 1 but is %u\n", phy); | |
1210 | #endif | |
663e8e51 TS |
1211 | data = 0; |
1212 | } else if (opcode != 1 && opcode != 2) { | |
1213 | /* Unsupported opcode. */ | |
1214 | logout("opcode must be 1 or 2 but is %u\n", opcode); | |
1215 | data = 0; | |
1216 | } else if (reg > 6) { | |
1217 | /* Unsupported register. */ | |
1218 | logout("register must be 0...6 but is %u\n", reg); | |
1219 | data = 0; | |
1220 | } else { | |
1221 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", | |
1222 | val, raiseint, mdi_op_name[opcode], phy, | |
aac443e6 | 1223 | reg2name(reg), data)); |
663e8e51 TS |
1224 | if (opcode == 1) { |
1225 | /* MDI write */ | |
1226 | switch (reg) { | |
1227 | case 0: /* Control Register */ | |
1228 | if (data & 0x8000) { | |
1229 | /* Reset status and control registers to default. */ | |
1230 | s->mdimem[0] = eepro100_mdi_default[0]; | |
1231 | s->mdimem[1] = eepro100_mdi_default[1]; | |
1232 | data = s->mdimem[reg]; | |
1233 | } else { | |
1234 | /* Restart Auto Configuration = Normal Operation */ | |
1235 | data &= ~0x0200; | |
1236 | } | |
1237 | break; | |
1238 | case 1: /* Status Register */ | |
1239 | missing("not writable"); | |
1240 | data = s->mdimem[reg]; | |
1241 | break; | |
1242 | case 2: /* PHY Identification Register (Word 1) */ | |
1243 | case 3: /* PHY Identification Register (Word 2) */ | |
1244 | missing("not implemented"); | |
1245 | break; | |
1246 | case 4: /* Auto-Negotiation Advertisement Register */ | |
1247 | case 5: /* Auto-Negotiation Link Partner Ability Register */ | |
1248 | break; | |
1249 | case 6: /* Auto-Negotiation Expansion Register */ | |
1250 | default: | |
1251 | missing("not implemented"); | |
1252 | } | |
1253 | s->mdimem[reg] = data; | |
1254 | } else if (opcode == 2) { | |
1255 | /* MDI read */ | |
1256 | switch (reg) { | |
1257 | case 0: /* Control Register */ | |
1258 | if (data & 0x8000) { | |
1259 | /* Reset status and control registers to default. */ | |
1260 | s->mdimem[0] = eepro100_mdi_default[0]; | |
1261 | s->mdimem[1] = eepro100_mdi_default[1]; | |
1262 | } | |
1263 | break; | |
1264 | case 1: /* Status Register */ | |
1265 | s->mdimem[reg] |= 0x0020; | |
1266 | break; | |
1267 | case 2: /* PHY Identification Register (Word 1) */ | |
1268 | case 3: /* PHY Identification Register (Word 2) */ | |
1269 | case 4: /* Auto-Negotiation Advertisement Register */ | |
1270 | break; | |
1271 | case 5: /* Auto-Negotiation Link Partner Ability Register */ | |
1272 | s->mdimem[reg] = 0x41fe; | |
1273 | break; | |
1274 | case 6: /* Auto-Negotiation Expansion Register */ | |
1275 | s->mdimem[reg] = 0x0001; | |
1276 | break; | |
1277 | } | |
1278 | data = s->mdimem[reg]; | |
1279 | } | |
1280 | /* Emulation takes no time to finish MDI transaction. | |
1281 | * Set MDI bit in SCB status register. */ | |
1282 | s->mem[SCBAck] |= 0x08; | |
1283 | val |= BIT(28); | |
1284 | if (raiseint) { | |
1285 | eepro100_mdi_interrupt(s); | |
1286 | } | |
1287 | } | |
1288 | val = (val & 0xffff0000) + data; | |
e5e23ab8 | 1289 | e100_write_reg4(s, SCBCtrlMDI, val); |
663e8e51 TS |
1290 | } |
1291 | ||
1292 | /***************************************************************************** | |
1293 | * | |
1294 | * Port emulation. | |
1295 | * | |
1296 | ****************************************************************************/ | |
1297 | ||
1298 | #define PORT_SOFTWARE_RESET 0 | |
1299 | #define PORT_SELFTEST 1 | |
1300 | #define PORT_SELECTIVE_RESET 2 | |
1301 | #define PORT_DUMP 3 | |
1302 | #define PORT_SELECTION_MASK 3 | |
1303 | ||
1304 | typedef struct { | |
1305 | uint32_t st_sign; /* Self Test Signature */ | |
1306 | uint32_t st_result; /* Self Test Results */ | |
c227f099 | 1307 | } eepro100_selftest_t; |
663e8e51 TS |
1308 | |
1309 | static uint32_t eepro100_read_port(EEPRO100State * s) | |
1310 | { | |
1311 | return 0; | |
1312 | } | |
1313 | ||
3fd3d0b4 | 1314 | static void eepro100_write_port(EEPRO100State *s) |
663e8e51 | 1315 | { |
3fd3d0b4 | 1316 | uint32_t val = e100_read_reg4(s, SCBPort); |
663e8e51 TS |
1317 | uint32_t address = (val & ~PORT_SELECTION_MASK); |
1318 | uint8_t selection = (val & PORT_SELECTION_MASK); | |
1319 | switch (selection) { | |
1320 | case PORT_SOFTWARE_RESET: | |
1321 | nic_reset(s); | |
1322 | break; | |
1323 | case PORT_SELFTEST: | |
aac443e6 | 1324 | TRACE(OTHER, logout("selftest address=0x%08x\n", address)); |
c227f099 | 1325 | eepro100_selftest_t data; |
77bee84e | 1326 | cpu_physical_memory_read(address, &data, sizeof(data)); |
663e8e51 TS |
1327 | data.st_sign = 0xffffffff; |
1328 | data.st_result = 0; | |
77bee84e | 1329 | cpu_physical_memory_write(address, &data, sizeof(data)); |
663e8e51 TS |
1330 | break; |
1331 | case PORT_SELECTIVE_RESET: | |
aac443e6 | 1332 | TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address)); |
663e8e51 TS |
1333 | nic_selective_reset(s); |
1334 | break; | |
1335 | default: | |
1336 | logout("val=0x%08x\n", val); | |
1337 | missing("unknown port selection"); | |
1338 | } | |
1339 | } | |
1340 | ||
1341 | /***************************************************************************** | |
1342 | * | |
1343 | * General hardware emulation. | |
1344 | * | |
1345 | ****************************************************************************/ | |
1346 | ||
1347 | static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr) | |
1348 | { | |
ef476062 | 1349 | uint8_t val = 0; |
663e8e51 | 1350 | if (addr <= sizeof(s->mem) - sizeof(val)) { |
e5e23ab8 | 1351 | val = s->mem[addr]; |
663e8e51 TS |
1352 | } |
1353 | ||
1354 | switch (addr) { | |
1355 | case SCBStatus: | |
663e8e51 | 1356 | case SCBAck: |
aac443e6 | 1357 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1358 | break; |
1359 | case SCBCmd: | |
aac443e6 | 1360 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
e7493b25 SW |
1361 | #if 0 |
1362 | val = eepro100_read_command(s); | |
1363 | #endif | |
663e8e51 TS |
1364 | break; |
1365 | case SCBIntmask: | |
aac443e6 | 1366 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1367 | break; |
1368 | case SCBPort + 3: | |
aac443e6 | 1369 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1370 | break; |
1371 | case SCBeeprom: | |
1372 | val = eepro100_read_eeprom(s); | |
1373 | break; | |
0113f48d SW |
1374 | case SCBCtrlMDI: |
1375 | case SCBCtrlMDI + 1: | |
1376 | case SCBCtrlMDI + 2: | |
1377 | case SCBCtrlMDI + 3: | |
1378 | val = (uint8_t)(eepro100_read_mdi(s) >> (8 * (addr & 3))); | |
1379 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); | |
1380 | break; | |
0908bba1 | 1381 | case SCBpmdr: /* Power Management Driver Register */ |
663e8e51 | 1382 | val = 0; |
aac443e6 | 1383 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 | 1384 | break; |
a39bd017 SW |
1385 | case SCBgctrl: /* General Control Register */ |
1386 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); | |
1387 | break; | |
0908bba1 | 1388 | case SCBgstat: /* General Status Register */ |
663e8e51 TS |
1389 | /* 100 Mbps full duplex, valid link */ |
1390 | val = 0x07; | |
aac443e6 | 1391 | TRACE(OTHER, logout("addr=General Status val=%02x\n", val)); |
663e8e51 TS |
1392 | break; |
1393 | default: | |
1394 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1395 | missing("unknown byte read"); | |
1396 | } | |
1397 | return val; | |
1398 | } | |
1399 | ||
1400 | static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr) | |
1401 | { | |
ef476062 | 1402 | uint16_t val = 0; |
663e8e51 | 1403 | if (addr <= sizeof(s->mem) - sizeof(val)) { |
e5e23ab8 | 1404 | val = e100_read_reg2(s, addr); |
663e8e51 TS |
1405 | } |
1406 | ||
663e8e51 TS |
1407 | switch (addr) { |
1408 | case SCBStatus: | |
dbbaaff6 | 1409 | case SCBCmd: |
aac443e6 | 1410 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1411 | break; |
1412 | case SCBeeprom: | |
1413 | val = eepro100_read_eeprom(s); | |
aac443e6 | 1414 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 | 1415 | break; |
0113f48d SW |
1416 | case SCBCtrlMDI: |
1417 | case SCBCtrlMDI + 2: | |
1418 | val = (uint16_t)(eepro100_read_mdi(s) >> (8 * (addr & 3))); | |
1419 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); | |
1420 | break; | |
663e8e51 TS |
1421 | default: |
1422 | logout("addr=%s val=0x%04x\n", regname(addr), val); | |
1423 | missing("unknown word read"); | |
1424 | } | |
1425 | return val; | |
1426 | } | |
1427 | ||
1428 | static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr) | |
1429 | { | |
ef476062 | 1430 | uint32_t val = 0; |
663e8e51 | 1431 | if (addr <= sizeof(s->mem) - sizeof(val)) { |
e5e23ab8 | 1432 | val = e100_read_reg4(s, addr); |
663e8e51 TS |
1433 | } |
1434 | ||
1435 | switch (addr) { | |
1436 | case SCBStatus: | |
aac443e6 | 1437 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1438 | break; |
1439 | case SCBPointer: | |
aac443e6 | 1440 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1441 | break; |
1442 | case SCBPort: | |
1443 | val = eepro100_read_port(s); | |
aac443e6 | 1444 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 | 1445 | break; |
072476ea SW |
1446 | case SCBflash: |
1447 | val = eepro100_read_eeprom(s); | |
1448 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); | |
1449 | break; | |
663e8e51 TS |
1450 | case SCBCtrlMDI: |
1451 | val = eepro100_read_mdi(s); | |
1452 | break; | |
1453 | default: | |
1454 | logout("addr=%s val=0x%08x\n", regname(addr), val); | |
1455 | missing("unknown longword read"); | |
1456 | } | |
1457 | return val; | |
1458 | } | |
1459 | ||
1460 | static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val) | |
1461 | { | |
e74818f3 SW |
1462 | /* SCBStatus is readonly. */ |
1463 | if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) { | |
e5e23ab8 | 1464 | s->mem[addr] = val; |
663e8e51 TS |
1465 | } |
1466 | ||
663e8e51 TS |
1467 | switch (addr) { |
1468 | case SCBStatus: | |
1b4f97d6 | 1469 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1470 | break; |
1471 | case SCBAck: | |
1b4f97d6 | 1472 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1473 | eepro100_acknowledge(s); |
1474 | break; | |
1475 | case SCBCmd: | |
1b4f97d6 | 1476 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1477 | eepro100_write_command(s, val); |
1478 | break; | |
1479 | case SCBIntmask: | |
1b4f97d6 | 1480 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1481 | if (val & BIT(1)) { |
1482 | eepro100_swi_interrupt(s); | |
1483 | } | |
1484 | eepro100_interrupt(s, 0); | |
1485 | break; | |
27a05006 SW |
1486 | case SCBPointer: |
1487 | case SCBPointer + 1: | |
1488 | case SCBPointer + 2: | |
1489 | case SCBPointer + 3: | |
1490 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); | |
1491 | break; | |
3fd3d0b4 SW |
1492 | case SCBPort: |
1493 | case SCBPort + 1: | |
1494 | case SCBPort + 2: | |
1495 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); | |
1496 | break; | |
663e8e51 | 1497 | case SCBPort + 3: |
3fd3d0b4 SW |
1498 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
1499 | eepro100_write_port(s); | |
1500 | break; | |
aac443e6 | 1501 | case SCBFlow: /* does not exist on 82557 */ |
3257d2b6 TS |
1502 | case SCBFlow + 1: |
1503 | case SCBFlow + 2: | |
0908bba1 | 1504 | case SCBpmdr: /* does not exist on 82557 */ |
aac443e6 | 1505 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1506 | break; |
1507 | case SCBeeprom: | |
1b4f97d6 | 1508 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1509 | eepro100_write_eeprom(s->eeprom, val); |
1510 | break; | |
0113f48d SW |
1511 | case SCBCtrlMDI: |
1512 | case SCBCtrlMDI + 1: | |
1513 | case SCBCtrlMDI + 2: | |
1514 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); | |
1515 | break; | |
1516 | case SCBCtrlMDI + 3: | |
1517 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); | |
1518 | eepro100_write_mdi(s); | |
1519 | break; | |
663e8e51 TS |
1520 | default: |
1521 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1522 | missing("unknown byte write"); | |
1523 | } | |
1524 | } | |
1525 | ||
1526 | static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val) | |
1527 | { | |
e74818f3 SW |
1528 | /* SCBStatus is readonly. */ |
1529 | if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) { | |
e5e23ab8 | 1530 | e100_write_reg2(s, addr, val); |
663e8e51 TS |
1531 | } |
1532 | ||
663e8e51 TS |
1533 | switch (addr) { |
1534 | case SCBStatus: | |
1b4f97d6 | 1535 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
e74818f3 | 1536 | s->mem[SCBAck] = (val >> 8); |
663e8e51 TS |
1537 | eepro100_acknowledge(s); |
1538 | break; | |
1539 | case SCBCmd: | |
1b4f97d6 | 1540 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1541 | eepro100_write_command(s, val); |
1542 | eepro100_write1(s, SCBIntmask, val >> 8); | |
1543 | break; | |
27a05006 SW |
1544 | case SCBPointer: |
1545 | case SCBPointer + 2: | |
1546 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); | |
1547 | break; | |
3fd3d0b4 SW |
1548 | case SCBPort: |
1549 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); | |
1550 | break; | |
1551 | case SCBPort + 2: | |
1552 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); | |
1553 | eepro100_write_port(s); | |
1554 | break; | |
663e8e51 | 1555 | case SCBeeprom: |
1b4f97d6 | 1556 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1557 | eepro100_write_eeprom(s->eeprom, val); |
1558 | break; | |
0113f48d SW |
1559 | case SCBCtrlMDI: |
1560 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); | |
1561 | break; | |
1562 | case SCBCtrlMDI + 2: | |
1563 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); | |
1564 | eepro100_write_mdi(s); | |
1565 | break; | |
663e8e51 TS |
1566 | default: |
1567 | logout("addr=%s val=0x%04x\n", regname(addr), val); | |
1568 | missing("unknown word write"); | |
1569 | } | |
1570 | } | |
1571 | ||
1572 | static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val) | |
1573 | { | |
1574 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
e5e23ab8 | 1575 | e100_write_reg4(s, addr, val); |
663e8e51 TS |
1576 | } |
1577 | ||
1578 | switch (addr) { | |
1579 | case SCBPointer: | |
27a05006 | 1580 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1581 | break; |
1582 | case SCBPort: | |
aac443e6 | 1583 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
3fd3d0b4 | 1584 | eepro100_write_port(s); |
663e8e51 | 1585 | break; |
072476ea SW |
1586 | case SCBflash: |
1587 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); | |
1588 | val = val >> 16; | |
1589 | eepro100_write_eeprom(s->eeprom, val); | |
1590 | break; | |
663e8e51 | 1591 | case SCBCtrlMDI: |
0113f48d SW |
1592 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
1593 | eepro100_write_mdi(s); | |
663e8e51 TS |
1594 | break; |
1595 | default: | |
1596 | logout("addr=%s val=0x%08x\n", regname(addr), val); | |
1597 | missing("unknown longword write"); | |
1598 | } | |
1599 | } | |
1600 | ||
aac443e6 SW |
1601 | /***************************************************************************** |
1602 | * | |
1603 | * Port mapped I/O. | |
1604 | * | |
1605 | ****************************************************************************/ | |
1606 | ||
663e8e51 TS |
1607 | static uint32_t ioport_read1(void *opaque, uint32_t addr) |
1608 | { | |
1609 | EEPRO100State *s = opaque; | |
e7493b25 SW |
1610 | #if 0 |
1611 | logout("addr=%s\n", regname(addr)); | |
1612 | #endif | |
22ec6093 | 1613 | return eepro100_read1(s, addr - s->region1); |
663e8e51 TS |
1614 | } |
1615 | ||
1616 | static uint32_t ioport_read2(void *opaque, uint32_t addr) | |
1617 | { | |
1618 | EEPRO100State *s = opaque; | |
22ec6093 | 1619 | return eepro100_read2(s, addr - s->region1); |
663e8e51 TS |
1620 | } |
1621 | ||
1622 | static uint32_t ioport_read4(void *opaque, uint32_t addr) | |
1623 | { | |
1624 | EEPRO100State *s = opaque; | |
22ec6093 | 1625 | return eepro100_read4(s, addr - s->region1); |
663e8e51 TS |
1626 | } |
1627 | ||
1628 | static void ioport_write1(void *opaque, uint32_t addr, uint32_t val) | |
1629 | { | |
1630 | EEPRO100State *s = opaque; | |
e7493b25 SW |
1631 | #if 0 |
1632 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1633 | #endif | |
22ec6093 | 1634 | eepro100_write1(s, addr - s->region1, val); |
663e8e51 TS |
1635 | } |
1636 | ||
1637 | static void ioport_write2(void *opaque, uint32_t addr, uint32_t val) | |
1638 | { | |
1639 | EEPRO100State *s = opaque; | |
22ec6093 | 1640 | eepro100_write2(s, addr - s->region1, val); |
663e8e51 TS |
1641 | } |
1642 | ||
1643 | static void ioport_write4(void *opaque, uint32_t addr, uint32_t val) | |
1644 | { | |
1645 | EEPRO100State *s = opaque; | |
22ec6093 | 1646 | eepro100_write4(s, addr - s->region1, val); |
663e8e51 TS |
1647 | } |
1648 | ||
1649 | /***********************************************************/ | |
1650 | /* PCI EEPRO100 definitions */ | |
1651 | ||
663e8e51 | 1652 | static void pci_map(PCIDevice * pci_dev, int region_num, |
6e355d90 | 1653 | pcibus_t addr, pcibus_t size, int type) |
663e8e51 | 1654 | { |
273a2142 | 1655 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
663e8e51 | 1656 | |
89e8b13c IY |
1657 | TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", " |
1658 | "size=0x%08"FMT_PCIBUS", type=%d\n", | |
aac443e6 | 1659 | region_num, addr, size, type)); |
663e8e51 TS |
1660 | |
1661 | assert(region_num == 1); | |
1662 | register_ioport_write(addr, size, 1, ioport_write1, s); | |
1663 | register_ioport_read(addr, size, 1, ioport_read1, s); | |
1664 | register_ioport_write(addr, size, 2, ioport_write2, s); | |
1665 | register_ioport_read(addr, size, 2, ioport_read2, s); | |
1666 | register_ioport_write(addr, size, 4, ioport_write4, s); | |
1667 | register_ioport_read(addr, size, 4, ioport_read4, s); | |
1668 | ||
22ec6093 | 1669 | s->region1 = addr; |
663e8e51 TS |
1670 | } |
1671 | ||
aac443e6 SW |
1672 | /***************************************************************************** |
1673 | * | |
1674 | * Memory mapped I/O. | |
1675 | * | |
1676 | ****************************************************************************/ | |
1677 | ||
c227f099 | 1678 | static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1679 | { |
1680 | EEPRO100State *s = opaque; | |
e7493b25 SW |
1681 | #if 0 |
1682 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1683 | #endif | |
663e8e51 TS |
1684 | eepro100_write1(s, addr, val); |
1685 | } | |
1686 | ||
c227f099 | 1687 | static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1688 | { |
1689 | EEPRO100State *s = opaque; | |
e7493b25 SW |
1690 | #if 0 |
1691 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1692 | #endif | |
663e8e51 TS |
1693 | eepro100_write2(s, addr, val); |
1694 | } | |
1695 | ||
c227f099 | 1696 | static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
663e8e51 TS |
1697 | { |
1698 | EEPRO100State *s = opaque; | |
e7493b25 SW |
1699 | #if 0 |
1700 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1701 | #endif | |
663e8e51 TS |
1702 | eepro100_write4(s, addr, val); |
1703 | } | |
1704 | ||
c227f099 | 1705 | static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1706 | { |
1707 | EEPRO100State *s = opaque; | |
e7493b25 SW |
1708 | #if 0 |
1709 | logout("addr=%s\n", regname(addr)); | |
1710 | #endif | |
663e8e51 TS |
1711 | return eepro100_read1(s, addr); |
1712 | } | |
1713 | ||
c227f099 | 1714 | static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1715 | { |
1716 | EEPRO100State *s = opaque; | |
e7493b25 SW |
1717 | #if 0 |
1718 | logout("addr=%s\n", regname(addr)); | |
1719 | #endif | |
663e8e51 TS |
1720 | return eepro100_read2(s, addr); |
1721 | } | |
1722 | ||
c227f099 | 1723 | static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr) |
663e8e51 TS |
1724 | { |
1725 | EEPRO100State *s = opaque; | |
e7493b25 SW |
1726 | #if 0 |
1727 | logout("addr=%s\n", regname(addr)); | |
1728 | #endif | |
663e8e51 TS |
1729 | return eepro100_read4(s, addr); |
1730 | } | |
1731 | ||
d60efc6b | 1732 | static CPUWriteMemoryFunc * const pci_mmio_write[] = { |
663e8e51 TS |
1733 | pci_mmio_writeb, |
1734 | pci_mmio_writew, | |
1735 | pci_mmio_writel | |
1736 | }; | |
1737 | ||
d60efc6b | 1738 | static CPUReadMemoryFunc * const pci_mmio_read[] = { |
663e8e51 TS |
1739 | pci_mmio_readb, |
1740 | pci_mmio_readw, | |
1741 | pci_mmio_readl | |
1742 | }; | |
1743 | ||
e00e365e | 1744 | static int nic_can_receive(VLANClientState *nc) |
663e8e51 | 1745 | { |
e00e365e | 1746 | EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
aac443e6 | 1747 | TRACE(RXTX, logout("%p\n", s)); |
663e8e51 | 1748 | return get_ru_state(s) == ru_ready; |
e7493b25 SW |
1749 | #if 0 |
1750 | return !eepro100_buffer_full(s); | |
1751 | #endif | |
663e8e51 TS |
1752 | } |
1753 | ||
e00e365e | 1754 | static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size) |
663e8e51 TS |
1755 | { |
1756 | /* TODO: | |
1757 | * - Magic packets should set bit 30 in power management driver register. | |
1758 | * - Interesting packets should set bit 29 in power management driver register. | |
1759 | */ | |
e00e365e | 1760 | EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
663e8e51 | 1761 | uint16_t rfd_status = 0xa000; |
792f1d63 SW |
1762 | #if defined(CONFIG_PAD_RECEIVED_FRAMES) |
1763 | uint8_t min_buf[60]; | |
1764 | #endif | |
663e8e51 TS |
1765 | static const uint8_t broadcast_macaddr[6] = |
1766 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
1767 | ||
792f1d63 SW |
1768 | #if defined(CONFIG_PAD_RECEIVED_FRAMES) |
1769 | /* Pad to minimum Ethernet frame length */ | |
1770 | if (size < sizeof(min_buf)) { | |
1771 | memcpy(min_buf, buf, size); | |
1772 | memset(&min_buf[size], 0, sizeof(min_buf) - size); | |
1773 | buf = min_buf; | |
1774 | size = sizeof(min_buf); | |
1775 | } | |
1776 | #endif | |
1777 | ||
663e8e51 TS |
1778 | if (s->configuration[8] & 0x80) { |
1779 | /* CSMA is disabled. */ | |
1780 | logout("%p received while CSMA is disabled\n", s); | |
4f1c942b | 1781 | return -1; |
792f1d63 | 1782 | #if !defined(CONFIG_PAD_RECEIVED_FRAMES) |
ced5296a | 1783 | } else if (size < 64 && (s->configuration[7] & BIT(0))) { |
663e8e51 TS |
1784 | /* Short frame and configuration byte 7/0 (discard short receive) set: |
1785 | * Short frame is discarded */ | |
067d01de | 1786 | logout("%p received short frame (%zu byte)\n", s, size); |
663e8e51 | 1787 | s->statistics.rx_short_frame_errors++; |
e7493b25 SW |
1788 | return -1; |
1789 | #endif | |
ced5296a | 1790 | } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) { |
663e8e51 TS |
1791 | /* Long frame and configuration byte 18/3 (long receive ok) not set: |
1792 | * Long frames are discarded. */ | |
067d01de | 1793 | logout("%p received long frame (%zu byte), ignored\n", s, size); |
4f1c942b | 1794 | return -1; |
e7493b25 | 1795 | } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */ |
663e8e51 TS |
1796 | /* Frame matches individual address. */ |
1797 | /* TODO: check configuration byte 15/4 (ignore U/L). */ | |
067d01de | 1798 | TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size)); |
663e8e51 TS |
1799 | } else if (memcmp(buf, broadcast_macaddr, 6) == 0) { |
1800 | /* Broadcast frame. */ | |
067d01de | 1801 | TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size)); |
663e8e51 | 1802 | rfd_status |= 0x0002; |
7b8737de | 1803 | } else if (buf[0] & 0x01) { |
663e8e51 | 1804 | /* Multicast frame. */ |
7b8737de | 1805 | TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size))); |
7f1e9d4e | 1806 | if (s->configuration[21] & BIT(3)) { |
7b8737de SW |
1807 | /* Multicast all bit is set, receive all multicast frames. */ |
1808 | } else { | |
1809 | unsigned mcast_idx = compute_mcast_idx(buf); | |
1810 | assert(mcast_idx < 64); | |
1811 | if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) { | |
1812 | /* Multicast frame is allowed in hash table. */ | |
ced5296a | 1813 | } else if (s->configuration[15] & BIT(0)) { |
7b8737de SW |
1814 | /* Promiscuous: receive all. */ |
1815 | rfd_status |= 0x0004; | |
1816 | } else { | |
1817 | TRACE(RXTX, logout("%p multicast ignored\n", s)); | |
1818 | return -1; | |
1819 | } | |
663e8e51 | 1820 | } |
7b8737de | 1821 | /* TODO: Next not for promiscuous mode? */ |
663e8e51 | 1822 | rfd_status |= 0x0002; |
ced5296a | 1823 | } else if (s->configuration[15] & BIT(0)) { |
663e8e51 | 1824 | /* Promiscuous: receive all. */ |
067d01de | 1825 | TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size)); |
663e8e51 | 1826 | rfd_status |= 0x0004; |
010ec629 SW |
1827 | } else if (s->configuration[20] & BIT(6)) { |
1828 | /* Multiple IA bit set. */ | |
1829 | unsigned mcast_idx = compute_mcast_idx(buf); | |
1830 | assert(mcast_idx < 64); | |
1831 | if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) { | |
1832 | TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s)); | |
1833 | } else { | |
1834 | TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s)); | |
1835 | return -1; | |
1836 | } | |
663e8e51 | 1837 | } else { |
067d01de | 1838 | TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size, |
aac443e6 | 1839 | nic_dump(buf, size))); |
4f1c942b | 1840 | return size; |
663e8e51 TS |
1841 | } |
1842 | ||
1843 | if (get_ru_state(s) != ru_ready) { | |
aac443e6 SW |
1844 | /* No resources available. */ |
1845 | logout("no resources, state=%u\n", get_ru_state(s)); | |
e824012b SW |
1846 | /* TODO: RNR interrupt only at first failed frame? */ |
1847 | eepro100_rnr_interrupt(s); | |
663e8e51 | 1848 | s->statistics.rx_resource_errors++; |
e7493b25 SW |
1849 | #if 0 |
1850 | assert(!"no resources"); | |
1851 | #endif | |
4f1c942b | 1852 | return -1; |
663e8e51 | 1853 | } |
e7493b25 | 1854 | /* !!! */ |
c227f099 | 1855 | eepro100_rx_t rx; |
77bee84e | 1856 | cpu_physical_memory_read(s->ru_base + s->ru_offset, &rx, |
27112f18 | 1857 | sizeof(eepro100_rx_t)); |
663e8e51 TS |
1858 | uint16_t rfd_command = le16_to_cpu(rx.command); |
1859 | uint16_t rfd_size = le16_to_cpu(rx.size); | |
7f1e9d4e KW |
1860 | |
1861 | if (size > rfd_size) { | |
1862 | logout("Receive buffer (%" PRId16 " bytes) too small for data " | |
1863 | "(%zu bytes); data truncated\n", rfd_size, size); | |
1864 | size = rfd_size; | |
1865 | } | |
792f1d63 | 1866 | #if !defined(CONFIG_PAD_RECEIVED_FRAMES) |
663e8e51 TS |
1867 | if (size < 64) { |
1868 | rfd_status |= 0x0080; | |
1869 | } | |
792f1d63 | 1870 | #endif |
aac443e6 SW |
1871 | TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", |
1872 | rfd_command, rx.link, rx.rx_buf_addr, rfd_size)); | |
e5e23ab8 SW |
1873 | e100_stw_le_phys(s->ru_base + s->ru_offset + |
1874 | offsetof(eepro100_rx_t, status), rfd_status); | |
1875 | e100_stw_le_phys(s->ru_base + s->ru_offset + | |
1876 | offsetof(eepro100_rx_t, count), size); | |
663e8e51 | 1877 | /* Early receive interrupt not supported. */ |
e7493b25 SW |
1878 | #if 0 |
1879 | eepro100_er_interrupt(s); | |
1880 | #endif | |
663e8e51 | 1881 | /* Receive CRC Transfer not supported. */ |
ced5296a | 1882 | if (s->configuration[18] & BIT(2)) { |
7f1e9d4e KW |
1883 | missing("Receive CRC Transfer"); |
1884 | return -1; | |
1885 | } | |
663e8e51 | 1886 | /* TODO: check stripping enable bit. */ |
e7493b25 SW |
1887 | #if 0 |
1888 | assert(!(s->configuration[17] & BIT(0))); | |
1889 | #endif | |
663e8e51 | 1890 | cpu_physical_memory_write(s->ru_base + s->ru_offset + |
27112f18 | 1891 | sizeof(eepro100_rx_t), buf, size); |
663e8e51 TS |
1892 | s->statistics.rx_good_frames++; |
1893 | eepro100_fr_interrupt(s); | |
1894 | s->ru_offset = le32_to_cpu(rx.link); | |
ced5296a | 1895 | if (rfd_command & COMMAND_EL) { |
663e8e51 | 1896 | /* EL bit is set, so this was the last frame. */ |
7f1e9d4e KW |
1897 | logout("receive: Running out of frames\n"); |
1898 | set_ru_state(s, ru_suspended); | |
663e8e51 | 1899 | } |
ced5296a | 1900 | if (rfd_command & COMMAND_S) { |
663e8e51 TS |
1901 | /* S bit is set. */ |
1902 | set_ru_state(s, ru_suspended); | |
1903 | } | |
4f1c942b | 1904 | return size; |
663e8e51 TS |
1905 | } |
1906 | ||
151b2986 JQ |
1907 | static const VMStateDescription vmstate_eepro100 = { |
1908 | .version_id = 3, | |
1909 | .minimum_version_id = 2, | |
1910 | .minimum_version_id_old = 2, | |
1911 | .fields = (VMStateField []) { | |
1912 | VMSTATE_PCI_DEVICE(dev, EEPRO100State), | |
1913 | VMSTATE_UNUSED(32), | |
1914 | VMSTATE_BUFFER(mult, EEPRO100State), | |
1915 | VMSTATE_BUFFER(mem, EEPRO100State), | |
1916 | /* Save all members of struct between scb_stat and mem. */ | |
1917 | VMSTATE_UINT8(scb_stat, EEPRO100State), | |
1918 | VMSTATE_UINT8(int_stat, EEPRO100State), | |
1919 | VMSTATE_UNUSED(3*4), | |
1920 | VMSTATE_MACADDR(conf.macaddr, EEPRO100State), | |
1921 | VMSTATE_UNUSED(19*4), | |
1922 | VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32), | |
1923 | /* The eeprom should be saved and restored by its own routines. */ | |
1924 | VMSTATE_UINT32(device, EEPRO100State), | |
1925 | /* TODO check device. */ | |
151b2986 JQ |
1926 | VMSTATE_UINT32(cu_base, EEPRO100State), |
1927 | VMSTATE_UINT32(cu_offset, EEPRO100State), | |
1928 | VMSTATE_UINT32(ru_base, EEPRO100State), | |
1929 | VMSTATE_UINT32(ru_offset, EEPRO100State), | |
1930 | VMSTATE_UINT32(statsaddr, EEPRO100State), | |
ba42b646 | 1931 | /* Save eepro100_stats_t statistics. */ |
151b2986 JQ |
1932 | VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State), |
1933 | VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State), | |
1934 | VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State), | |
1935 | VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State), | |
1936 | VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State), | |
1937 | VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State), | |
1938 | VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State), | |
1939 | VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State), | |
1940 | VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State), | |
1941 | VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State), | |
1942 | VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State), | |
1943 | VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State), | |
1944 | VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State), | |
1945 | VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State), | |
1946 | VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State), | |
1947 | VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State), | |
1948 | VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State), | |
1949 | VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State), | |
1950 | VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State), | |
1951 | VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State), | |
1952 | VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State), | |
151b2986 JQ |
1953 | /* Configuration bytes. */ |
1954 | VMSTATE_BUFFER(configuration, EEPRO100State), | |
1955 | VMSTATE_END_OF_LIST() | |
aac443e6 | 1956 | } |
151b2986 | 1957 | }; |
663e8e51 | 1958 | |
e00e365e | 1959 | static void nic_cleanup(VLANClientState *nc) |
b946a153 | 1960 | { |
e00e365e | 1961 | EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
b946a153 | 1962 | |
e00e365e | 1963 | s->nic = NULL; |
b946a153 AL |
1964 | } |
1965 | ||
c4c270e2 | 1966 | static int pci_nic_uninit(PCIDevice *pci_dev) |
b946a153 | 1967 | { |
c4c270e2 | 1968 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
b946a153 AL |
1969 | |
1970 | cpu_unregister_io_memory(s->mmio_index); | |
0be71e32 | 1971 | vmstate_unregister(&pci_dev->qdev, s->vmstate, s); |
5fce2b3e | 1972 | eeprom93xx_free(&pci_dev->qdev, s->eeprom); |
e00e365e | 1973 | qemu_del_vlan_client(&s->nic->nc); |
b946a153 AL |
1974 | return 0; |
1975 | } | |
1976 | ||
e00e365e MM |
1977 | static NetClientInfo net_eepro100_info = { |
1978 | .type = NET_CLIENT_TYPE_NIC, | |
1979 | .size = sizeof(NICState), | |
1980 | .can_receive = nic_can_receive, | |
1981 | .receive = nic_receive, | |
1982 | .cleanup = nic_cleanup, | |
1983 | }; | |
1984 | ||
558c8634 | 1985 | static int e100_nic_init(PCIDevice *pci_dev) |
663e8e51 | 1986 | { |
273a2142 | 1987 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
558c8634 SW |
1988 | E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev, |
1989 | pci_dev->qdev.info); | |
663e8e51 | 1990 | |
aac443e6 | 1991 | TRACE(OTHER, logout("\n")); |
663e8e51 | 1992 | |
558c8634 | 1993 | s->device = e100_device->device; |
663e8e51 | 1994 | |
558c8634 | 1995 | e100_pci_reset(s, e100_device); |
663e8e51 TS |
1996 | |
1997 | /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM, | |
1998 | * i82559 and later support 64 or 256 word EEPROM. */ | |
5fce2b3e | 1999 | s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE); |
663e8e51 TS |
2000 | |
2001 | /* Handler for memory-mapped I/O */ | |
273a2142 | 2002 | s->mmio_index = |
2507c12a | 2003 | cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s, |
e5e23ab8 | 2004 | DEVICE_LITTLE_ENDIAN); |
663e8e51 | 2005 | |
22ec6093 AK |
2006 | pci_register_bar_simple(&s->dev, 0, PCI_MEM_SIZE, |
2007 | PCI_BASE_ADDRESS_MEM_PREFETCH, s->mmio_index); | |
2008 | ||
0392a017 | 2009 | pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO, |
663e8e51 | 2010 | pci_map); |
22ec6093 | 2011 | pci_register_bar_simple(&s->dev, 2, PCI_FLASH_SIZE, 0, s->mmio_index); |
663e8e51 | 2012 | |
508ef936 | 2013 | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
ce0e58b3 | 2014 | logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)); |
22ec6093 | 2015 | assert(s->region1 == 0); |
663e8e51 TS |
2016 | |
2017 | nic_reset(s); | |
2018 | ||
e00e365e MM |
2019 | s->nic = qemu_new_nic(&net_eepro100_info, &s->conf, |
2020 | pci_dev->qdev.info->name, pci_dev->qdev.id, s); | |
663e8e51 | 2021 | |
e00e365e MM |
2022 | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
2023 | TRACE(OTHER, logout("%s\n", s->nic->nc.info_str)); | |
663e8e51 | 2024 | |
a08d4367 | 2025 | qemu_register_reset(nic_reset, s); |
663e8e51 | 2026 | |
151b2986 JQ |
2027 | s->vmstate = qemu_malloc(sizeof(vmstate_eepro100)); |
2028 | memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100)); | |
e00e365e | 2029 | s->vmstate->name = s->nic->nc.model; |
0be71e32 | 2030 | vmstate_register(&pci_dev->qdev, -1, s->vmstate, s); |
4e9df06a | 2031 | |
1ca4d09a GN |
2032 | add_boot_device_path(s->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0"); |
2033 | ||
81a322d4 | 2034 | return 0; |
663e8e51 TS |
2035 | } |
2036 | ||
558c8634 | 2037 | static E100PCIDeviceInfo e100_devices[] = { |
0aab0d3a | 2038 | { |
558c8634 SW |
2039 | .pci.qdev.name = "i82550", |
2040 | .pci.qdev.desc = "Intel i82550 Ethernet", | |
2041 | .device = i82550, | |
2042 | /* TODO: check device id. */ | |
2043 | .device_id = PCI_DEVICE_ID_INTEL_82551IT, | |
2044 | /* Revision ID: 0x0c, 0x0d, 0x0e. */ | |
2045 | .revision = 0x0e, | |
2046 | /* TODO: check size of statistical counters. */ | |
2047 | .stats_size = 80, | |
2048 | /* TODO: check extended tcb support. */ | |
2049 | .has_extended_tcb_support = true, | |
2050 | .power_management = true, | |
c4c270e2 | 2051 | },{ |
558c8634 SW |
2052 | .pci.qdev.name = "i82551", |
2053 | .pci.qdev.desc = "Intel i82551 Ethernet", | |
2054 | .device = i82551, | |
2055 | .device_id = PCI_DEVICE_ID_INTEL_82551IT, | |
2056 | /* Revision ID: 0x0f, 0x10. */ | |
2057 | .revision = 0x0f, | |
2058 | /* TODO: check size of statistical counters. */ | |
2059 | .stats_size = 80, | |
2060 | .has_extended_tcb_support = true, | |
2061 | .power_management = true, | |
0aab0d3a | 2062 | },{ |
558c8634 SW |
2063 | .pci.qdev.name = "i82557a", |
2064 | .pci.qdev.desc = "Intel i82557A Ethernet", | |
2065 | .device = i82557A, | |
2066 | .device_id = PCI_DEVICE_ID_INTEL_82557, | |
2067 | .revision = 0x01, | |
2068 | .power_management = false, | |
c4c270e2 | 2069 | },{ |
558c8634 SW |
2070 | .pci.qdev.name = "i82557b", |
2071 | .pci.qdev.desc = "Intel i82557B Ethernet", | |
2072 | .device = i82557B, | |
2073 | .device_id = PCI_DEVICE_ID_INTEL_82557, | |
2074 | .revision = 0x02, | |
2075 | .power_management = false, | |
c4c270e2 | 2076 | },{ |
558c8634 SW |
2077 | .pci.qdev.name = "i82557c", |
2078 | .pci.qdev.desc = "Intel i82557C Ethernet", | |
2079 | .device = i82557C, | |
2080 | .device_id = PCI_DEVICE_ID_INTEL_82557, | |
2081 | .revision = 0x03, | |
2082 | .power_management = false, | |
c4c270e2 | 2083 | },{ |
558c8634 SW |
2084 | .pci.qdev.name = "i82558a", |
2085 | .pci.qdev.desc = "Intel i82558A Ethernet", | |
2086 | .device = i82558A, | |
2087 | .device_id = PCI_DEVICE_ID_INTEL_82557, | |
2088 | .revision = 0x04, | |
2089 | .stats_size = 76, | |
2090 | .has_extended_tcb_support = true, | |
2091 | .power_management = true, | |
c4c270e2 | 2092 | },{ |
558c8634 SW |
2093 | .pci.qdev.name = "i82558b", |
2094 | .pci.qdev.desc = "Intel i82558B Ethernet", | |
2095 | .device = i82558B, | |
2096 | .device_id = PCI_DEVICE_ID_INTEL_82557, | |
2097 | .revision = 0x05, | |
2098 | .stats_size = 76, | |
2099 | .has_extended_tcb_support = true, | |
2100 | .power_management = true, | |
c4c270e2 | 2101 | },{ |
558c8634 SW |
2102 | .pci.qdev.name = "i82559a", |
2103 | .pci.qdev.desc = "Intel i82559A Ethernet", | |
2104 | .device = i82559A, | |
2105 | .device_id = PCI_DEVICE_ID_INTEL_82557, | |
2106 | .revision = 0x06, | |
2107 | .stats_size = 80, | |
2108 | .has_extended_tcb_support = true, | |
2109 | .power_management = true, | |
c4c270e2 | 2110 | },{ |
558c8634 SW |
2111 | .pci.qdev.name = "i82559b", |
2112 | .pci.qdev.desc = "Intel i82559B Ethernet", | |
2113 | .device = i82559B, | |
2114 | .device_id = PCI_DEVICE_ID_INTEL_82557, | |
2115 | .revision = 0x07, | |
2116 | .stats_size = 80, | |
2117 | .has_extended_tcb_support = true, | |
2118 | .power_management = true, | |
0aab0d3a | 2119 | },{ |
558c8634 SW |
2120 | .pci.qdev.name = "i82559c", |
2121 | .pci.qdev.desc = "Intel i82559C Ethernet", | |
2122 | .device = i82559C, | |
2123 | .device_id = PCI_DEVICE_ID_INTEL_82557, | |
2124 | #if 0 | |
2125 | .revision = 0x08, | |
2126 | #endif | |
2127 | /* TODO: Windows wants revision id 0x0c. */ | |
2128 | .revision = 0x0c, | |
2129 | .stats_size = 80, | |
2130 | .has_extended_tcb_support = true, | |
2131 | .power_management = true, | |
c4c270e2 | 2132 | },{ |
558c8634 SW |
2133 | .pci.qdev.name = "i82559er", |
2134 | .pci.qdev.desc = "Intel i82559ER Ethernet", | |
2135 | .device = i82559ER, | |
2136 | .device_id = PCI_DEVICE_ID_INTEL_82551IT, | |
2137 | .revision = 0x09, | |
2138 | .stats_size = 80, | |
2139 | .has_extended_tcb_support = true, | |
2140 | .power_management = true, | |
0aab0d3a | 2141 | },{ |
558c8634 SW |
2142 | .pci.qdev.name = "i82562", |
2143 | .pci.qdev.desc = "Intel i82562 Ethernet", | |
2144 | .device = i82562, | |
2145 | /* TODO: check device id. */ | |
2146 | .device_id = PCI_DEVICE_ID_INTEL_82551IT, | |
2147 | /* TODO: wrong revision id. */ | |
2148 | .revision = 0x0e, | |
2149 | .stats_size = 80, | |
2150 | .has_extended_tcb_support = true, | |
2151 | .power_management = true, | |
db667a12 SW |
2152 | },{ |
2153 | /* Toshiba Tecra 8200. */ | |
2154 | .pci.qdev.name = "i82801", | |
2155 | .pci.qdev.desc = "Intel i82801 Ethernet", | |
2156 | .device = i82801, | |
2157 | .device_id = 0x2449, | |
2158 | .revision = 0x03, | |
2159 | .stats_size = 80, | |
2160 | .has_extended_tcb_support = true, | |
2161 | .power_management = true, | |
0aab0d3a GH |
2162 | } |
2163 | }; | |
2164 | ||
558c8634 SW |
2165 | static Property e100_properties[] = { |
2166 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2167 | DEFINE_PROP_END_OF_LIST(), | |
2168 | }; | |
2169 | ||
9d07d757 | 2170 | static void eepro100_register_devices(void) |
663e8e51 | 2171 | { |
558c8634 SW |
2172 | size_t i; |
2173 | for (i = 0; i < ARRAY_SIZE(e100_devices); i++) { | |
2174 | PCIDeviceInfo *pci_dev = &e100_devices[i].pci; | |
0389ced4 SW |
2175 | /* We use the same rom file for all device ids. |
2176 | QEMU fixes the device id during rom load. */ | |
5ee8ad71 | 2177 | pci_dev->romfile = "pxe-eepro100.rom"; |
558c8634 SW |
2178 | pci_dev->init = e100_nic_init; |
2179 | pci_dev->exit = pci_nic_uninit; | |
2180 | pci_dev->qdev.props = e100_properties; | |
2181 | pci_dev->qdev.size = sizeof(EEPRO100State); | |
2182 | pci_qdev_register(pci_dev); | |
2183 | } | |
663e8e51 TS |
2184 | } |
2185 | ||
9d07d757 | 2186 | device_init(eepro100_register_devices) |