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Commit | Line | Data |
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6f7e9aec | 1 | /* |
67e999be | 2 | * QEMU ESP/NCR53C9x emulation |
5fafdf24 | 3 | * |
4e9aec74 | 4 | * Copyright (c) 2005-2006 Fabrice Bellard |
5fafdf24 | 5 | * |
6f7e9aec FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
5d20fa6b | 24 | |
cfb9de9c | 25 | #include "sysbus.h" |
43b443b6 | 26 | #include "scsi.h" |
1cd3af54 | 27 | #include "esp.h" |
bf4b9889 | 28 | #include "trace.h" |
6f7e9aec | 29 | |
67e999be | 30 | /* |
5ad6bb97 BS |
31 | * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), |
32 | * also produced as NCR89C100. See | |
67e999be FB |
33 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt |
34 | * and | |
35 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt | |
36 | */ | |
37 | ||
001faf32 BS |
38 | #define ESP_ERROR(fmt, ...) \ |
39 | do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) | |
8dea1dd4 | 40 | |
5aca8c3b | 41 | #define ESP_REGS 16 |
8dea1dd4 | 42 | #define TI_BUFSZ 16 |
67e999be | 43 | |
4e9aec74 | 44 | typedef struct ESPState ESPState; |
6f7e9aec | 45 | |
4e9aec74 | 46 | struct ESPState { |
cfb9de9c | 47 | SysBusDevice busdev; |
5aca8c3b BS |
48 | uint8_t rregs[ESP_REGS]; |
49 | uint8_t wregs[ESP_REGS]; | |
9a975d63 BS |
50 | qemu_irq irq; |
51 | uint32_t it_shift; | |
67e999be | 52 | int32_t ti_size; |
4f6200f0 | 53 | uint32_t ti_rptr, ti_wptr; |
3944966d | 54 | uint32_t status; |
22548760 | 55 | uint32_t dma; |
9a975d63 | 56 | uint8_t ti_buf[TI_BUFSZ]; |
ca9c39fa | 57 | SCSIBus bus; |
2e5d83bb | 58 | SCSIDevice *current_dev; |
5c6c0e51 | 59 | SCSIRequest *current_req; |
9f149aa9 | 60 | uint8_t cmdbuf[TI_BUFSZ]; |
22548760 BS |
61 | uint32_t cmdlen; |
62 | uint32_t do_cmd; | |
4d611c9a | 63 | |
6787f5fa | 64 | /* The amount of data left in the current DMA transfer. */ |
4d611c9a | 65 | uint32_t dma_left; |
6787f5fa PB |
66 | /* The size of the current DMA transfer. Zero if no transfer is in |
67 | progress. */ | |
68 | uint32_t dma_counter; | |
9a975d63 BS |
69 | int dma_enabled; |
70 | ||
4d611c9a | 71 | uint32_t async_len; |
9a975d63 | 72 | uint8_t *async_buf; |
8b17de88 | 73 | |
ff9868ec BS |
74 | ESPDMAMemoryReadWriteFunc dma_memory_read; |
75 | ESPDMAMemoryReadWriteFunc dma_memory_write; | |
67e999be | 76 | void *dma_opaque; |
73d74342 | 77 | void (*dma_cb)(ESPState *s); |
4e9aec74 | 78 | }; |
6f7e9aec | 79 | |
5ad6bb97 BS |
80 | #define ESP_TCLO 0x0 |
81 | #define ESP_TCMID 0x1 | |
82 | #define ESP_FIFO 0x2 | |
83 | #define ESP_CMD 0x3 | |
84 | #define ESP_RSTAT 0x4 | |
85 | #define ESP_WBUSID 0x4 | |
86 | #define ESP_RINTR 0x5 | |
87 | #define ESP_WSEL 0x5 | |
88 | #define ESP_RSEQ 0x6 | |
89 | #define ESP_WSYNTP 0x6 | |
90 | #define ESP_RFLAGS 0x7 | |
91 | #define ESP_WSYNO 0x7 | |
92 | #define ESP_CFG1 0x8 | |
93 | #define ESP_RRES1 0x9 | |
94 | #define ESP_WCCF 0x9 | |
95 | #define ESP_RRES2 0xa | |
96 | #define ESP_WTEST 0xa | |
97 | #define ESP_CFG2 0xb | |
98 | #define ESP_CFG3 0xc | |
99 | #define ESP_RES3 0xd | |
100 | #define ESP_TCHI 0xe | |
101 | #define ESP_RES4 0xf | |
102 | ||
103 | #define CMD_DMA 0x80 | |
104 | #define CMD_CMD 0x7f | |
105 | ||
106 | #define CMD_NOP 0x00 | |
107 | #define CMD_FLUSH 0x01 | |
108 | #define CMD_RESET 0x02 | |
109 | #define CMD_BUSRESET 0x03 | |
110 | #define CMD_TI 0x10 | |
111 | #define CMD_ICCS 0x11 | |
112 | #define CMD_MSGACC 0x12 | |
0fd0eb21 | 113 | #define CMD_PAD 0x18 |
5ad6bb97 | 114 | #define CMD_SATN 0x1a |
5e1e0a3b | 115 | #define CMD_SEL 0x41 |
5ad6bb97 BS |
116 | #define CMD_SELATN 0x42 |
117 | #define CMD_SELATNS 0x43 | |
118 | #define CMD_ENSEL 0x44 | |
119 | ||
2f275b8f FB |
120 | #define STAT_DO 0x00 |
121 | #define STAT_DI 0x01 | |
122 | #define STAT_CD 0x02 | |
123 | #define STAT_ST 0x03 | |
8dea1dd4 BS |
124 | #define STAT_MO 0x06 |
125 | #define STAT_MI 0x07 | |
5ad6bb97 | 126 | #define STAT_PIO_MASK 0x06 |
2f275b8f FB |
127 | |
128 | #define STAT_TC 0x10 | |
4d611c9a PB |
129 | #define STAT_PE 0x20 |
130 | #define STAT_GE 0x40 | |
c73f96fd | 131 | #define STAT_INT 0x80 |
2f275b8f | 132 | |
8dea1dd4 BS |
133 | #define BUSID_DID 0x07 |
134 | ||
2f275b8f FB |
135 | #define INTR_FC 0x08 |
136 | #define INTR_BS 0x10 | |
137 | #define INTR_DC 0x20 | |
9e61bde5 | 138 | #define INTR_RST 0x80 |
2f275b8f FB |
139 | |
140 | #define SEQ_0 0x0 | |
141 | #define SEQ_CD 0x4 | |
142 | ||
5ad6bb97 BS |
143 | #define CFG1_RESREPT 0x40 |
144 | ||
5ad6bb97 BS |
145 | #define TCHI_FAS100A 0x4 |
146 | ||
c73f96fd BS |
147 | static void esp_raise_irq(ESPState *s) |
148 | { | |
149 | if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { | |
150 | s->rregs[ESP_RSTAT] |= STAT_INT; | |
151 | qemu_irq_raise(s->irq); | |
bf4b9889 | 152 | trace_esp_raise_irq(); |
c73f96fd BS |
153 | } |
154 | } | |
155 | ||
156 | static void esp_lower_irq(ESPState *s) | |
157 | { | |
158 | if (s->rregs[ESP_RSTAT] & STAT_INT) { | |
159 | s->rregs[ESP_RSTAT] &= ~STAT_INT; | |
160 | qemu_irq_lower(s->irq); | |
bf4b9889 | 161 | trace_esp_lower_irq(); |
c73f96fd BS |
162 | } |
163 | } | |
164 | ||
73d74342 BS |
165 | static void esp_dma_enable(void *opaque, int irq, int level) |
166 | { | |
167 | DeviceState *d = opaque; | |
168 | ESPState *s = container_of(d, ESPState, busdev.qdev); | |
169 | ||
170 | if (level) { | |
171 | s->dma_enabled = 1; | |
bf4b9889 | 172 | trace_esp_dma_enable(); |
73d74342 BS |
173 | if (s->dma_cb) { |
174 | s->dma_cb(s); | |
175 | s->dma_cb = NULL; | |
176 | } | |
177 | } else { | |
bf4b9889 | 178 | trace_esp_dma_disable(); |
73d74342 BS |
179 | s->dma_enabled = 0; |
180 | } | |
181 | } | |
182 | ||
94d3f98a PB |
183 | static void esp_request_cancelled(SCSIRequest *req) |
184 | { | |
185 | ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent); | |
186 | ||
187 | if (req == s->current_req) { | |
188 | scsi_req_unref(s->current_req); | |
189 | s->current_req = NULL; | |
190 | s->current_dev = NULL; | |
191 | } | |
192 | } | |
193 | ||
22548760 | 194 | static uint32_t get_cmd(ESPState *s, uint8_t *buf) |
2f275b8f | 195 | { |
a917d384 | 196 | uint32_t dmalen; |
2f275b8f FB |
197 | int target; |
198 | ||
8dea1dd4 | 199 | target = s->wregs[ESP_WBUSID] & BUSID_DID; |
4f6200f0 | 200 | if (s->dma) { |
fc4d65da | 201 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8); |
8b17de88 | 202 | s->dma_memory_read(s->dma_opaque, buf, dmalen); |
4f6200f0 | 203 | } else { |
fc4d65da BS |
204 | dmalen = s->ti_size; |
205 | memcpy(buf, s->ti_buf, dmalen); | |
75ef8496 | 206 | buf[0] = buf[2] >> 5; |
4f6200f0 | 207 | } |
bf4b9889 | 208 | trace_esp_get_cmd(dmalen, target); |
2e5d83bb | 209 | |
2f275b8f | 210 | s->ti_size = 0; |
4f6200f0 FB |
211 | s->ti_rptr = 0; |
212 | s->ti_wptr = 0; | |
2f275b8f | 213 | |
429bef69 | 214 | if (s->current_req) { |
a917d384 | 215 | /* Started a new command before the old one finished. Cancel it. */ |
94d3f98a | 216 | scsi_req_cancel(s->current_req); |
a917d384 PB |
217 | s->async_len = 0; |
218 | } | |
219 | ||
0d3545e7 | 220 | s->current_dev = scsi_device_find(&s->bus, 0, target, 0); |
f48a7a6e | 221 | if (!s->current_dev) { |
2e5d83bb | 222 | // No such drive |
c73f96fd | 223 | s->rregs[ESP_RSTAT] = 0; |
5ad6bb97 BS |
224 | s->rregs[ESP_RINTR] = INTR_DC; |
225 | s->rregs[ESP_RSEQ] = SEQ_0; | |
c73f96fd | 226 | esp_raise_irq(s); |
f930d07e | 227 | return 0; |
2f275b8f | 228 | } |
9f149aa9 PB |
229 | return dmalen; |
230 | } | |
231 | ||
f2818f22 | 232 | static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) |
9f149aa9 PB |
233 | { |
234 | int32_t datalen; | |
235 | int lun; | |
f48a7a6e | 236 | SCSIDevice *current_lun; |
9f149aa9 | 237 | |
bf4b9889 | 238 | trace_esp_do_busid_cmd(busid); |
f2818f22 | 239 | lun = busid & 7; |
0d3545e7 | 240 | current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun); |
f48a7a6e | 241 | s->current_req = scsi_req_new(current_lun, 0, lun, buf, NULL); |
c39ce112 | 242 | datalen = scsi_req_enqueue(s->current_req); |
67e999be FB |
243 | s->ti_size = datalen; |
244 | if (datalen != 0) { | |
c73f96fd | 245 | s->rregs[ESP_RSTAT] = STAT_TC; |
a917d384 | 246 | s->dma_left = 0; |
6787f5fa | 247 | s->dma_counter = 0; |
2e5d83bb | 248 | if (datalen > 0) { |
5ad6bb97 | 249 | s->rregs[ESP_RSTAT] |= STAT_DI; |
2e5d83bb | 250 | } else { |
5ad6bb97 | 251 | s->rregs[ESP_RSTAT] |= STAT_DO; |
b9788fc4 | 252 | } |
ad3376cc | 253 | scsi_req_continue(s->current_req); |
2f275b8f | 254 | } |
5ad6bb97 BS |
255 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
256 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 257 | esp_raise_irq(s); |
2f275b8f FB |
258 | } |
259 | ||
f2818f22 AT |
260 | static void do_cmd(ESPState *s, uint8_t *buf) |
261 | { | |
262 | uint8_t busid = buf[0]; | |
263 | ||
264 | do_busid_cmd(s, &buf[1], busid); | |
265 | } | |
266 | ||
9f149aa9 PB |
267 | static void handle_satn(ESPState *s) |
268 | { | |
269 | uint8_t buf[32]; | |
270 | int len; | |
271 | ||
73d74342 BS |
272 | if (!s->dma_enabled) { |
273 | s->dma_cb = handle_satn; | |
274 | return; | |
275 | } | |
9f149aa9 PB |
276 | len = get_cmd(s, buf); |
277 | if (len) | |
278 | do_cmd(s, buf); | |
279 | } | |
280 | ||
f2818f22 AT |
281 | static void handle_s_without_atn(ESPState *s) |
282 | { | |
283 | uint8_t buf[32]; | |
284 | int len; | |
285 | ||
73d74342 BS |
286 | if (!s->dma_enabled) { |
287 | s->dma_cb = handle_s_without_atn; | |
288 | return; | |
289 | } | |
f2818f22 AT |
290 | len = get_cmd(s, buf); |
291 | if (len) { | |
292 | do_busid_cmd(s, buf, 0); | |
293 | } | |
294 | } | |
295 | ||
9f149aa9 PB |
296 | static void handle_satn_stop(ESPState *s) |
297 | { | |
73d74342 BS |
298 | if (!s->dma_enabled) { |
299 | s->dma_cb = handle_satn_stop; | |
300 | return; | |
301 | } | |
9f149aa9 PB |
302 | s->cmdlen = get_cmd(s, s->cmdbuf); |
303 | if (s->cmdlen) { | |
bf4b9889 | 304 | trace_esp_handle_satn_stop(s->cmdlen); |
9f149aa9 | 305 | s->do_cmd = 1; |
c73f96fd | 306 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
5ad6bb97 BS |
307 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
308 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 309 | esp_raise_irq(s); |
9f149aa9 PB |
310 | } |
311 | } | |
312 | ||
0fc5c15a | 313 | static void write_response(ESPState *s) |
2f275b8f | 314 | { |
bf4b9889 | 315 | trace_esp_write_response(s->status); |
3944966d | 316 | s->ti_buf[0] = s->status; |
0fc5c15a | 317 | s->ti_buf[1] = 0; |
4f6200f0 | 318 | if (s->dma) { |
8b17de88 | 319 | s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); |
c73f96fd | 320 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
5ad6bb97 BS |
321 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
322 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
4f6200f0 | 323 | } else { |
f930d07e BS |
324 | s->ti_size = 2; |
325 | s->ti_rptr = 0; | |
326 | s->ti_wptr = 0; | |
5ad6bb97 | 327 | s->rregs[ESP_RFLAGS] = 2; |
4f6200f0 | 328 | } |
c73f96fd | 329 | esp_raise_irq(s); |
2f275b8f | 330 | } |
4f6200f0 | 331 | |
a917d384 PB |
332 | static void esp_dma_done(ESPState *s) |
333 | { | |
c73f96fd | 334 | s->rregs[ESP_RSTAT] |= STAT_TC; |
5ad6bb97 BS |
335 | s->rregs[ESP_RINTR] = INTR_BS; |
336 | s->rregs[ESP_RSEQ] = 0; | |
337 | s->rregs[ESP_RFLAGS] = 0; | |
338 | s->rregs[ESP_TCLO] = 0; | |
339 | s->rregs[ESP_TCMID] = 0; | |
c73f96fd | 340 | esp_raise_irq(s); |
a917d384 PB |
341 | } |
342 | ||
4d611c9a PB |
343 | static void esp_do_dma(ESPState *s) |
344 | { | |
67e999be | 345 | uint32_t len; |
4d611c9a | 346 | int to_device; |
a917d384 | 347 | |
67e999be | 348 | to_device = (s->ti_size < 0); |
a917d384 | 349 | len = s->dma_left; |
4d611c9a | 350 | if (s->do_cmd) { |
bf4b9889 | 351 | trace_esp_do_dma(s->cmdlen, len); |
8b17de88 | 352 | s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); |
4d611c9a PB |
353 | s->ti_size = 0; |
354 | s->cmdlen = 0; | |
355 | s->do_cmd = 0; | |
356 | do_cmd(s, s->cmdbuf); | |
357 | return; | |
a917d384 PB |
358 | } |
359 | if (s->async_len == 0) { | |
360 | /* Defer until data is available. */ | |
361 | return; | |
362 | } | |
363 | if (len > s->async_len) { | |
364 | len = s->async_len; | |
365 | } | |
366 | if (to_device) { | |
8b17de88 | 367 | s->dma_memory_read(s->dma_opaque, s->async_buf, len); |
4d611c9a | 368 | } else { |
8b17de88 | 369 | s->dma_memory_write(s->dma_opaque, s->async_buf, len); |
a917d384 | 370 | } |
a917d384 PB |
371 | s->dma_left -= len; |
372 | s->async_buf += len; | |
373 | s->async_len -= len; | |
6787f5fa PB |
374 | if (to_device) |
375 | s->ti_size += len; | |
376 | else | |
377 | s->ti_size -= len; | |
a917d384 | 378 | if (s->async_len == 0) { |
ad3376cc PB |
379 | scsi_req_continue(s->current_req); |
380 | /* If there is still data to be read from the device then | |
381 | complete the DMA operation immediately. Otherwise defer | |
382 | until the scsi layer has completed. */ | |
383 | if (to_device || s->dma_left != 0 || s->ti_size == 0) { | |
384 | return; | |
4d611c9a | 385 | } |
a917d384 | 386 | } |
ad3376cc PB |
387 | |
388 | /* Partially filled a scsi buffer. Complete immediately. */ | |
389 | esp_dma_done(s); | |
4d611c9a PB |
390 | } |
391 | ||
aba1f023 | 392 | static void esp_command_complete(SCSIRequest *req, uint32_t status) |
2e5d83bb | 393 | { |
5c6c0e51 | 394 | ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent); |
2e5d83bb | 395 | |
bf4b9889 | 396 | trace_esp_command_complete(); |
c6df7102 | 397 | if (s->ti_size != 0) { |
bf4b9889 | 398 | trace_esp_command_complete_unexpected(); |
c6df7102 PB |
399 | } |
400 | s->ti_size = 0; | |
401 | s->dma_left = 0; | |
402 | s->async_len = 0; | |
aba1f023 | 403 | if (status) { |
bf4b9889 | 404 | trace_esp_command_complete_fail(); |
c6df7102 | 405 | } |
aba1f023 | 406 | s->status = status; |
c6df7102 PB |
407 | s->rregs[ESP_RSTAT] = STAT_ST; |
408 | esp_dma_done(s); | |
409 | if (s->current_req) { | |
410 | scsi_req_unref(s->current_req); | |
411 | s->current_req = NULL; | |
412 | s->current_dev = NULL; | |
413 | } | |
414 | } | |
415 | ||
aba1f023 | 416 | static void esp_transfer_data(SCSIRequest *req, uint32_t len) |
c6df7102 PB |
417 | { |
418 | ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent); | |
419 | ||
bf4b9889 | 420 | trace_esp_transfer_data(s->dma_left, s->ti_size); |
aba1f023 | 421 | s->async_len = len; |
c6df7102 PB |
422 | s->async_buf = scsi_req_get_buf(req); |
423 | if (s->dma_left) { | |
424 | esp_do_dma(s); | |
425 | } else if (s->dma_counter != 0 && s->ti_size <= 0) { | |
426 | /* If this was the last part of a DMA transfer then the | |
427 | completion interrupt is deferred to here. */ | |
a917d384 | 428 | esp_dma_done(s); |
4d611c9a | 429 | } |
2e5d83bb PB |
430 | } |
431 | ||
2f275b8f FB |
432 | static void handle_ti(ESPState *s) |
433 | { | |
4d611c9a | 434 | uint32_t dmalen, minlen; |
2f275b8f | 435 | |
5ad6bb97 | 436 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8); |
db59203d PB |
437 | if (dmalen==0) { |
438 | dmalen=0x10000; | |
439 | } | |
6787f5fa | 440 | s->dma_counter = dmalen; |
db59203d | 441 | |
9f149aa9 PB |
442 | if (s->do_cmd) |
443 | minlen = (dmalen < 32) ? dmalen : 32; | |
67e999be FB |
444 | else if (s->ti_size < 0) |
445 | minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; | |
9f149aa9 PB |
446 | else |
447 | minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; | |
bf4b9889 | 448 | trace_esp_handle_ti(minlen); |
4f6200f0 | 449 | if (s->dma) { |
4d611c9a | 450 | s->dma_left = minlen; |
5ad6bb97 | 451 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
4d611c9a | 452 | esp_do_dma(s); |
9f149aa9 | 453 | } else if (s->do_cmd) { |
bf4b9889 | 454 | trace_esp_handle_ti_cmd(s->cmdlen); |
9f149aa9 PB |
455 | s->ti_size = 0; |
456 | s->cmdlen = 0; | |
457 | s->do_cmd = 0; | |
458 | do_cmd(s, s->cmdbuf); | |
459 | return; | |
460 | } | |
2f275b8f FB |
461 | } |
462 | ||
85948643 | 463 | static void esp_hard_reset(DeviceState *d) |
6f7e9aec | 464 | { |
63235df8 | 465 | ESPState *s = container_of(d, ESPState, busdev.qdev); |
67e999be | 466 | |
5aca8c3b BS |
467 | memset(s->rregs, 0, ESP_REGS); |
468 | memset(s->wregs, 0, ESP_REGS); | |
5ad6bb97 | 469 | s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a |
4e9aec74 PB |
470 | s->ti_size = 0; |
471 | s->ti_rptr = 0; | |
472 | s->ti_wptr = 0; | |
4e9aec74 | 473 | s->dma = 0; |
9f149aa9 | 474 | s->do_cmd = 0; |
73d74342 | 475 | s->dma_cb = NULL; |
8dea1dd4 BS |
476 | |
477 | s->rregs[ESP_CFG1] = 7; | |
6f7e9aec FB |
478 | } |
479 | ||
85948643 BS |
480 | static void esp_soft_reset(DeviceState *d) |
481 | { | |
482 | ESPState *s = container_of(d, ESPState, busdev.qdev); | |
483 | ||
484 | qemu_irq_lower(s->irq); | |
485 | esp_hard_reset(d); | |
486 | } | |
487 | ||
2d069bab BS |
488 | static void parent_esp_reset(void *opaque, int irq, int level) |
489 | { | |
85948643 BS |
490 | if (level) { |
491 | esp_soft_reset(opaque); | |
492 | } | |
2d069bab BS |
493 | } |
494 | ||
73d74342 BS |
495 | static void esp_gpio_demux(void *opaque, int irq, int level) |
496 | { | |
497 | switch (irq) { | |
498 | case 0: | |
499 | parent_esp_reset(opaque, irq, level); | |
500 | break; | |
501 | case 1: | |
502 | esp_dma_enable(opaque, irq, level); | |
503 | break; | |
504 | } | |
505 | } | |
506 | ||
c227f099 | 507 | static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
6f7e9aec FB |
508 | { |
509 | ESPState *s = opaque; | |
2814df28 | 510 | uint32_t saddr, old_val; |
6f7e9aec | 511 | |
e64d7d59 | 512 | saddr = addr >> s->it_shift; |
bf4b9889 | 513 | trace_esp_mem_readb(saddr, s->rregs[saddr]); |
6f7e9aec | 514 | switch (saddr) { |
5ad6bb97 | 515 | case ESP_FIFO: |
f930d07e BS |
516 | if (s->ti_size > 0) { |
517 | s->ti_size--; | |
5ad6bb97 | 518 | if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { |
8dea1dd4 BS |
519 | /* Data out. */ |
520 | ESP_ERROR("PIO data read not implemented\n"); | |
5ad6bb97 | 521 | s->rregs[ESP_FIFO] = 0; |
2e5d83bb | 522 | } else { |
5ad6bb97 | 523 | s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; |
2e5d83bb | 524 | } |
c73f96fd | 525 | esp_raise_irq(s); |
f930d07e BS |
526 | } |
527 | if (s->ti_size == 0) { | |
4f6200f0 FB |
528 | s->ti_rptr = 0; |
529 | s->ti_wptr = 0; | |
530 | } | |
f930d07e | 531 | break; |
5ad6bb97 | 532 | case ESP_RINTR: |
2814df28 BS |
533 | /* Clear sequence step, interrupt register and all status bits |
534 | except TC */ | |
535 | old_val = s->rregs[ESP_RINTR]; | |
536 | s->rregs[ESP_RINTR] = 0; | |
537 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
538 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 539 | esp_lower_irq(s); |
2814df28 BS |
540 | |
541 | return old_val; | |
6f7e9aec | 542 | default: |
f930d07e | 543 | break; |
6f7e9aec | 544 | } |
2f275b8f | 545 | return s->rregs[saddr]; |
6f7e9aec FB |
546 | } |
547 | ||
c227f099 | 548 | static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
6f7e9aec FB |
549 | { |
550 | ESPState *s = opaque; | |
551 | uint32_t saddr; | |
552 | ||
e64d7d59 | 553 | saddr = addr >> s->it_shift; |
bf4b9889 | 554 | trace_esp_mem_writeb(saddr, s->wregs[saddr], val); |
6f7e9aec | 555 | switch (saddr) { |
5ad6bb97 BS |
556 | case ESP_TCLO: |
557 | case ESP_TCMID: | |
558 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
4f6200f0 | 559 | break; |
5ad6bb97 | 560 | case ESP_FIFO: |
9f149aa9 PB |
561 | if (s->do_cmd) { |
562 | s->cmdbuf[s->cmdlen++] = val & 0xff; | |
8dea1dd4 BS |
563 | } else if (s->ti_size == TI_BUFSZ - 1) { |
564 | ESP_ERROR("fifo overrun\n"); | |
2e5d83bb PB |
565 | } else { |
566 | s->ti_size++; | |
567 | s->ti_buf[s->ti_wptr++] = val & 0xff; | |
568 | } | |
f930d07e | 569 | break; |
5ad6bb97 | 570 | case ESP_CMD: |
4f6200f0 | 571 | s->rregs[saddr] = val; |
5ad6bb97 | 572 | if (val & CMD_DMA) { |
f930d07e | 573 | s->dma = 1; |
6787f5fa | 574 | /* Reload DMA counter. */ |
5ad6bb97 BS |
575 | s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; |
576 | s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; | |
f930d07e BS |
577 | } else { |
578 | s->dma = 0; | |
579 | } | |
5ad6bb97 BS |
580 | switch(val & CMD_CMD) { |
581 | case CMD_NOP: | |
bf4b9889 | 582 | trace_esp_mem_writeb_cmd_nop(val); |
f930d07e | 583 | break; |
5ad6bb97 | 584 | case CMD_FLUSH: |
bf4b9889 | 585 | trace_esp_mem_writeb_cmd_flush(val); |
9e61bde5 | 586 | //s->ti_size = 0; |
5ad6bb97 BS |
587 | s->rregs[ESP_RINTR] = INTR_FC; |
588 | s->rregs[ESP_RSEQ] = 0; | |
a214c598 | 589 | s->rregs[ESP_RFLAGS] = 0; |
f930d07e | 590 | break; |
5ad6bb97 | 591 | case CMD_RESET: |
bf4b9889 | 592 | trace_esp_mem_writeb_cmd_reset(val); |
85948643 | 593 | esp_soft_reset(&s->busdev.qdev); |
f930d07e | 594 | break; |
5ad6bb97 | 595 | case CMD_BUSRESET: |
bf4b9889 | 596 | trace_esp_mem_writeb_cmd_bus_reset(val); |
5ad6bb97 BS |
597 | s->rregs[ESP_RINTR] = INTR_RST; |
598 | if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { | |
c73f96fd | 599 | esp_raise_irq(s); |
9e61bde5 | 600 | } |
f930d07e | 601 | break; |
5ad6bb97 | 602 | case CMD_TI: |
f930d07e BS |
603 | handle_ti(s); |
604 | break; | |
5ad6bb97 | 605 | case CMD_ICCS: |
bf4b9889 | 606 | trace_esp_mem_writeb_cmd_iccs(val); |
f930d07e | 607 | write_response(s); |
4bf5801d BS |
608 | s->rregs[ESP_RINTR] = INTR_FC; |
609 | s->rregs[ESP_RSTAT] |= STAT_MI; | |
f930d07e | 610 | break; |
5ad6bb97 | 611 | case CMD_MSGACC: |
bf4b9889 | 612 | trace_esp_mem_writeb_cmd_msgacc(val); |
5ad6bb97 BS |
613 | s->rregs[ESP_RINTR] = INTR_DC; |
614 | s->rregs[ESP_RSEQ] = 0; | |
4e2a68c1 AT |
615 | s->rregs[ESP_RFLAGS] = 0; |
616 | esp_raise_irq(s); | |
f930d07e | 617 | break; |
0fd0eb21 | 618 | case CMD_PAD: |
bf4b9889 | 619 | trace_esp_mem_writeb_cmd_pad(val); |
0fd0eb21 BS |
620 | s->rregs[ESP_RSTAT] = STAT_TC; |
621 | s->rregs[ESP_RINTR] = INTR_FC; | |
622 | s->rregs[ESP_RSEQ] = 0; | |
623 | break; | |
5ad6bb97 | 624 | case CMD_SATN: |
bf4b9889 | 625 | trace_esp_mem_writeb_cmd_satn(val); |
f930d07e | 626 | break; |
5e1e0a3b | 627 | case CMD_SEL: |
bf4b9889 | 628 | trace_esp_mem_writeb_cmd_sel(val); |
f2818f22 | 629 | handle_s_without_atn(s); |
5e1e0a3b | 630 | break; |
5ad6bb97 | 631 | case CMD_SELATN: |
bf4b9889 | 632 | trace_esp_mem_writeb_cmd_selatn(val); |
f930d07e BS |
633 | handle_satn(s); |
634 | break; | |
5ad6bb97 | 635 | case CMD_SELATNS: |
bf4b9889 | 636 | trace_esp_mem_writeb_cmd_selatns(val); |
f930d07e BS |
637 | handle_satn_stop(s); |
638 | break; | |
5ad6bb97 | 639 | case CMD_ENSEL: |
bf4b9889 | 640 | trace_esp_mem_writeb_cmd_ensel(val); |
e3926838 | 641 | s->rregs[ESP_RINTR] = 0; |
74ec6048 | 642 | break; |
f930d07e | 643 | default: |
8dea1dd4 | 644 | ESP_ERROR("Unhandled ESP command (%2.2x)\n", val); |
f930d07e BS |
645 | break; |
646 | } | |
647 | break; | |
5ad6bb97 | 648 | case ESP_WBUSID ... ESP_WSYNO: |
f930d07e | 649 | break; |
5ad6bb97 | 650 | case ESP_CFG1: |
4f6200f0 FB |
651 | s->rregs[saddr] = val; |
652 | break; | |
5ad6bb97 | 653 | case ESP_WCCF ... ESP_WTEST: |
4f6200f0 | 654 | break; |
b44c08fa | 655 | case ESP_CFG2 ... ESP_RES4: |
4f6200f0 FB |
656 | s->rregs[saddr] = val; |
657 | break; | |
6f7e9aec | 658 | default: |
8dea1dd4 BS |
659 | ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr); |
660 | return; | |
6f7e9aec | 661 | } |
2f275b8f | 662 | s->wregs[saddr] = val; |
6f7e9aec FB |
663 | } |
664 | ||
d60efc6b | 665 | static CPUReadMemoryFunc * const esp_mem_read[3] = { |
6f7e9aec | 666 | esp_mem_readb, |
7c560456 BS |
667 | NULL, |
668 | NULL, | |
6f7e9aec FB |
669 | }; |
670 | ||
d60efc6b | 671 | static CPUWriteMemoryFunc * const esp_mem_write[3] = { |
6f7e9aec | 672 | esp_mem_writeb, |
7c560456 | 673 | NULL, |
daa41b00 | 674 | esp_mem_writeb, |
6f7e9aec FB |
675 | }; |
676 | ||
cc9952f3 BS |
677 | static const VMStateDescription vmstate_esp = { |
678 | .name ="esp", | |
679 | .version_id = 3, | |
680 | .minimum_version_id = 3, | |
681 | .minimum_version_id_old = 3, | |
682 | .fields = (VMStateField []) { | |
683 | VMSTATE_BUFFER(rregs, ESPState), | |
684 | VMSTATE_BUFFER(wregs, ESPState), | |
685 | VMSTATE_INT32(ti_size, ESPState), | |
686 | VMSTATE_UINT32(ti_rptr, ESPState), | |
687 | VMSTATE_UINT32(ti_wptr, ESPState), | |
688 | VMSTATE_BUFFER(ti_buf, ESPState), | |
3944966d | 689 | VMSTATE_UINT32(status, ESPState), |
cc9952f3 BS |
690 | VMSTATE_UINT32(dma, ESPState), |
691 | VMSTATE_BUFFER(cmdbuf, ESPState), | |
692 | VMSTATE_UINT32(cmdlen, ESPState), | |
693 | VMSTATE_UINT32(do_cmd, ESPState), | |
694 | VMSTATE_UINT32(dma_left, ESPState), | |
695 | VMSTATE_END_OF_LIST() | |
696 | } | |
697 | }; | |
6f7e9aec | 698 | |
c227f099 | 699 | void esp_init(target_phys_addr_t espaddr, int it_shift, |
ff9868ec BS |
700 | ESPDMAMemoryReadWriteFunc dma_memory_read, |
701 | ESPDMAMemoryReadWriteFunc dma_memory_write, | |
73d74342 BS |
702 | void *dma_opaque, qemu_irq irq, qemu_irq *reset, |
703 | qemu_irq *dma_enable) | |
6f7e9aec | 704 | { |
cfb9de9c PB |
705 | DeviceState *dev; |
706 | SysBusDevice *s; | |
ee6847d1 | 707 | ESPState *esp; |
cfb9de9c PB |
708 | |
709 | dev = qdev_create(NULL, "esp"); | |
ee6847d1 GH |
710 | esp = DO_UPCAST(ESPState, busdev.qdev, dev); |
711 | esp->dma_memory_read = dma_memory_read; | |
712 | esp->dma_memory_write = dma_memory_write; | |
713 | esp->dma_opaque = dma_opaque; | |
714 | esp->it_shift = it_shift; | |
73d74342 BS |
715 | /* XXX for now until rc4030 has been changed to use DMA enable signal */ |
716 | esp->dma_enabled = 1; | |
e23a1b33 | 717 | qdev_init_nofail(dev); |
cfb9de9c PB |
718 | s = sysbus_from_qdev(dev); |
719 | sysbus_connect_irq(s, 0, irq); | |
720 | sysbus_mmio_map(s, 0, espaddr); | |
74ff8d90 | 721 | *reset = qdev_get_gpio_in(dev, 0); |
73d74342 | 722 | *dma_enable = qdev_get_gpio_in(dev, 1); |
cfb9de9c | 723 | } |
6f7e9aec | 724 | |
afd4030c PB |
725 | static const struct SCSIBusInfo esp_scsi_info = { |
726 | .tcq = false, | |
7e0380b9 PB |
727 | .max_target = ESP_MAX_DEVS, |
728 | .max_lun = 7, | |
afd4030c | 729 | |
c6df7102 | 730 | .transfer_data = esp_transfer_data, |
94d3f98a PB |
731 | .complete = esp_command_complete, |
732 | .cancel = esp_request_cancelled | |
cfdc1bb0 PB |
733 | }; |
734 | ||
81a322d4 | 735 | static int esp_init1(SysBusDevice *dev) |
cfb9de9c PB |
736 | { |
737 | ESPState *s = FROM_SYSBUS(ESPState, dev); | |
738 | int esp_io_memory; | |
6f7e9aec | 739 | |
cfb9de9c | 740 | sysbus_init_irq(dev, &s->irq); |
cfb9de9c | 741 | assert(s->it_shift != -1); |
6f7e9aec | 742 | |
2507c12a AG |
743 | esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s, |
744 | DEVICE_NATIVE_ENDIAN); | |
cfb9de9c | 745 | sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory); |
6f7e9aec | 746 | |
73d74342 | 747 | qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2); |
2d069bab | 748 | |
afd4030c | 749 | scsi_bus_new(&s->bus, &dev->qdev, &esp_scsi_info); |
fa66b909 | 750 | return scsi_bus_legacy_handle_cmdline(&s->bus); |
67e999be | 751 | } |
cfb9de9c | 752 | |
63235df8 BS |
753 | static SysBusDeviceInfo esp_info = { |
754 | .init = esp_init1, | |
755 | .qdev.name = "esp", | |
756 | .qdev.size = sizeof(ESPState), | |
757 | .qdev.vmsd = &vmstate_esp, | |
85948643 | 758 | .qdev.reset = esp_hard_reset, |
63235df8 BS |
759 | .qdev.props = (Property[]) { |
760 | {.name = NULL} | |
761 | } | |
762 | }; | |
763 | ||
cfb9de9c PB |
764 | static void esp_register_devices(void) |
765 | { | |
63235df8 | 766 | sysbus_register_withprop(&esp_info); |
cfb9de9c PB |
767 | } |
768 | ||
769 | device_init(esp_register_devices) |