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Commit | Line | Data |
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16b29ae1 AL |
1 | /* |
2 | * High Precisition Event Timer emulation | |
3 | * | |
4 | * Copyright (c) 2007 Alexander Graf | |
5 | * Copyright (c) 2008 IBM Corporation | |
6 | * | |
7 | * Authors: Beth Kon <bkon@us.ibm.com> | |
8 | * | |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 20 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
16b29ae1 AL |
21 | * |
22 | * ***************************************************************** | |
23 | * | |
24 | * This driver attempts to emulate an HPET device in software. | |
25 | */ | |
26 | ||
27 | #include "hw.h" | |
bf4f74c0 | 28 | #include "pc.h" |
16b29ae1 AL |
29 | #include "console.h" |
30 | #include "qemu-timer.h" | |
31 | #include "hpet_emul.h" | |
822557eb | 32 | #include "sysbus.h" |
7d932dfd | 33 | #include "mc146818rtc.h" |
16b29ae1 | 34 | |
16b29ae1 AL |
35 | //#define HPET_DEBUG |
36 | #ifdef HPET_DEBUG | |
d0f2c4c6 | 37 | #define DPRINTF printf |
16b29ae1 | 38 | #else |
d0f2c4c6 | 39 | #define DPRINTF(...) |
16b29ae1 AL |
40 | #endif |
41 | ||
8caa0065 JK |
42 | #define HPET_MSI_SUPPORT 0 |
43 | ||
27bb0b2d JK |
44 | struct HPETState; |
45 | typedef struct HPETTimer { /* timers */ | |
46 | uint8_t tn; /*timer number*/ | |
47 | QEMUTimer *qemu_timer; | |
48 | struct HPETState *state; | |
49 | /* Memory-mapped, software visible timer registers */ | |
50 | uint64_t config; /* configuration/cap */ | |
51 | uint64_t cmp; /* comparator */ | |
8caa0065 | 52 | uint64_t fsb; /* FSB route */ |
27bb0b2d JK |
53 | /* Hidden register state */ |
54 | uint64_t period; /* Last value written to comparator */ | |
55 | uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit | |
56 | * mode. Next pop will be actual timer expiration. | |
57 | */ | |
58 | } HPETTimer; | |
59 | ||
60 | typedef struct HPETState { | |
822557eb | 61 | SysBusDevice busdev; |
e977aa37 | 62 | MemoryRegion iomem; |
27bb0b2d | 63 | uint64_t hpet_offset; |
822557eb | 64 | qemu_irq irqs[HPET_NUM_IRQ_ROUTES]; |
8caa0065 | 65 | uint32_t flags; |
7d932dfd | 66 | uint8_t rtc_irq_level; |
be4b44c5 JK |
67 | uint8_t num_timers; |
68 | HPETTimer timer[HPET_MAX_TIMERS]; | |
27bb0b2d JK |
69 | |
70 | /* Memory-mapped, software visible registers */ | |
71 | uint64_t capability; /* capabilities */ | |
72 | uint64_t config; /* configuration */ | |
73 | uint64_t isr; /* interrupt status reg */ | |
74 | uint64_t hpet_counter; /* main counter */ | |
40ac17cd | 75 | uint8_t hpet_id; /* instance id */ |
27bb0b2d JK |
76 | } HPETState; |
77 | ||
7d932dfd | 78 | static uint32_t hpet_in_legacy_mode(HPETState *s) |
16b29ae1 | 79 | { |
7d932dfd | 80 | return s->config & HPET_CFG_LEGACY; |
16b29ae1 AL |
81 | } |
82 | ||
c50c2d68 | 83 | static uint32_t timer_int_route(struct HPETTimer *timer) |
16b29ae1 | 84 | { |
27bb0b2d | 85 | return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT; |
16b29ae1 AL |
86 | } |
87 | ||
8caa0065 JK |
88 | static uint32_t timer_fsb_route(HPETTimer *t) |
89 | { | |
90 | return t->config & HPET_TN_FSB_ENABLE; | |
91 | } | |
92 | ||
b7eaa6c7 | 93 | static uint32_t hpet_enabled(HPETState *s) |
16b29ae1 | 94 | { |
b7eaa6c7 | 95 | return s->config & HPET_CFG_ENABLE; |
16b29ae1 AL |
96 | } |
97 | ||
98 | static uint32_t timer_is_periodic(HPETTimer *t) | |
99 | { | |
100 | return t->config & HPET_TN_PERIODIC; | |
101 | } | |
102 | ||
103 | static uint32_t timer_enabled(HPETTimer *t) | |
104 | { | |
105 | return t->config & HPET_TN_ENABLE; | |
106 | } | |
107 | ||
108 | static uint32_t hpet_time_after(uint64_t a, uint64_t b) | |
109 | { | |
110 | return ((int32_t)(b) - (int32_t)(a) < 0); | |
111 | } | |
112 | ||
113 | static uint32_t hpet_time_after64(uint64_t a, uint64_t b) | |
114 | { | |
115 | return ((int64_t)(b) - (int64_t)(a) < 0); | |
116 | } | |
117 | ||
c50c2d68 | 118 | static uint64_t ticks_to_ns(uint64_t value) |
16b29ae1 AL |
119 | { |
120 | return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS)); | |
121 | } | |
122 | ||
c50c2d68 | 123 | static uint64_t ns_to_ticks(uint64_t value) |
16b29ae1 AL |
124 | { |
125 | return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD)); | |
126 | } | |
127 | ||
128 | static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask) | |
129 | { | |
130 | new &= mask; | |
131 | new |= old & ~mask; | |
132 | return new; | |
133 | } | |
134 | ||
135 | static int activating_bit(uint64_t old, uint64_t new, uint64_t mask) | |
136 | { | |
c50c2d68 | 137 | return (!(old & mask) && (new & mask)); |
16b29ae1 AL |
138 | } |
139 | ||
140 | static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask) | |
141 | { | |
c50c2d68 | 142 | return ((old & mask) && !(new & mask)); |
16b29ae1 AL |
143 | } |
144 | ||
b7eaa6c7 | 145 | static uint64_t hpet_get_ticks(HPETState *s) |
16b29ae1 | 146 | { |
74475455 | 147 | return ns_to_ticks(qemu_get_clock_ns(vm_clock) + s->hpet_offset); |
16b29ae1 AL |
148 | } |
149 | ||
c50c2d68 AJ |
150 | /* |
151 | * calculate diff between comparator value and current ticks | |
16b29ae1 AL |
152 | */ |
153 | static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current) | |
154 | { | |
c50c2d68 | 155 | |
16b29ae1 AL |
156 | if (t->config & HPET_TN_32BIT) { |
157 | uint32_t diff, cmp; | |
27bb0b2d | 158 | |
16b29ae1 AL |
159 | cmp = (uint32_t)t->cmp; |
160 | diff = cmp - (uint32_t)current; | |
4f61927a | 161 | diff = (int32_t)diff > 0 ? diff : (uint32_t)1; |
16b29ae1 AL |
162 | return (uint64_t)diff; |
163 | } else { | |
164 | uint64_t diff, cmp; | |
27bb0b2d | 165 | |
16b29ae1 AL |
166 | cmp = t->cmp; |
167 | diff = cmp - current; | |
4f61927a | 168 | diff = (int64_t)diff > 0 ? diff : (uint64_t)1; |
16b29ae1 AL |
169 | return diff; |
170 | } | |
171 | } | |
172 | ||
22a9fe38 | 173 | static void update_irq(struct HPETTimer *timer, int set) |
16b29ae1 | 174 | { |
22a9fe38 JK |
175 | uint64_t mask; |
176 | HPETState *s; | |
16b29ae1 AL |
177 | int route; |
178 | ||
7d932dfd | 179 | if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) { |
16b29ae1 AL |
180 | /* if LegacyReplacementRoute bit is set, HPET specification requires |
181 | * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC, | |
c50c2d68 | 182 | * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC. |
16b29ae1 | 183 | */ |
7d932dfd | 184 | route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ; |
16b29ae1 | 185 | } else { |
27bb0b2d | 186 | route = timer_int_route(timer); |
16b29ae1 | 187 | } |
22a9fe38 JK |
188 | s = timer->state; |
189 | mask = 1 << timer->tn; | |
190 | if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) { | |
191 | s->isr &= ~mask; | |
8caa0065 JK |
192 | if (!timer_fsb_route(timer)) { |
193 | qemu_irq_lower(s->irqs[route]); | |
194 | } | |
195 | } else if (timer_fsb_route(timer)) { | |
8517263f | 196 | stl_le_phys(timer->fsb >> 32, timer->fsb & 0xffffffff); |
22a9fe38 JK |
197 | } else if (timer->config & HPET_TN_TYPE_LEVEL) { |
198 | s->isr |= mask; | |
199 | qemu_irq_raise(s->irqs[route]); | |
200 | } else { | |
201 | s->isr &= ~mask; | |
202 | qemu_irq_pulse(s->irqs[route]); | |
16b29ae1 AL |
203 | } |
204 | } | |
205 | ||
d4bfa4d7 | 206 | static void hpet_pre_save(void *opaque) |
16b29ae1 | 207 | { |
d4bfa4d7 | 208 | HPETState *s = opaque; |
27bb0b2d | 209 | |
16b29ae1 | 210 | /* save current counter value */ |
b7eaa6c7 | 211 | s->hpet_counter = hpet_get_ticks(s); |
16b29ae1 AL |
212 | } |
213 | ||
be4b44c5 JK |
214 | static int hpet_pre_load(void *opaque) |
215 | { | |
216 | HPETState *s = opaque; | |
217 | ||
218 | /* version 1 only supports 3, later versions will load the actual value */ | |
219 | s->num_timers = HPET_MIN_TIMERS; | |
220 | return 0; | |
221 | } | |
222 | ||
e59fb374 | 223 | static int hpet_post_load(void *opaque, int version_id) |
16b29ae1 AL |
224 | { |
225 | HPETState *s = opaque; | |
c50c2d68 | 226 | |
16b29ae1 | 227 | /* Recalculate the offset between the main counter and guest time */ |
74475455 | 228 | s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock); |
be4b44c5 JK |
229 | |
230 | /* Push number of timers into capability returned via HPET_ID */ | |
231 | s->capability &= ~HPET_ID_NUM_TIM_MASK; | |
232 | s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT; | |
40ac17cd | 233 | hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability; |
8caa0065 JK |
234 | |
235 | /* Derive HPET_MSI_SUPPORT from the capability of the first timer. */ | |
236 | s->flags &= ~(1 << HPET_MSI_SUPPORT); | |
237 | if (s->timer[0].config & HPET_TN_FSB_CAP) { | |
238 | s->flags |= 1 << HPET_MSI_SUPPORT; | |
239 | } | |
16b29ae1 AL |
240 | return 0; |
241 | } | |
242 | ||
5904ae4e JK |
243 | static bool hpet_rtc_irq_level_needed(void *opaque) |
244 | { | |
245 | HPETState *s = opaque; | |
246 | ||
247 | return s->rtc_irq_level != 0; | |
248 | } | |
249 | ||
250 | static const VMStateDescription vmstate_hpet_rtc_irq_level = { | |
251 | .name = "hpet/rtc_irq_level", | |
252 | .version_id = 1, | |
253 | .minimum_version_id = 1, | |
254 | .minimum_version_id_old = 1, | |
255 | .fields = (VMStateField[]) { | |
256 | VMSTATE_UINT8(rtc_irq_level, HPETState), | |
257 | VMSTATE_END_OF_LIST() | |
258 | } | |
259 | }; | |
260 | ||
e6cb4d45 JQ |
261 | static const VMStateDescription vmstate_hpet_timer = { |
262 | .name = "hpet_timer", | |
263 | .version_id = 1, | |
264 | .minimum_version_id = 1, | |
265 | .minimum_version_id_old = 1, | |
266 | .fields = (VMStateField []) { | |
267 | VMSTATE_UINT8(tn, HPETTimer), | |
268 | VMSTATE_UINT64(config, HPETTimer), | |
269 | VMSTATE_UINT64(cmp, HPETTimer), | |
270 | VMSTATE_UINT64(fsb, HPETTimer), | |
271 | VMSTATE_UINT64(period, HPETTimer), | |
272 | VMSTATE_UINT8(wrap_flag, HPETTimer), | |
273 | VMSTATE_TIMER(qemu_timer, HPETTimer), | |
274 | VMSTATE_END_OF_LIST() | |
275 | } | |
276 | }; | |
277 | ||
278 | static const VMStateDescription vmstate_hpet = { | |
279 | .name = "hpet", | |
be4b44c5 | 280 | .version_id = 2, |
e6cb4d45 JQ |
281 | .minimum_version_id = 1, |
282 | .minimum_version_id_old = 1, | |
283 | .pre_save = hpet_pre_save, | |
be4b44c5 | 284 | .pre_load = hpet_pre_load, |
e6cb4d45 JQ |
285 | .post_load = hpet_post_load, |
286 | .fields = (VMStateField []) { | |
287 | VMSTATE_UINT64(config, HPETState), | |
288 | VMSTATE_UINT64(isr, HPETState), | |
289 | VMSTATE_UINT64(hpet_counter, HPETState), | |
be4b44c5 JK |
290 | VMSTATE_UINT8_V(num_timers, HPETState, 2), |
291 | VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0, | |
292 | vmstate_hpet_timer, HPETTimer), | |
e6cb4d45 | 293 | VMSTATE_END_OF_LIST() |
5904ae4e JK |
294 | }, |
295 | .subsections = (VMStateSubsection[]) { | |
296 | { | |
297 | .vmsd = &vmstate_hpet_rtc_irq_level, | |
298 | .needed = hpet_rtc_irq_level_needed, | |
299 | }, { | |
300 | /* empty */ | |
301 | } | |
e6cb4d45 JQ |
302 | } |
303 | }; | |
304 | ||
c50c2d68 | 305 | /* |
16b29ae1 AL |
306 | * timer expiration callback |
307 | */ | |
308 | static void hpet_timer(void *opaque) | |
309 | { | |
27bb0b2d | 310 | HPETTimer *t = opaque; |
16b29ae1 AL |
311 | uint64_t diff; |
312 | ||
313 | uint64_t period = t->period; | |
b7eaa6c7 | 314 | uint64_t cur_tick = hpet_get_ticks(t->state); |
16b29ae1 AL |
315 | |
316 | if (timer_is_periodic(t) && period != 0) { | |
317 | if (t->config & HPET_TN_32BIT) { | |
27bb0b2d | 318 | while (hpet_time_after(cur_tick, t->cmp)) { |
16b29ae1 | 319 | t->cmp = (uint32_t)(t->cmp + t->period); |
27bb0b2d JK |
320 | } |
321 | } else { | |
322 | while (hpet_time_after64(cur_tick, t->cmp)) { | |
16b29ae1 | 323 | t->cmp += period; |
27bb0b2d JK |
324 | } |
325 | } | |
16b29ae1 | 326 | diff = hpet_calculate_diff(t, cur_tick); |
27bb0b2d | 327 | qemu_mod_timer(t->qemu_timer, |
74475455 | 328 | qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff)); |
16b29ae1 AL |
329 | } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { |
330 | if (t->wrap_flag) { | |
331 | diff = hpet_calculate_diff(t, cur_tick); | |
74475455 | 332 | qemu_mod_timer(t->qemu_timer, qemu_get_clock_ns(vm_clock) + |
27bb0b2d | 333 | (int64_t)ticks_to_ns(diff)); |
16b29ae1 AL |
334 | t->wrap_flag = 0; |
335 | } | |
336 | } | |
22a9fe38 | 337 | update_irq(t, 1); |
16b29ae1 AL |
338 | } |
339 | ||
340 | static void hpet_set_timer(HPETTimer *t) | |
341 | { | |
342 | uint64_t diff; | |
343 | uint32_t wrap_diff; /* how many ticks until we wrap? */ | |
b7eaa6c7 | 344 | uint64_t cur_tick = hpet_get_ticks(t->state); |
c50c2d68 | 345 | |
16b29ae1 AL |
346 | /* whenever new timer is being set up, make sure wrap_flag is 0 */ |
347 | t->wrap_flag = 0; | |
348 | diff = hpet_calculate_diff(t, cur_tick); | |
349 | ||
c50c2d68 | 350 | /* hpet spec says in one-shot 32-bit mode, generate an interrupt when |
16b29ae1 | 351 | * counter wraps in addition to an interrupt with comparator match. |
c50c2d68 | 352 | */ |
16b29ae1 AL |
353 | if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { |
354 | wrap_diff = 0xffffffff - (uint32_t)cur_tick; | |
355 | if (wrap_diff < (uint32_t)diff) { | |
356 | diff = wrap_diff; | |
c50c2d68 | 357 | t->wrap_flag = 1; |
16b29ae1 AL |
358 | } |
359 | } | |
27bb0b2d | 360 | qemu_mod_timer(t->qemu_timer, |
74475455 | 361 | qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff)); |
16b29ae1 AL |
362 | } |
363 | ||
364 | static void hpet_del_timer(HPETTimer *t) | |
365 | { | |
366 | qemu_del_timer(t->qemu_timer); | |
22a9fe38 | 367 | update_irq(t, 0); |
16b29ae1 AL |
368 | } |
369 | ||
370 | #ifdef HPET_DEBUG | |
c227f099 | 371 | static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr) |
16b29ae1 AL |
372 | { |
373 | printf("qemu: hpet_read b at %" PRIx64 "\n", addr); | |
374 | return 0; | |
375 | } | |
376 | ||
c227f099 | 377 | static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr) |
16b29ae1 AL |
378 | { |
379 | printf("qemu: hpet_read w at %" PRIx64 "\n", addr); | |
380 | return 0; | |
381 | } | |
382 | #endif | |
383 | ||
e977aa37 AK |
384 | static uint64_t hpet_ram_read(void *opaque, target_phys_addr_t addr, |
385 | unsigned size) | |
16b29ae1 | 386 | { |
27bb0b2d | 387 | HPETState *s = opaque; |
16b29ae1 AL |
388 | uint64_t cur_tick, index; |
389 | ||
d0f2c4c6 | 390 | DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr); |
16b29ae1 AL |
391 | index = addr; |
392 | /*address range of all TN regs*/ | |
393 | if (index >= 0x100 && index <= 0x3ff) { | |
394 | uint8_t timer_id = (addr - 0x100) / 0x20; | |
27bb0b2d JK |
395 | HPETTimer *timer = &s->timer[timer_id]; |
396 | ||
be4b44c5 | 397 | if (timer_id > s->num_timers) { |
6982d664 | 398 | DPRINTF("qemu: timer id out of range\n"); |
16b29ae1 AL |
399 | return 0; |
400 | } | |
16b29ae1 AL |
401 | |
402 | switch ((addr - 0x100) % 0x20) { | |
27bb0b2d JK |
403 | case HPET_TN_CFG: |
404 | return timer->config; | |
405 | case HPET_TN_CFG + 4: // Interrupt capabilities | |
406 | return timer->config >> 32; | |
407 | case HPET_TN_CMP: // comparator register | |
408 | return timer->cmp; | |
409 | case HPET_TN_CMP + 4: | |
410 | return timer->cmp >> 32; | |
411 | case HPET_TN_ROUTE: | |
8caa0065 JK |
412 | return timer->fsb; |
413 | case HPET_TN_ROUTE + 4: | |
27bb0b2d JK |
414 | return timer->fsb >> 32; |
415 | default: | |
416 | DPRINTF("qemu: invalid hpet_ram_readl\n"); | |
417 | break; | |
16b29ae1 AL |
418 | } |
419 | } else { | |
420 | switch (index) { | |
27bb0b2d JK |
421 | case HPET_ID: |
422 | return s->capability; | |
423 | case HPET_PERIOD: | |
424 | return s->capability >> 32; | |
425 | case HPET_CFG: | |
426 | return s->config; | |
427 | case HPET_CFG + 4: | |
b2bedb21 | 428 | DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n"); |
27bb0b2d JK |
429 | return 0; |
430 | case HPET_COUNTER: | |
b7eaa6c7 JK |
431 | if (hpet_enabled(s)) { |
432 | cur_tick = hpet_get_ticks(s); | |
27bb0b2d JK |
433 | } else { |
434 | cur_tick = s->hpet_counter; | |
435 | } | |
436 | DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick); | |
437 | return cur_tick; | |
438 | case HPET_COUNTER + 4: | |
b7eaa6c7 JK |
439 | if (hpet_enabled(s)) { |
440 | cur_tick = hpet_get_ticks(s); | |
27bb0b2d JK |
441 | } else { |
442 | cur_tick = s->hpet_counter; | |
443 | } | |
444 | DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick); | |
445 | return cur_tick >> 32; | |
446 | case HPET_STATUS: | |
447 | return s->isr; | |
448 | default: | |
449 | DPRINTF("qemu: invalid hpet_ram_readl\n"); | |
450 | break; | |
16b29ae1 AL |
451 | } |
452 | } | |
453 | return 0; | |
454 | } | |
455 | ||
e977aa37 AK |
456 | static void hpet_ram_write(void *opaque, target_phys_addr_t addr, |
457 | uint64_t value, unsigned size) | |
16b29ae1 AL |
458 | { |
459 | int i; | |
27bb0b2d | 460 | HPETState *s = opaque; |
ce536cfd | 461 | uint64_t old_val, new_val, val, index; |
16b29ae1 | 462 | |
d0f2c4c6 | 463 | DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value); |
16b29ae1 | 464 | index = addr; |
e977aa37 | 465 | old_val = hpet_ram_read(opaque, addr, 4); |
16b29ae1 AL |
466 | new_val = value; |
467 | ||
468 | /*address range of all TN regs*/ | |
469 | if (index >= 0x100 && index <= 0x3ff) { | |
470 | uint8_t timer_id = (addr - 0x100) / 0x20; | |
16b29ae1 | 471 | HPETTimer *timer = &s->timer[timer_id]; |
c50c2d68 | 472 | |
b2bedb21 | 473 | DPRINTF("qemu: hpet_ram_writel timer_id = %#x\n", timer_id); |
be4b44c5 | 474 | if (timer_id > s->num_timers) { |
6982d664 JK |
475 | DPRINTF("qemu: timer id out of range\n"); |
476 | return; | |
477 | } | |
16b29ae1 | 478 | switch ((addr - 0x100) % 0x20) { |
27bb0b2d JK |
479 | case HPET_TN_CFG: |
480 | DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n"); | |
8caa0065 JK |
481 | if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) { |
482 | update_irq(timer, 0); | |
483 | } | |
27bb0b2d JK |
484 | val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); |
485 | timer->config = (timer->config & 0xffffffff00000000ULL) | val; | |
486 | if (new_val & HPET_TN_32BIT) { | |
487 | timer->cmp = (uint32_t)timer->cmp; | |
488 | timer->period = (uint32_t)timer->period; | |
489 | } | |
9cec89e8 JK |
490 | if (activating_bit(old_val, new_val, HPET_TN_ENABLE)) { |
491 | hpet_set_timer(timer); | |
492 | } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) { | |
493 | hpet_del_timer(timer); | |
494 | } | |
27bb0b2d JK |
495 | break; |
496 | case HPET_TN_CFG + 4: // Interrupt capabilities | |
497 | DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n"); | |
498 | break; | |
499 | case HPET_TN_CMP: // comparator register | |
b2bedb21 | 500 | DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n"); |
27bb0b2d JK |
501 | if (timer->config & HPET_TN_32BIT) { |
502 | new_val = (uint32_t)new_val; | |
503 | } | |
504 | if (!timer_is_periodic(timer) | |
505 | || (timer->config & HPET_TN_SETVAL)) { | |
506 | timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val; | |
507 | } | |
508 | if (timer_is_periodic(timer)) { | |
509 | /* | |
510 | * FIXME: Clamp period to reasonable min value? | |
511 | * Clamp period to reasonable max value | |
512 | */ | |
513 | new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; | |
514 | timer->period = | |
515 | (timer->period & 0xffffffff00000000ULL) | new_val; | |
516 | } | |
517 | timer->config &= ~HPET_TN_SETVAL; | |
b7eaa6c7 | 518 | if (hpet_enabled(s)) { |
27bb0b2d JK |
519 | hpet_set_timer(timer); |
520 | } | |
521 | break; | |
522 | case HPET_TN_CMP + 4: // comparator register high order | |
523 | DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n"); | |
524 | if (!timer_is_periodic(timer) | |
525 | || (timer->config & HPET_TN_SETVAL)) { | |
526 | timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32; | |
527 | } else { | |
528 | /* | |
529 | * FIXME: Clamp period to reasonable min value? | |
530 | * Clamp period to reasonable max value | |
531 | */ | |
532 | new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; | |
533 | timer->period = | |
534 | (timer->period & 0xffffffffULL) | new_val << 32; | |
16b29ae1 AL |
535 | } |
536 | timer->config &= ~HPET_TN_SETVAL; | |
b7eaa6c7 | 537 | if (hpet_enabled(s)) { |
16b29ae1 | 538 | hpet_set_timer(timer); |
16b29ae1 | 539 | } |
16b29ae1 | 540 | break; |
8caa0065 JK |
541 | case HPET_TN_ROUTE: |
542 | timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val; | |
543 | break; | |
27bb0b2d | 544 | case HPET_TN_ROUTE + 4: |
8caa0065 | 545 | timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff); |
27bb0b2d JK |
546 | break; |
547 | default: | |
548 | DPRINTF("qemu: invalid hpet_ram_writel\n"); | |
549 | break; | |
16b29ae1 AL |
550 | } |
551 | return; | |
552 | } else { | |
553 | switch (index) { | |
27bb0b2d JK |
554 | case HPET_ID: |
555 | return; | |
556 | case HPET_CFG: | |
557 | val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); | |
558 | s->config = (s->config & 0xffffffff00000000ULL) | val; | |
559 | if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) { | |
560 | /* Enable main counter and interrupt generation. */ | |
561 | s->hpet_offset = | |
74475455 | 562 | ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock); |
be4b44c5 | 563 | for (i = 0; i < s->num_timers; i++) { |
27bb0b2d JK |
564 | if ((&s->timer[i])->cmp != ~0ULL) { |
565 | hpet_set_timer(&s->timer[i]); | |
566 | } | |
16b29ae1 | 567 | } |
27bb0b2d JK |
568 | } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) { |
569 | /* Halt main counter and disable interrupt generation. */ | |
b7eaa6c7 | 570 | s->hpet_counter = hpet_get_ticks(s); |
be4b44c5 | 571 | for (i = 0; i < s->num_timers; i++) { |
27bb0b2d | 572 | hpet_del_timer(&s->timer[i]); |
16b29ae1 | 573 | } |
27bb0b2d JK |
574 | } |
575 | /* i8254 and RTC are disabled when HPET is in legacy mode */ | |
576 | if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) { | |
577 | hpet_pit_disable(); | |
7d932dfd | 578 | qemu_irq_lower(s->irqs[RTC_ISA_IRQ]); |
27bb0b2d JK |
579 | } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) { |
580 | hpet_pit_enable(); | |
7d932dfd | 581 | qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level); |
27bb0b2d JK |
582 | } |
583 | break; | |
584 | case HPET_CFG + 4: | |
b2bedb21 | 585 | DPRINTF("qemu: invalid HPET_CFG+4 write\n"); |
27bb0b2d JK |
586 | break; |
587 | case HPET_STATUS: | |
22a9fe38 | 588 | val = new_val & s->isr; |
be4b44c5 | 589 | for (i = 0; i < s->num_timers; i++) { |
22a9fe38 JK |
590 | if (val & (1 << i)) { |
591 | update_irq(&s->timer[i], 0); | |
592 | } | |
593 | } | |
27bb0b2d JK |
594 | break; |
595 | case HPET_COUNTER: | |
b7eaa6c7 | 596 | if (hpet_enabled(s)) { |
ad0a6551 | 597 | DPRINTF("qemu: Writing counter while HPET enabled!\n"); |
27bb0b2d JK |
598 | } |
599 | s->hpet_counter = | |
600 | (s->hpet_counter & 0xffffffff00000000ULL) | value; | |
601 | DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n", | |
602 | value, s->hpet_counter); | |
603 | break; | |
604 | case HPET_COUNTER + 4: | |
b7eaa6c7 | 605 | if (hpet_enabled(s)) { |
ad0a6551 | 606 | DPRINTF("qemu: Writing counter while HPET enabled!\n"); |
27bb0b2d JK |
607 | } |
608 | s->hpet_counter = | |
609 | (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32); | |
610 | DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n", | |
611 | value, s->hpet_counter); | |
612 | break; | |
613 | default: | |
614 | DPRINTF("qemu: invalid hpet_ram_writel\n"); | |
615 | break; | |
16b29ae1 AL |
616 | } |
617 | } | |
618 | } | |
619 | ||
e977aa37 AK |
620 | static const MemoryRegionOps hpet_ram_ops = { |
621 | .read = hpet_ram_read, | |
622 | .write = hpet_ram_write, | |
623 | .valid = { | |
624 | .min_access_size = 4, | |
625 | .max_access_size = 4, | |
626 | }, | |
627 | .endianness = DEVICE_NATIVE_ENDIAN, | |
16b29ae1 AL |
628 | }; |
629 | ||
822557eb | 630 | static void hpet_reset(DeviceState *d) |
27bb0b2d | 631 | { |
822557eb | 632 | HPETState *s = FROM_SYSBUS(HPETState, sysbus_from_qdev(d)); |
16b29ae1 AL |
633 | int i; |
634 | static int count = 0; | |
635 | ||
be4b44c5 | 636 | for (i = 0; i < s->num_timers; i++) { |
16b29ae1 | 637 | HPETTimer *timer = &s->timer[i]; |
27bb0b2d | 638 | |
16b29ae1 | 639 | hpet_del_timer(timer); |
16b29ae1 | 640 | timer->cmp = ~0ULL; |
8caa0065 JK |
641 | timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP; |
642 | if (s->flags & (1 << HPET_MSI_SUPPORT)) { | |
643 | timer->config |= HPET_TN_FSB_CAP; | |
644 | } | |
ce536cfd BK |
645 | /* advertise availability of ioapic inti2 */ |
646 | timer->config |= 0x00000004ULL << 32; | |
16b29ae1 AL |
647 | timer->period = 0ULL; |
648 | timer->wrap_flag = 0; | |
649 | } | |
650 | ||
651 | s->hpet_counter = 0ULL; | |
652 | s->hpet_offset = 0ULL; | |
7d93b1fa | 653 | s->config = 0ULL; |
27bb0b2d | 654 | if (count > 0) { |
c50c2d68 | 655 | /* we don't enable pit when hpet_reset is first called (by hpet_init) |
16b29ae1 AL |
656 | * because hpet is taking over for pit here. On subsequent invocations, |
657 | * hpet_reset is called due to system reset. At this point control must | |
c50c2d68 | 658 | * be returned to pit until SW reenables hpet. |
16b29ae1 AL |
659 | */ |
660 | hpet_pit_enable(); | |
27bb0b2d | 661 | } |
40ac17cd GN |
662 | hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability; |
663 | hpet_cfg.hpet[s->hpet_id].address = sysbus_from_qdev(d)->mmio[0].addr; | |
16b29ae1 | 664 | count = 1; |
5904ae4e JK |
665 | |
666 | /* to document that the RTC lowers its output on reset as well */ | |
667 | s->rtc_irq_level = 0; | |
16b29ae1 AL |
668 | } |
669 | ||
7d932dfd JK |
670 | static void hpet_handle_rtc_irq(void *opaque, int n, int level) |
671 | { | |
672 | HPETState *s = FROM_SYSBUS(HPETState, opaque); | |
673 | ||
674 | s->rtc_irq_level = level; | |
675 | if (!hpet_in_legacy_mode(s)) { | |
676 | qemu_set_irq(s->irqs[RTC_ISA_IRQ], level); | |
677 | } | |
678 | } | |
679 | ||
822557eb | 680 | static int hpet_init(SysBusDevice *dev) |
27bb0b2d | 681 | { |
822557eb | 682 | HPETState *s = FROM_SYSBUS(HPETState, dev); |
e977aa37 | 683 | int i; |
27bb0b2d | 684 | HPETTimer *timer; |
16b29ae1 | 685 | |
d2c5efd8 SW |
686 | if (hpet_cfg.count == UINT8_MAX) { |
687 | /* first instance */ | |
40ac17cd | 688 | hpet_cfg.count = 0; |
d2c5efd8 | 689 | } |
40ac17cd GN |
690 | |
691 | if (hpet_cfg.count == 8) { | |
692 | fprintf(stderr, "Only 8 instances of HPET is allowed\n"); | |
693 | return -1; | |
694 | } | |
695 | ||
696 | s->hpet_id = hpet_cfg.count++; | |
697 | ||
822557eb JK |
698 | for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) { |
699 | sysbus_init_irq(dev, &s->irqs[i]); | |
700 | } | |
be4b44c5 JK |
701 | |
702 | if (s->num_timers < HPET_MIN_TIMERS) { | |
703 | s->num_timers = HPET_MIN_TIMERS; | |
704 | } else if (s->num_timers > HPET_MAX_TIMERS) { | |
705 | s->num_timers = HPET_MAX_TIMERS; | |
706 | } | |
707 | for (i = 0; i < HPET_MAX_TIMERS; i++) { | |
27bb0b2d | 708 | timer = &s->timer[i]; |
74475455 | 709 | timer->qemu_timer = qemu_new_timer_ns(vm_clock, hpet_timer, timer); |
7afbecc9 JK |
710 | timer->tn = i; |
711 | timer->state = s; | |
16b29ae1 | 712 | } |
822557eb | 713 | |
072c2c31 JK |
714 | /* 64-bit main counter; LegacyReplacementRoute. */ |
715 | s->capability = 0x8086a001ULL; | |
716 | s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT; | |
717 | s->capability |= ((HPET_CLK_PERIOD) << 32); | |
718 | ||
7d932dfd JK |
719 | qdev_init_gpio_in(&dev->qdev, hpet_handle_rtc_irq, 1); |
720 | ||
16b29ae1 | 721 | /* HPET Area */ |
e977aa37 | 722 | memory_region_init_io(&s->iomem, &hpet_ram_ops, s, "hpet", 0x400); |
750ecd44 | 723 | sysbus_init_mmio(dev, &s->iomem); |
822557eb | 724 | return 0; |
16b29ae1 | 725 | } |
822557eb | 726 | |
999e12bb AL |
727 | static Property hpet_device_properties[] = { |
728 | DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS), | |
729 | DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false), | |
730 | DEFINE_PROP_END_OF_LIST(), | |
731 | }; | |
732 | ||
733 | static void hpet_device_class_init(ObjectClass *klass, void *data) | |
734 | { | |
39bffca2 | 735 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
736 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
737 | ||
738 | k->init = hpet_init; | |
39bffca2 AL |
739 | dc->no_user = 1; |
740 | dc->reset = hpet_reset; | |
741 | dc->vmsd = &vmstate_hpet; | |
742 | dc->props = hpet_device_properties; | |
999e12bb AL |
743 | } |
744 | ||
39bffca2 AL |
745 | static TypeInfo hpet_device_info = { |
746 | .name = "hpet", | |
747 | .parent = TYPE_SYS_BUS_DEVICE, | |
748 | .instance_size = sizeof(HPETState), | |
749 | .class_init = hpet_device_class_init, | |
822557eb JK |
750 | }; |
751 | ||
83f7d43a | 752 | static void hpet_register_types(void) |
822557eb | 753 | { |
39bffca2 | 754 | type_register_static(&hpet_device_info); |
822557eb JK |
755 | } |
756 | ||
83f7d43a | 757 | type_init(hpet_register_types) |