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Commit | Line | Data |
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16b29ae1 AL |
1 | /* |
2 | * High Precisition Event Timer emulation | |
3 | * | |
4 | * Copyright (c) 2007 Alexander Graf | |
5 | * Copyright (c) 2008 IBM Corporation | |
6 | * | |
7 | * Authors: Beth Kon <bkon@us.ibm.com> | |
8 | * | |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 20 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
16b29ae1 AL |
21 | * |
22 | * ***************************************************************** | |
23 | * | |
24 | * This driver attempts to emulate an HPET device in software. | |
25 | */ | |
26 | ||
27 | #include "hw.h" | |
bf4f74c0 | 28 | #include "pc.h" |
16b29ae1 AL |
29 | #include "console.h" |
30 | #include "qemu-timer.h" | |
31 | #include "hpet_emul.h" | |
822557eb | 32 | #include "sysbus.h" |
16b29ae1 | 33 | |
16b29ae1 AL |
34 | //#define HPET_DEBUG |
35 | #ifdef HPET_DEBUG | |
d0f2c4c6 | 36 | #define DPRINTF printf |
16b29ae1 | 37 | #else |
d0f2c4c6 | 38 | #define DPRINTF(...) |
16b29ae1 AL |
39 | #endif |
40 | ||
27bb0b2d JK |
41 | struct HPETState; |
42 | typedef struct HPETTimer { /* timers */ | |
43 | uint8_t tn; /*timer number*/ | |
44 | QEMUTimer *qemu_timer; | |
45 | struct HPETState *state; | |
46 | /* Memory-mapped, software visible timer registers */ | |
47 | uint64_t config; /* configuration/cap */ | |
48 | uint64_t cmp; /* comparator */ | |
49 | uint64_t fsb; /* FSB route, not supported now */ | |
50 | /* Hidden register state */ | |
51 | uint64_t period; /* Last value written to comparator */ | |
52 | uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit | |
53 | * mode. Next pop will be actual timer expiration. | |
54 | */ | |
55 | } HPETTimer; | |
56 | ||
57 | typedef struct HPETState { | |
822557eb | 58 | SysBusDevice busdev; |
27bb0b2d | 59 | uint64_t hpet_offset; |
822557eb | 60 | qemu_irq irqs[HPET_NUM_IRQ_ROUTES]; |
27bb0b2d JK |
61 | HPETTimer timer[HPET_NUM_TIMERS]; |
62 | ||
63 | /* Memory-mapped, software visible registers */ | |
64 | uint64_t capability; /* capabilities */ | |
65 | uint64_t config; /* configuration */ | |
66 | uint64_t isr; /* interrupt status reg */ | |
67 | uint64_t hpet_counter; /* main counter */ | |
68 | } HPETState; | |
69 | ||
16b29ae1 AL |
70 | static HPETState *hpet_statep; |
71 | ||
72 | uint32_t hpet_in_legacy_mode(void) | |
73 | { | |
27bb0b2d | 74 | if (!hpet_statep) { |
16b29ae1 | 75 | return 0; |
27bb0b2d JK |
76 | } |
77 | return hpet_statep->config & HPET_CFG_LEGACY; | |
16b29ae1 AL |
78 | } |
79 | ||
c50c2d68 | 80 | static uint32_t timer_int_route(struct HPETTimer *timer) |
16b29ae1 | 81 | { |
27bb0b2d | 82 | return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT; |
16b29ae1 AL |
83 | } |
84 | ||
85 | static uint32_t hpet_enabled(void) | |
86 | { | |
87 | return hpet_statep->config & HPET_CFG_ENABLE; | |
88 | } | |
89 | ||
90 | static uint32_t timer_is_periodic(HPETTimer *t) | |
91 | { | |
92 | return t->config & HPET_TN_PERIODIC; | |
93 | } | |
94 | ||
95 | static uint32_t timer_enabled(HPETTimer *t) | |
96 | { | |
97 | return t->config & HPET_TN_ENABLE; | |
98 | } | |
99 | ||
100 | static uint32_t hpet_time_after(uint64_t a, uint64_t b) | |
101 | { | |
102 | return ((int32_t)(b) - (int32_t)(a) < 0); | |
103 | } | |
104 | ||
105 | static uint32_t hpet_time_after64(uint64_t a, uint64_t b) | |
106 | { | |
107 | return ((int64_t)(b) - (int64_t)(a) < 0); | |
108 | } | |
109 | ||
c50c2d68 | 110 | static uint64_t ticks_to_ns(uint64_t value) |
16b29ae1 AL |
111 | { |
112 | return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS)); | |
113 | } | |
114 | ||
c50c2d68 | 115 | static uint64_t ns_to_ticks(uint64_t value) |
16b29ae1 AL |
116 | { |
117 | return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD)); | |
118 | } | |
119 | ||
120 | static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask) | |
121 | { | |
122 | new &= mask; | |
123 | new |= old & ~mask; | |
124 | return new; | |
125 | } | |
126 | ||
127 | static int activating_bit(uint64_t old, uint64_t new, uint64_t mask) | |
128 | { | |
c50c2d68 | 129 | return (!(old & mask) && (new & mask)); |
16b29ae1 AL |
130 | } |
131 | ||
132 | static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask) | |
133 | { | |
c50c2d68 | 134 | return ((old & mask) && !(new & mask)); |
16b29ae1 AL |
135 | } |
136 | ||
c50c2d68 | 137 | static uint64_t hpet_get_ticks(void) |
16b29ae1 | 138 | { |
27bb0b2d | 139 | return ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset); |
16b29ae1 AL |
140 | } |
141 | ||
c50c2d68 AJ |
142 | /* |
143 | * calculate diff between comparator value and current ticks | |
16b29ae1 AL |
144 | */ |
145 | static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current) | |
146 | { | |
c50c2d68 | 147 | |
16b29ae1 AL |
148 | if (t->config & HPET_TN_32BIT) { |
149 | uint32_t diff, cmp; | |
27bb0b2d | 150 | |
16b29ae1 AL |
151 | cmp = (uint32_t)t->cmp; |
152 | diff = cmp - (uint32_t)current; | |
153 | diff = (int32_t)diff > 0 ? diff : (uint32_t)0; | |
154 | return (uint64_t)diff; | |
155 | } else { | |
156 | uint64_t diff, cmp; | |
27bb0b2d | 157 | |
16b29ae1 AL |
158 | cmp = t->cmp; |
159 | diff = cmp - current; | |
160 | diff = (int64_t)diff > 0 ? diff : (uint64_t)0; | |
161 | return diff; | |
162 | } | |
163 | } | |
164 | ||
165 | static void update_irq(struct HPETTimer *timer) | |
166 | { | |
16b29ae1 AL |
167 | int route; |
168 | ||
169 | if (timer->tn <= 1 && hpet_in_legacy_mode()) { | |
170 | /* if LegacyReplacementRoute bit is set, HPET specification requires | |
171 | * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC, | |
c50c2d68 | 172 | * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC. |
16b29ae1 | 173 | */ |
27bb0b2d | 174 | route = (timer->tn == 0) ? 0 : 8; |
16b29ae1 | 175 | } else { |
27bb0b2d | 176 | route = timer_int_route(timer); |
16b29ae1 | 177 | } |
27bb0b2d JK |
178 | if (!timer_enabled(timer) || !hpet_enabled()) { |
179 | return; | |
16b29ae1 | 180 | } |
27bb0b2d | 181 | qemu_irq_pulse(timer->state->irqs[route]); |
16b29ae1 AL |
182 | } |
183 | ||
d4bfa4d7 | 184 | static void hpet_pre_save(void *opaque) |
16b29ae1 | 185 | { |
d4bfa4d7 | 186 | HPETState *s = opaque; |
27bb0b2d | 187 | |
16b29ae1 | 188 | /* save current counter value */ |
c50c2d68 | 189 | s->hpet_counter = hpet_get_ticks(); |
16b29ae1 AL |
190 | } |
191 | ||
e59fb374 | 192 | static int hpet_post_load(void *opaque, int version_id) |
16b29ae1 AL |
193 | { |
194 | HPETState *s = opaque; | |
c50c2d68 | 195 | |
16b29ae1 AL |
196 | /* Recalculate the offset between the main counter and guest time */ |
197 | s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock); | |
16b29ae1 AL |
198 | return 0; |
199 | } | |
200 | ||
e6cb4d45 JQ |
201 | static const VMStateDescription vmstate_hpet_timer = { |
202 | .name = "hpet_timer", | |
203 | .version_id = 1, | |
204 | .minimum_version_id = 1, | |
205 | .minimum_version_id_old = 1, | |
206 | .fields = (VMStateField []) { | |
207 | VMSTATE_UINT8(tn, HPETTimer), | |
208 | VMSTATE_UINT64(config, HPETTimer), | |
209 | VMSTATE_UINT64(cmp, HPETTimer), | |
210 | VMSTATE_UINT64(fsb, HPETTimer), | |
211 | VMSTATE_UINT64(period, HPETTimer), | |
212 | VMSTATE_UINT8(wrap_flag, HPETTimer), | |
213 | VMSTATE_TIMER(qemu_timer, HPETTimer), | |
214 | VMSTATE_END_OF_LIST() | |
215 | } | |
216 | }; | |
217 | ||
218 | static const VMStateDescription vmstate_hpet = { | |
219 | .name = "hpet", | |
220 | .version_id = 1, | |
221 | .minimum_version_id = 1, | |
222 | .minimum_version_id_old = 1, | |
223 | .pre_save = hpet_pre_save, | |
224 | .post_load = hpet_post_load, | |
225 | .fields = (VMStateField []) { | |
226 | VMSTATE_UINT64(config, HPETState), | |
227 | VMSTATE_UINT64(isr, HPETState), | |
228 | VMSTATE_UINT64(hpet_counter, HPETState), | |
229 | VMSTATE_STRUCT_ARRAY(timer, HPETState, HPET_NUM_TIMERS, 0, | |
230 | vmstate_hpet_timer, HPETTimer), | |
231 | VMSTATE_END_OF_LIST() | |
232 | } | |
233 | }; | |
234 | ||
c50c2d68 | 235 | /* |
16b29ae1 AL |
236 | * timer expiration callback |
237 | */ | |
238 | static void hpet_timer(void *opaque) | |
239 | { | |
27bb0b2d | 240 | HPETTimer *t = opaque; |
16b29ae1 AL |
241 | uint64_t diff; |
242 | ||
243 | uint64_t period = t->period; | |
244 | uint64_t cur_tick = hpet_get_ticks(); | |
245 | ||
246 | if (timer_is_periodic(t) && period != 0) { | |
247 | if (t->config & HPET_TN_32BIT) { | |
27bb0b2d | 248 | while (hpet_time_after(cur_tick, t->cmp)) { |
16b29ae1 | 249 | t->cmp = (uint32_t)(t->cmp + t->period); |
27bb0b2d JK |
250 | } |
251 | } else { | |
252 | while (hpet_time_after64(cur_tick, t->cmp)) { | |
16b29ae1 | 253 | t->cmp += period; |
27bb0b2d JK |
254 | } |
255 | } | |
16b29ae1 | 256 | diff = hpet_calculate_diff(t, cur_tick); |
27bb0b2d JK |
257 | qemu_mod_timer(t->qemu_timer, |
258 | qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff)); | |
16b29ae1 AL |
259 | } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { |
260 | if (t->wrap_flag) { | |
261 | diff = hpet_calculate_diff(t, cur_tick); | |
27bb0b2d JK |
262 | qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) + |
263 | (int64_t)ticks_to_ns(diff)); | |
16b29ae1 AL |
264 | t->wrap_flag = 0; |
265 | } | |
266 | } | |
267 | update_irq(t); | |
268 | } | |
269 | ||
270 | static void hpet_set_timer(HPETTimer *t) | |
271 | { | |
272 | uint64_t diff; | |
273 | uint32_t wrap_diff; /* how many ticks until we wrap? */ | |
274 | uint64_t cur_tick = hpet_get_ticks(); | |
c50c2d68 | 275 | |
16b29ae1 AL |
276 | /* whenever new timer is being set up, make sure wrap_flag is 0 */ |
277 | t->wrap_flag = 0; | |
278 | diff = hpet_calculate_diff(t, cur_tick); | |
279 | ||
c50c2d68 | 280 | /* hpet spec says in one-shot 32-bit mode, generate an interrupt when |
16b29ae1 | 281 | * counter wraps in addition to an interrupt with comparator match. |
c50c2d68 | 282 | */ |
16b29ae1 AL |
283 | if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { |
284 | wrap_diff = 0xffffffff - (uint32_t)cur_tick; | |
285 | if (wrap_diff < (uint32_t)diff) { | |
286 | diff = wrap_diff; | |
c50c2d68 | 287 | t->wrap_flag = 1; |
16b29ae1 AL |
288 | } |
289 | } | |
27bb0b2d JK |
290 | qemu_mod_timer(t->qemu_timer, |
291 | qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff)); | |
16b29ae1 AL |
292 | } |
293 | ||
294 | static void hpet_del_timer(HPETTimer *t) | |
295 | { | |
296 | qemu_del_timer(t->qemu_timer); | |
297 | } | |
298 | ||
299 | #ifdef HPET_DEBUG | |
c227f099 | 300 | static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr) |
16b29ae1 AL |
301 | { |
302 | printf("qemu: hpet_read b at %" PRIx64 "\n", addr); | |
303 | return 0; | |
304 | } | |
305 | ||
c227f099 | 306 | static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr) |
16b29ae1 AL |
307 | { |
308 | printf("qemu: hpet_read w at %" PRIx64 "\n", addr); | |
309 | return 0; | |
310 | } | |
311 | #endif | |
312 | ||
c227f099 | 313 | static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr) |
16b29ae1 | 314 | { |
27bb0b2d | 315 | HPETState *s = opaque; |
16b29ae1 AL |
316 | uint64_t cur_tick, index; |
317 | ||
d0f2c4c6 | 318 | DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr); |
16b29ae1 AL |
319 | index = addr; |
320 | /*address range of all TN regs*/ | |
321 | if (index >= 0x100 && index <= 0x3ff) { | |
322 | uint8_t timer_id = (addr - 0x100) / 0x20; | |
27bb0b2d JK |
323 | HPETTimer *timer = &s->timer[timer_id]; |
324 | ||
16b29ae1 | 325 | if (timer_id > HPET_NUM_TIMERS - 1) { |
6982d664 | 326 | DPRINTF("qemu: timer id out of range\n"); |
16b29ae1 AL |
327 | return 0; |
328 | } | |
16b29ae1 AL |
329 | |
330 | switch ((addr - 0x100) % 0x20) { | |
27bb0b2d JK |
331 | case HPET_TN_CFG: |
332 | return timer->config; | |
333 | case HPET_TN_CFG + 4: // Interrupt capabilities | |
334 | return timer->config >> 32; | |
335 | case HPET_TN_CMP: // comparator register | |
336 | return timer->cmp; | |
337 | case HPET_TN_CMP + 4: | |
338 | return timer->cmp >> 32; | |
339 | case HPET_TN_ROUTE: | |
340 | return timer->fsb >> 32; | |
341 | default: | |
342 | DPRINTF("qemu: invalid hpet_ram_readl\n"); | |
343 | break; | |
16b29ae1 AL |
344 | } |
345 | } else { | |
346 | switch (index) { | |
27bb0b2d JK |
347 | case HPET_ID: |
348 | return s->capability; | |
349 | case HPET_PERIOD: | |
350 | return s->capability >> 32; | |
351 | case HPET_CFG: | |
352 | return s->config; | |
353 | case HPET_CFG + 4: | |
354 | DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n"); | |
355 | return 0; | |
356 | case HPET_COUNTER: | |
357 | if (hpet_enabled()) { | |
358 | cur_tick = hpet_get_ticks(); | |
359 | } else { | |
360 | cur_tick = s->hpet_counter; | |
361 | } | |
362 | DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick); | |
363 | return cur_tick; | |
364 | case HPET_COUNTER + 4: | |
365 | if (hpet_enabled()) { | |
366 | cur_tick = hpet_get_ticks(); | |
367 | } else { | |
368 | cur_tick = s->hpet_counter; | |
369 | } | |
370 | DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick); | |
371 | return cur_tick >> 32; | |
372 | case HPET_STATUS: | |
373 | return s->isr; | |
374 | default: | |
375 | DPRINTF("qemu: invalid hpet_ram_readl\n"); | |
376 | break; | |
16b29ae1 AL |
377 | } |
378 | } | |
379 | return 0; | |
380 | } | |
381 | ||
382 | #ifdef HPET_DEBUG | |
c227f099 | 383 | static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr, |
16b29ae1 AL |
384 | uint32_t value) |
385 | { | |
c50c2d68 | 386 | printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n", |
16b29ae1 AL |
387 | addr, value); |
388 | } | |
389 | ||
c227f099 | 390 | static void hpet_ram_writew(void *opaque, target_phys_addr_t addr, |
16b29ae1 AL |
391 | uint32_t value) |
392 | { | |
c50c2d68 | 393 | printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n", |
16b29ae1 AL |
394 | addr, value); |
395 | } | |
396 | #endif | |
397 | ||
c227f099 | 398 | static void hpet_ram_writel(void *opaque, target_phys_addr_t addr, |
16b29ae1 AL |
399 | uint32_t value) |
400 | { | |
401 | int i; | |
27bb0b2d | 402 | HPETState *s = opaque; |
ce536cfd | 403 | uint64_t old_val, new_val, val, index; |
16b29ae1 | 404 | |
d0f2c4c6 | 405 | DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value); |
16b29ae1 AL |
406 | index = addr; |
407 | old_val = hpet_ram_readl(opaque, addr); | |
408 | new_val = value; | |
409 | ||
410 | /*address range of all TN regs*/ | |
411 | if (index >= 0x100 && index <= 0x3ff) { | |
412 | uint8_t timer_id = (addr - 0x100) / 0x20; | |
16b29ae1 | 413 | HPETTimer *timer = &s->timer[timer_id]; |
c50c2d68 | 414 | |
27bb0b2d | 415 | DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id); |
6982d664 JK |
416 | if (timer_id > HPET_NUM_TIMERS - 1) { |
417 | DPRINTF("qemu: timer id out of range\n"); | |
418 | return; | |
419 | } | |
16b29ae1 | 420 | switch ((addr - 0x100) % 0x20) { |
27bb0b2d JK |
421 | case HPET_TN_CFG: |
422 | DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n"); | |
423 | val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); | |
424 | timer->config = (timer->config & 0xffffffff00000000ULL) | val; | |
425 | if (new_val & HPET_TN_32BIT) { | |
426 | timer->cmp = (uint32_t)timer->cmp; | |
427 | timer->period = (uint32_t)timer->period; | |
428 | } | |
429 | if (new_val & HPET_TN_TYPE_LEVEL) { | |
430 | printf("qemu: level-triggered hpet not supported\n"); | |
431 | exit (-1); | |
432 | } | |
433 | break; | |
434 | case HPET_TN_CFG + 4: // Interrupt capabilities | |
435 | DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n"); | |
436 | break; | |
437 | case HPET_TN_CMP: // comparator register | |
438 | DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n"); | |
439 | if (timer->config & HPET_TN_32BIT) { | |
440 | new_val = (uint32_t)new_val; | |
441 | } | |
442 | if (!timer_is_periodic(timer) | |
443 | || (timer->config & HPET_TN_SETVAL)) { | |
444 | timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val; | |
445 | } | |
446 | if (timer_is_periodic(timer)) { | |
447 | /* | |
448 | * FIXME: Clamp period to reasonable min value? | |
449 | * Clamp period to reasonable max value | |
450 | */ | |
451 | new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; | |
452 | timer->period = | |
453 | (timer->period & 0xffffffff00000000ULL) | new_val; | |
454 | } | |
455 | timer->config &= ~HPET_TN_SETVAL; | |
456 | if (hpet_enabled()) { | |
457 | hpet_set_timer(timer); | |
458 | } | |
459 | break; | |
460 | case HPET_TN_CMP + 4: // comparator register high order | |
461 | DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n"); | |
462 | if (!timer_is_periodic(timer) | |
463 | || (timer->config & HPET_TN_SETVAL)) { | |
464 | timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32; | |
465 | } else { | |
466 | /* | |
467 | * FIXME: Clamp period to reasonable min value? | |
468 | * Clamp period to reasonable max value | |
469 | */ | |
470 | new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; | |
471 | timer->period = | |
472 | (timer->period & 0xffffffffULL) | new_val << 32; | |
16b29ae1 AL |
473 | } |
474 | timer->config &= ~HPET_TN_SETVAL; | |
27bb0b2d | 475 | if (hpet_enabled()) { |
16b29ae1 | 476 | hpet_set_timer(timer); |
16b29ae1 | 477 | } |
16b29ae1 | 478 | break; |
27bb0b2d JK |
479 | case HPET_TN_ROUTE + 4: |
480 | DPRINTF("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n"); | |
481 | break; | |
482 | default: | |
483 | DPRINTF("qemu: invalid hpet_ram_writel\n"); | |
484 | break; | |
16b29ae1 AL |
485 | } |
486 | return; | |
487 | } else { | |
488 | switch (index) { | |
27bb0b2d JK |
489 | case HPET_ID: |
490 | return; | |
491 | case HPET_CFG: | |
492 | val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); | |
493 | s->config = (s->config & 0xffffffff00000000ULL) | val; | |
494 | if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) { | |
495 | /* Enable main counter and interrupt generation. */ | |
496 | s->hpet_offset = | |
497 | ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock); | |
498 | for (i = 0; i < HPET_NUM_TIMERS; i++) { | |
499 | if ((&s->timer[i])->cmp != ~0ULL) { | |
500 | hpet_set_timer(&s->timer[i]); | |
501 | } | |
16b29ae1 | 502 | } |
27bb0b2d JK |
503 | } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) { |
504 | /* Halt main counter and disable interrupt generation. */ | |
505 | s->hpet_counter = hpet_get_ticks(); | |
506 | for (i = 0; i < HPET_NUM_TIMERS; i++) { | |
507 | hpet_del_timer(&s->timer[i]); | |
16b29ae1 | 508 | } |
27bb0b2d JK |
509 | } |
510 | /* i8254 and RTC are disabled when HPET is in legacy mode */ | |
511 | if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) { | |
512 | hpet_pit_disable(); | |
513 | } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) { | |
514 | hpet_pit_enable(); | |
515 | } | |
516 | break; | |
517 | case HPET_CFG + 4: | |
518 | DPRINTF("qemu: invalid HPET_CFG+4 write \n"); | |
519 | break; | |
520 | case HPET_STATUS: | |
521 | /* FIXME: need to handle level-triggered interrupts */ | |
522 | break; | |
523 | case HPET_COUNTER: | |
524 | if (hpet_enabled()) { | |
ad0a6551 | 525 | DPRINTF("qemu: Writing counter while HPET enabled!\n"); |
27bb0b2d JK |
526 | } |
527 | s->hpet_counter = | |
528 | (s->hpet_counter & 0xffffffff00000000ULL) | value; | |
529 | DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n", | |
530 | value, s->hpet_counter); | |
531 | break; | |
532 | case HPET_COUNTER + 4: | |
533 | if (hpet_enabled()) { | |
ad0a6551 | 534 | DPRINTF("qemu: Writing counter while HPET enabled!\n"); |
27bb0b2d JK |
535 | } |
536 | s->hpet_counter = | |
537 | (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32); | |
538 | DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n", | |
539 | value, s->hpet_counter); | |
540 | break; | |
541 | default: | |
542 | DPRINTF("qemu: invalid hpet_ram_writel\n"); | |
543 | break; | |
16b29ae1 AL |
544 | } |
545 | } | |
546 | } | |
547 | ||
d60efc6b | 548 | static CPUReadMemoryFunc * const hpet_ram_read[] = { |
16b29ae1 AL |
549 | #ifdef HPET_DEBUG |
550 | hpet_ram_readb, | |
551 | hpet_ram_readw, | |
552 | #else | |
553 | NULL, | |
554 | NULL, | |
555 | #endif | |
556 | hpet_ram_readl, | |
557 | }; | |
558 | ||
d60efc6b | 559 | static CPUWriteMemoryFunc * const hpet_ram_write[] = { |
16b29ae1 AL |
560 | #ifdef HPET_DEBUG |
561 | hpet_ram_writeb, | |
562 | hpet_ram_writew, | |
563 | #else | |
564 | NULL, | |
565 | NULL, | |
566 | #endif | |
567 | hpet_ram_writel, | |
568 | }; | |
569 | ||
822557eb | 570 | static void hpet_reset(DeviceState *d) |
27bb0b2d | 571 | { |
822557eb | 572 | HPETState *s = FROM_SYSBUS(HPETState, sysbus_from_qdev(d)); |
16b29ae1 AL |
573 | int i; |
574 | static int count = 0; | |
575 | ||
27bb0b2d | 576 | for (i = 0; i < HPET_NUM_TIMERS; i++) { |
16b29ae1 | 577 | HPETTimer *timer = &s->timer[i]; |
27bb0b2d | 578 | |
16b29ae1 | 579 | hpet_del_timer(timer); |
16b29ae1 AL |
580 | timer->cmp = ~0ULL; |
581 | timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP; | |
ce536cfd BK |
582 | /* advertise availability of ioapic inti2 */ |
583 | timer->config |= 0x00000004ULL << 32; | |
16b29ae1 AL |
584 | timer->period = 0ULL; |
585 | timer->wrap_flag = 0; | |
586 | } | |
587 | ||
588 | s->hpet_counter = 0ULL; | |
589 | s->hpet_offset = 0ULL; | |
590 | /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */ | |
591 | s->capability = 0x8086a201ULL; | |
592 | s->capability |= ((HPET_CLK_PERIOD) << 32); | |
7d93b1fa | 593 | s->config = 0ULL; |
27bb0b2d | 594 | if (count > 0) { |
c50c2d68 | 595 | /* we don't enable pit when hpet_reset is first called (by hpet_init) |
16b29ae1 AL |
596 | * because hpet is taking over for pit here. On subsequent invocations, |
597 | * hpet_reset is called due to system reset. At this point control must | |
c50c2d68 | 598 | * be returned to pit until SW reenables hpet. |
16b29ae1 AL |
599 | */ |
600 | hpet_pit_enable(); | |
27bb0b2d | 601 | } |
16b29ae1 AL |
602 | count = 1; |
603 | } | |
604 | ||
822557eb | 605 | static int hpet_init(SysBusDevice *dev) |
27bb0b2d | 606 | { |
822557eb | 607 | HPETState *s = FROM_SYSBUS(HPETState, dev); |
16b29ae1 | 608 | int i, iomemtype; |
27bb0b2d | 609 | HPETTimer *timer; |
16b29ae1 | 610 | |
822557eb | 611 | assert(!hpet_statep); |
16b29ae1 | 612 | hpet_statep = s; |
822557eb JK |
613 | for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) { |
614 | sysbus_init_irq(dev, &s->irqs[i]); | |
615 | } | |
27bb0b2d JK |
616 | for (i = 0; i < HPET_NUM_TIMERS; i++) { |
617 | timer = &s->timer[i]; | |
16b29ae1 | 618 | timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer); |
7afbecc9 JK |
619 | timer->tn = i; |
620 | timer->state = s; | |
16b29ae1 | 621 | } |
822557eb | 622 | |
16b29ae1 | 623 | /* HPET Area */ |
1eed09cb | 624 | iomemtype = cpu_register_io_memory(hpet_ram_read, |
16b29ae1 | 625 | hpet_ram_write, s); |
822557eb JK |
626 | sysbus_init_mmio(dev, 0x400, iomemtype); |
627 | return 0; | |
16b29ae1 | 628 | } |
822557eb JK |
629 | |
630 | static SysBusDeviceInfo hpet_device_info = { | |
631 | .qdev.name = "hpet", | |
632 | .qdev.size = sizeof(HPETState), | |
633 | .qdev.no_user = 1, | |
634 | .qdev.vmsd = &vmstate_hpet, | |
635 | .qdev.reset = hpet_reset, | |
636 | .init = hpet_init, | |
637 | }; | |
638 | ||
639 | static void hpet_register_device(void) | |
640 | { | |
641 | sysbus_register_withprop(&hpet_device_info); | |
642 | } | |
643 | ||
644 | device_init(hpet_register_device) |