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Commit | Line | Data |
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16b29ae1 AL |
1 | /* |
2 | * High Precisition Event Timer emulation | |
3 | * | |
4 | * Copyright (c) 2007 Alexander Graf | |
5 | * Copyright (c) 2008 IBM Corporation | |
6 | * | |
7 | * Authors: Beth Kon <bkon@us.ibm.com> | |
8 | * | |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 20 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
16b29ae1 AL |
21 | * |
22 | * ***************************************************************** | |
23 | * | |
24 | * This driver attempts to emulate an HPET device in software. | |
25 | */ | |
26 | ||
27 | #include "hw.h" | |
bf4f74c0 | 28 | #include "pc.h" |
16b29ae1 AL |
29 | #include "console.h" |
30 | #include "qemu-timer.h" | |
31 | #include "hpet_emul.h" | |
822557eb | 32 | #include "sysbus.h" |
7d932dfd | 33 | #include "mc146818rtc.h" |
16b29ae1 | 34 | |
16b29ae1 AL |
35 | //#define HPET_DEBUG |
36 | #ifdef HPET_DEBUG | |
d0f2c4c6 | 37 | #define DPRINTF printf |
16b29ae1 | 38 | #else |
d0f2c4c6 | 39 | #define DPRINTF(...) |
16b29ae1 AL |
40 | #endif |
41 | ||
27bb0b2d JK |
42 | struct HPETState; |
43 | typedef struct HPETTimer { /* timers */ | |
44 | uint8_t tn; /*timer number*/ | |
45 | QEMUTimer *qemu_timer; | |
46 | struct HPETState *state; | |
47 | /* Memory-mapped, software visible timer registers */ | |
48 | uint64_t config; /* configuration/cap */ | |
49 | uint64_t cmp; /* comparator */ | |
50 | uint64_t fsb; /* FSB route, not supported now */ | |
51 | /* Hidden register state */ | |
52 | uint64_t period; /* Last value written to comparator */ | |
53 | uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit | |
54 | * mode. Next pop will be actual timer expiration. | |
55 | */ | |
56 | } HPETTimer; | |
57 | ||
58 | typedef struct HPETState { | |
822557eb | 59 | SysBusDevice busdev; |
27bb0b2d | 60 | uint64_t hpet_offset; |
822557eb | 61 | qemu_irq irqs[HPET_NUM_IRQ_ROUTES]; |
7d932dfd | 62 | uint8_t rtc_irq_level; |
be4b44c5 JK |
63 | uint8_t num_timers; |
64 | HPETTimer timer[HPET_MAX_TIMERS]; | |
27bb0b2d JK |
65 | |
66 | /* Memory-mapped, software visible registers */ | |
67 | uint64_t capability; /* capabilities */ | |
68 | uint64_t config; /* configuration */ | |
69 | uint64_t isr; /* interrupt status reg */ | |
70 | uint64_t hpet_counter; /* main counter */ | |
71 | } HPETState; | |
72 | ||
7d932dfd | 73 | static uint32_t hpet_in_legacy_mode(HPETState *s) |
16b29ae1 | 74 | { |
7d932dfd | 75 | return s->config & HPET_CFG_LEGACY; |
16b29ae1 AL |
76 | } |
77 | ||
c50c2d68 | 78 | static uint32_t timer_int_route(struct HPETTimer *timer) |
16b29ae1 | 79 | { |
27bb0b2d | 80 | return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT; |
16b29ae1 AL |
81 | } |
82 | ||
b7eaa6c7 | 83 | static uint32_t hpet_enabled(HPETState *s) |
16b29ae1 | 84 | { |
b7eaa6c7 | 85 | return s->config & HPET_CFG_ENABLE; |
16b29ae1 AL |
86 | } |
87 | ||
88 | static uint32_t timer_is_periodic(HPETTimer *t) | |
89 | { | |
90 | return t->config & HPET_TN_PERIODIC; | |
91 | } | |
92 | ||
93 | static uint32_t timer_enabled(HPETTimer *t) | |
94 | { | |
95 | return t->config & HPET_TN_ENABLE; | |
96 | } | |
97 | ||
98 | static uint32_t hpet_time_after(uint64_t a, uint64_t b) | |
99 | { | |
100 | return ((int32_t)(b) - (int32_t)(a) < 0); | |
101 | } | |
102 | ||
103 | static uint32_t hpet_time_after64(uint64_t a, uint64_t b) | |
104 | { | |
105 | return ((int64_t)(b) - (int64_t)(a) < 0); | |
106 | } | |
107 | ||
c50c2d68 | 108 | static uint64_t ticks_to_ns(uint64_t value) |
16b29ae1 AL |
109 | { |
110 | return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS)); | |
111 | } | |
112 | ||
c50c2d68 | 113 | static uint64_t ns_to_ticks(uint64_t value) |
16b29ae1 AL |
114 | { |
115 | return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD)); | |
116 | } | |
117 | ||
118 | static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask) | |
119 | { | |
120 | new &= mask; | |
121 | new |= old & ~mask; | |
122 | return new; | |
123 | } | |
124 | ||
125 | static int activating_bit(uint64_t old, uint64_t new, uint64_t mask) | |
126 | { | |
c50c2d68 | 127 | return (!(old & mask) && (new & mask)); |
16b29ae1 AL |
128 | } |
129 | ||
130 | static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask) | |
131 | { | |
c50c2d68 | 132 | return ((old & mask) && !(new & mask)); |
16b29ae1 AL |
133 | } |
134 | ||
b7eaa6c7 | 135 | static uint64_t hpet_get_ticks(HPETState *s) |
16b29ae1 | 136 | { |
b7eaa6c7 | 137 | return ns_to_ticks(qemu_get_clock(vm_clock) + s->hpet_offset); |
16b29ae1 AL |
138 | } |
139 | ||
c50c2d68 AJ |
140 | /* |
141 | * calculate diff between comparator value and current ticks | |
16b29ae1 AL |
142 | */ |
143 | static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current) | |
144 | { | |
c50c2d68 | 145 | |
16b29ae1 AL |
146 | if (t->config & HPET_TN_32BIT) { |
147 | uint32_t diff, cmp; | |
27bb0b2d | 148 | |
16b29ae1 AL |
149 | cmp = (uint32_t)t->cmp; |
150 | diff = cmp - (uint32_t)current; | |
151 | diff = (int32_t)diff > 0 ? diff : (uint32_t)0; | |
152 | return (uint64_t)diff; | |
153 | } else { | |
154 | uint64_t diff, cmp; | |
27bb0b2d | 155 | |
16b29ae1 AL |
156 | cmp = t->cmp; |
157 | diff = cmp - current; | |
158 | diff = (int64_t)diff > 0 ? diff : (uint64_t)0; | |
159 | return diff; | |
160 | } | |
161 | } | |
162 | ||
22a9fe38 | 163 | static void update_irq(struct HPETTimer *timer, int set) |
16b29ae1 | 164 | { |
22a9fe38 JK |
165 | uint64_t mask; |
166 | HPETState *s; | |
16b29ae1 AL |
167 | int route; |
168 | ||
7d932dfd | 169 | if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) { |
16b29ae1 AL |
170 | /* if LegacyReplacementRoute bit is set, HPET specification requires |
171 | * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC, | |
c50c2d68 | 172 | * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC. |
16b29ae1 | 173 | */ |
7d932dfd | 174 | route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ; |
16b29ae1 | 175 | } else { |
27bb0b2d | 176 | route = timer_int_route(timer); |
16b29ae1 | 177 | } |
22a9fe38 JK |
178 | s = timer->state; |
179 | mask = 1 << timer->tn; | |
180 | if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) { | |
181 | s->isr &= ~mask; | |
182 | qemu_irq_lower(s->irqs[route]); | |
183 | } else if (timer->config & HPET_TN_TYPE_LEVEL) { | |
184 | s->isr |= mask; | |
185 | qemu_irq_raise(s->irqs[route]); | |
186 | } else { | |
187 | s->isr &= ~mask; | |
188 | qemu_irq_pulse(s->irqs[route]); | |
16b29ae1 AL |
189 | } |
190 | } | |
191 | ||
d4bfa4d7 | 192 | static void hpet_pre_save(void *opaque) |
16b29ae1 | 193 | { |
d4bfa4d7 | 194 | HPETState *s = opaque; |
27bb0b2d | 195 | |
16b29ae1 | 196 | /* save current counter value */ |
b7eaa6c7 | 197 | s->hpet_counter = hpet_get_ticks(s); |
16b29ae1 AL |
198 | } |
199 | ||
be4b44c5 JK |
200 | static int hpet_pre_load(void *opaque) |
201 | { | |
202 | HPETState *s = opaque; | |
203 | ||
204 | /* version 1 only supports 3, later versions will load the actual value */ | |
205 | s->num_timers = HPET_MIN_TIMERS; | |
206 | return 0; | |
207 | } | |
208 | ||
e59fb374 | 209 | static int hpet_post_load(void *opaque, int version_id) |
16b29ae1 AL |
210 | { |
211 | HPETState *s = opaque; | |
c50c2d68 | 212 | |
16b29ae1 AL |
213 | /* Recalculate the offset between the main counter and guest time */ |
214 | s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock); | |
be4b44c5 JK |
215 | |
216 | /* Push number of timers into capability returned via HPET_ID */ | |
217 | s->capability &= ~HPET_ID_NUM_TIM_MASK; | |
218 | s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT; | |
16b29ae1 AL |
219 | return 0; |
220 | } | |
221 | ||
e6cb4d45 JQ |
222 | static const VMStateDescription vmstate_hpet_timer = { |
223 | .name = "hpet_timer", | |
224 | .version_id = 1, | |
225 | .minimum_version_id = 1, | |
226 | .minimum_version_id_old = 1, | |
227 | .fields = (VMStateField []) { | |
228 | VMSTATE_UINT8(tn, HPETTimer), | |
229 | VMSTATE_UINT64(config, HPETTimer), | |
230 | VMSTATE_UINT64(cmp, HPETTimer), | |
231 | VMSTATE_UINT64(fsb, HPETTimer), | |
232 | VMSTATE_UINT64(period, HPETTimer), | |
233 | VMSTATE_UINT8(wrap_flag, HPETTimer), | |
234 | VMSTATE_TIMER(qemu_timer, HPETTimer), | |
235 | VMSTATE_END_OF_LIST() | |
236 | } | |
237 | }; | |
238 | ||
239 | static const VMStateDescription vmstate_hpet = { | |
240 | .name = "hpet", | |
be4b44c5 | 241 | .version_id = 2, |
e6cb4d45 JQ |
242 | .minimum_version_id = 1, |
243 | .minimum_version_id_old = 1, | |
244 | .pre_save = hpet_pre_save, | |
be4b44c5 | 245 | .pre_load = hpet_pre_load, |
e6cb4d45 JQ |
246 | .post_load = hpet_post_load, |
247 | .fields = (VMStateField []) { | |
248 | VMSTATE_UINT64(config, HPETState), | |
249 | VMSTATE_UINT64(isr, HPETState), | |
250 | VMSTATE_UINT64(hpet_counter, HPETState), | |
be4b44c5 JK |
251 | VMSTATE_UINT8_V(num_timers, HPETState, 2), |
252 | VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0, | |
253 | vmstate_hpet_timer, HPETTimer), | |
e6cb4d45 JQ |
254 | VMSTATE_END_OF_LIST() |
255 | } | |
256 | }; | |
257 | ||
c50c2d68 | 258 | /* |
16b29ae1 AL |
259 | * timer expiration callback |
260 | */ | |
261 | static void hpet_timer(void *opaque) | |
262 | { | |
27bb0b2d | 263 | HPETTimer *t = opaque; |
16b29ae1 AL |
264 | uint64_t diff; |
265 | ||
266 | uint64_t period = t->period; | |
b7eaa6c7 | 267 | uint64_t cur_tick = hpet_get_ticks(t->state); |
16b29ae1 AL |
268 | |
269 | if (timer_is_periodic(t) && period != 0) { | |
270 | if (t->config & HPET_TN_32BIT) { | |
27bb0b2d | 271 | while (hpet_time_after(cur_tick, t->cmp)) { |
16b29ae1 | 272 | t->cmp = (uint32_t)(t->cmp + t->period); |
27bb0b2d JK |
273 | } |
274 | } else { | |
275 | while (hpet_time_after64(cur_tick, t->cmp)) { | |
16b29ae1 | 276 | t->cmp += period; |
27bb0b2d JK |
277 | } |
278 | } | |
16b29ae1 | 279 | diff = hpet_calculate_diff(t, cur_tick); |
27bb0b2d JK |
280 | qemu_mod_timer(t->qemu_timer, |
281 | qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff)); | |
16b29ae1 AL |
282 | } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { |
283 | if (t->wrap_flag) { | |
284 | diff = hpet_calculate_diff(t, cur_tick); | |
27bb0b2d JK |
285 | qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) + |
286 | (int64_t)ticks_to_ns(diff)); | |
16b29ae1 AL |
287 | t->wrap_flag = 0; |
288 | } | |
289 | } | |
22a9fe38 | 290 | update_irq(t, 1); |
16b29ae1 AL |
291 | } |
292 | ||
293 | static void hpet_set_timer(HPETTimer *t) | |
294 | { | |
295 | uint64_t diff; | |
296 | uint32_t wrap_diff; /* how many ticks until we wrap? */ | |
b7eaa6c7 | 297 | uint64_t cur_tick = hpet_get_ticks(t->state); |
c50c2d68 | 298 | |
16b29ae1 AL |
299 | /* whenever new timer is being set up, make sure wrap_flag is 0 */ |
300 | t->wrap_flag = 0; | |
301 | diff = hpet_calculate_diff(t, cur_tick); | |
302 | ||
c50c2d68 | 303 | /* hpet spec says in one-shot 32-bit mode, generate an interrupt when |
16b29ae1 | 304 | * counter wraps in addition to an interrupt with comparator match. |
c50c2d68 | 305 | */ |
16b29ae1 AL |
306 | if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { |
307 | wrap_diff = 0xffffffff - (uint32_t)cur_tick; | |
308 | if (wrap_diff < (uint32_t)diff) { | |
309 | diff = wrap_diff; | |
c50c2d68 | 310 | t->wrap_flag = 1; |
16b29ae1 AL |
311 | } |
312 | } | |
27bb0b2d JK |
313 | qemu_mod_timer(t->qemu_timer, |
314 | qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff)); | |
16b29ae1 AL |
315 | } |
316 | ||
317 | static void hpet_del_timer(HPETTimer *t) | |
318 | { | |
319 | qemu_del_timer(t->qemu_timer); | |
22a9fe38 | 320 | update_irq(t, 0); |
16b29ae1 AL |
321 | } |
322 | ||
323 | #ifdef HPET_DEBUG | |
c227f099 | 324 | static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr) |
16b29ae1 AL |
325 | { |
326 | printf("qemu: hpet_read b at %" PRIx64 "\n", addr); | |
327 | return 0; | |
328 | } | |
329 | ||
c227f099 | 330 | static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr) |
16b29ae1 AL |
331 | { |
332 | printf("qemu: hpet_read w at %" PRIx64 "\n", addr); | |
333 | return 0; | |
334 | } | |
335 | #endif | |
336 | ||
c227f099 | 337 | static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr) |
16b29ae1 | 338 | { |
27bb0b2d | 339 | HPETState *s = opaque; |
16b29ae1 AL |
340 | uint64_t cur_tick, index; |
341 | ||
d0f2c4c6 | 342 | DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr); |
16b29ae1 AL |
343 | index = addr; |
344 | /*address range of all TN regs*/ | |
345 | if (index >= 0x100 && index <= 0x3ff) { | |
346 | uint8_t timer_id = (addr - 0x100) / 0x20; | |
27bb0b2d JK |
347 | HPETTimer *timer = &s->timer[timer_id]; |
348 | ||
be4b44c5 | 349 | if (timer_id > s->num_timers) { |
6982d664 | 350 | DPRINTF("qemu: timer id out of range\n"); |
16b29ae1 AL |
351 | return 0; |
352 | } | |
16b29ae1 AL |
353 | |
354 | switch ((addr - 0x100) % 0x20) { | |
27bb0b2d JK |
355 | case HPET_TN_CFG: |
356 | return timer->config; | |
357 | case HPET_TN_CFG + 4: // Interrupt capabilities | |
358 | return timer->config >> 32; | |
359 | case HPET_TN_CMP: // comparator register | |
360 | return timer->cmp; | |
361 | case HPET_TN_CMP + 4: | |
362 | return timer->cmp >> 32; | |
363 | case HPET_TN_ROUTE: | |
364 | return timer->fsb >> 32; | |
365 | default: | |
366 | DPRINTF("qemu: invalid hpet_ram_readl\n"); | |
367 | break; | |
16b29ae1 AL |
368 | } |
369 | } else { | |
370 | switch (index) { | |
27bb0b2d JK |
371 | case HPET_ID: |
372 | return s->capability; | |
373 | case HPET_PERIOD: | |
374 | return s->capability >> 32; | |
375 | case HPET_CFG: | |
376 | return s->config; | |
377 | case HPET_CFG + 4: | |
378 | DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n"); | |
379 | return 0; | |
380 | case HPET_COUNTER: | |
b7eaa6c7 JK |
381 | if (hpet_enabled(s)) { |
382 | cur_tick = hpet_get_ticks(s); | |
27bb0b2d JK |
383 | } else { |
384 | cur_tick = s->hpet_counter; | |
385 | } | |
386 | DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick); | |
387 | return cur_tick; | |
388 | case HPET_COUNTER + 4: | |
b7eaa6c7 JK |
389 | if (hpet_enabled(s)) { |
390 | cur_tick = hpet_get_ticks(s); | |
27bb0b2d JK |
391 | } else { |
392 | cur_tick = s->hpet_counter; | |
393 | } | |
394 | DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick); | |
395 | return cur_tick >> 32; | |
396 | case HPET_STATUS: | |
397 | return s->isr; | |
398 | default: | |
399 | DPRINTF("qemu: invalid hpet_ram_readl\n"); | |
400 | break; | |
16b29ae1 AL |
401 | } |
402 | } | |
403 | return 0; | |
404 | } | |
405 | ||
406 | #ifdef HPET_DEBUG | |
c227f099 | 407 | static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr, |
16b29ae1 AL |
408 | uint32_t value) |
409 | { | |
c50c2d68 | 410 | printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n", |
16b29ae1 AL |
411 | addr, value); |
412 | } | |
413 | ||
c227f099 | 414 | static void hpet_ram_writew(void *opaque, target_phys_addr_t addr, |
16b29ae1 AL |
415 | uint32_t value) |
416 | { | |
c50c2d68 | 417 | printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n", |
16b29ae1 AL |
418 | addr, value); |
419 | } | |
420 | #endif | |
421 | ||
c227f099 | 422 | static void hpet_ram_writel(void *opaque, target_phys_addr_t addr, |
16b29ae1 AL |
423 | uint32_t value) |
424 | { | |
425 | int i; | |
27bb0b2d | 426 | HPETState *s = opaque; |
ce536cfd | 427 | uint64_t old_val, new_val, val, index; |
16b29ae1 | 428 | |
d0f2c4c6 | 429 | DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value); |
16b29ae1 AL |
430 | index = addr; |
431 | old_val = hpet_ram_readl(opaque, addr); | |
432 | new_val = value; | |
433 | ||
434 | /*address range of all TN regs*/ | |
435 | if (index >= 0x100 && index <= 0x3ff) { | |
436 | uint8_t timer_id = (addr - 0x100) / 0x20; | |
16b29ae1 | 437 | HPETTimer *timer = &s->timer[timer_id]; |
c50c2d68 | 438 | |
27bb0b2d | 439 | DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id); |
be4b44c5 | 440 | if (timer_id > s->num_timers) { |
6982d664 JK |
441 | DPRINTF("qemu: timer id out of range\n"); |
442 | return; | |
443 | } | |
16b29ae1 | 444 | switch ((addr - 0x100) % 0x20) { |
27bb0b2d JK |
445 | case HPET_TN_CFG: |
446 | DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n"); | |
447 | val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); | |
448 | timer->config = (timer->config & 0xffffffff00000000ULL) | val; | |
449 | if (new_val & HPET_TN_32BIT) { | |
450 | timer->cmp = (uint32_t)timer->cmp; | |
451 | timer->period = (uint32_t)timer->period; | |
452 | } | |
9cec89e8 JK |
453 | if (activating_bit(old_val, new_val, HPET_TN_ENABLE)) { |
454 | hpet_set_timer(timer); | |
455 | } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) { | |
456 | hpet_del_timer(timer); | |
457 | } | |
27bb0b2d JK |
458 | break; |
459 | case HPET_TN_CFG + 4: // Interrupt capabilities | |
460 | DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n"); | |
461 | break; | |
462 | case HPET_TN_CMP: // comparator register | |
463 | DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n"); | |
464 | if (timer->config & HPET_TN_32BIT) { | |
465 | new_val = (uint32_t)new_val; | |
466 | } | |
467 | if (!timer_is_periodic(timer) | |
468 | || (timer->config & HPET_TN_SETVAL)) { | |
469 | timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val; | |
470 | } | |
471 | if (timer_is_periodic(timer)) { | |
472 | /* | |
473 | * FIXME: Clamp period to reasonable min value? | |
474 | * Clamp period to reasonable max value | |
475 | */ | |
476 | new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; | |
477 | timer->period = | |
478 | (timer->period & 0xffffffff00000000ULL) | new_val; | |
479 | } | |
480 | timer->config &= ~HPET_TN_SETVAL; | |
b7eaa6c7 | 481 | if (hpet_enabled(s)) { |
27bb0b2d JK |
482 | hpet_set_timer(timer); |
483 | } | |
484 | break; | |
485 | case HPET_TN_CMP + 4: // comparator register high order | |
486 | DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n"); | |
487 | if (!timer_is_periodic(timer) | |
488 | || (timer->config & HPET_TN_SETVAL)) { | |
489 | timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32; | |
490 | } else { | |
491 | /* | |
492 | * FIXME: Clamp period to reasonable min value? | |
493 | * Clamp period to reasonable max value | |
494 | */ | |
495 | new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; | |
496 | timer->period = | |
497 | (timer->period & 0xffffffffULL) | new_val << 32; | |
16b29ae1 AL |
498 | } |
499 | timer->config &= ~HPET_TN_SETVAL; | |
b7eaa6c7 | 500 | if (hpet_enabled(s)) { |
16b29ae1 | 501 | hpet_set_timer(timer); |
16b29ae1 | 502 | } |
16b29ae1 | 503 | break; |
27bb0b2d JK |
504 | case HPET_TN_ROUTE + 4: |
505 | DPRINTF("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n"); | |
506 | break; | |
507 | default: | |
508 | DPRINTF("qemu: invalid hpet_ram_writel\n"); | |
509 | break; | |
16b29ae1 AL |
510 | } |
511 | return; | |
512 | } else { | |
513 | switch (index) { | |
27bb0b2d JK |
514 | case HPET_ID: |
515 | return; | |
516 | case HPET_CFG: | |
517 | val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); | |
518 | s->config = (s->config & 0xffffffff00000000ULL) | val; | |
519 | if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) { | |
520 | /* Enable main counter and interrupt generation. */ | |
521 | s->hpet_offset = | |
522 | ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock); | |
be4b44c5 | 523 | for (i = 0; i < s->num_timers; i++) { |
27bb0b2d JK |
524 | if ((&s->timer[i])->cmp != ~0ULL) { |
525 | hpet_set_timer(&s->timer[i]); | |
526 | } | |
16b29ae1 | 527 | } |
27bb0b2d JK |
528 | } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) { |
529 | /* Halt main counter and disable interrupt generation. */ | |
b7eaa6c7 | 530 | s->hpet_counter = hpet_get_ticks(s); |
be4b44c5 | 531 | for (i = 0; i < s->num_timers; i++) { |
27bb0b2d | 532 | hpet_del_timer(&s->timer[i]); |
16b29ae1 | 533 | } |
27bb0b2d JK |
534 | } |
535 | /* i8254 and RTC are disabled when HPET is in legacy mode */ | |
536 | if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) { | |
537 | hpet_pit_disable(); | |
7d932dfd | 538 | qemu_irq_lower(s->irqs[RTC_ISA_IRQ]); |
27bb0b2d JK |
539 | } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) { |
540 | hpet_pit_enable(); | |
7d932dfd | 541 | qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level); |
27bb0b2d JK |
542 | } |
543 | break; | |
544 | case HPET_CFG + 4: | |
545 | DPRINTF("qemu: invalid HPET_CFG+4 write \n"); | |
546 | break; | |
547 | case HPET_STATUS: | |
22a9fe38 | 548 | val = new_val & s->isr; |
be4b44c5 | 549 | for (i = 0; i < s->num_timers; i++) { |
22a9fe38 JK |
550 | if (val & (1 << i)) { |
551 | update_irq(&s->timer[i], 0); | |
552 | } | |
553 | } | |
27bb0b2d JK |
554 | break; |
555 | case HPET_COUNTER: | |
b7eaa6c7 | 556 | if (hpet_enabled(s)) { |
ad0a6551 | 557 | DPRINTF("qemu: Writing counter while HPET enabled!\n"); |
27bb0b2d JK |
558 | } |
559 | s->hpet_counter = | |
560 | (s->hpet_counter & 0xffffffff00000000ULL) | value; | |
561 | DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n", | |
562 | value, s->hpet_counter); | |
563 | break; | |
564 | case HPET_COUNTER + 4: | |
b7eaa6c7 | 565 | if (hpet_enabled(s)) { |
ad0a6551 | 566 | DPRINTF("qemu: Writing counter while HPET enabled!\n"); |
27bb0b2d JK |
567 | } |
568 | s->hpet_counter = | |
569 | (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32); | |
570 | DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n", | |
571 | value, s->hpet_counter); | |
572 | break; | |
573 | default: | |
574 | DPRINTF("qemu: invalid hpet_ram_writel\n"); | |
575 | break; | |
16b29ae1 AL |
576 | } |
577 | } | |
578 | } | |
579 | ||
d60efc6b | 580 | static CPUReadMemoryFunc * const hpet_ram_read[] = { |
16b29ae1 AL |
581 | #ifdef HPET_DEBUG |
582 | hpet_ram_readb, | |
583 | hpet_ram_readw, | |
584 | #else | |
585 | NULL, | |
586 | NULL, | |
587 | #endif | |
588 | hpet_ram_readl, | |
589 | }; | |
590 | ||
d60efc6b | 591 | static CPUWriteMemoryFunc * const hpet_ram_write[] = { |
16b29ae1 AL |
592 | #ifdef HPET_DEBUG |
593 | hpet_ram_writeb, | |
594 | hpet_ram_writew, | |
595 | #else | |
596 | NULL, | |
597 | NULL, | |
598 | #endif | |
599 | hpet_ram_writel, | |
600 | }; | |
601 | ||
822557eb | 602 | static void hpet_reset(DeviceState *d) |
27bb0b2d | 603 | { |
822557eb | 604 | HPETState *s = FROM_SYSBUS(HPETState, sysbus_from_qdev(d)); |
16b29ae1 AL |
605 | int i; |
606 | static int count = 0; | |
607 | ||
be4b44c5 | 608 | for (i = 0; i < s->num_timers; i++) { |
16b29ae1 | 609 | HPETTimer *timer = &s->timer[i]; |
27bb0b2d | 610 | |
16b29ae1 | 611 | hpet_del_timer(timer); |
16b29ae1 AL |
612 | timer->cmp = ~0ULL; |
613 | timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP; | |
ce536cfd BK |
614 | /* advertise availability of ioapic inti2 */ |
615 | timer->config |= 0x00000004ULL << 32; | |
16b29ae1 AL |
616 | timer->period = 0ULL; |
617 | timer->wrap_flag = 0; | |
618 | } | |
619 | ||
620 | s->hpet_counter = 0ULL; | |
621 | s->hpet_offset = 0ULL; | |
be4b44c5 JK |
622 | /* 64-bit main counter; LegacyReplacementRoute. */ |
623 | s->capability = 0x8086a001ULL; | |
624 | s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT; | |
16b29ae1 | 625 | s->capability |= ((HPET_CLK_PERIOD) << 32); |
7d93b1fa | 626 | s->config = 0ULL; |
27bb0b2d | 627 | if (count > 0) { |
c50c2d68 | 628 | /* we don't enable pit when hpet_reset is first called (by hpet_init) |
16b29ae1 AL |
629 | * because hpet is taking over for pit here. On subsequent invocations, |
630 | * hpet_reset is called due to system reset. At this point control must | |
c50c2d68 | 631 | * be returned to pit until SW reenables hpet. |
16b29ae1 AL |
632 | */ |
633 | hpet_pit_enable(); | |
27bb0b2d | 634 | } |
16b29ae1 AL |
635 | count = 1; |
636 | } | |
637 | ||
7d932dfd JK |
638 | static void hpet_handle_rtc_irq(void *opaque, int n, int level) |
639 | { | |
640 | HPETState *s = FROM_SYSBUS(HPETState, opaque); | |
641 | ||
642 | s->rtc_irq_level = level; | |
643 | if (!hpet_in_legacy_mode(s)) { | |
644 | qemu_set_irq(s->irqs[RTC_ISA_IRQ], level); | |
645 | } | |
646 | } | |
647 | ||
822557eb | 648 | static int hpet_init(SysBusDevice *dev) |
27bb0b2d | 649 | { |
822557eb | 650 | HPETState *s = FROM_SYSBUS(HPETState, dev); |
16b29ae1 | 651 | int i, iomemtype; |
27bb0b2d | 652 | HPETTimer *timer; |
16b29ae1 | 653 | |
822557eb JK |
654 | for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) { |
655 | sysbus_init_irq(dev, &s->irqs[i]); | |
656 | } | |
be4b44c5 JK |
657 | |
658 | if (s->num_timers < HPET_MIN_TIMERS) { | |
659 | s->num_timers = HPET_MIN_TIMERS; | |
660 | } else if (s->num_timers > HPET_MAX_TIMERS) { | |
661 | s->num_timers = HPET_MAX_TIMERS; | |
662 | } | |
663 | for (i = 0; i < HPET_MAX_TIMERS; i++) { | |
27bb0b2d | 664 | timer = &s->timer[i]; |
16b29ae1 | 665 | timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer); |
7afbecc9 JK |
666 | timer->tn = i; |
667 | timer->state = s; | |
16b29ae1 | 668 | } |
822557eb | 669 | |
7d932dfd JK |
670 | isa_reserve_irq(RTC_ISA_IRQ); |
671 | qdev_init_gpio_in(&dev->qdev, hpet_handle_rtc_irq, 1); | |
672 | ||
16b29ae1 | 673 | /* HPET Area */ |
1eed09cb | 674 | iomemtype = cpu_register_io_memory(hpet_ram_read, |
16b29ae1 | 675 | hpet_ram_write, s); |
822557eb JK |
676 | sysbus_init_mmio(dev, 0x400, iomemtype); |
677 | return 0; | |
16b29ae1 | 678 | } |
822557eb JK |
679 | |
680 | static SysBusDeviceInfo hpet_device_info = { | |
681 | .qdev.name = "hpet", | |
682 | .qdev.size = sizeof(HPETState), | |
683 | .qdev.no_user = 1, | |
684 | .qdev.vmsd = &vmstate_hpet, | |
685 | .qdev.reset = hpet_reset, | |
686 | .init = hpet_init, | |
be4b44c5 JK |
687 | .qdev.props = (Property[]) { |
688 | DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS), | |
689 | DEFINE_PROP_END_OF_LIST(), | |
690 | }, | |
822557eb JK |
691 | }; |
692 | ||
693 | static void hpet_register_device(void) | |
694 | { | |
695 | sysbus_register_withprop(&hpet_device_info); | |
696 | } | |
697 | ||
698 | device_init(hpet_register_device) |