[mirror_qemu.git] / hw / i2c / omap_i2c.c

/*
 * TI OMAP on-chip I2C controller.  Only "new I2C" mode supported.
 *
 * Copyright (C) 2007 Andrzej Zaborowski  <balrog@zabor.org>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/i2c/i2c.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/arm/omap.h"
#include "hw/sysbus.h"
#include "qemu/error-report.h"
#include "qapi/error.h"

struct OMAPI2CState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    qemu_irq irq;
    qemu_irq drq[2];
    I2CBus *bus;

    uint8_t revision;
    void *iclk;
    void *fclk;

    uint8_t mask;
    uint16_t stat;
    uint16_t dma;
    uint16_t count;
    int count_cur;
    uint32_t fifo;
    int rxlen;
    int txlen;
    uint16_t control;
    uint16_t addr[2];
    uint8_t divider;
    uint8_t times[2];
    uint16_t test;
};

#define OMAP2_INTR_REV	0x34
#define OMAP2_GC_REV	0x34

static void omap_i2c_interrupts_update(OMAPI2CState *s)
{
    qemu_set_irq(s->irq, s->stat & s->mask);
    if ((s->dma >> 15) & 1)					/* RDMA_EN */
        qemu_set_irq(s->drq[0], (s->stat >> 3) & 1);		/* RRDY */
    if ((s->dma >> 7) & 1)					/* XDMA_EN */
        qemu_set_irq(s->drq[1], (s->stat >> 4) & 1);		/* XRDY */
}

static void omap_i2c_fifo_run(OMAPI2CState *s)
{
    int ack = 1;

    if (!i2c_bus_busy(s->bus))
        return;

    if ((s->control >> 2) & 1) {				/* RM */
        if ((s->control >> 1) & 1) {				/* STP */
            i2c_end_transfer(s->bus);
            s->control &= ~(1 << 1);				/* STP */
            s->count_cur = s->count;
            s->txlen = 0;
        } else if ((s->control >> 9) & 1) {			/* TRX */
            while (ack && s->txlen)
                ack = (i2c_send(s->bus,
                                        (s->fifo >> ((-- s->txlen) << 3)) &
                                        0xff) >= 0);
            s->stat |= 1 << 4;					/* XRDY */
        } else {
            while (s->rxlen < 4)
                s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
            s->stat |= 1 << 3;					/* RRDY */
        }
    } else {
        if ((s->control >> 9) & 1) {				/* TRX */
            while (ack && s->count_cur && s->txlen) {
                ack = (i2c_send(s->bus,
                                        (s->fifo >> ((-- s->txlen) << 3)) &
                                        0xff) >= 0);
                s->count_cur --;
            }
            if (ack && s->count_cur)
                s->stat |= 1 << 4;				/* XRDY */
            else
                s->stat &= ~(1 << 4);				/* XRDY */
            if (!s->count_cur) {
                s->stat |= 1 << 2;				/* ARDY */
                s->control &= ~(1 << 10);			/* MST */
            }
        } else {
            while (s->count_cur && s->rxlen < 4) {
                s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
                s->count_cur --;
            }
            if (s->rxlen)
                s->stat |= 1 << 3;				/* RRDY */
            else
                s->stat &= ~(1 << 3);				/* RRDY */
        }
        if (!s->count_cur) {
            if ((s->control >> 1) & 1) {			/* STP */
                i2c_end_transfer(s->bus);
                s->control &= ~(1 << 1);			/* STP */
                s->count_cur = s->count;
                s->txlen = 0;
            } else {
                s->stat |= 1 << 2;				/* ARDY */
                s->control &= ~(1 << 10);			/* MST */
            }
        }
    }

    s->stat |= (!ack) << 1;					/* NACK */
    if (!ack)
        s->control &= ~(1 << 1);				/* STP */
}

static void omap_i2c_reset(DeviceState *dev)
{
    OMAPI2CState *s = OMAP_I2C(dev);

    s->mask = 0;
    s->stat = 0;
    s->dma = 0;
    s->count = 0;
    s->count_cur = 0;
    s->fifo = 0;
    s->rxlen = 0;
    s->txlen = 0;
    s->control = 0;
    s->addr[0] = 0;
    s->addr[1] = 0;
    s->divider = 0;
    s->times[0] = 0;
    s->times[1] = 0;
    s->test = 0;
}

static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
{
    OMAPI2CState *s = opaque;
    int offset = addr & OMAP_MPUI_REG_MASK;
    uint16_t ret;

    switch (offset) {
    case 0x00:	/* I2C_REV */
        return s->revision;					/* REV */

    case 0x04:	/* I2C_IE */
        return s->mask;

    case 0x08:	/* I2C_STAT */
        return s->stat | (i2c_bus_busy(s->bus) << 12);

    case 0x0c:	/* I2C_IV */
        if (s->revision >= OMAP2_INTR_REV)
            break;
        ret = ctz32(s->stat & s->mask);
        if (ret != 32) {
            s->stat ^= 1 << ret;
            ret++;
        } else {
            ret = 0;
        }
        omap_i2c_interrupts_update(s);
        return ret;

    case 0x10:	/* I2C_SYSS */
        return (s->control >> 15) & 1;				/* I2C_EN */

    case 0x14:	/* I2C_BUF */
        return s->dma;

    case 0x18:	/* I2C_CNT */
        return s->count_cur;					/* DCOUNT */

    case 0x1c:	/* I2C_DATA */
        ret = 0;
        if (s->control & (1 << 14)) {				/* BE */
            ret |= ((s->fifo >> 0) & 0xff) << 8;
            ret |= ((s->fifo >> 8) & 0xff) << 0;
        } else {
            ret |= ((s->fifo >> 8) & 0xff) << 8;
            ret |= ((s->fifo >> 0) & 0xff) << 0;
        }
        if (s->rxlen == 1) {
            s->stat |= 1 << 15;					/* SBD */
            s->rxlen = 0;
        } else if (s->rxlen > 1) {
            if (s->rxlen > 2)
                s->fifo >>= 16;
            s->rxlen -= 2;
        } else {
            /* XXX: remote access (qualifier) error - what's that?  */
        }
        if (!s->rxlen) {
            s->stat &= ~(1 << 3);				/* RRDY */
            if (((s->control >> 10) & 1) &&			/* MST */
                            ((~s->control >> 9) & 1)) {		/* TRX */
                s->stat |= 1 << 2;				/* ARDY */
                s->control &= ~(1 << 10);			/* MST */
            }
        }
        s->stat &= ~(1 << 11);					/* ROVR */
        omap_i2c_fifo_run(s);
        omap_i2c_interrupts_update(s);
        return ret;

    case 0x20:	/* I2C_SYSC */
        return 0;

    case 0x24:	/* I2C_CON */
        return s->control;

    case 0x28:	/* I2C_OA */
        return s->addr[0];

    case 0x2c:	/* I2C_SA */
        return s->addr[1];

    case 0x30:	/* I2C_PSC */
        return s->divider;

    case 0x34:	/* I2C_SCLL */
        return s->times[0];

    case 0x38:	/* I2C_SCLH */
        return s->times[1];

    case 0x3c:	/* I2C_SYSTEST */
        if (s->test & (1 << 15)) {				/* ST_EN */
            s->test ^= 0xa;
            return s->test;
        } else
            return s->test & ~0x300f;
    }

    OMAP_BAD_REG(addr);
    return 0;
}

static void omap_i2c_write(void *opaque, hwaddr addr,
                uint32_t value)
{
    OMAPI2CState *s = opaque;
    int offset = addr & OMAP_MPUI_REG_MASK;
    int nack;

    switch (offset) {
    case 0x00:	/* I2C_REV */
    case 0x0c:	/* I2C_IV */
    case 0x10:	/* I2C_SYSS */
        OMAP_RO_REG(addr);
        return;

    case 0x04:	/* I2C_IE */
        s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f);
        break;

    case 0x08:	/* I2C_STAT */
        if (s->revision < OMAP2_INTR_REV) {
            OMAP_RO_REG(addr);
            return;
        }

        /* RRDY and XRDY are reset by hardware. (in all versions???) */
        s->stat &= ~(value & 0x27);
        omap_i2c_interrupts_update(s);
        break;

    case 0x14:	/* I2C_BUF */
        s->dma = value & 0x8080;
        if (value & (1 << 15))					/* RDMA_EN */
            s->mask &= ~(1 << 3);				/* RRDY_IE */
        if (value & (1 << 7))					/* XDMA_EN */
            s->mask &= ~(1 << 4);				/* XRDY_IE */
        break;

    case 0x18:	/* I2C_CNT */
        s->count = value;					/* DCOUNT */
        break;

    case 0x1c:	/* I2C_DATA */
        if (s->txlen > 2) {
            /* XXX: remote access (qualifier) error - what's that?  */
            break;
        }
        s->fifo <<= 16;
        s->txlen += 2;
        if (s->control & (1 << 14)) {				/* BE */
            s->fifo |= ((value >> 8) & 0xff) << 8;
            s->fifo |= ((value >> 0) & 0xff) << 0;
        } else {
            s->fifo |= ((value >> 0) & 0xff) << 8;
            s->fifo |= ((value >> 8) & 0xff) << 0;
        }
        s->stat &= ~(1 << 10);					/* XUDF */
        if (s->txlen > 2)
            s->stat &= ~(1 << 4);				/* XRDY */
        omap_i2c_fifo_run(s);
        omap_i2c_interrupts_update(s);
        break;

    case 0x20:	/* I2C_SYSC */
        if (s->revision < OMAP2_INTR_REV) {
            OMAP_BAD_REG(addr);
            return;
        }

        if (value & 2) {
            omap_i2c_reset(DEVICE(s));
        }
        break;

    case 0x24:	/* I2C_CON */
        s->control = value & 0xcf87;
        if (~value & (1 << 15)) {				/* I2C_EN */
            if (s->revision < OMAP2_INTR_REV) {
                omap_i2c_reset(DEVICE(s));
            }
            break;
        }
        if ((value & (1 << 15)) && !(value & (1 << 10))) {    /* MST */
            qemu_log_mask(LOG_UNIMP, "%s: I^2C slave mode not supported\n",
                          __func__);
            break;
        }
        if ((value & (1 << 15)) && value & (1 << 8)) {        /* XA */
            qemu_log_mask(LOG_UNIMP,
                          "%s: 10-bit addressing mode not supported\n",
                          __func__);
            break;
        }
        if ((value & (1 << 15)) && value & (1 << 0)) {		/* STT */
            nack = !!i2c_start_transfer(s->bus, s->addr[1],	/* SA */
                            (~value >> 9) & 1);			/* TRX */
            s->stat |= nack << 1;				/* NACK */
            s->control &= ~(1 << 0);				/* STT */
            s->fifo = 0;
            if (nack)
                s->control &= ~(1 << 1);			/* STP */
            else {
                s->count_cur = s->count;
                omap_i2c_fifo_run(s);
            }
            omap_i2c_interrupts_update(s);
        }
        break;

    case 0x28:	/* I2C_OA */
        s->addr[0] = value & 0x3ff;
        break;

    case 0x2c:	/* I2C_SA */
        s->addr[1] = value & 0x3ff;
        break;

    case 0x30:	/* I2C_PSC */
        s->divider = value;
        break;

    case 0x34:	/* I2C_SCLL */
        s->times[0] = value;
        break;

    case 0x38:	/* I2C_SCLH */
        s->times[1] = value;
        break;

    case 0x3c:	/* I2C_SYSTEST */
        s->test = value & 0xf80f;
        if (value & (1 << 11))					/* SBB */
            if (s->revision >= OMAP2_INTR_REV) {
                s->stat |= 0x3f;
                omap_i2c_interrupts_update(s);
            }
        if (value & (1 << 15)) {                    /* ST_EN */
            qemu_log_mask(LOG_UNIMP,
                          "%s: System Test not supported\n", __func__);
        }
        break;

    default:
        OMAP_BAD_REG(addr);
        return;
    }
}

static void omap_i2c_writeb(void *opaque, hwaddr addr,
                uint32_t value)
{
    OMAPI2CState *s = opaque;
    int offset = addr & OMAP_MPUI_REG_MASK;

    switch (offset) {
    case 0x1c:	/* I2C_DATA */
        if (s->txlen > 2) {
            /* XXX: remote access (qualifier) error - what's that?  */
            break;
        }
        s->fifo <<= 8;
        s->txlen += 1;
        s->fifo |= value & 0xff;
        s->stat &= ~(1 << 10);					/* XUDF */
        if (s->txlen > 2)
            s->stat &= ~(1 << 4);				/* XRDY */
        omap_i2c_fifo_run(s);
        omap_i2c_interrupts_update(s);
        break;

    default:
        OMAP_BAD_REG(addr);
        return;
    }
}

static uint64_t omap_i2c_readfn(void *opaque, hwaddr addr,
                                unsigned size)
{
    switch (size) {
    case 2:
        return omap_i2c_read(opaque, addr);
    default:
        return omap_badwidth_read16(opaque, addr);
    }
}

static void omap_i2c_writefn(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
{
    switch (size) {
    case 1:
        /* Only the last fifo write can be 8 bit. */
        omap_i2c_writeb(opaque, addr, value);
        break;
    case 2:
        omap_i2c_write(opaque, addr, value);
        break;
    default:
        omap_badwidth_write16(opaque, addr, value);
        break;
    }
}

static const MemoryRegionOps omap_i2c_ops = {
    .read = omap_i2c_readfn,
    .write = omap_i2c_writefn,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void omap_i2c_init(Object *obj)
{
    DeviceState *dev = DEVICE(obj);
    OMAPI2CState *s = OMAP_I2C(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

    sysbus_init_irq(sbd, &s->irq);
    sysbus_init_irq(sbd, &s->drq[0]);
    sysbus_init_irq(sbd, &s->drq[1]);
    sysbus_init_mmio(sbd, &s->iomem);
    s->bus = i2c_init_bus(dev, NULL);
}

static void omap_i2c_realize(DeviceState *dev, Error **errp)
{
    OMAPI2CState *s = OMAP_I2C(dev);

    memory_region_init_io(&s->iomem, OBJECT(dev), &omap_i2c_ops, s, "omap.i2c",
                          (s->revision < OMAP2_INTR_REV) ? 0x800 : 0x1000);

    if (!s->fclk) {
        error_setg(errp, "omap_i2c: fclk not connected");
        return;
    }
    if (s->revision >= OMAP2_INTR_REV && !s->iclk) {
        /* Note that OMAP1 doesn't have a separate interface clock */
        error_setg(errp, "omap_i2c: iclk not connected");
        return;
    }
}

void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk)
{
    i2c->iclk = clk;
}

void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk)
{
    i2c->fclk = clk;
}

static Property omap_i2c_properties[] = {
    DEFINE_PROP_UINT8("revision", OMAPI2CState, revision, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void omap_i2c_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    device_class_set_props(dc, omap_i2c_properties);
    dc->reset = omap_i2c_reset;
    /* Reason: pointer properties "iclk", "fclk" */
    dc->user_creatable = false;
    dc->realize = omap_i2c_realize;
}

static const TypeInfo omap_i2c_info = {
    .name = TYPE_OMAP_I2C,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(OMAPI2CState),
    .instance_init = omap_i2c_init,
    .class_init = omap_i2c_class_init,
};

static void omap_i2c_register_types(void)
{
    type_register_static(&omap_i2c_info);
}

I2CBus *omap_i2c_bus(DeviceState *omap_i2c)
{
    OMAPI2CState *s = OMAP_I2C(omap_i2c);
    return s->bus;
}

type_init(omap_i2c_register_types)
Commit	Line	Data
02645926 AZ	1	/*
	2	* TI OMAP on-chip I2C controller. Only "new I2C" mode supported.
	3	*
	4	* Copyright (C) 2007 Andrzej Zaborowski <balrog@zabor.org>
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
fad6cb1a	16	* You should have received a copy of the GNU General Public License along
8167ee88	17	* with this program; if not, see <http://www.gnu.org/licenses/>.
02645926	18	*/
0b8fa32f	19
17b7f2db	20	#include "qemu/osdep.h"
8d2774f0	21	#include "qemu/log.h"
0b8fa32f	22	#include "qemu/module.h"
0d09e41a	23	#include "hw/i2c/i2c.h"
64552b6b	24	#include "hw/irq.h"
a27bd6c7	25	#include "hw/qdev-properties.h"
0d09e41a	26	#include "hw/arm/omap.h"
83c9f4ca	27	#include "hw/sysbus.h"
84a3a53c	28	#include "qemu/error-report.h"
758aba7d	29	#include "qapi/error.h"
02645926	30
0fd20c53	31	struct OMAPI2CState {
60ecfcb3 AF	32	SysBusDevice parent_obj;
60ecfcb3 AF	33
74878139	34	MemoryRegion iomem;
02645926 AZ	35	qemu_irq irq;
02645926 AZ	36	qemu_irq drq[2];
a5c82852	37	I2CBus *bus;
02645926	38
29885477	39	uint8_t revision;
54e17933 JR	40	void *iclk;
	41	void *fclk;
	42
02645926 AZ	43	uint8_t mask;
	44	uint16_t stat;
	45	uint16_t dma;
	46	uint16_t count;
	47	int count_cur;
	48	uint32_t fifo;
	49	int rxlen;
	50	int txlen;
	51	uint16_t control;
	52	uint16_t addr[2];
	53	uint8_t divider;
	54	uint8_t times[2];
	55	uint16_t test;
0fd20c53	56	};
02645926	57
29885477 AZ	58	#define OMAP2_INTR_REV 0x34
	59	#define OMAP2_GC_REV 0x34
	60
54e17933	61	static void omap_i2c_interrupts_update(OMAPI2CState *s)
02645926 AZ	62	{
	63	qemu_set_irq(s->irq, s->stat & s->mask);
	64	if ((s->dma >> 15) & 1) /* RDMA_EN */
	65	qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */
	66	if ((s->dma >> 7) & 1) /* XDMA_EN */
	67	qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
	68	}
	69
54e17933	70	static void omap_i2c_fifo_run(OMAPI2CState *s)
02645926 AZ	71	{
	72	int ack = 1;
	73
	74	if (!i2c_bus_busy(s->bus))
	75	return;
	76
	77	if ((s->control >> 2) & 1) { /* RM */
	78	if ((s->control >> 1) & 1) { /* STP */
	79	i2c_end_transfer(s->bus);
	80	s->control &= ~(1 << 1); /* STP */
	81	s->count_cur = s->count;
29885477	82	s->txlen = 0;
02645926 AZ	83	} else if ((s->control >> 9) & 1) { /* TRX */
	84	while (ack && s->txlen)
	85	ack = (i2c_send(s->bus,
	86	(s->fifo >> ((-- s->txlen) << 3)) &
	87	0xff) >= 0);
	88	s->stat \|= 1 << 4; /* XRDY */
	89	} else {
	90	while (s->rxlen < 4)
	91	s->fifo \|= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
	92	s->stat \|= 1 << 3; /* RRDY */
	93	}
	94	} else {
	95	if ((s->control >> 9) & 1) { /* TRX */
	96	while (ack && s->count_cur && s->txlen) {
	97	ack = (i2c_send(s->bus,
	98	(s->fifo >> ((-- s->txlen) << 3)) &
	99	0xff) >= 0);
	100	s->count_cur --;
	101	}
	102	if (ack && s->count_cur)
	103	s->stat \|= 1 << 4; /* XRDY */
827df9f3 AZ	104	else
827df9f3 AZ	105	s->stat &= ~(1 << 4); /* XRDY */
02645926 AZ	106	if (!s->count_cur) {
	107	s->stat \|= 1 << 2; /* ARDY */
	108	s->control &= ~(1 << 10); /* MST */
	109	}
	110	} else {
	111	while (s->count_cur && s->rxlen < 4) {
	112	s->fifo \|= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
	113	s->count_cur --;
	114	}
	115	if (s->rxlen)
	116	s->stat \|= 1 << 3; /* RRDY */
827df9f3 AZ	117	else
827df9f3 AZ	118	s->stat &= ~(1 << 3); /* RRDY */
02645926 AZ	119	}
	120	if (!s->count_cur) {
	121	if ((s->control >> 1) & 1) { /* STP */
	122	i2c_end_transfer(s->bus);
	123	s->control &= ~(1 << 1); /* STP */
	124	s->count_cur = s->count;
29885477	125	s->txlen = 0;
02645926 AZ	126	} else {
	127	s->stat \|= 1 << 2; /* ARDY */
	128	s->control &= ~(1 << 10); /* MST */
	129	}
	130	}
	131	}
	132
	133	s->stat \|= (!ack) << 1; /* NACK */
	134	if (!ack)
	135	s->control &= ~(1 << 1); /* STP */
	136	}
	137
54e17933	138	static void omap_i2c_reset(DeviceState *dev)
02645926	139	{
60ecfcb3 AF	140	OMAPI2CState *s = OMAP_I2C(dev);
60ecfcb3 AF	141
02645926 AZ	142	s->mask = 0;
	143	s->stat = 0;
	144	s->dma = 0;
	145	s->count = 0;
	146	s->count_cur = 0;
	147	s->fifo = 0;
	148	s->rxlen = 0;
	149	s->txlen = 0;
	150	s->control = 0;
	151	s->addr[0] = 0;
	152	s->addr[1] = 0;
	153	s->divider = 0;
	154	s->times[0] = 0;
	155	s->times[1] = 0;
	156	s->test = 0;
	157	}
	158
a8170e5e	159	static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
02645926	160	{
54e17933	161	OMAPI2CState *s = opaque;
cf965d24	162	int offset = addr & OMAP_MPUI_REG_MASK;
02645926 AZ	163	uint16_t ret;
	164
	165	switch (offset) {
	166	case 0x00: /* I2C_REV */
29885477	167	return s->revision; /* REV */
02645926 AZ	168
	169	case 0x04: /* I2C_IE */
	170	return s->mask;
	171
	172	case 0x08: /* I2C_STAT */
	173	return s->stat \| (i2c_bus_busy(s->bus) << 12);
	174
	175	case 0x0c: /* I2C_IV */
29885477 AZ	176	if (s->revision >= OMAP2_INTR_REV)
29885477 AZ	177	break;
bd2a8884 SH	178	ret = ctz32(s->stat & s->mask);
	179	if (ret != 32) {
	180	s->stat ^= 1 << ret;
	181	ret++;
	182	} else {
	183	ret = 0;
	184	}
02645926 AZ	185	omap_i2c_interrupts_update(s);
	186	return ret;
	187
29885477 AZ	188	case 0x10: /* I2C_SYSS */
	189	return (s->control >> 15) & 1; /* I2C_EN */
	190
02645926 AZ	191	case 0x14: /* I2C_BUF */
	192	return s->dma;
	193
	194	case 0x18: /* I2C_CNT */
	195	return s->count_cur; /* DCOUNT */
	196
	197	case 0x1c: /* I2C_DATA */
	198	ret = 0;
	199	if (s->control & (1 << 14)) { /* BE */
	200	ret \|= ((s->fifo >> 0) & 0xff) << 8;
	201	ret \|= ((s->fifo >> 8) & 0xff) << 0;
	202	} else {
	203	ret \|= ((s->fifo >> 8) & 0xff) << 8;
	204	ret \|= ((s->fifo >> 0) & 0xff) << 0;
	205	}
	206	if (s->rxlen == 1) {
	207	s->stat \|= 1 << 15; /* SBD */
	208	s->rxlen = 0;
	209	} else if (s->rxlen > 1) {
	210	if (s->rxlen > 2)
	211	s->fifo >>= 16;
	212	s->rxlen -= 2;
3ffd710e BS	213	} else {
	214	/* XXX: remote access (qualifier) error - what's that? */
	215	}
02645926	216	if (!s->rxlen) {
29885477	217	s->stat &= ~(1 << 3); /* RRDY */
02645926 AZ	218	if (((s->control >> 10) & 1) && /* MST */
	219	((~s->control >> 9) & 1)) { /* TRX */
	220	s->stat \|= 1 << 2; /* ARDY */
	221	s->control &= ~(1 << 10); /* MST */
	222	}
	223	}
	224	s->stat &= ~(1 << 11); /* ROVR */
	225	omap_i2c_fifo_run(s);
	226	omap_i2c_interrupts_update(s);
	227	return ret;
	228
29885477 AZ	229	case 0x20: /* I2C_SYSC */
	230	return 0;
	231
02645926 AZ	232	case 0x24: /* I2C_CON */
	233	return s->control;
	234
	235	case 0x28: /* I2C_OA */
	236	return s->addr[0];
	237
	238	case 0x2c: /* I2C_SA */
	239	return s->addr[1];
	240
	241	case 0x30: /* I2C_PSC */
	242	return s->divider;
	243
	244	case 0x34: /* I2C_SCLL */
	245	return s->times[0];
	246
	247	case 0x38: /* I2C_SCLH */
	248	return s->times[1];
	249
	250	case 0x3c: /* I2C_SYSTEST */
	251	if (s->test & (1 << 15)) { /* ST_EN */
	252	s->test ^= 0xa;
	253	return s->test;
	254	} else
	255	return s->test & ~0x300f;
	256	}
	257
	258	OMAP_BAD_REG(addr);
	259	return 0;
	260	}
	261
a8170e5e	262	static void omap_i2c_write(void *opaque, hwaddr addr,
02645926 AZ	263	uint32_t value)
02645926 AZ	264	{
54e17933	265	OMAPI2CState *s = opaque;
cf965d24	266	int offset = addr & OMAP_MPUI_REG_MASK;
02645926 AZ	267	int nack;
	268
	269	switch (offset) {
	270	case 0x00: /* I2C_REV */
02645926	271	case 0x0c: /* I2C_IV */
29885477 AZ	272	case 0x10: /* I2C_SYSS */
29885477 AZ	273	OMAP_RO_REG(addr);
02645926 AZ	274	return;
	275
	276	case 0x04: /* I2C_IE */
29885477 AZ	277	s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f);
	278	break;
	279
	280	case 0x08: /* I2C_STAT */
	281	if (s->revision < OMAP2_INTR_REV) {
	282	OMAP_RO_REG(addr);
	283	return;
	284	}
	285
827df9f3 AZ	286	/* RRDY and XRDY are reset by hardware. (in all versions???) */
827df9f3 AZ	287	s->stat &= ~(value & 0x27);
29885477	288	omap_i2c_interrupts_update(s);
02645926 AZ	289	break;
	290
	291	case 0x14: /* I2C_BUF */
	292	s->dma = value & 0x8080;
	293	if (value & (1 << 15)) /* RDMA_EN */
	294	s->mask &= ~(1 << 3); /* RRDY_IE */
	295	if (value & (1 << 7)) /* XDMA_EN */
	296	s->mask &= ~(1 << 4); /* XRDY_IE */
	297	break;
	298
	299	case 0x18: /* I2C_CNT */
	300	s->count = value; /* DCOUNT */
	301	break;
	302
	303	case 0x1c: /* I2C_DATA */
	304	if (s->txlen > 2) {
	305	/* XXX: remote access (qualifier) error - what's that? */
	306	break;
	307	}
	308	s->fifo <<= 16;
	309	s->txlen += 2;
	310	if (s->control & (1 << 14)) { /* BE */
	311	s->fifo \|= ((value >> 8) & 0xff) << 8;
	312	s->fifo \|= ((value >> 0) & 0xff) << 0;
	313	} else {
	314	s->fifo \|= ((value >> 0) & 0xff) << 8;
	315	s->fifo \|= ((value >> 8) & 0xff) << 0;
	316	}
	317	s->stat &= ~(1 << 10); /* XUDF */
	318	if (s->txlen > 2)
	319	s->stat &= ~(1 << 4); /* XRDY */
	320	omap_i2c_fifo_run(s);
	321	omap_i2c_interrupts_update(s);
	322	break;
	323
29885477 AZ	324	case 0x20: /* I2C_SYSC */
	325	if (s->revision < OMAP2_INTR_REV) {
	326	OMAP_BAD_REG(addr);
	327	return;
	328	}
	329
60ecfcb3 AF	330	if (value & 2) {
	331	omap_i2c_reset(DEVICE(s));
	332	}
29885477 AZ	333	break;
29885477 AZ	334
02645926	335	case 0x24: /* I2C_CON */
29885477	336	s->control = value & 0xcf87;
02645926	337	if (~value & (1 << 15)) { /* I2C_EN */
60ecfcb3 AF	338	if (s->revision < OMAP2_INTR_REV) {
	339	omap_i2c_reset(DEVICE(s));
	340	}
02645926 AZ	341	break;
02645926 AZ	342	}
8d2774f0 PMD	343	if ((value & (1 << 15)) && !(value & (1 << 10))) { /* MST */
	344	qemu_log_mask(LOG_UNIMP, "%s: I^2C slave mode not supported\n",
	345	__func__);
02645926 AZ	346	break;
02645926 AZ	347	}
8d2774f0 PMD	348	if ((value & (1 << 15)) && value & (1 << 8)) { /* XA */
	349	qemu_log_mask(LOG_UNIMP,
	350	"%s: 10-bit addressing mode not supported\n",
	351	__func__);
02645926 AZ	352	break;
02645926 AZ	353	}
29885477	354	if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */
02645926 AZ	355	nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */
	356	(~value >> 9) & 1); /* TRX */
	357	s->stat \|= nack << 1; /* NACK */
	358	s->control &= ~(1 << 0); /* STT */
51fec3cc	359	s->fifo = 0;
02645926 AZ	360	if (nack)
02645926 AZ	361	s->control &= ~(1 << 1); /* STP */
29885477 AZ	362	else {
29885477 AZ	363	s->count_cur = s->count;
02645926	364	omap_i2c_fifo_run(s);
29885477	365	}
02645926 AZ	366	omap_i2c_interrupts_update(s);
	367	}
	368	break;
	369
	370	case 0x28: /* I2C_OA */
	371	s->addr[0] = value & 0x3ff;
02645926 AZ	372	break;
	373
	374	case 0x2c: /* I2C_SA */
	375	s->addr[1] = value & 0x3ff;
	376	break;
	377
	378	case 0x30: /* I2C_PSC */
	379	s->divider = value;
	380	break;
	381
	382	case 0x34: /* I2C_SCLL */
	383	s->times[0] = value;
	384	break;
	385
	386	case 0x38: /* I2C_SCLH */
	387	s->times[1] = value;
	388	break;
	389
	390	case 0x3c: /* I2C_SYSTEST */
29885477 AZ	391	s->test = value & 0xf80f;
	392	if (value & (1 << 11)) /* SBB */
	393	if (s->revision >= OMAP2_INTR_REV) {
	394	s->stat \|= 0x3f;
	395	omap_i2c_interrupts_update(s);
	396	}
8d2774f0 PMD	397	if (value & (1 << 15)) { /* ST_EN */
	398	qemu_log_mask(LOG_UNIMP,
	399	"%s: System Test not supported\n", __func__);
	400	}
02645926 AZ	401	break;
	402
	403	default:
	404	OMAP_BAD_REG(addr);
	405	return;
	406	}
	407	}
	408
a8170e5e	409	static void omap_i2c_writeb(void *opaque, hwaddr addr,
29885477 AZ	410	uint32_t value)
29885477 AZ	411	{
54e17933	412	OMAPI2CState *s = opaque;
29885477 AZ	413	int offset = addr & OMAP_MPUI_REG_MASK;
	414
	415	switch (offset) {
	416	case 0x1c: /* I2C_DATA */
	417	if (s->txlen > 2) {
	418	/* XXX: remote access (qualifier) error - what's that? */
	419	break;
	420	}
	421	s->fifo <<= 8;
	422	s->txlen += 1;
	423	s->fifo \|= value & 0xff;
	424	s->stat &= ~(1 << 10); /* XUDF */
	425	if (s->txlen > 2)
	426	s->stat &= ~(1 << 4); /* XRDY */
	427	omap_i2c_fifo_run(s);
	428	omap_i2c_interrupts_update(s);
	429	break;
	430
	431	default:
	432	OMAP_BAD_REG(addr);
	433	return;
	434	}
	435	}
	436
28dc207f PM	437	static uint64_t omap_i2c_readfn(void *opaque, hwaddr addr,
	438	unsigned size)
	439	{
	440	switch (size) {
	441	case 2:
	442	return omap_i2c_read(opaque, addr);
	443	default:
	444	return omap_badwidth_read16(opaque, addr);
	445	}
	446	}
	447
	448	static void omap_i2c_writefn(void *opaque, hwaddr addr,
	449	uint64_t value, unsigned size)
	450	{
	451	switch (size) {
	452	case 1:
	453	/* Only the last fifo write can be 8 bit. */
	454	omap_i2c_writeb(opaque, addr, value);
	455	break;
	456	case 2:
	457	omap_i2c_write(opaque, addr, value);
	458	break;
	459	default:
	460	omap_badwidth_write16(opaque, addr, value);
	461	break;
	462	}
	463	}
	464
74878139	465	static const MemoryRegionOps omap_i2c_ops = {
28dc207f PM	466	.read = omap_i2c_readfn,
	467	.write = omap_i2c_writefn,
	468	.valid.min_access_size = 1,
	469	.valid.max_access_size = 4,
74878139	470	.endianness = DEVICE_NATIVE_ENDIAN,
02645926 AZ	471	};
02645926 AZ	472
758aba7d XZ	473	static void omap_i2c_init(Object *obj)
	474	{
	475	DeviceState *dev = DEVICE(obj);
	476	OMAPI2CState *s = OMAP_I2C(obj);
	477	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	478
	479	sysbus_init_irq(sbd, &s->irq);
	480	sysbus_init_irq(sbd, &s->drq[0]);
	481	sysbus_init_irq(sbd, &s->drq[1]);
	482	sysbus_init_mmio(sbd, &s->iomem);
	483	s->bus = i2c_init_bus(dev, NULL);
	484	}
	485
	486	static void omap_i2c_realize(DeviceState dev, Error *errp)
02645926	487	{
60ecfcb3	488	OMAPI2CState *s = OMAP_I2C(dev);
02645926	489
758aba7d XZ	490	memory_region_init_io(&s->iomem, OBJECT(dev), &omap_i2c_ops, s, "omap.i2c",
	491	(s->revision < OMAP2_INTR_REV) ? 0x800 : 0x1000);
	492
54e17933	493	if (!s->fclk) {
758aba7d XZ	494	error_setg(errp, "omap_i2c: fclk not connected");
758aba7d XZ	495	return;
54e17933 JR	496	}
	497	if (s->revision >= OMAP2_INTR_REV && !s->iclk) {
	498	/* Note that OMAP1 doesn't have a separate interface clock */
758aba7d XZ	499	error_setg(errp, "omap_i2c: iclk not connected");
758aba7d XZ	500	return;
54e17933	501	}
02645926 AZ	502	}
02645926 AZ	503
0fd20c53 MAL	504	void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk)
	505	{
	506	i2c->iclk = clk;
	507	}
	508
	509	void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk)
	510	{
	511	i2c->fclk = clk;
	512	}
	513
54e17933 JR	514	static Property omap_i2c_properties[] = {
54e17933 JR	515	DEFINE_PROP_UINT8("revision", OMAPI2CState, revision, 0),
54e17933 JR	516	DEFINE_PROP_END_OF_LIST(),
54e17933 JR	517	};
29885477	518
54e17933 JR	519	static void omap_i2c_class_init(ObjectClass klass, void data)
	520	{
	521	DeviceClass *dc = DEVICE_CLASS(klass);
758aba7d	522
4f67d30b	523	device_class_set_props(dc, omap_i2c_properties);
54e17933	524	dc->reset = omap_i2c_reset;
1b111dc1	525	/* Reason: pointer properties "iclk", "fclk" */
e90f2a8c	526	dc->user_creatable = false;
758aba7d	527	dc->realize = omap_i2c_realize;
54e17933	528	}
29885477	529
8c43a6f0	530	static const TypeInfo omap_i2c_info = {
60ecfcb3	531	.name = TYPE_OMAP_I2C,
54e17933 JR	532	.parent = TYPE_SYS_BUS_DEVICE,
54e17933 JR	533	.instance_size = sizeof(OMAPI2CState),
758aba7d	534	.instance_init = omap_i2c_init,
54e17933 JR	535	.class_init = omap_i2c_class_init,
54e17933 JR	536	};
29885477	537
54e17933 JR	538	static void omap_i2c_register_types(void)
	539	{
	540	type_register_static(&omap_i2c_info);
29885477 AZ	541	}
29885477 AZ	542
a5c82852	543	I2CBus omap_i2c_bus(DeviceState omap_i2c)
02645926	544	{
60ecfcb3	545	OMAPI2CState *s = OMAP_I2C(omap_i2c);
02645926 AZ	546	return s->bus;
02645926 AZ	547	}
54e17933 JR	548
54e17933 JR	549	type_init(omap_i2c_register_types)