[mirror_qemu.git] / hw / ide / pci.c

/*
 * QEMU IDE Emulation: PCI Bus support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <hw/hw.h>
#include <hw/i386/pc.h>
#include <hw/pci/pci.h>
#include <hw/isa/isa.h>
#include "block/block.h"
#include "sysemu/dma.h"

#include <hw/ide/pci.h>

#define BMDMA_PAGE_SIZE 4096

static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
                            BlockDriverCompletionFunc *dma_cb)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);

    bm->unit = s->unit;
    bm->dma_cb = dma_cb;
    bm->cur_prd_last = 0;
    bm->cur_prd_addr = 0;
    bm->cur_prd_len = 0;
    bm->sector_num = ide_get_sector(s);
    bm->nsector = s->nsector;

    if (bm->status & BM_STATUS_DMAING) {
        bm->dma_cb(bmdma_active_if(bm), 0);
    }
}

/* return 0 if buffer completed */
static int bmdma_prepare_buf(IDEDMA *dma, int is_write)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
    IDEState *s = bmdma_active_if(bm);
    PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
    struct {
        uint32_t addr;
        uint32_t size;
    } prd;
    int l, len;

    pci_dma_sglist_init(&s->sg, pci_dev,
                        s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
    s->io_buffer_size = 0;
    for(;;) {
        if (bm->cur_prd_len == 0) {
            /* end of table (with a fail safe of one page) */
            if (bm->cur_prd_last ||
                (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
                return s->io_buffer_size != 0;
            pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
            bm->cur_addr += 8;
            prd.addr = le32_to_cpu(prd.addr);
            prd.size = le32_to_cpu(prd.size);
            len = prd.size & 0xfffe;
            if (len == 0)
                len = 0x10000;
            bm->cur_prd_len = len;
            bm->cur_prd_addr = prd.addr;
            bm->cur_prd_last = (prd.size & 0x80000000);
        }
        l = bm->cur_prd_len;
        if (l > 0) {
            qemu_sglist_add(&s->sg, bm->cur_prd_addr, l);
            bm->cur_prd_addr += l;
            bm->cur_prd_len -= l;
            s->io_buffer_size += l;
        }
    }
    return 1;
}

/* return 0 if buffer completed */
static int bmdma_rw_buf(IDEDMA *dma, int is_write)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
    IDEState *s = bmdma_active_if(bm);
    PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
    struct {
        uint32_t addr;
        uint32_t size;
    } prd;
    int l, len;

    for(;;) {
        l = s->io_buffer_size - s->io_buffer_index;
        if (l <= 0)
            break;
        if (bm->cur_prd_len == 0) {
            /* end of table (with a fail safe of one page) */
            if (bm->cur_prd_last ||
                (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
                return 0;
            pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
            bm->cur_addr += 8;
            prd.addr = le32_to_cpu(prd.addr);
            prd.size = le32_to_cpu(prd.size);
            len = prd.size & 0xfffe;
            if (len == 0)
                len = 0x10000;
            bm->cur_prd_len = len;
            bm->cur_prd_addr = prd.addr;
            bm->cur_prd_last = (prd.size & 0x80000000);
        }
        if (l > bm->cur_prd_len)
            l = bm->cur_prd_len;
        if (l > 0) {
            if (is_write) {
                pci_dma_write(pci_dev, bm->cur_prd_addr,
                              s->io_buffer + s->io_buffer_index, l);
            } else {
                pci_dma_read(pci_dev, bm->cur_prd_addr,
                             s->io_buffer + s->io_buffer_index, l);
            }
            bm->cur_prd_addr += l;
            bm->cur_prd_len -= l;
            s->io_buffer_index += l;
        }
    }
    return 1;
}

static int bmdma_set_unit(IDEDMA *dma, int unit)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
    bm->unit = unit;

    return 0;
}

static int bmdma_add_status(IDEDMA *dma, int status)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
    bm->status |= status;

    return 0;
}

static void bmdma_set_inactive(IDEDMA *dma)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);

    bm->status &= ~BM_STATUS_DMAING;
    bm->dma_cb = NULL;
    bm->unit = -1;
}

static void bmdma_restart_dma(BMDMAState *bm, enum ide_dma_cmd dma_cmd)
{
    IDEState *s = bmdma_active_if(bm);

    ide_set_sector(s, bm->sector_num);
    s->io_buffer_index = 0;
    s->io_buffer_size = 0;
    s->nsector = bm->nsector;
    s->dma_cmd = dma_cmd;
    bm->cur_addr = bm->addr;
    bm->dma_cb = ide_dma_cb;
    bmdma_start_dma(&bm->dma, s, bm->dma_cb);
}

/* TODO This should be common IDE code */
static void bmdma_restart_bh(void *opaque)
{
    BMDMAState *bm = opaque;
    IDEBus *bus = bm->bus;
    bool is_read;
    int error_status;

    qemu_bh_delete(bm->bh);
    bm->bh = NULL;

    if (bm->unit == (uint8_t) -1) {
        return;
    }

    is_read = (bus->error_status & BM_STATUS_RETRY_READ) != 0;

    /* The error status must be cleared before resubmitting the request: The
     * request may fail again, and this case can only be distinguished if the
     * called function can set a new error status. */
    error_status = bus->error_status;
    bus->error_status = 0;

    if (error_status & BM_STATUS_DMA_RETRY) {
        if (error_status & BM_STATUS_RETRY_TRIM) {
            bmdma_restart_dma(bm, IDE_DMA_TRIM);
        } else {
            bmdma_restart_dma(bm, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
        }
    } else if (error_status & BM_STATUS_PIO_RETRY) {
        if (is_read) {
            ide_sector_read(bmdma_active_if(bm));
        } else {
            ide_sector_write(bmdma_active_if(bm));
        }
    } else if (error_status & BM_STATUS_RETRY_FLUSH) {
        ide_flush_cache(bmdma_active_if(bm));
    }
}

static void bmdma_restart_cb(void *opaque, int running, RunState state)
{
    IDEDMA *dma = opaque;
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);

    if (!running)
        return;

    if (!bm->bh) {
        bm->bh = qemu_bh_new(bmdma_restart_bh, &bm->dma);
        qemu_bh_schedule(bm->bh);
    }
}

static void bmdma_cancel(BMDMAState *bm)
{
    if (bm->status & BM_STATUS_DMAING) {
        /* cancel DMA request */
        bmdma_set_inactive(&bm->dma);
    }
}

static void bmdma_reset(IDEDMA *dma)
{
    BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);

#ifdef DEBUG_IDE
    printf("ide: dma_reset\n");
#endif
    bmdma_cancel(bm);
    bm->cmd = 0;
    bm->status = 0;
    bm->addr = 0;
    bm->cur_addr = 0;
    bm->cur_prd_last = 0;
    bm->cur_prd_addr = 0;
    bm->cur_prd_len = 0;
    bm->sector_num = 0;
    bm->nsector = 0;
}

static void bmdma_irq(void *opaque, int n, int level)
{
    BMDMAState *bm = opaque;

    if (!level) {
        /* pass through lower */
        qemu_set_irq(bm->irq, level);
        return;
    }

    bm->status |= BM_STATUS_INT;

    /* trigger the real irq */
    qemu_set_irq(bm->irq, level);
}

void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
{
#ifdef DEBUG_IDE
    printf("%s: 0x%08x\n", __func__, val);
#endif

    /* Ignore writes to SSBM if it keeps the old value */
    if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
        if (!(val & BM_CMD_START)) {
            /*
             * We can't cancel Scatter Gather DMA in the middle of the
             * operation or a partial (not full) DMA transfer would reach
             * the storage so we wait for completion instead (we beahve
             * like if the DMA was completed by the time the guest trying
             * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
             * set).
             *
             * In the future we'll be able to safely cancel the I/O if the
             * whole DMA operation will be submitted to disk with a single
             * aio operation with preadv/pwritev.
             */
            if (bm->bus->dma->aiocb) {
                bdrv_drain_all();
                assert(bm->bus->dma->aiocb == NULL);
            }
            bm->status &= ~BM_STATUS_DMAING;
        } else {
            bm->cur_addr = bm->addr;
            if (!(bm->status & BM_STATUS_DMAING)) {
                bm->status |= BM_STATUS_DMAING;
                /* start dma transfer if possible */
                if (bm->dma_cb)
                    bm->dma_cb(bmdma_active_if(bm), 0);
            }
        }
    }

    bm->cmd = val & 0x09;
}

static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
                                unsigned width)
{
    BMDMAState *bm = opaque;
    uint32_t mask = (1ULL << (width * 8)) - 1;
    uint64_t data;

    data = (bm->addr >> (addr * 8)) & mask;
#ifdef DEBUG_IDE
    printf("%s: 0x%08x\n", __func__, (unsigned)data);
#endif
    return data;
}

static void bmdma_addr_write(void *opaque, hwaddr addr,
                             uint64_t data, unsigned width)
{
    BMDMAState *bm = opaque;
    int shift = addr * 8;
    uint32_t mask = (1ULL << (width * 8)) - 1;

#ifdef DEBUG_IDE
    printf("%s: 0x%08x\n", __func__, (unsigned)data);
#endif
    bm->addr &= ~(mask << shift);
    bm->addr |= ((data & mask) << shift) & ~3;
}

MemoryRegionOps bmdma_addr_ioport_ops = {
    .read = bmdma_addr_read,
    .write = bmdma_addr_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static bool ide_bmdma_current_needed(void *opaque)
{
    BMDMAState *bm = opaque;

    return (bm->cur_prd_len != 0);
}

static bool ide_bmdma_status_needed(void *opaque)
{
    BMDMAState *bm = opaque;

    /* Older versions abused some bits in the status register for internal
     * error state. If any of these bits are set, we must add a subsection to
     * transfer the real status register */
    uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;

    return ((bm->status & abused_bits) != 0);
}

static void ide_bmdma_pre_save(void *opaque)
{
    BMDMAState *bm = opaque;
    uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;

    bm->migration_compat_status =
        (bm->status & ~abused_bits) | (bm->bus->error_status & abused_bits);
}

/* This function accesses bm->bus->error_status which is loaded only after
 * BMDMA itself. This is why the function is called from ide_pci_post_load
 * instead of being registered with VMState where it would run too early. */
static int ide_bmdma_post_load(void *opaque, int version_id)
{
    BMDMAState *bm = opaque;
    uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;

    if (bm->status == 0) {
        bm->status = bm->migration_compat_status & ~abused_bits;
        bm->bus->error_status |= bm->migration_compat_status & abused_bits;
    }

    return 0;
}

static const VMStateDescription vmstate_bmdma_current = {
    .name = "ide bmdma_current",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(cur_addr, BMDMAState),
        VMSTATE_UINT32(cur_prd_last, BMDMAState),
        VMSTATE_UINT32(cur_prd_addr, BMDMAState),
        VMSTATE_UINT32(cur_prd_len, BMDMAState),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_bmdma_status = {
    .name ="ide bmdma/status",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(status, BMDMAState),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_bmdma = {
    .name = "ide bmdma",
    .version_id = 3,
    .minimum_version_id = 0,
    .pre_save  = ide_bmdma_pre_save,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(cmd, BMDMAState),
        VMSTATE_UINT8(migration_compat_status, BMDMAState),
        VMSTATE_UINT32(addr, BMDMAState),
        VMSTATE_INT64(sector_num, BMDMAState),
        VMSTATE_UINT32(nsector, BMDMAState),
        VMSTATE_UINT8(unit, BMDMAState),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (VMStateSubsection []) {
        {
            .vmsd = &vmstate_bmdma_current,
            .needed = ide_bmdma_current_needed,
        }, {
            .vmsd = &vmstate_bmdma_status,
            .needed = ide_bmdma_status_needed,
        }, {
            /* empty */
        }
    }
};

static int ide_pci_post_load(void *opaque, int version_id)
{
    PCIIDEState *d = opaque;
    int i;

    for(i = 0; i < 2; i++) {
        /* current versions always store 0/1, but older version
           stored bigger values. We only need last bit */
        d->bmdma[i].unit &= 1;
        ide_bmdma_post_load(&d->bmdma[i], -1);
    }

    return 0;
}

const VMStateDescription vmstate_ide_pci = {
    .name = "ide",
    .version_id = 3,
    .minimum_version_id = 0,
    .post_load = ide_pci_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(parent_obj, PCIIDEState),
        VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
                             vmstate_bmdma, BMDMAState),
        VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
        VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
        VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
        VMSTATE_END_OF_LIST()
    }
};

void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
{
    PCIIDEState *d = PCI_IDE(dev);
    static const int bus[4]  = { 0, 0, 1, 1 };
    static const int unit[4] = { 0, 1, 0, 1 };
    int i;

    for (i = 0; i < 4; i++) {
        if (hd_table[i] == NULL)
            continue;
        ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
    }
}

static const struct IDEDMAOps bmdma_ops = {
    .start_dma = bmdma_start_dma,
    .prepare_buf = bmdma_prepare_buf,
    .rw_buf = bmdma_rw_buf,
    .set_unit = bmdma_set_unit,
    .add_status = bmdma_add_status,
    .set_inactive = bmdma_set_inactive,
    .restart_cb = bmdma_restart_cb,
    .reset = bmdma_reset,
};

void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
{
    qemu_irq *irq;

    if (bus->dma == &bm->dma) {
        return;
    }

    bm->dma.ops = &bmdma_ops;
    bus->dma = &bm->dma;
    bm->irq = bus->irq;
    irq = qemu_allocate_irqs(bmdma_irq, bm, 1);
    bus->irq = *irq;
    bm->pci_dev = d;
}

static const TypeInfo pci_ide_type_info = {
    .name = TYPE_PCI_IDE,
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIIDEState),
    .abstract = true,
};

static void pci_ide_register_types(void)
{
    type_register_static(&pci_ide_type_info);
}

type_init(pci_ide_register_types)
Commit	Line	Data
977e1244 GH	1	/*
	2	* QEMU IDE Emulation: PCI Bus support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
59f2a787	25	#include <hw/hw.h>
0d09e41a	26	#include <hw/i386/pc.h>
a2cb15b0	27	#include <hw/pci/pci.h>
0d09e41a	28	#include <hw/isa/isa.h>
737e150e	29	#include "block/block.h"
9c17d615	30	#include "sysemu/dma.h"
59f2a787	31
65c0f135	32	#include <hw/ide/pci.h>
977e1244	33
40a6238a AG	34	#define BMDMA_PAGE_SIZE 4096
	35
	36	static void bmdma_start_dma(IDEDMA dma, IDEState s,
	37	BlockDriverCompletionFunc *dma_cb)
	38	{
	39	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	40
	41	bm->unit = s->unit;
	42	bm->dma_cb = dma_cb;
	43	bm->cur_prd_last = 0;
	44	bm->cur_prd_addr = 0;
	45	bm->cur_prd_len = 0;
	46	bm->sector_num = ide_get_sector(s);
	47	bm->nsector = s->nsector;
	48
	49	if (bm->status & BM_STATUS_DMAING) {
	50	bm->dma_cb(bmdma_active_if(bm), 0);
	51	}
	52	}
	53
	54	/* return 0 if buffer completed */
	55	static int bmdma_prepare_buf(IDEDMA *dma, int is_write)
	56	{
	57	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	58	IDEState *s = bmdma_active_if(bm);
f6c11d56	59	PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
40a6238a AG	60	struct {
	61	uint32_t addr;
	62	uint32_t size;
	63	} prd;
	64	int l, len;
	65
f6c11d56	66	pci_dma_sglist_init(&s->sg, pci_dev,
552908fe	67	s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
40a6238a AG	68	s->io_buffer_size = 0;
	69	for(;;) {
	70	if (bm->cur_prd_len == 0) {
	71	/* end of table (with a fail safe of one page) */
	72	if (bm->cur_prd_last \|\|
	73	(bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
	74	return s->io_buffer_size != 0;
f6c11d56	75	pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
40a6238a AG	76	bm->cur_addr += 8;
	77	prd.addr = le32_to_cpu(prd.addr);
	78	prd.size = le32_to_cpu(prd.size);
	79	len = prd.size & 0xfffe;
	80	if (len == 0)
	81	len = 0x10000;
	82	bm->cur_prd_len = len;
	83	bm->cur_prd_addr = prd.addr;
	84	bm->cur_prd_last = (prd.size & 0x80000000);
	85	}
	86	l = bm->cur_prd_len;
	87	if (l > 0) {
	88	qemu_sglist_add(&s->sg, bm->cur_prd_addr, l);
	89	bm->cur_prd_addr += l;
	90	bm->cur_prd_len -= l;
	91	s->io_buffer_size += l;
	92	}
	93	}
	94	return 1;
	95	}
	96
	97	/* return 0 if buffer completed */
	98	static int bmdma_rw_buf(IDEDMA *dma, int is_write)
	99	{
	100	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	101	IDEState *s = bmdma_active_if(bm);
f6c11d56	102	PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
40a6238a AG	103	struct {
	104	uint32_t addr;
	105	uint32_t size;
	106	} prd;
	107	int l, len;
	108
	109	for(;;) {
	110	l = s->io_buffer_size - s->io_buffer_index;
	111	if (l <= 0)
	112	break;
	113	if (bm->cur_prd_len == 0) {
	114	/* end of table (with a fail safe of one page) */
	115	if (bm->cur_prd_last \|\|
	116	(bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
	117	return 0;
f6c11d56	118	pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
40a6238a AG	119	bm->cur_addr += 8;
	120	prd.addr = le32_to_cpu(prd.addr);
	121	prd.size = le32_to_cpu(prd.size);
	122	len = prd.size & 0xfffe;
	123	if (len == 0)
	124	len = 0x10000;
	125	bm->cur_prd_len = len;
	126	bm->cur_prd_addr = prd.addr;
	127	bm->cur_prd_last = (prd.size & 0x80000000);
	128	}
	129	if (l > bm->cur_prd_len)
	130	l = bm->cur_prd_len;
	131	if (l > 0) {
	132	if (is_write) {
f6c11d56	133	pci_dma_write(pci_dev, bm->cur_prd_addr,
552908fe	134	s->io_buffer + s->io_buffer_index, l);
40a6238a	135	} else {
f6c11d56	136	pci_dma_read(pci_dev, bm->cur_prd_addr,
552908fe	137	s->io_buffer + s->io_buffer_index, l);
40a6238a AG	138	}
	139	bm->cur_prd_addr += l;
	140	bm->cur_prd_len -= l;
	141	s->io_buffer_index += l;
	142	}
	143	}
	144	return 1;
	145	}
	146
	147	static int bmdma_set_unit(IDEDMA *dma, int unit)
	148	{
	149	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	150	bm->unit = unit;
	151
	152	return 0;
	153	}
	154
	155	static int bmdma_add_status(IDEDMA *dma, int status)
	156	{
	157	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	158	bm->status \|= status;
	159
	160	return 0;
	161	}
	162
829b933b	163	static void bmdma_set_inactive(IDEDMA *dma)
40a6238a AG	164	{
	165	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	166
	167	bm->status &= ~BM_STATUS_DMAING;
	168	bm->dma_cb = NULL;
	169	bm->unit = -1;
40a6238a AG	170	}
40a6238a AG	171
4e1e0051	172	static void bmdma_restart_dma(BMDMAState *bm, enum ide_dma_cmd dma_cmd)
40a6238a AG	173	{
	174	IDEState *s = bmdma_active_if(bm);
	175
	176	ide_set_sector(s, bm->sector_num);
	177	s->io_buffer_index = 0;
	178	s->io_buffer_size = 0;
	179	s->nsector = bm->nsector;
4e1e0051	180	s->dma_cmd = dma_cmd;
40a6238a	181	bm->cur_addr = bm->addr;
cd369c46	182	bm->dma_cb = ide_dma_cb;
40a6238a AG	183	bmdma_start_dma(&bm->dma, s, bm->dma_cb);
	184	}
	185
def93791	186	/* TODO This should be common IDE code */
40a6238a AG	187	static void bmdma_restart_bh(void *opaque)
	188	{
	189	BMDMAState *bm = opaque;
def93791	190	IDEBus *bus = bm->bus;
1ceee0d5	191	bool is_read;
ee752da7	192	int error_status;
40a6238a AG	193
	194	qemu_bh_delete(bm->bh);
	195	bm->bh = NULL;
	196
def93791 KW	197	if (bm->unit == (uint8_t) -1) {
	198	return;
	199	}
40a6238a	200
1ceee0d5	201	is_read = (bus->error_status & BM_STATUS_RETRY_READ) != 0;
def93791	202
ee752da7 KW	203	/* The error status must be cleared before resubmitting the request: The
	204	* request may fail again, and this case can only be distinguished if the
	205	* called function can set a new error status. */
	206	error_status = bus->error_status;
	207	bus->error_status = 0;
	208
	209	if (error_status & BM_STATUS_DMA_RETRY) {
	210	if (error_status & BM_STATUS_RETRY_TRIM) {
d353fb72 CH	211	bmdma_restart_dma(bm, IDE_DMA_TRIM);
d353fb72 CH	212	} else {
d353fb72 CH	213	bmdma_restart_dma(bm, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
d353fb72 CH	214	}
ee752da7	215	} else if (error_status & BM_STATUS_PIO_RETRY) {
40a6238a AG	216	if (is_read) {
	217	ide_sector_read(bmdma_active_if(bm));
	218	} else {
	219	ide_sector_write(bmdma_active_if(bm));
	220	}
ee752da7	221	} else if (error_status & BM_STATUS_RETRY_FLUSH) {
40a6238a AG	222	ide_flush_cache(bmdma_active_if(bm));
	223	}
	224	}
	225
1dfb4dd9	226	static void bmdma_restart_cb(void *opaque, int running, RunState state)
40a6238a AG	227	{
	228	IDEDMA *dma = opaque;
	229	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	230
	231	if (!running)
	232	return;
	233
	234	if (!bm->bh) {
	235	bm->bh = qemu_bh_new(bmdma_restart_bh, &bm->dma);
	236	qemu_bh_schedule(bm->bh);
	237	}
	238	}
	239
	240	static void bmdma_cancel(BMDMAState *bm)
	241	{
	242	if (bm->status & BM_STATUS_DMAING) {
	243	/* cancel DMA request */
	244	bmdma_set_inactive(&bm->dma);
	245	}
	246	}
	247
1374bec0	248	static void bmdma_reset(IDEDMA *dma)
40a6238a AG	249	{
	250	BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
	251
	252	#ifdef DEBUG_IDE
	253	printf("ide: dma_reset\n");
	254	#endif
	255	bmdma_cancel(bm);
	256	bm->cmd = 0;
	257	bm->status = 0;
	258	bm->addr = 0;
	259	bm->cur_addr = 0;
	260	bm->cur_prd_last = 0;
	261	bm->cur_prd_addr = 0;
	262	bm->cur_prd_len = 0;
	263	bm->sector_num = 0;
	264	bm->nsector = 0;
40a6238a AG	265	}
40a6238a AG	266
40a6238a AG	267	static void bmdma_irq(void *opaque, int n, int level)
	268	{
	269	BMDMAState *bm = opaque;
	270
	271	if (!level) {
	272	/* pass through lower */
	273	qemu_set_irq(bm->irq, level);
	274	return;
	275	}
	276
1635eecc	277	bm->status \|= BM_STATUS_INT;
40a6238a AG	278
	279	/* trigger the real irq */
	280	qemu_set_irq(bm->irq, level);
	281	}
	282
a9deb8c6	283	void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
977e1244	284	{
977e1244 GH	285	#ifdef DEBUG_IDE
	286	printf("%s: 0x%08x\n", __func__, val);
	287	#endif
c29947bb KW	288
	289	/* Ignore writes to SSBM if it keeps the old value */
	290	if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
	291	if (!(val & BM_CMD_START)) {
	292	/*
	293	* We can't cancel Scatter Gather DMA in the middle of the
	294	* operation or a partial (not full) DMA transfer would reach
	295	* the storage so we wait for completion instead (we beahve
	296	* like if the DMA was completed by the time the guest trying
	297	* to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
	298	* set).
	299	*
	300	* In the future we'll be able to safely cancel the I/O if the
	301	* whole DMA operation will be submitted to disk with a single
	302	* aio operation with preadv/pwritev.
	303	*/
40a6238a	304	if (bm->bus->dma->aiocb) {
922453bc	305	bdrv_drain_all();
2860e3eb	306	assert(bm->bus->dma->aiocb == NULL);
c29947bb	307	}
b39f9612	308	bm->status &= ~BM_STATUS_DMAING;
c29947bb	309	} else {
b76876e6	310	bm->cur_addr = bm->addr;
c29947bb KW	311	if (!(bm->status & BM_STATUS_DMAING)) {
	312	bm->status \|= BM_STATUS_DMAING;
	313	/* start dma transfer if possible */
	314	if (bm->dma_cb)
40a6238a	315	bm->dma_cb(bmdma_active_if(bm), 0);
c29947bb	316	}
953844d1	317	}
977e1244	318	}
c29947bb KW	319
c29947bb KW	320	bm->cmd = val & 0x09;
977e1244 GH	321	}
977e1244 GH	322
a8170e5e	323	static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
a9deb8c6	324	unsigned width)
977e1244	325	{
a9deb8c6	326	BMDMAState *bm = opaque;
9fbef1ac	327	uint32_t mask = (1ULL << (width * 8)) - 1;
a9deb8c6	328	uint64_t data;
977e1244	329
a9deb8c6	330	data = (bm->addr >> (addr * 8)) & mask;
977e1244	331	#ifdef DEBUG_IDE
cb67be85	332	printf("%s: 0x%08x\n", __func__, (unsigned)data);
977e1244	333	#endif
a9deb8c6	334	return data;
977e1244 GH	335	}
977e1244 GH	336
a8170e5e	337	static void bmdma_addr_write(void *opaque, hwaddr addr,
a9deb8c6	338	uint64_t data, unsigned width)
977e1244	339	{
a9deb8c6	340	BMDMAState *bm = opaque;
9fbef1ac AK	341	int shift = addr * 8;
9fbef1ac AK	342	uint32_t mask = (1ULL << (width * 8)) - 1;
977e1244	343
977e1244	344	#ifdef DEBUG_IDE
9fbef1ac	345	printf("%s: 0x%08x\n", __func__, (unsigned)data);
977e1244	346	#endif
9fbef1ac AK	347	bm->addr &= ~(mask << shift);
9fbef1ac AK	348	bm->addr \|= ((data & mask) << shift) & ~3;
977e1244 GH	349	}
977e1244 GH	350
a9deb8c6	351	MemoryRegionOps bmdma_addr_ioport_ops = {
9fbef1ac AK	352	.read = bmdma_addr_read,
9fbef1ac AK	353	.write = bmdma_addr_write,
a9deb8c6	354	.endianness = DEVICE_LITTLE_ENDIAN,
9fbef1ac	355	};
977e1244	356
5ee84c33 JQ	357	static bool ide_bmdma_current_needed(void *opaque)
	358	{
	359	BMDMAState *bm = opaque;
	360
	361	return (bm->cur_prd_len != 0);
	362	}
	363
def93791 KW	364	static bool ide_bmdma_status_needed(void *opaque)
	365	{
	366	BMDMAState *bm = opaque;
	367
	368	/* Older versions abused some bits in the status register for internal
	369	* error state. If any of these bits are set, we must add a subsection to
	370	* transfer the real status register */
	371	uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
	372
	373	return ((bm->status & abused_bits) != 0);
	374	}
	375
	376	static void ide_bmdma_pre_save(void *opaque)
	377	{
	378	BMDMAState *bm = opaque;
	379	uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
	380
	381	bm->migration_compat_status =
	382	(bm->status & ~abused_bits) \| (bm->bus->error_status & abused_bits);
	383	}
	384
	385	/* This function accesses bm->bus->error_status which is loaded only after
	386	* BMDMA itself. This is why the function is called from ide_pci_post_load
	387	* instead of being registered with VMState where it would run too early. */
	388	static int ide_bmdma_post_load(void *opaque, int version_id)
	389	{
	390	BMDMAState *bm = opaque;
	391	uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
	392
	393	if (bm->status == 0) {
	394	bm->status = bm->migration_compat_status & ~abused_bits;
	395	bm->bus->error_status \|= bm->migration_compat_status & abused_bits;
	396	}
	397
	398	return 0;
	399	}
	400
5ee84c33 JQ	401	static const VMStateDescription vmstate_bmdma_current = {
	402	.name = "ide bmdma_current",
	403	.version_id = 1,
	404	.minimum_version_id = 1,
d49805ae	405	.fields = (VMStateField[]) {
5ee84c33 JQ	406	VMSTATE_UINT32(cur_addr, BMDMAState),
	407	VMSTATE_UINT32(cur_prd_last, BMDMAState),
	408	VMSTATE_UINT32(cur_prd_addr, BMDMAState),
	409	VMSTATE_UINT32(cur_prd_len, BMDMAState),
	410	VMSTATE_END_OF_LIST()
	411	}
	412	};
	413
06ab66cf	414	static const VMStateDescription vmstate_bmdma_status = {
def93791 KW	415	.name ="ide bmdma/status",
	416	.version_id = 1,
	417	.minimum_version_id = 1,
d49805ae	418	.fields = (VMStateField[]) {
def93791 KW	419	VMSTATE_UINT8(status, BMDMAState),
	420	VMSTATE_END_OF_LIST()
	421	}
	422	};
5ee84c33	423
407a4f30 JQ	424	static const VMStateDescription vmstate_bmdma = {
407a4f30 JQ	425	.name = "ide bmdma",
57338424	426	.version_id = 3,
407a4f30	427	.minimum_version_id = 0,
def93791	428	.pre_save = ide_bmdma_pre_save,
d49805ae	429	.fields = (VMStateField[]) {
407a4f30	430	VMSTATE_UINT8(cmd, BMDMAState),
def93791	431	VMSTATE_UINT8(migration_compat_status, BMDMAState),
407a4f30 JQ	432	VMSTATE_UINT32(addr, BMDMAState),
	433	VMSTATE_INT64(sector_num, BMDMAState),
	434	VMSTATE_UINT32(nsector, BMDMAState),
	435	VMSTATE_UINT8(unit, BMDMAState),
	436	VMSTATE_END_OF_LIST()
5ee84c33 JQ	437	},
	438	.subsections = (VMStateSubsection []) {
	439	{
	440	.vmsd = &vmstate_bmdma_current,
	441	.needed = ide_bmdma_current_needed,
def93791 KW	442	}, {
	443	.vmsd = &vmstate_bmdma_status,
	444	.needed = ide_bmdma_status_needed,
5ee84c33 JQ	445	}, {
	446	/* empty */
	447	}
977e1244	448	}
407a4f30	449	};
977e1244	450
407a4f30	451	static int ide_pci_post_load(void *opaque, int version_id)
977e1244 GH	452	{
977e1244 GH	453	PCIIDEState *d = opaque;
407a4f30	454	int i;
977e1244	455
977e1244	456	for(i = 0; i < 2; i++) {
407a4f30 JQ	457	/* current versions always store 0/1, but older version
	458	stored bigger values. We only need last bit */
	459	d->bmdma[i].unit &= 1;
def93791	460	ide_bmdma_post_load(&d->bmdma[i], -1);
977e1244	461	}
def93791	462
977e1244 GH	463	return 0;
	464	}
	465
407a4f30 JQ	466	const VMStateDescription vmstate_ide_pci = {
407a4f30 JQ	467	.name = "ide",
57338424	468	.version_id = 3,
407a4f30	469	.minimum_version_id = 0,
407a4f30	470	.post_load = ide_pci_post_load,
d49805ae	471	.fields = (VMStateField[]) {
f6c11d56	472	VMSTATE_PCI_DEVICE(parent_obj, PCIIDEState),
407a4f30 JQ	473	VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
	474	vmstate_bmdma, BMDMAState),
	475	VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
	476	VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
	477	VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
	478	VMSTATE_END_OF_LIST()
	479	}
	480	};
	481
3e7e1558	482	void pci_ide_create_devs(PCIDevice dev, DriveInfo *hd_table)
feef3102	483	{
f6c11d56	484	PCIIDEState *d = PCI_IDE(dev);
feef3102 GH	485	static const int bus[4] = { 0, 0, 1, 1 };
	486	static const int unit[4] = { 0, 1, 0, 1 };
	487	int i;
	488
	489	for (i = 0; i < 4; i++) {
	490	if (hd_table[i] == NULL)
	491	continue;
1f850f10	492	ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
feef3102 GH	493	}
feef3102 GH	494	}
40a6238a AG	495
	496	static const struct IDEDMAOps bmdma_ops = {
	497	.start_dma = bmdma_start_dma,
40a6238a AG	498	.prepare_buf = bmdma_prepare_buf,
	499	.rw_buf = bmdma_rw_buf,
	500	.set_unit = bmdma_set_unit,
	501	.add_status = bmdma_add_status,
	502	.set_inactive = bmdma_set_inactive,
	503	.restart_cb = bmdma_restart_cb,
	504	.reset = bmdma_reset,
	505	};
	506
a9deb8c6	507	void bmdma_init(IDEBus bus, BMDMAState bm, PCIIDEState *d)
40a6238a AG	508	{
	509	qemu_irq *irq;
	510
	511	if (bus->dma == &bm->dma) {
	512	return;
	513	}
	514
	515	bm->dma.ops = &bmdma_ops;
	516	bus->dma = &bm->dma;
	517	bm->irq = bus->irq;
	518	irq = qemu_allocate_irqs(bmdma_irq, bm, 1);
	519	bus->irq = *irq;
a9deb8c6	520	bm->pci_dev = d;
40a6238a	521	}
f6c11d56 AF	522
	523	static const TypeInfo pci_ide_type_info = {
	524	.name = TYPE_PCI_IDE,
	525	.parent = TYPE_PCI_DEVICE,
	526	.instance_size = sizeof(PCIIDEState),
	527	.abstract = true,
	528	};
	529
	530	static void pci_ide_register_types(void)
	531	{
	532	type_register_static(&pci_ide_type_info);
	533	}
	534
	535	type_init(pci_ide_register_types)