]>
Commit | Line | Data |
---|---|---|
977e1244 GH |
1 | /* |
2 | * QEMU IDE Emulation: PCI Bus support. | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * Copyright (c) 2006 Openedhand Ltd. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
59f2a787 GH |
25 | #include <hw/hw.h> |
26 | #include <hw/pc.h> | |
27 | #include <hw/pci.h> | |
feef3102 | 28 | #include <hw/isa.h> |
977e1244 GH |
29 | #include "block.h" |
30 | #include "block_int.h" | |
31 | #include "sysemu.h" | |
32 | #include "dma.h" | |
59f2a787 | 33 | |
65c0f135 | 34 | #include <hw/ide/pci.h> |
977e1244 | 35 | |
3e7e1558 | 36 | void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val) |
977e1244 GH |
37 | { |
38 | BMDMAState *bm = opaque; | |
39 | #ifdef DEBUG_IDE | |
40 | printf("%s: 0x%08x\n", __func__, val); | |
41 | #endif | |
c29947bb KW |
42 | |
43 | /* Ignore writes to SSBM if it keeps the old value */ | |
44 | if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) { | |
45 | if (!(val & BM_CMD_START)) { | |
46 | /* | |
47 | * We can't cancel Scatter Gather DMA in the middle of the | |
48 | * operation or a partial (not full) DMA transfer would reach | |
49 | * the storage so we wait for completion instead (we beahve | |
50 | * like if the DMA was completed by the time the guest trying | |
51 | * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not | |
52 | * set). | |
53 | * | |
54 | * In the future we'll be able to safely cancel the I/O if the | |
55 | * whole DMA operation will be submitted to disk with a single | |
56 | * aio operation with preadv/pwritev. | |
57 | */ | |
58 | if (bm->aiocb) { | |
59 | qemu_aio_flush(); | |
953844d1 | 60 | #ifdef DEBUG_IDE |
c29947bb KW |
61 | if (bm->aiocb) |
62 | printf("ide_dma_cancel: aiocb still pending"); | |
63 | if (bm->status & BM_STATUS_DMAING) | |
64 | printf("ide_dma_cancel: BM_STATUS_DMAING still pending"); | |
953844d1 | 65 | #endif |
c29947bb KW |
66 | } |
67 | } else { | |
b76876e6 | 68 | bm->cur_addr = bm->addr; |
c29947bb KW |
69 | if (!(bm->status & BM_STATUS_DMAING)) { |
70 | bm->status |= BM_STATUS_DMAING; | |
71 | /* start dma transfer if possible */ | |
72 | if (bm->dma_cb) | |
73 | bm->dma_cb(bm, 0); | |
74 | } | |
953844d1 | 75 | } |
977e1244 | 76 | } |
c29947bb KW |
77 | |
78 | bm->cmd = val & 0x09; | |
977e1244 GH |
79 | } |
80 | ||
9fbef1ac AK |
81 | static void bmdma_addr_read(IORange *ioport, uint64_t addr, |
82 | unsigned width, uint64_t *data) | |
977e1244 | 83 | { |
9fbef1ac AK |
84 | BMDMAState *bm = container_of(ioport, BMDMAState, addr_ioport); |
85 | uint32_t mask = (1ULL << (width * 8)) - 1; | |
977e1244 | 86 | |
9fbef1ac | 87 | *data = (bm->addr >> (addr * 8)) & mask; |
977e1244 | 88 | #ifdef DEBUG_IDE |
9fbef1ac | 89 | printf("%s: 0x%08x\n", __func__, (unsigned)*data); |
977e1244 | 90 | #endif |
977e1244 GH |
91 | } |
92 | ||
9fbef1ac AK |
93 | static void bmdma_addr_write(IORange *ioport, uint64_t addr, |
94 | unsigned width, uint64_t data) | |
977e1244 | 95 | { |
9fbef1ac AK |
96 | BMDMAState *bm = container_of(ioport, BMDMAState, addr_ioport); |
97 | int shift = addr * 8; | |
98 | uint32_t mask = (1ULL << (width * 8)) - 1; | |
977e1244 | 99 | |
977e1244 | 100 | #ifdef DEBUG_IDE |
9fbef1ac | 101 | printf("%s: 0x%08x\n", __func__, (unsigned)data); |
977e1244 | 102 | #endif |
9fbef1ac AK |
103 | bm->addr &= ~(mask << shift); |
104 | bm->addr |= ((data & mask) << shift) & ~3; | |
977e1244 GH |
105 | } |
106 | ||
9fbef1ac AK |
107 | const IORangeOps bmdma_addr_ioport_ops = { |
108 | .read = bmdma_addr_read, | |
109 | .write = bmdma_addr_write, | |
110 | }; | |
977e1244 | 111 | |
5ee84c33 JQ |
112 | static bool ide_bmdma_current_needed(void *opaque) |
113 | { | |
114 | BMDMAState *bm = opaque; | |
115 | ||
116 | return (bm->cur_prd_len != 0); | |
117 | } | |
118 | ||
119 | static const VMStateDescription vmstate_bmdma_current = { | |
120 | .name = "ide bmdma_current", | |
121 | .version_id = 1, | |
122 | .minimum_version_id = 1, | |
123 | .minimum_version_id_old = 1, | |
124 | .fields = (VMStateField []) { | |
125 | VMSTATE_UINT32(cur_addr, BMDMAState), | |
126 | VMSTATE_UINT32(cur_prd_last, BMDMAState), | |
127 | VMSTATE_UINT32(cur_prd_addr, BMDMAState), | |
128 | VMSTATE_UINT32(cur_prd_len, BMDMAState), | |
129 | VMSTATE_END_OF_LIST() | |
130 | } | |
131 | }; | |
132 | ||
133 | ||
407a4f30 JQ |
134 | static const VMStateDescription vmstate_bmdma = { |
135 | .name = "ide bmdma", | |
57338424 | 136 | .version_id = 3, |
407a4f30 JQ |
137 | .minimum_version_id = 0, |
138 | .minimum_version_id_old = 0, | |
139 | .fields = (VMStateField []) { | |
140 | VMSTATE_UINT8(cmd, BMDMAState), | |
141 | VMSTATE_UINT8(status, BMDMAState), | |
142 | VMSTATE_UINT32(addr, BMDMAState), | |
143 | VMSTATE_INT64(sector_num, BMDMAState), | |
144 | VMSTATE_UINT32(nsector, BMDMAState), | |
145 | VMSTATE_UINT8(unit, BMDMAState), | |
146 | VMSTATE_END_OF_LIST() | |
5ee84c33 JQ |
147 | }, |
148 | .subsections = (VMStateSubsection []) { | |
149 | { | |
150 | .vmsd = &vmstate_bmdma_current, | |
151 | .needed = ide_bmdma_current_needed, | |
152 | }, { | |
153 | /* empty */ | |
154 | } | |
977e1244 | 155 | } |
407a4f30 | 156 | }; |
977e1244 | 157 | |
407a4f30 | 158 | static int ide_pci_post_load(void *opaque, int version_id) |
977e1244 GH |
159 | { |
160 | PCIIDEState *d = opaque; | |
407a4f30 | 161 | int i; |
977e1244 | 162 | |
977e1244 | 163 | for(i = 0; i < 2; i++) { |
407a4f30 JQ |
164 | /* current versions always store 0/1, but older version |
165 | stored bigger values. We only need last bit */ | |
166 | d->bmdma[i].unit &= 1; | |
977e1244 GH |
167 | } |
168 | return 0; | |
169 | } | |
170 | ||
407a4f30 JQ |
171 | const VMStateDescription vmstate_ide_pci = { |
172 | .name = "ide", | |
57338424 | 173 | .version_id = 3, |
407a4f30 JQ |
174 | .minimum_version_id = 0, |
175 | .minimum_version_id_old = 0, | |
176 | .post_load = ide_pci_post_load, | |
177 | .fields = (VMStateField []) { | |
178 | VMSTATE_PCI_DEVICE(dev, PCIIDEState), | |
179 | VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0, | |
180 | vmstate_bmdma, BMDMAState), | |
181 | VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2), | |
182 | VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState), | |
183 | VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState), | |
184 | VMSTATE_END_OF_LIST() | |
185 | } | |
186 | }; | |
187 | ||
3e7e1558 | 188 | void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table) |
feef3102 GH |
189 | { |
190 | PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); | |
191 | static const int bus[4] = { 0, 0, 1, 1 }; | |
192 | static const int unit[4] = { 0, 1, 0, 1 }; | |
193 | int i; | |
194 | ||
195 | for (i = 0; i < 4; i++) { | |
196 | if (hd_table[i] == NULL) | |
197 | continue; | |
1f850f10 | 198 | ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]); |
feef3102 GH |
199 | } |
200 | } |