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1 | /* |
2 | * Copyright (C) 2010 Red Hat, Inc. | |
3 | * | |
4 | * written by Gerd Hoffmann <kraxel@redhat.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 or | |
9 | * (at your option) version 3 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "hw.h" | |
21 | #include "pci.h" | |
22 | #include "qemu-timer.h" | |
23 | #include "audiodev.h" | |
24 | #include "intel-hda.h" | |
25 | #include "intel-hda-defs.h" | |
26 | ||
27 | /* --------------------------------------------------------------------- */ | |
28 | /* hda bus */ | |
29 | ||
30 | static struct BusInfo hda_codec_bus_info = { | |
31 | .name = "HDA", | |
32 | .size = sizeof(HDACodecBus), | |
33 | .props = (Property[]) { | |
34 | DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1), | |
35 | DEFINE_PROP_END_OF_LIST() | |
36 | } | |
37 | }; | |
38 | ||
39 | void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, | |
40 | hda_codec_response_func response, | |
41 | hda_codec_xfer_func xfer) | |
42 | { | |
43 | qbus_create_inplace(&bus->qbus, &hda_codec_bus_info, dev, NULL); | |
44 | bus->response = response; | |
45 | bus->xfer = xfer; | |
46 | } | |
47 | ||
48 | static int hda_codec_dev_init(DeviceState *qdev, DeviceInfo *base) | |
49 | { | |
50 | HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus); | |
51 | HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev); | |
52 | HDACodecDeviceInfo *info = DO_UPCAST(HDACodecDeviceInfo, qdev, base); | |
53 | ||
54 | dev->info = info; | |
55 | if (dev->cad == -1) { | |
56 | dev->cad = bus->next_cad; | |
57 | } | |
58 | if (dev->cad > 15) | |
59 | return -1; | |
60 | bus->next_cad = dev->cad + 1; | |
61 | return info->init(dev); | |
62 | } | |
63 | ||
64 | void hda_codec_register(HDACodecDeviceInfo *info) | |
65 | { | |
66 | info->qdev.init = hda_codec_dev_init; | |
67 | info->qdev.bus_info = &hda_codec_bus_info; | |
68 | qdev_register(&info->qdev); | |
69 | } | |
70 | ||
71 | HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad) | |
72 | { | |
73 | DeviceState *qdev; | |
74 | HDACodecDevice *cdev; | |
75 | ||
76 | QLIST_FOREACH(qdev, &bus->qbus.children, sibling) { | |
77 | cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); | |
78 | if (cdev->cad == cad) { | |
79 | return cdev; | |
80 | } | |
81 | } | |
82 | return NULL; | |
83 | } | |
84 | ||
85 | void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response) | |
86 | { | |
87 | HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); | |
88 | bus->response(dev, solicited, response); | |
89 | } | |
90 | ||
91 | bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, | |
92 | uint8_t *buf, uint32_t len) | |
93 | { | |
94 | HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); | |
95 | return bus->xfer(dev, stnr, output, buf, len); | |
96 | } | |
97 | ||
98 | /* --------------------------------------------------------------------- */ | |
99 | /* intel hda emulation */ | |
100 | ||
101 | typedef struct IntelHDAStream IntelHDAStream; | |
102 | typedef struct IntelHDAState IntelHDAState; | |
103 | typedef struct IntelHDAReg IntelHDAReg; | |
104 | ||
105 | typedef struct bpl { | |
106 | uint64_t addr; | |
107 | uint32_t len; | |
108 | uint32_t flags; | |
109 | } bpl; | |
110 | ||
111 | struct IntelHDAStream { | |
112 | /* registers */ | |
113 | uint32_t ctl; | |
114 | uint32_t lpib; | |
115 | uint32_t cbl; | |
116 | uint32_t lvi; | |
117 | uint32_t fmt; | |
118 | uint32_t bdlp_lbase; | |
119 | uint32_t bdlp_ubase; | |
120 | ||
121 | /* state */ | |
122 | bpl *bpl; | |
123 | uint32_t bentries; | |
124 | uint32_t bsize, be, bp; | |
125 | }; | |
126 | ||
127 | struct IntelHDAState { | |
128 | PCIDevice pci; | |
129 | const char *name; | |
130 | HDACodecBus codecs; | |
131 | ||
132 | /* registers */ | |
133 | uint32_t g_ctl; | |
134 | uint32_t wake_en; | |
135 | uint32_t state_sts; | |
136 | uint32_t int_ctl; | |
137 | uint32_t int_sts; | |
138 | uint32_t wall_clk; | |
139 | ||
140 | uint32_t corb_lbase; | |
141 | uint32_t corb_ubase; | |
142 | uint32_t corb_rp; | |
143 | uint32_t corb_wp; | |
144 | uint32_t corb_ctl; | |
145 | uint32_t corb_sts; | |
146 | uint32_t corb_size; | |
147 | ||
148 | uint32_t rirb_lbase; | |
149 | uint32_t rirb_ubase; | |
150 | uint32_t rirb_wp; | |
151 | uint32_t rirb_cnt; | |
152 | uint32_t rirb_ctl; | |
153 | uint32_t rirb_sts; | |
154 | uint32_t rirb_size; | |
155 | ||
156 | uint32_t dp_lbase; | |
157 | uint32_t dp_ubase; | |
158 | ||
159 | uint32_t icw; | |
160 | uint32_t irr; | |
161 | uint32_t ics; | |
162 | ||
163 | /* streams */ | |
164 | IntelHDAStream st[8]; | |
165 | ||
166 | /* state */ | |
167 | int mmio_addr; | |
168 | uint32_t rirb_count; | |
169 | int64_t wall_base_ns; | |
170 | ||
171 | /* debug logging */ | |
172 | const IntelHDAReg *last_reg; | |
173 | uint32_t last_val; | |
174 | uint32_t last_write; | |
175 | uint32_t last_sec; | |
176 | uint32_t repeat_count; | |
177 | ||
178 | /* properties */ | |
179 | uint32_t debug; | |
180 | }; | |
181 | ||
182 | struct IntelHDAReg { | |
183 | const char *name; /* register name */ | |
184 | uint32_t size; /* size in bytes */ | |
185 | uint32_t reset; /* reset value */ | |
186 | uint32_t wmask; /* write mask */ | |
187 | uint32_t wclear; /* write 1 to clear bits */ | |
188 | uint32_t offset; /* location in IntelHDAState */ | |
189 | uint32_t shift; /* byte access entries for dwords */ | |
190 | uint32_t stream; | |
191 | void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old); | |
192 | void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg); | |
193 | }; | |
194 | ||
195 | static void intel_hda_reset(DeviceState *dev); | |
196 | ||
197 | /* --------------------------------------------------------------------- */ | |
198 | ||
199 | static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase) | |
200 | { | |
201 | target_phys_addr_t addr; | |
202 | ||
203 | #if TARGET_PHYS_ADDR_BITS == 32 | |
204 | addr = lbase; | |
205 | #else | |
206 | addr = ubase; | |
207 | addr <<= 32; | |
208 | addr |= lbase; | |
209 | #endif | |
210 | return addr; | |
211 | } | |
212 | ||
213 | static void stl_phys_le(target_phys_addr_t addr, uint32_t value) | |
214 | { | |
215 | uint32_t value_le = cpu_to_le32(value); | |
216 | cpu_physical_memory_write(addr, (uint8_t*)(&value_le), sizeof(value_le)); | |
217 | } | |
218 | ||
219 | static uint32_t ldl_phys_le(target_phys_addr_t addr) | |
220 | { | |
221 | uint32_t value_le; | |
222 | cpu_physical_memory_read(addr, (uint8_t*)(&value_le), sizeof(value_le)); | |
223 | return le32_to_cpu(value_le); | |
224 | } | |
225 | ||
226 | static void intel_hda_update_int_sts(IntelHDAState *d) | |
227 | { | |
228 | uint32_t sts = 0; | |
229 | uint32_t i; | |
230 | ||
231 | /* update controller status */ | |
232 | if (d->rirb_sts & ICH6_RBSTS_IRQ) { | |
233 | sts |= (1 << 30); | |
234 | } | |
235 | if (d->rirb_sts & ICH6_RBSTS_OVERRUN) { | |
236 | sts |= (1 << 30); | |
237 | } | |
238 | if (d->state_sts) { | |
239 | sts |= (1 << 30); | |
240 | } | |
241 | ||
242 | /* update stream status */ | |
243 | for (i = 0; i < 8; i++) { | |
244 | /* buffer completion interrupt */ | |
245 | if (d->st[i].ctl & (1 << 26)) { | |
246 | sts |= (1 << i); | |
247 | } | |
248 | } | |
249 | ||
250 | /* update global status */ | |
251 | if (sts & d->int_ctl) { | |
252 | sts |= (1 << 31); | |
253 | } | |
254 | ||
255 | d->int_sts = sts; | |
256 | } | |
257 | ||
258 | static void intel_hda_update_irq(IntelHDAState *d) | |
259 | { | |
260 | int level; | |
261 | ||
262 | intel_hda_update_int_sts(d); | |
263 | if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) { | |
264 | level = 1; | |
265 | } else { | |
266 | level = 0; | |
267 | } | |
268 | dprint(d, 2, "%s: level %d\n", __FUNCTION__, level); | |
269 | qemu_set_irq(d->pci.irq[0], level); | |
270 | } | |
271 | ||
272 | static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) | |
273 | { | |
274 | uint32_t cad, nid, data; | |
275 | HDACodecDevice *codec; | |
276 | ||
277 | cad = (verb >> 28) & 0x0f; | |
278 | if (verb & (1 << 27)) { | |
279 | /* indirect node addressing, not specified in HDA 1.0 */ | |
280 | dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__); | |
281 | return -1; | |
282 | } | |
283 | nid = (verb >> 20) & 0x7f; | |
284 | data = verb & 0xfffff; | |
285 | ||
286 | codec = hda_codec_find(&d->codecs, cad); | |
287 | if (codec == NULL) { | |
288 | dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__); | |
289 | return -1; | |
290 | } | |
291 | codec->info->command(codec, nid, data); | |
292 | return 0; | |
293 | } | |
294 | ||
295 | static void intel_hda_corb_run(IntelHDAState *d) | |
296 | { | |
297 | target_phys_addr_t addr; | |
298 | uint32_t rp, verb; | |
299 | ||
300 | if (d->ics & ICH6_IRS_BUSY) { | |
301 | dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw); | |
302 | intel_hda_send_command(d, d->icw); | |
303 | return; | |
304 | } | |
305 | ||
306 | for (;;) { | |
307 | if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) { | |
308 | dprint(d, 2, "%s: !run\n", __FUNCTION__); | |
309 | return; | |
310 | } | |
311 | if ((d->corb_rp & 0xff) == d->corb_wp) { | |
312 | dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__); | |
313 | return; | |
314 | } | |
315 | if (d->rirb_count == d->rirb_cnt) { | |
316 | dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__); | |
317 | return; | |
318 | } | |
319 | ||
320 | rp = (d->corb_rp + 1) & 0xff; | |
321 | addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); | |
322 | verb = ldl_phys_le(addr + 4*rp); | |
323 | d->corb_rp = rp; | |
324 | ||
325 | dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb); | |
326 | intel_hda_send_command(d, verb); | |
327 | } | |
328 | } | |
329 | ||
330 | static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response) | |
331 | { | |
332 | HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); | |
333 | IntelHDAState *d = container_of(bus, IntelHDAState, codecs); | |
334 | target_phys_addr_t addr; | |
335 | uint32_t wp, ex; | |
336 | ||
337 | if (d->ics & ICH6_IRS_BUSY) { | |
338 | dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", | |
339 | __FUNCTION__, response, dev->cad); | |
340 | d->irr = response; | |
341 | d->ics &= ~(ICH6_IRS_BUSY | 0xf0); | |
342 | d->ics |= (ICH6_IRS_VALID | (dev->cad << 4)); | |
343 | return; | |
344 | } | |
345 | ||
346 | if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) { | |
347 | dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__); | |
348 | return; | |
349 | } | |
350 | ||
351 | ex = (solicited ? 0 : (1 << 4)) | dev->cad; | |
352 | wp = (d->rirb_wp + 1) & 0xff; | |
353 | addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); | |
354 | stl_phys_le(addr + 8*wp, response); | |
355 | stl_phys_le(addr + 8*wp + 4, ex); | |
356 | d->rirb_wp = wp; | |
357 | ||
358 | dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", | |
359 | __FUNCTION__, wp, response, ex); | |
360 | ||
361 | d->rirb_count++; | |
362 | if (d->rirb_count == d->rirb_cnt) { | |
363 | dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count); | |
364 | if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { | |
365 | d->rirb_sts |= ICH6_RBSTS_IRQ; | |
366 | intel_hda_update_irq(d); | |
367 | } | |
368 | } else if ((d->corb_rp & 0xff) == d->corb_wp) { | |
369 | dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__, | |
370 | d->rirb_count, d->rirb_cnt); | |
371 | if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { | |
372 | d->rirb_sts |= ICH6_RBSTS_IRQ; | |
373 | intel_hda_update_irq(d); | |
374 | } | |
375 | } | |
376 | } | |
377 | ||
378 | static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, | |
379 | uint8_t *buf, uint32_t len) | |
380 | { | |
381 | HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); | |
382 | IntelHDAState *d = container_of(bus, IntelHDAState, codecs); | |
383 | IntelHDAStream *st = NULL; | |
384 | target_phys_addr_t addr; | |
385 | uint32_t s, copy, left; | |
386 | bool irq = false; | |
387 | ||
388 | for (s = 0; s < ARRAY_SIZE(d->st); s++) { | |
389 | if (stnr == ((d->st[s].ctl >> 20) & 0x0f)) { | |
390 | st = d->st + s; | |
391 | break; | |
392 | } | |
393 | } | |
394 | if (st == NULL) { | |
395 | return false; | |
396 | } | |
397 | if (st->bpl == NULL) { | |
398 | return false; | |
399 | } | |
400 | if (st->ctl & (1 << 26)) { | |
401 | /* | |
402 | * Wait with the next DMA xfer until the guest | |
403 | * has acked the buffer completion interrupt | |
404 | */ | |
405 | return false; | |
406 | } | |
407 | ||
408 | left = len; | |
409 | while (left > 0) { | |
410 | copy = left; | |
411 | if (copy > st->bsize - st->lpib) | |
412 | copy = st->bsize - st->lpib; | |
413 | if (copy > st->bpl[st->be].len - st->bp) | |
414 | copy = st->bpl[st->be].len - st->bp; | |
415 | ||
416 | dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", | |
417 | st->be, st->bp, st->bpl[st->be].len, copy); | |
418 | ||
419 | cpu_physical_memory_rw(st->bpl[st->be].addr + st->bp, | |
420 | buf, copy, !output); | |
421 | st->lpib += copy; | |
422 | st->bp += copy; | |
423 | buf += copy; | |
424 | left -= copy; | |
425 | ||
426 | if (st->bpl[st->be].len == st->bp) { | |
427 | /* bpl entry filled */ | |
428 | if (st->bpl[st->be].flags & 0x01) { | |
429 | irq = true; | |
430 | } | |
431 | st->bp = 0; | |
432 | st->be++; | |
433 | if (st->be == st->bentries) { | |
434 | /* bpl wrap around */ | |
435 | st->be = 0; | |
436 | st->lpib = 0; | |
437 | } | |
438 | } | |
439 | } | |
440 | if (d->dp_lbase & 0x01) { | |
441 | addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase); | |
442 | stl_phys_le(addr + 8*s, st->lpib); | |
443 | } | |
444 | dprint(d, 3, "dma: --\n"); | |
445 | ||
446 | if (irq) { | |
447 | st->ctl |= (1 << 26); /* buffer completion interrupt */ | |
448 | intel_hda_update_irq(d); | |
449 | } | |
450 | return true; | |
451 | } | |
452 | ||
453 | static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) | |
454 | { | |
455 | target_phys_addr_t addr; | |
456 | uint8_t buf[16]; | |
457 | uint32_t i; | |
458 | ||
459 | addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); | |
460 | st->bentries = st->lvi +1; | |
461 | qemu_free(st->bpl); | |
462 | st->bpl = qemu_malloc(sizeof(bpl) * st->bentries); | |
463 | for (i = 0; i < st->bentries; i++, addr += 16) { | |
464 | cpu_physical_memory_read(addr, buf, 16); | |
465 | st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); | |
466 | st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8)); | |
467 | st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12)); | |
468 | dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", | |
469 | i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); | |
470 | } | |
471 | ||
472 | st->bsize = st->cbl; | |
473 | st->lpib = 0; | |
474 | st->be = 0; | |
475 | st->bp = 0; | |
476 | } | |
477 | ||
478 | static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running) | |
479 | { | |
480 | DeviceState *qdev; | |
481 | HDACodecDevice *cdev; | |
482 | ||
483 | QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) { | |
484 | cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); | |
485 | if (cdev->info->stream) { | |
486 | cdev->info->stream(cdev, stream, running); | |
487 | } | |
488 | } | |
489 | } | |
490 | ||
491 | /* --------------------------------------------------------------------- */ | |
492 | ||
493 | static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) | |
494 | { | |
495 | if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { | |
496 | intel_hda_reset(&d->pci.qdev); | |
497 | } | |
498 | } | |
499 | ||
500 | static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) | |
501 | { | |
502 | intel_hda_update_irq(d); | |
503 | } | |
504 | ||
505 | static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) | |
506 | { | |
507 | intel_hda_update_irq(d); | |
508 | } | |
509 | ||
510 | static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) | |
511 | { | |
512 | int64_t ns; | |
513 | ||
514 | ns = qemu_get_clock_ns(vm_clock) - d->wall_base_ns; | |
515 | d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ | |
516 | } | |
517 | ||
518 | static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) | |
519 | { | |
520 | intel_hda_corb_run(d); | |
521 | } | |
522 | ||
523 | static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) | |
524 | { | |
525 | intel_hda_corb_run(d); | |
526 | } | |
527 | ||
528 | static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) | |
529 | { | |
530 | if (d->rirb_wp & ICH6_RIRBWP_RST) { | |
531 | d->rirb_wp = 0; | |
532 | } | |
533 | } | |
534 | ||
535 | static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) | |
536 | { | |
537 | intel_hda_update_irq(d); | |
538 | ||
539 | if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) { | |
540 | /* cleared ICH6_RBSTS_IRQ */ | |
541 | d->rirb_count = 0; | |
542 | intel_hda_corb_run(d); | |
543 | } | |
544 | } | |
545 | ||
546 | static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) | |
547 | { | |
548 | if (d->ics & ICH6_IRS_BUSY) { | |
549 | intel_hda_corb_run(d); | |
550 | } | |
551 | } | |
552 | ||
553 | static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) | |
554 | { | |
555 | IntelHDAStream *st = d->st + reg->stream; | |
556 | ||
557 | if (st->ctl & 0x01) { | |
558 | /* reset */ | |
559 | dprint(d, 1, "st #%d: reset\n", reg->stream); | |
560 | st->ctl = 0; | |
561 | } | |
562 | if ((st->ctl & 0x02) != (old & 0x02)) { | |
563 | uint32_t stnr = (st->ctl >> 20) & 0x0f; | |
564 | /* run bit flipped */ | |
565 | if (st->ctl & 0x02) { | |
566 | /* start */ | |
567 | dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", | |
568 | reg->stream, stnr, st->cbl); | |
569 | intel_hda_parse_bdl(d, st); | |
570 | intel_hda_notify_codecs(d, stnr, true); | |
571 | } else { | |
572 | /* stop */ | |
573 | dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); | |
574 | intel_hda_notify_codecs(d, stnr, false); | |
575 | } | |
576 | } | |
577 | intel_hda_update_irq(d); | |
578 | } | |
579 | ||
580 | /* --------------------------------------------------------------------- */ | |
581 | ||
582 | #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o)) | |
583 | ||
584 | static const struct IntelHDAReg regtab[] = { | |
585 | /* global */ | |
586 | [ ICH6_REG_GCAP ] = { | |
587 | .name = "GCAP", | |
588 | .size = 2, | |
589 | .reset = 0x4401, | |
590 | }, | |
591 | [ ICH6_REG_VMIN ] = { | |
592 | .name = "VMIN", | |
593 | .size = 1, | |
594 | }, | |
595 | [ ICH6_REG_VMAJ ] = { | |
596 | .name = "VMAJ", | |
597 | .size = 1, | |
598 | .reset = 1, | |
599 | }, | |
600 | [ ICH6_REG_OUTPAY ] = { | |
601 | .name = "OUTPAY", | |
602 | .size = 2, | |
603 | .reset = 0x3c, | |
604 | }, | |
605 | [ ICH6_REG_INPAY ] = { | |
606 | .name = "INPAY", | |
607 | .size = 2, | |
608 | .reset = 0x1d, | |
609 | }, | |
610 | [ ICH6_REG_GCTL ] = { | |
611 | .name = "GCTL", | |
612 | .size = 4, | |
613 | .wmask = 0x0103, | |
614 | .offset = offsetof(IntelHDAState, g_ctl), | |
615 | .whandler = intel_hda_set_g_ctl, | |
616 | }, | |
617 | [ ICH6_REG_WAKEEN ] = { | |
618 | .name = "WAKEEN", | |
619 | .size = 2, | |
620 | .offset = offsetof(IntelHDAState, wake_en), | |
621 | }, | |
622 | [ ICH6_REG_STATESTS ] = { | |
623 | .name = "STATESTS", | |
624 | .size = 2, | |
625 | .wmask = 0x3fff, | |
626 | .wclear = 0x3fff, | |
627 | .offset = offsetof(IntelHDAState, state_sts), | |
628 | .whandler = intel_hda_set_state_sts, | |
629 | }, | |
630 | ||
631 | /* interrupts */ | |
632 | [ ICH6_REG_INTCTL ] = { | |
633 | .name = "INTCTL", | |
634 | .size = 4, | |
635 | .wmask = 0xc00000ff, | |
636 | .offset = offsetof(IntelHDAState, int_ctl), | |
637 | .whandler = intel_hda_set_int_ctl, | |
638 | }, | |
639 | [ ICH6_REG_INTSTS ] = { | |
640 | .name = "INTSTS", | |
641 | .size = 4, | |
642 | .wmask = 0xc00000ff, | |
643 | .wclear = 0xc00000ff, | |
644 | .offset = offsetof(IntelHDAState, int_sts), | |
645 | }, | |
646 | ||
647 | /* misc */ | |
648 | [ ICH6_REG_WALLCLK ] = { | |
649 | .name = "WALLCLK", | |
650 | .size = 4, | |
651 | .offset = offsetof(IntelHDAState, wall_clk), | |
652 | .rhandler = intel_hda_get_wall_clk, | |
653 | }, | |
654 | [ ICH6_REG_WALLCLK + 0x2000 ] = { | |
655 | .name = "WALLCLK(alias)", | |
656 | .size = 4, | |
657 | .offset = offsetof(IntelHDAState, wall_clk), | |
658 | .rhandler = intel_hda_get_wall_clk, | |
659 | }, | |
660 | ||
661 | /* dma engine */ | |
662 | [ ICH6_REG_CORBLBASE ] = { | |
663 | .name = "CORBLBASE", | |
664 | .size = 4, | |
665 | .wmask = 0xffffff80, | |
666 | .offset = offsetof(IntelHDAState, corb_lbase), | |
667 | }, | |
668 | [ ICH6_REG_CORBUBASE ] = { | |
669 | .name = "CORBUBASE", | |
670 | .size = 4, | |
671 | .wmask = 0xffffffff, | |
672 | .offset = offsetof(IntelHDAState, corb_ubase), | |
673 | }, | |
674 | [ ICH6_REG_CORBWP ] = { | |
675 | .name = "CORBWP", | |
676 | .size = 2, | |
677 | .wmask = 0xff, | |
678 | .offset = offsetof(IntelHDAState, corb_wp), | |
679 | .whandler = intel_hda_set_corb_wp, | |
680 | }, | |
681 | [ ICH6_REG_CORBRP ] = { | |
682 | .name = "CORBRP", | |
683 | .size = 2, | |
684 | .wmask = 0x80ff, | |
685 | .offset = offsetof(IntelHDAState, corb_rp), | |
686 | }, | |
687 | [ ICH6_REG_CORBCTL ] = { | |
688 | .name = "CORBCTL", | |
689 | .size = 1, | |
690 | .wmask = 0x03, | |
691 | .offset = offsetof(IntelHDAState, corb_ctl), | |
692 | .whandler = intel_hda_set_corb_ctl, | |
693 | }, | |
694 | [ ICH6_REG_CORBSTS ] = { | |
695 | .name = "CORBSTS", | |
696 | .size = 1, | |
697 | .wmask = 0x01, | |
698 | .wclear = 0x01, | |
699 | .offset = offsetof(IntelHDAState, corb_sts), | |
700 | }, | |
701 | [ ICH6_REG_CORBSIZE ] = { | |
702 | .name = "CORBSIZE", | |
703 | .size = 1, | |
704 | .reset = 0x42, | |
705 | .offset = offsetof(IntelHDAState, corb_size), | |
706 | }, | |
707 | [ ICH6_REG_RIRBLBASE ] = { | |
708 | .name = "RIRBLBASE", | |
709 | .size = 4, | |
710 | .wmask = 0xffffff80, | |
711 | .offset = offsetof(IntelHDAState, rirb_lbase), | |
712 | }, | |
713 | [ ICH6_REG_RIRBUBASE ] = { | |
714 | .name = "RIRBUBASE", | |
715 | .size = 4, | |
716 | .wmask = 0xffffffff, | |
717 | .offset = offsetof(IntelHDAState, rirb_ubase), | |
718 | }, | |
719 | [ ICH6_REG_RIRBWP ] = { | |
720 | .name = "RIRBWP", | |
721 | .size = 2, | |
722 | .wmask = 0x8000, | |
723 | .offset = offsetof(IntelHDAState, rirb_wp), | |
724 | .whandler = intel_hda_set_rirb_wp, | |
725 | }, | |
726 | [ ICH6_REG_RINTCNT ] = { | |
727 | .name = "RINTCNT", | |
728 | .size = 2, | |
729 | .wmask = 0xff, | |
730 | .offset = offsetof(IntelHDAState, rirb_cnt), | |
731 | }, | |
732 | [ ICH6_REG_RIRBCTL ] = { | |
733 | .name = "RIRBCTL", | |
734 | .size = 1, | |
735 | .wmask = 0x07, | |
736 | .offset = offsetof(IntelHDAState, rirb_ctl), | |
737 | }, | |
738 | [ ICH6_REG_RIRBSTS ] = { | |
739 | .name = "RIRBSTS", | |
740 | .size = 1, | |
741 | .wmask = 0x05, | |
742 | .wclear = 0x05, | |
743 | .offset = offsetof(IntelHDAState, rirb_sts), | |
744 | .whandler = intel_hda_set_rirb_sts, | |
745 | }, | |
746 | [ ICH6_REG_RIRBSIZE ] = { | |
747 | .name = "RIRBSIZE", | |
748 | .size = 1, | |
749 | .reset = 0x42, | |
750 | .offset = offsetof(IntelHDAState, rirb_size), | |
751 | }, | |
752 | ||
753 | [ ICH6_REG_DPLBASE ] = { | |
754 | .name = "DPLBASE", | |
755 | .size = 4, | |
756 | .wmask = 0xffffff81, | |
757 | .offset = offsetof(IntelHDAState, dp_lbase), | |
758 | }, | |
759 | [ ICH6_REG_DPUBASE ] = { | |
760 | .name = "DPUBASE", | |
761 | .size = 4, | |
762 | .wmask = 0xffffffff, | |
763 | .offset = offsetof(IntelHDAState, dp_ubase), | |
764 | }, | |
765 | ||
766 | [ ICH6_REG_IC ] = { | |
767 | .name = "ICW", | |
768 | .size = 4, | |
769 | .wmask = 0xffffffff, | |
770 | .offset = offsetof(IntelHDAState, icw), | |
771 | }, | |
772 | [ ICH6_REG_IR ] = { | |
773 | .name = "IRR", | |
774 | .size = 4, | |
775 | .offset = offsetof(IntelHDAState, irr), | |
776 | }, | |
777 | [ ICH6_REG_IRS ] = { | |
778 | .name = "ICS", | |
779 | .size = 2, | |
780 | .wmask = 0x0003, | |
781 | .wclear = 0x0002, | |
782 | .offset = offsetof(IntelHDAState, ics), | |
783 | .whandler = intel_hda_set_ics, | |
784 | }, | |
785 | ||
786 | #define HDA_STREAM(_t, _i) \ | |
787 | [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \ | |
788 | .stream = _i, \ | |
789 | .name = _t stringify(_i) " CTL", \ | |
790 | .size = 4, \ | |
791 | .wmask = 0x1cff001f, \ | |
792 | .offset = offsetof(IntelHDAState, st[_i].ctl), \ | |
793 | .whandler = intel_hda_set_st_ctl, \ | |
794 | }, \ | |
795 | [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \ | |
796 | .stream = _i, \ | |
797 | .name = _t stringify(_i) " CTL(stnr)", \ | |
798 | .size = 1, \ | |
799 | .shift = 16, \ | |
800 | .wmask = 0x00ff0000, \ | |
801 | .offset = offsetof(IntelHDAState, st[_i].ctl), \ | |
802 | .whandler = intel_hda_set_st_ctl, \ | |
803 | }, \ | |
804 | [ ST_REG(_i, ICH6_REG_SD_STS)] = { \ | |
805 | .stream = _i, \ | |
806 | .name = _t stringify(_i) " CTL(sts)", \ | |
807 | .size = 1, \ | |
808 | .shift = 24, \ | |
809 | .wmask = 0x1c000000, \ | |
810 | .wclear = 0x1c000000, \ | |
811 | .offset = offsetof(IntelHDAState, st[_i].ctl), \ | |
812 | .whandler = intel_hda_set_st_ctl, \ | |
813 | }, \ | |
814 | [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \ | |
815 | .stream = _i, \ | |
816 | .name = _t stringify(_i) " LPIB", \ | |
817 | .size = 4, \ | |
818 | .offset = offsetof(IntelHDAState, st[_i].lpib), \ | |
819 | }, \ | |
820 | [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \ | |
821 | .stream = _i, \ | |
822 | .name = _t stringify(_i) " LPIB(alias)", \ | |
823 | .size = 4, \ | |
824 | .offset = offsetof(IntelHDAState, st[_i].lpib), \ | |
825 | }, \ | |
826 | [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \ | |
827 | .stream = _i, \ | |
828 | .name = _t stringify(_i) " CBL", \ | |
829 | .size = 4, \ | |
830 | .wmask = 0xffffffff, \ | |
831 | .offset = offsetof(IntelHDAState, st[_i].cbl), \ | |
832 | }, \ | |
833 | [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \ | |
834 | .stream = _i, \ | |
835 | .name = _t stringify(_i) " LVI", \ | |
836 | .size = 2, \ | |
837 | .wmask = 0x00ff, \ | |
838 | .offset = offsetof(IntelHDAState, st[_i].lvi), \ | |
839 | }, \ | |
840 | [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \ | |
841 | .stream = _i, \ | |
842 | .name = _t stringify(_i) " FIFOS", \ | |
843 | .size = 2, \ | |
844 | .reset = HDA_BUFFER_SIZE, \ | |
845 | }, \ | |
846 | [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \ | |
847 | .stream = _i, \ | |
848 | .name = _t stringify(_i) " FMT", \ | |
849 | .size = 2, \ | |
850 | .wmask = 0x7f7f, \ | |
851 | .offset = offsetof(IntelHDAState, st[_i].fmt), \ | |
852 | }, \ | |
853 | [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \ | |
854 | .stream = _i, \ | |
855 | .name = _t stringify(_i) " BDLPL", \ | |
856 | .size = 4, \ | |
857 | .wmask = 0xffffff80, \ | |
858 | .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \ | |
859 | }, \ | |
860 | [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \ | |
861 | .stream = _i, \ | |
862 | .name = _t stringify(_i) " BDLPU", \ | |
863 | .size = 4, \ | |
864 | .wmask = 0xffffffff, \ | |
865 | .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \ | |
866 | }, \ | |
867 | ||
868 | HDA_STREAM("IN", 0) | |
869 | HDA_STREAM("IN", 1) | |
870 | HDA_STREAM("IN", 2) | |
871 | HDA_STREAM("IN", 3) | |
872 | ||
873 | HDA_STREAM("OUT", 4) | |
874 | HDA_STREAM("OUT", 5) | |
875 | HDA_STREAM("OUT", 6) | |
876 | HDA_STREAM("OUT", 7) | |
877 | ||
878 | }; | |
879 | ||
880 | static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr) | |
881 | { | |
882 | const IntelHDAReg *reg; | |
883 | ||
884 | if (addr >= sizeof(regtab)/sizeof(regtab[0])) { | |
885 | goto noreg; | |
886 | } | |
887 | reg = regtab+addr; | |
888 | if (reg->name == NULL) { | |
889 | goto noreg; | |
890 | } | |
891 | return reg; | |
892 | ||
893 | noreg: | |
894 | dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); | |
895 | return NULL; | |
896 | } | |
897 | ||
898 | static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) | |
899 | { | |
900 | uint8_t *addr = (void*)d; | |
901 | ||
902 | addr += reg->offset; | |
903 | return (uint32_t*)addr; | |
904 | } | |
905 | ||
906 | static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, | |
907 | uint32_t wmask) | |
908 | { | |
909 | uint32_t *addr; | |
910 | uint32_t old; | |
911 | ||
912 | if (!reg) { | |
913 | return; | |
914 | } | |
915 | ||
916 | if (d->debug) { | |
917 | time_t now = time(NULL); | |
918 | if (d->last_write && d->last_reg == reg && d->last_val == val) { | |
919 | d->repeat_count++; | |
920 | if (d->last_sec != now) { | |
921 | dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); | |
922 | d->last_sec = now; | |
923 | d->repeat_count = 0; | |
924 | } | |
925 | } else { | |
926 | if (d->repeat_count) { | |
927 | dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); | |
928 | } | |
929 | dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); | |
930 | d->last_write = 1; | |
931 | d->last_reg = reg; | |
932 | d->last_val = val; | |
933 | d->last_sec = now; | |
934 | d->repeat_count = 0; | |
935 | } | |
936 | } | |
937 | assert(reg->offset != 0); | |
938 | ||
939 | addr = intel_hda_reg_addr(d, reg); | |
940 | old = *addr; | |
941 | ||
942 | if (reg->shift) { | |
943 | val <<= reg->shift; | |
944 | wmask <<= reg->shift; | |
945 | } | |
946 | wmask &= reg->wmask; | |
947 | *addr &= ~wmask; | |
948 | *addr |= wmask & val; | |
949 | *addr &= ~(val & reg->wclear); | |
950 | ||
951 | if (reg->whandler) { | |
952 | reg->whandler(d, reg, old); | |
953 | } | |
954 | } | |
955 | ||
956 | static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, | |
957 | uint32_t rmask) | |
958 | { | |
959 | uint32_t *addr, ret; | |
960 | ||
961 | if (!reg) { | |
962 | return 0; | |
963 | } | |
964 | ||
965 | if (reg->rhandler) { | |
966 | reg->rhandler(d, reg); | |
967 | } | |
968 | ||
969 | if (reg->offset == 0) { | |
970 | /* constant read-only register */ | |
971 | ret = reg->reset; | |
972 | } else { | |
973 | addr = intel_hda_reg_addr(d, reg); | |
974 | ret = *addr; | |
975 | if (reg->shift) { | |
976 | ret >>= reg->shift; | |
977 | } | |
978 | ret &= rmask; | |
979 | } | |
980 | if (d->debug) { | |
981 | time_t now = time(NULL); | |
982 | if (!d->last_write && d->last_reg == reg && d->last_val == ret) { | |
983 | d->repeat_count++; | |
984 | if (d->last_sec != now) { | |
985 | dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); | |
986 | d->last_sec = now; | |
987 | d->repeat_count = 0; | |
988 | } | |
989 | } else { | |
990 | if (d->repeat_count) { | |
991 | dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); | |
992 | } | |
993 | dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); | |
994 | d->last_write = 0; | |
995 | d->last_reg = reg; | |
996 | d->last_val = ret; | |
997 | d->last_sec = now; | |
998 | d->repeat_count = 0; | |
999 | } | |
1000 | } | |
1001 | return ret; | |
1002 | } | |
1003 | ||
1004 | static void intel_hda_regs_reset(IntelHDAState *d) | |
1005 | { | |
1006 | uint32_t *addr; | |
1007 | int i; | |
1008 | ||
1009 | for (i = 0; i < sizeof(regtab)/sizeof(regtab[0]); i++) { | |
1010 | if (regtab[i].name == NULL) { | |
1011 | continue; | |
1012 | } | |
1013 | if (regtab[i].offset == 0) { | |
1014 | continue; | |
1015 | } | |
1016 | addr = intel_hda_reg_addr(d, regtab + i); | |
1017 | *addr = regtab[i].reset; | |
1018 | } | |
1019 | } | |
1020 | ||
1021 | /* --------------------------------------------------------------------- */ | |
1022 | ||
1023 | static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | |
1024 | { | |
1025 | IntelHDAState *d = opaque; | |
1026 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); | |
1027 | ||
1028 | intel_hda_reg_write(d, reg, val, 0xff); | |
1029 | } | |
1030 | ||
1031 | static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) | |
1032 | { | |
1033 | IntelHDAState *d = opaque; | |
1034 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); | |
1035 | ||
1036 | intel_hda_reg_write(d, reg, val, 0xffff); | |
1037 | } | |
1038 | ||
1039 | static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) | |
1040 | { | |
1041 | IntelHDAState *d = opaque; | |
1042 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); | |
1043 | ||
1044 | intel_hda_reg_write(d, reg, val, 0xffffffff); | |
1045 | } | |
1046 | ||
1047 | static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr) | |
1048 | { | |
1049 | IntelHDAState *d = opaque; | |
1050 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); | |
1051 | ||
1052 | return intel_hda_reg_read(d, reg, 0xff); | |
1053 | } | |
1054 | ||
1055 | static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr) | |
1056 | { | |
1057 | IntelHDAState *d = opaque; | |
1058 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); | |
1059 | ||
1060 | return intel_hda_reg_read(d, reg, 0xffff); | |
1061 | } | |
1062 | ||
1063 | static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr) | |
1064 | { | |
1065 | IntelHDAState *d = opaque; | |
1066 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); | |
1067 | ||
1068 | return intel_hda_reg_read(d, reg, 0xffffffff); | |
1069 | } | |
1070 | ||
1071 | static CPUReadMemoryFunc * const intel_hda_mmio_read[3] = { | |
1072 | intel_hda_mmio_readb, | |
1073 | intel_hda_mmio_readw, | |
1074 | intel_hda_mmio_readl, | |
1075 | }; | |
1076 | ||
1077 | static CPUWriteMemoryFunc * const intel_hda_mmio_write[3] = { | |
1078 | intel_hda_mmio_writeb, | |
1079 | intel_hda_mmio_writew, | |
1080 | intel_hda_mmio_writel, | |
1081 | }; | |
1082 | ||
1083 | static void intel_hda_map(PCIDevice *pci, int region_num, | |
1084 | pcibus_t addr, pcibus_t size, int type) | |
1085 | { | |
1086 | IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); | |
1087 | ||
1088 | cpu_register_physical_memory(addr, 0x4000, d->mmio_addr); | |
1089 | } | |
1090 | ||
1091 | /* --------------------------------------------------------------------- */ | |
1092 | ||
1093 | static void intel_hda_reset(DeviceState *dev) | |
1094 | { | |
1095 | IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev); | |
1096 | DeviceState *qdev; | |
1097 | HDACodecDevice *cdev; | |
1098 | ||
1099 | intel_hda_regs_reset(d); | |
1100 | d->wall_base_ns = qemu_get_clock(vm_clock); | |
1101 | ||
1102 | /* reset codecs */ | |
1103 | QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) { | |
1104 | cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); | |
1105 | if (qdev->info->reset) { | |
1106 | qdev->info->reset(qdev); | |
1107 | } | |
1108 | d->state_sts |= (1 << cdev->cad); | |
1109 | } | |
1110 | intel_hda_update_irq(d); | |
1111 | } | |
1112 | ||
1113 | static int intel_hda_init(PCIDevice *pci) | |
1114 | { | |
1115 | IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); | |
1116 | uint8_t *conf = d->pci.config; | |
1117 | ||
1118 | d->name = d->pci.qdev.info->name; | |
1119 | ||
1120 | pci_config_set_vendor_id(conf, PCI_VENDOR_ID_INTEL); | |
1121 | pci_config_set_device_id(conf, 0x2668); | |
1122 | pci_config_set_revision(conf, 1); | |
1123 | pci_config_set_class(conf, PCI_CLASS_MULTIMEDIA_HD_AUDIO); | |
1124 | pci_config_set_interrupt_pin(conf, 1); | |
1125 | ||
1126 | /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */ | |
1127 | conf[0x40] = 0x01; | |
1128 | ||
1129 | d->mmio_addr = cpu_register_io_memory(intel_hda_mmio_read, | |
1130 | intel_hda_mmio_write, d); | |
1131 | pci_register_bar(&d->pci, 0, 0x4000, PCI_BASE_ADDRESS_SPACE_MEMORY, | |
1132 | intel_hda_map); | |
1133 | ||
1134 | hda_codec_bus_init(&d->pci.qdev, &d->codecs, | |
1135 | intel_hda_response, intel_hda_xfer); | |
1136 | ||
1137 | return 0; | |
1138 | } | |
1139 | ||
1140 | static int intel_hda_post_load(void *opaque, int version) | |
1141 | { | |
1142 | IntelHDAState* d = opaque; | |
1143 | int i; | |
1144 | ||
1145 | dprint(d, 1, "%s\n", __FUNCTION__); | |
1146 | for (i = 0; i < ARRAY_SIZE(d->st); i++) { | |
1147 | if (d->st[i].ctl & 0x02) { | |
1148 | intel_hda_parse_bdl(d, &d->st[i]); | |
1149 | } | |
1150 | } | |
1151 | intel_hda_update_irq(d); | |
1152 | return 0; | |
1153 | } | |
1154 | ||
1155 | static const VMStateDescription vmstate_intel_hda_stream = { | |
1156 | .name = "intel-hda-stream", | |
1157 | .version_id = 1, | |
1158 | .fields = (VMStateField []) { | |
1159 | VMSTATE_UINT32(ctl, IntelHDAStream), | |
1160 | VMSTATE_UINT32(lpib, IntelHDAStream), | |
1161 | VMSTATE_UINT32(cbl, IntelHDAStream), | |
1162 | VMSTATE_UINT32(lvi, IntelHDAStream), | |
1163 | VMSTATE_UINT32(fmt, IntelHDAStream), | |
1164 | VMSTATE_UINT32(bdlp_lbase, IntelHDAStream), | |
1165 | VMSTATE_UINT32(bdlp_ubase, IntelHDAStream), | |
1166 | VMSTATE_END_OF_LIST() | |
1167 | } | |
1168 | }; | |
1169 | ||
1170 | static const VMStateDescription vmstate_intel_hda = { | |
1171 | .name = "intel-hda", | |
1172 | .version_id = 1, | |
1173 | .post_load = intel_hda_post_load, | |
1174 | .fields = (VMStateField []) { | |
1175 | VMSTATE_PCI_DEVICE(pci, IntelHDAState), | |
1176 | ||
1177 | /* registers */ | |
1178 | VMSTATE_UINT32(g_ctl, IntelHDAState), | |
1179 | VMSTATE_UINT32(wake_en, IntelHDAState), | |
1180 | VMSTATE_UINT32(state_sts, IntelHDAState), | |
1181 | VMSTATE_UINT32(int_ctl, IntelHDAState), | |
1182 | VMSTATE_UINT32(int_sts, IntelHDAState), | |
1183 | VMSTATE_UINT32(wall_clk, IntelHDAState), | |
1184 | VMSTATE_UINT32(corb_lbase, IntelHDAState), | |
1185 | VMSTATE_UINT32(corb_ubase, IntelHDAState), | |
1186 | VMSTATE_UINT32(corb_rp, IntelHDAState), | |
1187 | VMSTATE_UINT32(corb_wp, IntelHDAState), | |
1188 | VMSTATE_UINT32(corb_ctl, IntelHDAState), | |
1189 | VMSTATE_UINT32(corb_sts, IntelHDAState), | |
1190 | VMSTATE_UINT32(corb_size, IntelHDAState), | |
1191 | VMSTATE_UINT32(rirb_lbase, IntelHDAState), | |
1192 | VMSTATE_UINT32(rirb_ubase, IntelHDAState), | |
1193 | VMSTATE_UINT32(rirb_wp, IntelHDAState), | |
1194 | VMSTATE_UINT32(rirb_cnt, IntelHDAState), | |
1195 | VMSTATE_UINT32(rirb_ctl, IntelHDAState), | |
1196 | VMSTATE_UINT32(rirb_sts, IntelHDAState), | |
1197 | VMSTATE_UINT32(rirb_size, IntelHDAState), | |
1198 | VMSTATE_UINT32(dp_lbase, IntelHDAState), | |
1199 | VMSTATE_UINT32(dp_ubase, IntelHDAState), | |
1200 | VMSTATE_UINT32(icw, IntelHDAState), | |
1201 | VMSTATE_UINT32(irr, IntelHDAState), | |
1202 | VMSTATE_UINT32(ics, IntelHDAState), | |
1203 | VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0, | |
1204 | vmstate_intel_hda_stream, | |
1205 | IntelHDAStream), | |
1206 | ||
1207 | /* additional state info */ | |
1208 | VMSTATE_UINT32(rirb_count, IntelHDAState), | |
1209 | VMSTATE_INT64(wall_base_ns, IntelHDAState), | |
1210 | ||
1211 | VMSTATE_END_OF_LIST() | |
1212 | } | |
1213 | }; | |
1214 | ||
1215 | static PCIDeviceInfo intel_hda_info = { | |
1216 | .qdev.name = "intel-hda", | |
1217 | .qdev.desc = "Intel HD Audio Controller", | |
1218 | .qdev.size = sizeof(IntelHDAState), | |
1219 | .qdev.vmsd = &vmstate_intel_hda, | |
1220 | .qdev.reset = intel_hda_reset, | |
1221 | .init = intel_hda_init, | |
1222 | .qdev.props = (Property[]) { | |
1223 | DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0), | |
1224 | DEFINE_PROP_END_OF_LIST(), | |
1225 | } | |
1226 | }; | |
1227 | ||
1228 | static void intel_hda_register(void) | |
1229 | { | |
1230 | pci_qdev_register(&intel_hda_info); | |
1231 | } | |
1232 | device_init(intel_hda_register); | |
1233 | ||
1234 | /* | |
1235 | * create intel hda controller with codec attached to it, | |
1236 | * so '-soundhw hda' works. | |
1237 | */ | |
1238 | int intel_hda_and_codec_init(PCIBus *bus) | |
1239 | { | |
1240 | PCIDevice *controller; | |
1241 | BusState *hdabus; | |
1242 | DeviceState *codec; | |
1243 | ||
1244 | controller = pci_create_simple(bus, -1, "intel-hda"); | |
1245 | hdabus = QLIST_FIRST(&controller->qdev.child_bus); | |
1246 | codec = qdev_create(hdabus, "hda-duplex"); | |
1247 | qdev_init_nofail(codec); | |
1248 | return 0; | |
1249 | } | |
1250 |