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420557e8 FB |
1 | /* |
2 | * QEMU SPARC iommu emulation | |
3 | * | |
66321a11 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5fafdf24 | 5 | * |
420557e8 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "sun4m.h" | |
420557e8 FB |
26 | |
27 | /* debug iommu */ | |
28 | //#define DEBUG_IOMMU | |
29 | ||
66321a11 FB |
30 | #ifdef DEBUG_IOMMU |
31 | #define DPRINTF(fmt, args...) \ | |
32 | do { printf("IOMMU: " fmt , ##args); } while (0) | |
33 | #else | |
34 | #define DPRINTF(fmt, args...) | |
35 | #endif | |
420557e8 | 36 | |
e5e38121 | 37 | #define IOMMU_NREGS (4*4096/4) |
4e3b1ea1 | 38 | #define IOMMU_CTRL (0x0000 >> 2) |
420557e8 FB |
39 | #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ |
40 | #define IOMMU_CTRL_VERS 0x0f000000 /* Version */ | |
41 | #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */ | |
42 | #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */ | |
43 | #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */ | |
44 | #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */ | |
45 | #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */ | |
46 | #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */ | |
47 | #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */ | |
48 | #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */ | |
49 | #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */ | |
50 | #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */ | |
4e3b1ea1 FB |
51 | #define IOMMU_CTRL_MASK 0x0000001d |
52 | ||
53 | #define IOMMU_BASE (0x0004 >> 2) | |
54 | #define IOMMU_BASE_MASK 0x07fffc00 | |
55 | ||
56 | #define IOMMU_TLBFLUSH (0x0014 >> 2) | |
57 | #define IOMMU_TLBFLUSH_MASK 0xffffffff | |
58 | ||
59 | #define IOMMU_PGFLUSH (0x0018 >> 2) | |
60 | #define IOMMU_PGFLUSH_MASK 0xffffffff | |
61 | ||
225d4be7 BS |
62 | #define IOMMU_AFSR (0x1000 >> 2) |
63 | #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */ | |
5ad6bb97 BS |
64 | #define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after |
65 | transaction */ | |
66 | #define IOMMU_AFSR_TO 0x20000000 /* Write access took more than | |
67 | 12.8 us. */ | |
68 | #define IOMMU_AFSR_BE 0x10000000 /* Write access received error | |
69 | acknowledge */ | |
225d4be7 BS |
70 | #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */ |
71 | #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */ | |
5ad6bb97 BS |
72 | #define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by |
73 | hardware */ | |
225d4be7 BS |
74 | #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */ |
75 | #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */ | |
76 | #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */ | |
c52428fc | 77 | #define IOMMU_AFSR_MASK 0xff0fffff |
225d4be7 BS |
78 | |
79 | #define IOMMU_AFAR (0x1004 >> 2) | |
80 | ||
4e3b1ea1 FB |
81 | #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */ |
82 | #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ | |
83 | #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ | |
84 | #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */ | |
5ad6bb97 BS |
85 | #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when |
86 | bypass enabled */ | |
4e3b1ea1 FB |
87 | #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ |
88 | #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ | |
89 | #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses | |
f930d07e | 90 | produced by this device as pure |
4e3b1ea1 FB |
91 | physical. */ |
92 | #define IOMMU_SBCFG_MASK 0x00010003 | |
93 | ||
94 | #define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */ | |
95 | #define IOMMU_ARBEN_MASK 0x001f0000 | |
96 | #define IOMMU_MID 0x00000008 | |
420557e8 | 97 | |
e5e38121 BS |
98 | #define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */ |
99 | #define IOMMU_MASK_ID_MASK 0x00ffffff | |
100 | ||
101 | #define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */ | |
102 | #define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */ | |
103 | ||
420557e8 | 104 | /* The format of an iopte in the page tables */ |
498fbd8a | 105 | #define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */ |
5ad6bb97 BS |
106 | #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or |
107 | Viking/MXCC) */ | |
420557e8 FB |
108 | #define IOPTE_WRITE 0x00000004 /* Writeable */ |
109 | #define IOPTE_VALID 0x00000002 /* IOPTE is valid */ | |
110 | #define IOPTE_WAZ 0x00000001 /* Write as zeros */ | |
111 | ||
8b0de438 BS |
112 | #define IOMMU_PAGE_SHIFT 12 |
113 | #define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT) | |
114 | #define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1) | |
420557e8 FB |
115 | |
116 | typedef struct IOMMUState { | |
66321a11 | 117 | uint32_t regs[IOMMU_NREGS]; |
5dcb6b91 | 118 | target_phys_addr_t iostart; |
7fbfb139 | 119 | uint32_t version; |
ff403da6 | 120 | qemu_irq irq; |
420557e8 FB |
121 | } IOMMUState; |
122 | ||
7c560456 | 123 | static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr) |
420557e8 FB |
124 | { |
125 | IOMMUState *s = opaque; | |
5dcb6b91 | 126 | target_phys_addr_t saddr; |
ff403da6 | 127 | uint32_t ret; |
420557e8 | 128 | |
8da3ff18 | 129 | saddr = addr >> 2; |
420557e8 FB |
130 | switch (saddr) { |
131 | default: | |
ff403da6 BS |
132 | ret = s->regs[saddr]; |
133 | break; | |
134 | case IOMMU_AFAR: | |
135 | case IOMMU_AFSR: | |
136 | ret = s->regs[saddr]; | |
137 | qemu_irq_lower(s->irq); | |
f930d07e | 138 | break; |
420557e8 | 139 | } |
ff403da6 BS |
140 | DPRINTF("read reg[%d] = %x\n", (int)saddr, ret); |
141 | return ret; | |
420557e8 FB |
142 | } |
143 | ||
7c560456 | 144 | static void iommu_mem_writel(void *opaque, target_phys_addr_t addr, |
5ad6bb97 | 145 | uint32_t val) |
420557e8 FB |
146 | { |
147 | IOMMUState *s = opaque; | |
5dcb6b91 | 148 | target_phys_addr_t saddr; |
420557e8 | 149 | |
8da3ff18 | 150 | saddr = addr >> 2; |
981a2e99 | 151 | DPRINTF("write reg[%d] = %x\n", (int)saddr, val); |
420557e8 | 152 | switch (saddr) { |
4e3b1ea1 | 153 | case IOMMU_CTRL: |
f930d07e BS |
154 | switch (val & IOMMU_CTRL_RNGE) { |
155 | case IOMMU_RNGE_16MB: | |
156 | s->iostart = 0xffffffffff000000ULL; | |
157 | break; | |
158 | case IOMMU_RNGE_32MB: | |
159 | s->iostart = 0xfffffffffe000000ULL; | |
160 | break; | |
161 | case IOMMU_RNGE_64MB: | |
162 | s->iostart = 0xfffffffffc000000ULL; | |
163 | break; | |
164 | case IOMMU_RNGE_128MB: | |
165 | s->iostart = 0xfffffffff8000000ULL; | |
166 | break; | |
167 | case IOMMU_RNGE_256MB: | |
168 | s->iostart = 0xfffffffff0000000ULL; | |
169 | break; | |
170 | case IOMMU_RNGE_512MB: | |
171 | s->iostart = 0xffffffffe0000000ULL; | |
172 | break; | |
173 | case IOMMU_RNGE_1GB: | |
174 | s->iostart = 0xffffffffc0000000ULL; | |
175 | break; | |
176 | default: | |
177 | case IOMMU_RNGE_2GB: | |
178 | s->iostart = 0xffffffff80000000ULL; | |
179 | break; | |
180 | } | |
181 | DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart); | |
7fbfb139 | 182 | s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version); |
f930d07e | 183 | break; |
4e3b1ea1 | 184 | case IOMMU_BASE: |
f930d07e BS |
185 | s->regs[saddr] = val & IOMMU_BASE_MASK; |
186 | break; | |
4e3b1ea1 | 187 | case IOMMU_TLBFLUSH: |
f930d07e BS |
188 | DPRINTF("tlb flush %x\n", val); |
189 | s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; | |
190 | break; | |
4e3b1ea1 | 191 | case IOMMU_PGFLUSH: |
f930d07e BS |
192 | DPRINTF("page flush %x\n", val); |
193 | s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; | |
194 | break; | |
ff403da6 BS |
195 | case IOMMU_AFAR: |
196 | s->regs[saddr] = val; | |
197 | qemu_irq_lower(s->irq); | |
198 | break; | |
c52428fc BS |
199 | case IOMMU_AFSR: |
200 | s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV; | |
ff403da6 | 201 | qemu_irq_lower(s->irq); |
c52428fc | 202 | break; |
4e3b1ea1 FB |
203 | case IOMMU_SBCFG0: |
204 | case IOMMU_SBCFG1: | |
205 | case IOMMU_SBCFG2: | |
206 | case IOMMU_SBCFG3: | |
f930d07e BS |
207 | s->regs[saddr] = val & IOMMU_SBCFG_MASK; |
208 | break; | |
4e3b1ea1 FB |
209 | case IOMMU_ARBEN: |
210 | // XXX implement SBus probing: fault when reading unmapped | |
211 | // addresses, fault cause and address stored to MMU/IOMMU | |
f930d07e BS |
212 | s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; |
213 | break; | |
e5e38121 BS |
214 | case IOMMU_MASK_ID: |
215 | s->regs[saddr] |= val & IOMMU_MASK_ID_MASK; | |
216 | break; | |
420557e8 | 217 | default: |
f930d07e BS |
218 | s->regs[saddr] = val; |
219 | break; | |
420557e8 FB |
220 | } |
221 | } | |
222 | ||
223 | static CPUReadMemoryFunc *iommu_mem_read[3] = { | |
7c560456 BS |
224 | NULL, |
225 | NULL, | |
226 | iommu_mem_readl, | |
420557e8 FB |
227 | }; |
228 | ||
229 | static CPUWriteMemoryFunc *iommu_mem_write[3] = { | |
7c560456 BS |
230 | NULL, |
231 | NULL, | |
232 | iommu_mem_writel, | |
420557e8 FB |
233 | }; |
234 | ||
5dcb6b91 | 235 | static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr) |
420557e8 | 236 | { |
5e3b100b BS |
237 | uint32_t ret; |
238 | target_phys_addr_t iopte; | |
981a2e99 BS |
239 | #ifdef DEBUG_IOMMU |
240 | target_phys_addr_t pa = addr; | |
241 | #endif | |
420557e8 | 242 | |
981a2e99 | 243 | iopte = s->regs[IOMMU_BASE] << 4; |
66321a11 | 244 | addr &= ~s->iostart; |
8b0de438 | 245 | iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3; |
5e3b100b | 246 | cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4); |
748e4993 | 247 | tswap32s(&ret); |
5e3b100b BS |
248 | DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx |
249 | ", *pte = %x\n", pa, iopte, ret); | |
981a2e99 BS |
250 | |
251 | return ret; | |
a917d384 PB |
252 | } |
253 | ||
22548760 | 254 | static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr, |
5dcb6b91 | 255 | uint32_t pte) |
a917d384 PB |
256 | { |
257 | uint32_t tmppte; | |
5dcb6b91 BS |
258 | target_phys_addr_t pa; |
259 | ||
260 | tmppte = pte; | |
8b0de438 | 261 | pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK); |
5dcb6b91 BS |
262 | DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx |
263 | " (iopte = %x)\n", addr, pa, tmppte); | |
a917d384 | 264 | |
66321a11 | 265 | return pa; |
420557e8 FB |
266 | } |
267 | ||
5ad6bb97 BS |
268 | static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, |
269 | int is_write) | |
225d4be7 BS |
270 | { |
271 | DPRINTF("bad addr " TARGET_FMT_plx "\n", addr); | |
5ad6bb97 | 272 | s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV | |
225d4be7 BS |
273 | IOMMU_AFSR_FAV; |
274 | if (!is_write) | |
275 | s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD; | |
276 | s->regs[IOMMU_AFAR] = addr; | |
ff403da6 | 277 | qemu_irq_raise(s->irq); |
225d4be7 BS |
278 | } |
279 | ||
67e999be FB |
280 | void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
281 | uint8_t *buf, int len, int is_write) | |
a917d384 | 282 | { |
5dcb6b91 BS |
283 | int l; |
284 | uint32_t flags; | |
285 | target_phys_addr_t page, phys_addr; | |
a917d384 PB |
286 | |
287 | while (len > 0) { | |
8b0de438 BS |
288 | page = addr & IOMMU_PAGE_MASK; |
289 | l = (page + IOMMU_PAGE_SIZE) - addr; | |
a917d384 PB |
290 | if (l > len) |
291 | l = len; | |
292 | flags = iommu_page_get_flags(opaque, page); | |
225d4be7 BS |
293 | if (!(flags & IOPTE_VALID)) { |
294 | iommu_bad_addr(opaque, page, is_write); | |
a917d384 | 295 | return; |
225d4be7 | 296 | } |
22548760 | 297 | phys_addr = iommu_translate_pa(addr, flags); |
a917d384 | 298 | if (is_write) { |
225d4be7 BS |
299 | if (!(flags & IOPTE_WRITE)) { |
300 | iommu_bad_addr(opaque, page, is_write); | |
a917d384 | 301 | return; |
225d4be7 | 302 | } |
a5cdf952 | 303 | cpu_physical_memory_write(phys_addr, buf, l); |
a917d384 | 304 | } else { |
a5cdf952 | 305 | cpu_physical_memory_read(phys_addr, buf, l); |
a917d384 PB |
306 | } |
307 | len -= l; | |
308 | buf += l; | |
309 | addr += l; | |
310 | } | |
311 | } | |
312 | ||
e80cfcfc FB |
313 | static void iommu_save(QEMUFile *f, void *opaque) |
314 | { | |
315 | IOMMUState *s = opaque; | |
316 | int i; | |
3b46e624 | 317 | |
66321a11 | 318 | for (i = 0; i < IOMMU_NREGS; i++) |
f930d07e | 319 | qemu_put_be32s(f, &s->regs[i]); |
5dcb6b91 | 320 | qemu_put_be64s(f, &s->iostart); |
e80cfcfc FB |
321 | } |
322 | ||
323 | static int iommu_load(QEMUFile *f, void *opaque, int version_id) | |
324 | { | |
325 | IOMMUState *s = opaque; | |
326 | int i; | |
3b46e624 | 327 | |
5dcb6b91 | 328 | if (version_id != 2) |
e80cfcfc FB |
329 | return -EINVAL; |
330 | ||
66321a11 | 331 | for (i = 0; i < IOMMU_NREGS; i++) |
fda77c2d | 332 | qemu_get_be32s(f, &s->regs[i]); |
5dcb6b91 | 333 | qemu_get_be64s(f, &s->iostart); |
e80cfcfc FB |
334 | |
335 | return 0; | |
336 | } | |
337 | ||
338 | static void iommu_reset(void *opaque) | |
339 | { | |
340 | IOMMUState *s = opaque; | |
341 | ||
66321a11 | 342 | memset(s->regs, 0, IOMMU_NREGS * 4); |
e80cfcfc | 343 | s->iostart = 0; |
7fbfb139 BS |
344 | s->regs[IOMMU_CTRL] = s->version; |
345 | s->regs[IOMMU_ARBEN] = IOMMU_MID; | |
5ad6bb97 | 346 | s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; |
e5e38121 | 347 | s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; |
ff403da6 | 348 | qemu_irq_lower(s->irq); |
e80cfcfc FB |
349 | } |
350 | ||
ff403da6 | 351 | void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) |
420557e8 FB |
352 | { |
353 | IOMMUState *s; | |
8d5f07fa | 354 | int iommu_io_memory; |
420557e8 FB |
355 | |
356 | s = qemu_mallocz(sizeof(IOMMUState)); | |
357 | if (!s) | |
e80cfcfc | 358 | return NULL; |
420557e8 | 359 | |
7fbfb139 | 360 | s->version = version; |
ff403da6 | 361 | s->irq = irq; |
8d5f07fa | 362 | |
5ad6bb97 BS |
363 | iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, |
364 | iommu_mem_write, s); | |
66321a11 | 365 | cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory); |
3b46e624 | 366 | |
5dcb6b91 | 367 | register_savevm("iommu", addr, 2, iommu_save, iommu_load, s); |
e80cfcfc | 368 | qemu_register_reset(iommu_reset, s); |
7fbfb139 | 369 | iommu_reset(s); |
e80cfcfc | 370 | return s; |
420557e8 | 371 | } |