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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU MC146818 RTC emulation | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "qemu-timer.h" | |
26 | #include "sysemu.h" | |
27 | #include "pc.h" | |
28 | #include "isa.h" | |
16b29ae1 | 29 | #include "hpet_emul.h" |
80cabfad FB |
30 | |
31 | //#define DEBUG_CMOS | |
32 | ||
33 | #define RTC_SECONDS 0 | |
34 | #define RTC_SECONDS_ALARM 1 | |
35 | #define RTC_MINUTES 2 | |
36 | #define RTC_MINUTES_ALARM 3 | |
37 | #define RTC_HOURS 4 | |
38 | #define RTC_HOURS_ALARM 5 | |
39 | #define RTC_ALARM_DONT_CARE 0xC0 | |
40 | ||
41 | #define RTC_DAY_OF_WEEK 6 | |
42 | #define RTC_DAY_OF_MONTH 7 | |
43 | #define RTC_MONTH 8 | |
44 | #define RTC_YEAR 9 | |
45 | ||
46 | #define RTC_REG_A 10 | |
47 | #define RTC_REG_B 11 | |
48 | #define RTC_REG_C 12 | |
49 | #define RTC_REG_D 13 | |
50 | ||
dff38e7b | 51 | #define REG_A_UIP 0x80 |
80cabfad | 52 | |
100d9891 AJ |
53 | #define REG_B_SET 0x80 |
54 | #define REG_B_PIE 0x40 | |
55 | #define REG_B_AIE 0x20 | |
56 | #define REG_B_UIE 0x10 | |
57 | #define REG_B_SQWE 0x08 | |
58 | #define REG_B_DM 0x04 | |
dff38e7b | 59 | |
72716184 AL |
60 | #define REG_C_UF 0x10 |
61 | #define REG_C_IRQF 0x80 | |
62 | #define REG_C_PF 0x40 | |
63 | #define REG_C_AF 0x20 | |
64 | ||
dff38e7b | 65 | struct RTCState { |
32e0c826 | 66 | ISADevice dev; |
dff38e7b FB |
67 | uint8_t cmos_data[128]; |
68 | uint8_t cmos_index; | |
43f493af | 69 | struct tm current_tm; |
32e0c826 | 70 | int32_t base_year; |
d537cf6c | 71 | qemu_irq irq; |
100d9891 | 72 | qemu_irq sqw_irq; |
18c6e2ff | 73 | int it_shift; |
dff38e7b FB |
74 | /* periodic timer */ |
75 | QEMUTimer *periodic_timer; | |
76 | int64_t next_periodic_time; | |
77 | /* second update */ | |
78 | int64_t next_second_time; | |
73822ec8 AL |
79 | #ifdef TARGET_I386 |
80 | uint32_t irq_coalesced; | |
81 | uint32_t period; | |
93b66569 | 82 | QEMUTimer *coalesced_timer; |
73822ec8 | 83 | #endif |
dff38e7b FB |
84 | QEMUTimer *second_timer; |
85 | QEMUTimer *second_timer2; | |
86 | }; | |
87 | ||
16b29ae1 | 88 | static void rtc_irq_raise(qemu_irq irq) { |
c50c2d68 | 89 | /* When HPET is operating in legacy mode, RTC interrupts are disabled |
16b29ae1 | 90 | * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy |
c50c2d68 | 91 | * mode is established while interrupt is raised. We want it to |
16b29ae1 | 92 | * be lowered in any case |
c50c2d68 | 93 | */ |
16b29ae1 | 94 | #if defined TARGET_I386 || defined TARGET_X86_64 |
c50c2d68 | 95 | if (!hpet_in_legacy_mode()) |
16b29ae1 AL |
96 | #endif |
97 | qemu_irq_raise(irq); | |
98 | } | |
99 | ||
dff38e7b | 100 | static void rtc_set_time(RTCState *s); |
dff38e7b FB |
101 | static void rtc_copy_date(RTCState *s); |
102 | ||
93b66569 AL |
103 | #ifdef TARGET_I386 |
104 | static void rtc_coalesced_timer_update(RTCState *s) | |
105 | { | |
106 | if (s->irq_coalesced == 0) { | |
107 | qemu_del_timer(s->coalesced_timer); | |
108 | } else { | |
109 | /* divide each RTC interval to 2 - 8 smaller intervals */ | |
110 | int c = MIN(s->irq_coalesced, 7) + 1; | |
6875204c JK |
111 | int64_t next_clock = qemu_get_clock(rtc_clock) + |
112 | muldiv64(s->period / c, get_ticks_per_sec(), 32768); | |
93b66569 AL |
113 | qemu_mod_timer(s->coalesced_timer, next_clock); |
114 | } | |
115 | } | |
116 | ||
117 | static void rtc_coalesced_timer(void *opaque) | |
118 | { | |
119 | RTCState *s = opaque; | |
120 | ||
121 | if (s->irq_coalesced != 0) { | |
122 | apic_reset_irq_delivered(); | |
123 | s->cmos_data[RTC_REG_C] |= 0xc0; | |
124 | rtc_irq_raise(s->irq); | |
125 | if (apic_get_irq_delivered()) { | |
126 | s->irq_coalesced--; | |
127 | } | |
128 | } | |
129 | ||
130 | rtc_coalesced_timer_update(s); | |
131 | } | |
132 | #endif | |
133 | ||
dff38e7b FB |
134 | static void rtc_timer_update(RTCState *s, int64_t current_time) |
135 | { | |
136 | int period_code, period; | |
137 | int64_t cur_clock, next_irq_clock; | |
100d9891 | 138 | int enable_pie; |
dff38e7b FB |
139 | |
140 | period_code = s->cmos_data[RTC_REG_A] & 0x0f; | |
16b29ae1 | 141 | #if defined TARGET_I386 || defined TARGET_X86_64 |
c50c2d68 | 142 | /* disable periodic timer if hpet is in legacy mode, since interrupts are |
16b29ae1 AL |
143 | * disabled anyway. |
144 | */ | |
a8b01dd8 | 145 | enable_pie = !hpet_in_legacy_mode(); |
16b29ae1 | 146 | #else |
100d9891 | 147 | enable_pie = 1; |
16b29ae1 | 148 | #endif |
100d9891 AJ |
149 | if (period_code != 0 |
150 | && (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie) | |
151 | || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) { | |
dff38e7b FB |
152 | if (period_code <= 2) |
153 | period_code += 7; | |
154 | /* period in 32 Khz cycles */ | |
155 | period = 1 << (period_code - 1); | |
73822ec8 AL |
156 | #ifdef TARGET_I386 |
157 | if(period != s->period) | |
158 | s->irq_coalesced = (s->irq_coalesced * s->period) / period; | |
159 | s->period = period; | |
160 | #endif | |
dff38e7b | 161 | /* compute 32 khz clock */ |
6ee093c9 | 162 | cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec()); |
dff38e7b | 163 | next_irq_clock = (cur_clock & ~(period - 1)) + period; |
6875204c JK |
164 | s->next_periodic_time = |
165 | muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1; | |
dff38e7b FB |
166 | qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
167 | } else { | |
73822ec8 AL |
168 | #ifdef TARGET_I386 |
169 | s->irq_coalesced = 0; | |
170 | #endif | |
dff38e7b FB |
171 | qemu_del_timer(s->periodic_timer); |
172 | } | |
173 | } | |
174 | ||
175 | static void rtc_periodic_timer(void *opaque) | |
176 | { | |
177 | RTCState *s = opaque; | |
178 | ||
179 | rtc_timer_update(s, s->next_periodic_time); | |
100d9891 AJ |
180 | if (s->cmos_data[RTC_REG_B] & REG_B_PIE) { |
181 | s->cmos_data[RTC_REG_C] |= 0xc0; | |
93b66569 AL |
182 | #ifdef TARGET_I386 |
183 | if(rtc_td_hack) { | |
184 | apic_reset_irq_delivered(); | |
185 | rtc_irq_raise(s->irq); | |
186 | if (!apic_get_irq_delivered()) { | |
187 | s->irq_coalesced++; | |
188 | rtc_coalesced_timer_update(s); | |
189 | } | |
190 | } else | |
191 | #endif | |
100d9891 AJ |
192 | rtc_irq_raise(s->irq); |
193 | } | |
194 | if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) { | |
195 | /* Not square wave at all but we don't want 2048Hz interrupts! | |
196 | Must be seen as a pulse. */ | |
197 | qemu_irq_raise(s->sqw_irq); | |
198 | } | |
dff38e7b | 199 | } |
80cabfad | 200 | |
b41a2cd1 | 201 | static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
80cabfad | 202 | { |
b41a2cd1 | 203 | RTCState *s = opaque; |
80cabfad FB |
204 | |
205 | if ((addr & 1) == 0) { | |
206 | s->cmos_index = data & 0x7f; | |
207 | } else { | |
208 | #ifdef DEBUG_CMOS | |
209 | printf("cmos: write index=0x%02x val=0x%02x\n", | |
210 | s->cmos_index, data); | |
3b46e624 | 211 | #endif |
dff38e7b | 212 | switch(s->cmos_index) { |
80cabfad FB |
213 | case RTC_SECONDS_ALARM: |
214 | case RTC_MINUTES_ALARM: | |
215 | case RTC_HOURS_ALARM: | |
216 | /* XXX: not supported */ | |
217 | s->cmos_data[s->cmos_index] = data; | |
218 | break; | |
219 | case RTC_SECONDS: | |
220 | case RTC_MINUTES: | |
221 | case RTC_HOURS: | |
222 | case RTC_DAY_OF_WEEK: | |
223 | case RTC_DAY_OF_MONTH: | |
224 | case RTC_MONTH: | |
225 | case RTC_YEAR: | |
226 | s->cmos_data[s->cmos_index] = data; | |
dff38e7b FB |
227 | /* if in set mode, do not update the time */ |
228 | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { | |
229 | rtc_set_time(s); | |
230 | } | |
80cabfad FB |
231 | break; |
232 | case RTC_REG_A: | |
dff38e7b FB |
233 | /* UIP bit is read only */ |
234 | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | | |
235 | (s->cmos_data[RTC_REG_A] & REG_A_UIP); | |
6875204c | 236 | rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
dff38e7b | 237 | break; |
80cabfad | 238 | case RTC_REG_B: |
dff38e7b FB |
239 | if (data & REG_B_SET) { |
240 | /* set mode: reset UIP mode */ | |
241 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
242 | data &= ~REG_B_UIE; | |
243 | } else { | |
244 | /* if disabling set mode, update the time */ | |
245 | if (s->cmos_data[RTC_REG_B] & REG_B_SET) { | |
246 | rtc_set_time(s); | |
247 | } | |
248 | } | |
249 | s->cmos_data[RTC_REG_B] = data; | |
6875204c | 250 | rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
80cabfad FB |
251 | break; |
252 | case RTC_REG_C: | |
253 | case RTC_REG_D: | |
254 | /* cannot write to them */ | |
255 | break; | |
256 | default: | |
257 | s->cmos_data[s->cmos_index] = data; | |
258 | break; | |
259 | } | |
260 | } | |
261 | } | |
262 | ||
dff38e7b | 263 | static inline int to_bcd(RTCState *s, int a) |
80cabfad | 264 | { |
6f1bf24d | 265 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) { |
dff38e7b FB |
266 | return a; |
267 | } else { | |
268 | return ((a / 10) << 4) | (a % 10); | |
269 | } | |
80cabfad FB |
270 | } |
271 | ||
dff38e7b | 272 | static inline int from_bcd(RTCState *s, int a) |
80cabfad | 273 | { |
6f1bf24d | 274 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) { |
dff38e7b FB |
275 | return a; |
276 | } else { | |
277 | return ((a >> 4) * 10) + (a & 0x0f); | |
278 | } | |
279 | } | |
280 | ||
281 | static void rtc_set_time(RTCState *s) | |
282 | { | |
43f493af | 283 | struct tm *tm = &s->current_tm; |
dff38e7b FB |
284 | |
285 | tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]); | |
286 | tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]); | |
43f493af FB |
287 | tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f); |
288 | if (!(s->cmos_data[RTC_REG_B] & 0x02) && | |
289 | (s->cmos_data[RTC_HOURS] & 0x80)) { | |
290 | tm->tm_hour += 12; | |
291 | } | |
6f1bf24d | 292 | tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1; |
dff38e7b FB |
293 | tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
294 | tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1; | |
42fc73a1 | 295 | tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900; |
43f493af FB |
296 | } |
297 | ||
298 | static void rtc_copy_date(RTCState *s) | |
299 | { | |
300 | const struct tm *tm = &s->current_tm; | |
42fc73a1 | 301 | int year; |
dff38e7b | 302 | |
43f493af FB |
303 | s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec); |
304 | s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min); | |
305 | if (s->cmos_data[RTC_REG_B] & 0x02) { | |
306 | /* 24 hour format */ | |
307 | s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour); | |
308 | } else { | |
309 | /* 12 hour format */ | |
310 | s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12); | |
311 | if (tm->tm_hour >= 12) | |
312 | s->cmos_data[RTC_HOURS] |= 0x80; | |
313 | } | |
6f1bf24d | 314 | s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday + 1); |
43f493af FB |
315 | s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday); |
316 | s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1); | |
42fc73a1 AJ |
317 | year = (tm->tm_year - s->base_year) % 100; |
318 | if (year < 0) | |
319 | year += 100; | |
320 | s->cmos_data[RTC_YEAR] = to_bcd(s, year); | |
43f493af FB |
321 | } |
322 | ||
323 | /* month is between 0 and 11. */ | |
324 | static int get_days_in_month(int month, int year) | |
325 | { | |
5fafdf24 TS |
326 | static const int days_tab[12] = { |
327 | 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 | |
43f493af FB |
328 | }; |
329 | int d; | |
330 | if ((unsigned )month >= 12) | |
331 | return 31; | |
332 | d = days_tab[month]; | |
333 | if (month == 1) { | |
334 | if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) | |
335 | d++; | |
336 | } | |
337 | return d; | |
338 | } | |
339 | ||
340 | /* update 'tm' to the next second */ | |
341 | static void rtc_next_second(struct tm *tm) | |
342 | { | |
343 | int days_in_month; | |
344 | ||
345 | tm->tm_sec++; | |
346 | if ((unsigned)tm->tm_sec >= 60) { | |
347 | tm->tm_sec = 0; | |
348 | tm->tm_min++; | |
349 | if ((unsigned)tm->tm_min >= 60) { | |
350 | tm->tm_min = 0; | |
351 | tm->tm_hour++; | |
352 | if ((unsigned)tm->tm_hour >= 24) { | |
353 | tm->tm_hour = 0; | |
354 | /* next day */ | |
355 | tm->tm_wday++; | |
356 | if ((unsigned)tm->tm_wday >= 7) | |
357 | tm->tm_wday = 0; | |
5fafdf24 | 358 | days_in_month = get_days_in_month(tm->tm_mon, |
43f493af FB |
359 | tm->tm_year + 1900); |
360 | tm->tm_mday++; | |
361 | if (tm->tm_mday < 1) { | |
362 | tm->tm_mday = 1; | |
363 | } else if (tm->tm_mday > days_in_month) { | |
364 | tm->tm_mday = 1; | |
365 | tm->tm_mon++; | |
366 | if (tm->tm_mon >= 12) { | |
367 | tm->tm_mon = 0; | |
368 | tm->tm_year++; | |
369 | } | |
370 | } | |
371 | } | |
372 | } | |
373 | } | |
dff38e7b FB |
374 | } |
375 | ||
43f493af | 376 | |
dff38e7b FB |
377 | static void rtc_update_second(void *opaque) |
378 | { | |
379 | RTCState *s = opaque; | |
4721c457 | 380 | int64_t delay; |
dff38e7b FB |
381 | |
382 | /* if the oscillator is not in normal operation, we do not update */ | |
383 | if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { | |
6ee093c9 | 384 | s->next_second_time += get_ticks_per_sec(); |
dff38e7b FB |
385 | qemu_mod_timer(s->second_timer, s->next_second_time); |
386 | } else { | |
43f493af | 387 | rtc_next_second(&s->current_tm); |
3b46e624 | 388 | |
dff38e7b FB |
389 | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { |
390 | /* update in progress bit */ | |
391 | s->cmos_data[RTC_REG_A] |= REG_A_UIP; | |
392 | } | |
4721c457 FB |
393 | /* should be 244 us = 8 / 32768 seconds, but currently the |
394 | timers do not have the necessary resolution. */ | |
6ee093c9 | 395 | delay = (get_ticks_per_sec() * 1) / 100; |
4721c457 FB |
396 | if (delay < 1) |
397 | delay = 1; | |
5fafdf24 | 398 | qemu_mod_timer(s->second_timer2, |
4721c457 | 399 | s->next_second_time + delay); |
dff38e7b FB |
400 | } |
401 | } | |
402 | ||
403 | static void rtc_update_second2(void *opaque) | |
404 | { | |
405 | RTCState *s = opaque; | |
dff38e7b FB |
406 | |
407 | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { | |
408 | rtc_copy_date(s); | |
409 | } | |
410 | ||
411 | /* check alarm */ | |
412 | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) { | |
413 | if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 || | |
43f493af | 414 | s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) && |
dff38e7b | 415 | ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 || |
43f493af | 416 | s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) && |
dff38e7b | 417 | ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 || |
43f493af | 418 | s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) { |
dff38e7b | 419 | |
5fafdf24 | 420 | s->cmos_data[RTC_REG_C] |= 0xa0; |
16b29ae1 | 421 | rtc_irq_raise(s->irq); |
dff38e7b FB |
422 | } |
423 | } | |
424 | ||
425 | /* update ended interrupt */ | |
98815437 | 426 | s->cmos_data[RTC_REG_C] |= REG_C_UF; |
dff38e7b | 427 | if (s->cmos_data[RTC_REG_B] & REG_B_UIE) { |
98815437 BK |
428 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
429 | rtc_irq_raise(s->irq); | |
dff38e7b FB |
430 | } |
431 | ||
432 | /* clear update in progress bit */ | |
433 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
434 | ||
6ee093c9 | 435 | s->next_second_time += get_ticks_per_sec(); |
dff38e7b | 436 | qemu_mod_timer(s->second_timer, s->next_second_time); |
80cabfad FB |
437 | } |
438 | ||
b41a2cd1 | 439 | static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
80cabfad | 440 | { |
b41a2cd1 | 441 | RTCState *s = opaque; |
80cabfad FB |
442 | int ret; |
443 | if ((addr & 1) == 0) { | |
444 | return 0xff; | |
445 | } else { | |
446 | switch(s->cmos_index) { | |
447 | case RTC_SECONDS: | |
448 | case RTC_MINUTES: | |
449 | case RTC_HOURS: | |
450 | case RTC_DAY_OF_WEEK: | |
451 | case RTC_DAY_OF_MONTH: | |
452 | case RTC_MONTH: | |
453 | case RTC_YEAR: | |
80cabfad FB |
454 | ret = s->cmos_data[s->cmos_index]; |
455 | break; | |
456 | case RTC_REG_A: | |
457 | ret = s->cmos_data[s->cmos_index]; | |
80cabfad FB |
458 | break; |
459 | case RTC_REG_C: | |
460 | ret = s->cmos_data[s->cmos_index]; | |
d537cf6c | 461 | qemu_irq_lower(s->irq); |
5fafdf24 | 462 | s->cmos_data[RTC_REG_C] = 0x00; |
80cabfad FB |
463 | break; |
464 | default: | |
465 | ret = s->cmos_data[s->cmos_index]; | |
466 | break; | |
467 | } | |
468 | #ifdef DEBUG_CMOS | |
469 | printf("cmos: read index=0x%02x val=0x%02x\n", | |
470 | s->cmos_index, ret); | |
471 | #endif | |
472 | return ret; | |
473 | } | |
474 | } | |
475 | ||
dff38e7b FB |
476 | void rtc_set_memory(RTCState *s, int addr, int val) |
477 | { | |
478 | if (addr >= 0 && addr <= 127) | |
479 | s->cmos_data[addr] = val; | |
480 | } | |
481 | ||
482 | void rtc_set_date(RTCState *s, const struct tm *tm) | |
483 | { | |
43f493af | 484 | s->current_tm = *tm; |
dff38e7b FB |
485 | rtc_copy_date(s); |
486 | } | |
487 | ||
ea55ffb3 TS |
488 | /* PC cmos mappings */ |
489 | #define REG_IBM_CENTURY_BYTE 0x32 | |
490 | #define REG_IBM_PS2_CENTURY_BYTE 0x37 | |
491 | ||
9596ebb7 | 492 | static void rtc_set_date_from_host(RTCState *s) |
ea55ffb3 | 493 | { |
f6503059 | 494 | struct tm tm; |
ea55ffb3 TS |
495 | int val; |
496 | ||
497 | /* set the CMOS date */ | |
f6503059 AZ |
498 | qemu_get_timedate(&tm, 0); |
499 | rtc_set_date(s, &tm); | |
ea55ffb3 | 500 | |
f6503059 | 501 | val = to_bcd(s, (tm.tm_year / 100) + 19); |
ea55ffb3 TS |
502 | rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val); |
503 | rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val); | |
504 | } | |
505 | ||
dff38e7b FB |
506 | static void rtc_save(QEMUFile *f, void *opaque) |
507 | { | |
508 | RTCState *s = opaque; | |
509 | ||
510 | qemu_put_buffer(f, s->cmos_data, 128); | |
511 | qemu_put_8s(f, &s->cmos_index); | |
3b46e624 | 512 | |
bee8d684 TS |
513 | qemu_put_be32(f, s->current_tm.tm_sec); |
514 | qemu_put_be32(f, s->current_tm.tm_min); | |
515 | qemu_put_be32(f, s->current_tm.tm_hour); | |
516 | qemu_put_be32(f, s->current_tm.tm_wday); | |
517 | qemu_put_be32(f, s->current_tm.tm_mday); | |
518 | qemu_put_be32(f, s->current_tm.tm_mon); | |
519 | qemu_put_be32(f, s->current_tm.tm_year); | |
dff38e7b FB |
520 | |
521 | qemu_put_timer(f, s->periodic_timer); | |
bee8d684 | 522 | qemu_put_be64(f, s->next_periodic_time); |
dff38e7b | 523 | |
bee8d684 | 524 | qemu_put_be64(f, s->next_second_time); |
dff38e7b FB |
525 | qemu_put_timer(f, s->second_timer); |
526 | qemu_put_timer(f, s->second_timer2); | |
80cabfad FB |
527 | } |
528 | ||
dff38e7b | 529 | static int rtc_load(QEMUFile *f, void *opaque, int version_id) |
80cabfad | 530 | { |
dff38e7b FB |
531 | RTCState *s = opaque; |
532 | ||
533 | if (version_id != 1) | |
534 | return -EINVAL; | |
80cabfad | 535 | |
dff38e7b FB |
536 | qemu_get_buffer(f, s->cmos_data, 128); |
537 | qemu_get_8s(f, &s->cmos_index); | |
43f493af | 538 | |
bee8d684 TS |
539 | s->current_tm.tm_sec=qemu_get_be32(f); |
540 | s->current_tm.tm_min=qemu_get_be32(f); | |
541 | s->current_tm.tm_hour=qemu_get_be32(f); | |
542 | s->current_tm.tm_wday=qemu_get_be32(f); | |
543 | s->current_tm.tm_mday=qemu_get_be32(f); | |
544 | s->current_tm.tm_mon=qemu_get_be32(f); | |
545 | s->current_tm.tm_year=qemu_get_be32(f); | |
dff38e7b FB |
546 | |
547 | qemu_get_timer(f, s->periodic_timer); | |
bee8d684 | 548 | s->next_periodic_time=qemu_get_be64(f); |
dff38e7b | 549 | |
bee8d684 | 550 | s->next_second_time=qemu_get_be64(f); |
dff38e7b FB |
551 | qemu_get_timer(f, s->second_timer); |
552 | qemu_get_timer(f, s->second_timer2); | |
553 | return 0; | |
554 | } | |
555 | ||
73822ec8 AL |
556 | #ifdef TARGET_I386 |
557 | static void rtc_save_td(QEMUFile *f, void *opaque) | |
558 | { | |
559 | RTCState *s = opaque; | |
560 | ||
561 | qemu_put_be32(f, s->irq_coalesced); | |
562 | qemu_put_be32(f, s->period); | |
563 | } | |
564 | ||
565 | static int rtc_load_td(QEMUFile *f, void *opaque, int version_id) | |
566 | { | |
567 | RTCState *s = opaque; | |
568 | ||
569 | if (version_id != 1) | |
570 | return -EINVAL; | |
571 | ||
572 | s->irq_coalesced = qemu_get_be32(f); | |
573 | s->period = qemu_get_be32(f); | |
93b66569 | 574 | rtc_coalesced_timer_update(s); |
73822ec8 AL |
575 | return 0; |
576 | } | |
577 | #endif | |
578 | ||
eeb7c03c GN |
579 | static void rtc_reset(void *opaque) |
580 | { | |
581 | RTCState *s = opaque; | |
582 | ||
72716184 AL |
583 | s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
584 | s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); | |
eeb7c03c | 585 | |
72716184 | 586 | qemu_irq_lower(s->irq); |
eeb7c03c GN |
587 | |
588 | #ifdef TARGET_I386 | |
589 | if (rtc_td_hack) | |
590 | s->irq_coalesced = 0; | |
591 | #endif | |
592 | } | |
593 | ||
32e0c826 | 594 | static int rtc_initfn(ISADevice *dev) |
dff38e7b | 595 | { |
32e0c826 GH |
596 | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
597 | int base = 0x70; | |
598 | int isairq = 8; | |
dff38e7b | 599 | |
32e0c826 | 600 | isa_init_irq(dev, &s->irq, isairq); |
80cabfad | 601 | |
80cabfad FB |
602 | s->cmos_data[RTC_REG_A] = 0x26; |
603 | s->cmos_data[RTC_REG_B] = 0x02; | |
604 | s->cmos_data[RTC_REG_C] = 0x00; | |
605 | s->cmos_data[RTC_REG_D] = 0x80; | |
606 | ||
ea55ffb3 TS |
607 | rtc_set_date_from_host(s); |
608 | ||
6875204c | 609 | s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s); |
93b66569 AL |
610 | #ifdef TARGET_I386 |
611 | if (rtc_td_hack) | |
6875204c JK |
612 | s->coalesced_timer = |
613 | qemu_new_timer(rtc_clock, rtc_coalesced_timer, s); | |
93b66569 | 614 | #endif |
6875204c JK |
615 | s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s); |
616 | s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s); | |
dff38e7b | 617 | |
6875204c JK |
618 | s->next_second_time = |
619 | qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100; | |
dff38e7b FB |
620 | qemu_mod_timer(s->second_timer2, s->next_second_time); |
621 | ||
b41a2cd1 FB |
622 | register_ioport_write(base, 2, 1, cmos_ioport_write, s); |
623 | register_ioport_read(base, 2, 1, cmos_ioport_read, s); | |
dff38e7b FB |
624 | |
625 | register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s); | |
73822ec8 AL |
626 | #ifdef TARGET_I386 |
627 | if (rtc_td_hack) | |
628 | register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s); | |
629 | #endif | |
a08d4367 | 630 | qemu_register_reset(rtc_reset, s); |
32e0c826 GH |
631 | return 0; |
632 | } | |
633 | ||
634 | RTCState *rtc_init(int base_year) | |
635 | { | |
636 | ISADevice *dev; | |
eeb7c03c | 637 | |
32e0c826 GH |
638 | dev = isa_create("mc146818rtc"); |
639 | qdev_prop_set_int32(&dev->qdev, "base_year", base_year); | |
640 | qdev_init(&dev->qdev); | |
641 | return DO_UPCAST(RTCState, dev, dev); | |
80cabfad FB |
642 | } |
643 | ||
32e0c826 GH |
644 | static ISADeviceInfo mc146818rtc_info = { |
645 | .qdev.name = "mc146818rtc", | |
646 | .qdev.size = sizeof(RTCState), | |
647 | .qdev.no_user = 1, | |
648 | .init = rtc_initfn, | |
649 | .qdev.props = (Property[]) { | |
650 | DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), | |
651 | DEFINE_PROP_END_OF_LIST(), | |
652 | } | |
653 | }; | |
654 | ||
655 | static void mc146818rtc_register(void) | |
100d9891 | 656 | { |
32e0c826 | 657 | isa_qdev_register(&mc146818rtc_info); |
100d9891 | 658 | } |
32e0c826 | 659 | device_init(mc146818rtc_register) |
100d9891 | 660 | |
2ca9d013 | 661 | /* Memory mapped interface */ |
c227f099 | 662 | static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr) |
2ca9d013 TS |
663 | { |
664 | RTCState *s = opaque; | |
665 | ||
8da3ff18 | 666 | return cmos_ioport_read(s, addr >> s->it_shift) & 0xFF; |
2ca9d013 TS |
667 | } |
668 | ||
9596ebb7 | 669 | static void cmos_mm_writeb (void *opaque, |
c227f099 | 670 | target_phys_addr_t addr, uint32_t value) |
2ca9d013 TS |
671 | { |
672 | RTCState *s = opaque; | |
673 | ||
8da3ff18 | 674 | cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF); |
2ca9d013 TS |
675 | } |
676 | ||
c227f099 | 677 | static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr) |
2ca9d013 TS |
678 | { |
679 | RTCState *s = opaque; | |
18c6e2ff | 680 | uint32_t val; |
2ca9d013 | 681 | |
8da3ff18 | 682 | val = cmos_ioport_read(s, addr >> s->it_shift) & 0xFFFF; |
18c6e2ff TS |
683 | #ifdef TARGET_WORDS_BIGENDIAN |
684 | val = bswap16(val); | |
685 | #endif | |
686 | return val; | |
2ca9d013 TS |
687 | } |
688 | ||
9596ebb7 | 689 | static void cmos_mm_writew (void *opaque, |
c227f099 | 690 | target_phys_addr_t addr, uint32_t value) |
2ca9d013 TS |
691 | { |
692 | RTCState *s = opaque; | |
18c6e2ff TS |
693 | #ifdef TARGET_WORDS_BIGENDIAN |
694 | value = bswap16(value); | |
695 | #endif | |
8da3ff18 | 696 | cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF); |
2ca9d013 TS |
697 | } |
698 | ||
c227f099 | 699 | static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr) |
2ca9d013 TS |
700 | { |
701 | RTCState *s = opaque; | |
18c6e2ff | 702 | uint32_t val; |
2ca9d013 | 703 | |
8da3ff18 | 704 | val = cmos_ioport_read(s, addr >> s->it_shift); |
18c6e2ff TS |
705 | #ifdef TARGET_WORDS_BIGENDIAN |
706 | val = bswap32(val); | |
707 | #endif | |
708 | return val; | |
2ca9d013 TS |
709 | } |
710 | ||
9596ebb7 | 711 | static void cmos_mm_writel (void *opaque, |
c227f099 | 712 | target_phys_addr_t addr, uint32_t value) |
2ca9d013 TS |
713 | { |
714 | RTCState *s = opaque; | |
18c6e2ff TS |
715 | #ifdef TARGET_WORDS_BIGENDIAN |
716 | value = bswap32(value); | |
717 | #endif | |
8da3ff18 | 718 | cmos_ioport_write(s, addr >> s->it_shift, value); |
2ca9d013 TS |
719 | } |
720 | ||
d60efc6b | 721 | static CPUReadMemoryFunc * const rtc_mm_read[] = { |
2ca9d013 TS |
722 | &cmos_mm_readb, |
723 | &cmos_mm_readw, | |
724 | &cmos_mm_readl, | |
725 | }; | |
726 | ||
d60efc6b | 727 | static CPUWriteMemoryFunc * const rtc_mm_write[] = { |
2ca9d013 TS |
728 | &cmos_mm_writeb, |
729 | &cmos_mm_writew, | |
730 | &cmos_mm_writel, | |
731 | }; | |
732 | ||
c227f099 | 733 | RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, |
42fc73a1 | 734 | int base_year) |
2ca9d013 TS |
735 | { |
736 | RTCState *s; | |
737 | int io_memory; | |
738 | ||
739 | s = qemu_mallocz(sizeof(RTCState)); | |
2ca9d013 TS |
740 | |
741 | s->irq = irq; | |
742 | s->cmos_data[RTC_REG_A] = 0x26; | |
743 | s->cmos_data[RTC_REG_B] = 0x02; | |
744 | s->cmos_data[RTC_REG_C] = 0x00; | |
745 | s->cmos_data[RTC_REG_D] = 0x80; | |
2ca9d013 | 746 | |
42fc73a1 | 747 | s->base_year = base_year; |
2ca9d013 TS |
748 | rtc_set_date_from_host(s); |
749 | ||
6875204c JK |
750 | s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s); |
751 | s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s); | |
752 | s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s); | |
2ca9d013 | 753 | |
6875204c JK |
754 | s->next_second_time = |
755 | qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100; | |
2ca9d013 TS |
756 | qemu_mod_timer(s->second_timer2, s->next_second_time); |
757 | ||
1eed09cb | 758 | io_memory = cpu_register_io_memory(rtc_mm_read, rtc_mm_write, s); |
18c6e2ff | 759 | cpu_register_physical_memory(base, 2 << it_shift, io_memory); |
2ca9d013 TS |
760 | |
761 | register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s); | |
73822ec8 AL |
762 | #ifdef TARGET_I386 |
763 | if (rtc_td_hack) | |
764 | register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s); | |
765 | #endif | |
a08d4367 | 766 | qemu_register_reset(rtc_reset, s); |
2ca9d013 TS |
767 | return s; |
768 | } |