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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU MC146818 RTC emulation | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "qemu-timer.h" | |
26 | #include "sysemu.h" | |
27 | #include "pc.h" | |
28 | #include "isa.h" | |
16b29ae1 | 29 | #include "hpet_emul.h" |
80cabfad FB |
30 | |
31 | //#define DEBUG_CMOS | |
32 | ||
dd17765b | 33 | #define RTC_REINJECT_ON_ACK_COUNT 20 |
ba32edab | 34 | |
80cabfad FB |
35 | #define RTC_SECONDS 0 |
36 | #define RTC_SECONDS_ALARM 1 | |
37 | #define RTC_MINUTES 2 | |
38 | #define RTC_MINUTES_ALARM 3 | |
39 | #define RTC_HOURS 4 | |
40 | #define RTC_HOURS_ALARM 5 | |
41 | #define RTC_ALARM_DONT_CARE 0xC0 | |
42 | ||
43 | #define RTC_DAY_OF_WEEK 6 | |
44 | #define RTC_DAY_OF_MONTH 7 | |
45 | #define RTC_MONTH 8 | |
46 | #define RTC_YEAR 9 | |
47 | ||
48 | #define RTC_REG_A 10 | |
49 | #define RTC_REG_B 11 | |
50 | #define RTC_REG_C 12 | |
51 | #define RTC_REG_D 13 | |
52 | ||
dff38e7b | 53 | #define REG_A_UIP 0x80 |
80cabfad | 54 | |
100d9891 AJ |
55 | #define REG_B_SET 0x80 |
56 | #define REG_B_PIE 0x40 | |
57 | #define REG_B_AIE 0x20 | |
58 | #define REG_B_UIE 0x10 | |
59 | #define REG_B_SQWE 0x08 | |
60 | #define REG_B_DM 0x04 | |
dff38e7b | 61 | |
72716184 AL |
62 | #define REG_C_UF 0x10 |
63 | #define REG_C_IRQF 0x80 | |
64 | #define REG_C_PF 0x40 | |
65 | #define REG_C_AF 0x20 | |
66 | ||
dff38e7b | 67 | struct RTCState { |
32e0c826 | 68 | ISADevice dev; |
dff38e7b FB |
69 | uint8_t cmos_data[128]; |
70 | uint8_t cmos_index; | |
43f493af | 71 | struct tm current_tm; |
32e0c826 | 72 | int32_t base_year; |
d537cf6c | 73 | qemu_irq irq; |
100d9891 | 74 | qemu_irq sqw_irq; |
18c6e2ff | 75 | int it_shift; |
dff38e7b FB |
76 | /* periodic timer */ |
77 | QEMUTimer *periodic_timer; | |
78 | int64_t next_periodic_time; | |
79 | /* second update */ | |
80 | int64_t next_second_time; | |
ba32edab | 81 | uint16_t irq_reinject_on_ack_count; |
73822ec8 AL |
82 | uint32_t irq_coalesced; |
83 | uint32_t period; | |
93b66569 | 84 | QEMUTimer *coalesced_timer; |
dff38e7b FB |
85 | QEMUTimer *second_timer; |
86 | QEMUTimer *second_timer2; | |
87 | }; | |
88 | ||
e0ca7b94 JQ |
89 | static void rtc_irq_raise(qemu_irq irq) |
90 | { | |
c50c2d68 | 91 | /* When HPET is operating in legacy mode, RTC interrupts are disabled |
16b29ae1 | 92 | * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy |
c50c2d68 | 93 | * mode is established while interrupt is raised. We want it to |
16b29ae1 | 94 | * be lowered in any case |
c50c2d68 | 95 | */ |
ce88f890 | 96 | #if defined TARGET_I386 |
c50c2d68 | 97 | if (!hpet_in_legacy_mode()) |
16b29ae1 AL |
98 | #endif |
99 | qemu_irq_raise(irq); | |
100 | } | |
101 | ||
dff38e7b | 102 | static void rtc_set_time(RTCState *s); |
dff38e7b FB |
103 | static void rtc_copy_date(RTCState *s); |
104 | ||
93b66569 AL |
105 | #ifdef TARGET_I386 |
106 | static void rtc_coalesced_timer_update(RTCState *s) | |
107 | { | |
108 | if (s->irq_coalesced == 0) { | |
109 | qemu_del_timer(s->coalesced_timer); | |
110 | } else { | |
111 | /* divide each RTC interval to 2 - 8 smaller intervals */ | |
112 | int c = MIN(s->irq_coalesced, 7) + 1; | |
6875204c JK |
113 | int64_t next_clock = qemu_get_clock(rtc_clock) + |
114 | muldiv64(s->period / c, get_ticks_per_sec(), 32768); | |
93b66569 AL |
115 | qemu_mod_timer(s->coalesced_timer, next_clock); |
116 | } | |
117 | } | |
118 | ||
119 | static void rtc_coalesced_timer(void *opaque) | |
120 | { | |
121 | RTCState *s = opaque; | |
122 | ||
123 | if (s->irq_coalesced != 0) { | |
124 | apic_reset_irq_delivered(); | |
125 | s->cmos_data[RTC_REG_C] |= 0xc0; | |
126 | rtc_irq_raise(s->irq); | |
127 | if (apic_get_irq_delivered()) { | |
128 | s->irq_coalesced--; | |
129 | } | |
130 | } | |
131 | ||
132 | rtc_coalesced_timer_update(s); | |
133 | } | |
134 | #endif | |
135 | ||
dff38e7b FB |
136 | static void rtc_timer_update(RTCState *s, int64_t current_time) |
137 | { | |
138 | int period_code, period; | |
139 | int64_t cur_clock, next_irq_clock; | |
100d9891 | 140 | int enable_pie; |
dff38e7b FB |
141 | |
142 | period_code = s->cmos_data[RTC_REG_A] & 0x0f; | |
ce88f890 | 143 | #if defined TARGET_I386 |
c50c2d68 | 144 | /* disable periodic timer if hpet is in legacy mode, since interrupts are |
16b29ae1 AL |
145 | * disabled anyway. |
146 | */ | |
a8b01dd8 | 147 | enable_pie = !hpet_in_legacy_mode(); |
16b29ae1 | 148 | #else |
100d9891 | 149 | enable_pie = 1; |
16b29ae1 | 150 | #endif |
100d9891 AJ |
151 | if (period_code != 0 |
152 | && (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie) | |
153 | || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) { | |
dff38e7b FB |
154 | if (period_code <= 2) |
155 | period_code += 7; | |
156 | /* period in 32 Khz cycles */ | |
157 | period = 1 << (period_code - 1); | |
73822ec8 AL |
158 | #ifdef TARGET_I386 |
159 | if(period != s->period) | |
160 | s->irq_coalesced = (s->irq_coalesced * s->period) / period; | |
161 | s->period = period; | |
162 | #endif | |
dff38e7b | 163 | /* compute 32 khz clock */ |
6ee093c9 | 164 | cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec()); |
dff38e7b | 165 | next_irq_clock = (cur_clock & ~(period - 1)) + period; |
6875204c JK |
166 | s->next_periodic_time = |
167 | muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1; | |
dff38e7b FB |
168 | qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
169 | } else { | |
73822ec8 AL |
170 | #ifdef TARGET_I386 |
171 | s->irq_coalesced = 0; | |
172 | #endif | |
dff38e7b FB |
173 | qemu_del_timer(s->periodic_timer); |
174 | } | |
175 | } | |
176 | ||
177 | static void rtc_periodic_timer(void *opaque) | |
178 | { | |
179 | RTCState *s = opaque; | |
180 | ||
181 | rtc_timer_update(s, s->next_periodic_time); | |
100d9891 AJ |
182 | if (s->cmos_data[RTC_REG_B] & REG_B_PIE) { |
183 | s->cmos_data[RTC_REG_C] |= 0xc0; | |
93b66569 AL |
184 | #ifdef TARGET_I386 |
185 | if(rtc_td_hack) { | |
ba32edab GN |
186 | if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT) |
187 | s->irq_reinject_on_ack_count = 0; | |
93b66569 AL |
188 | apic_reset_irq_delivered(); |
189 | rtc_irq_raise(s->irq); | |
190 | if (!apic_get_irq_delivered()) { | |
191 | s->irq_coalesced++; | |
192 | rtc_coalesced_timer_update(s); | |
193 | } | |
194 | } else | |
195 | #endif | |
100d9891 AJ |
196 | rtc_irq_raise(s->irq); |
197 | } | |
198 | if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) { | |
199 | /* Not square wave at all but we don't want 2048Hz interrupts! | |
200 | Must be seen as a pulse. */ | |
201 | qemu_irq_raise(s->sqw_irq); | |
202 | } | |
dff38e7b | 203 | } |
80cabfad | 204 | |
b41a2cd1 | 205 | static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
80cabfad | 206 | { |
b41a2cd1 | 207 | RTCState *s = opaque; |
80cabfad FB |
208 | |
209 | if ((addr & 1) == 0) { | |
210 | s->cmos_index = data & 0x7f; | |
211 | } else { | |
212 | #ifdef DEBUG_CMOS | |
213 | printf("cmos: write index=0x%02x val=0x%02x\n", | |
214 | s->cmos_index, data); | |
3b46e624 | 215 | #endif |
dff38e7b | 216 | switch(s->cmos_index) { |
80cabfad FB |
217 | case RTC_SECONDS_ALARM: |
218 | case RTC_MINUTES_ALARM: | |
219 | case RTC_HOURS_ALARM: | |
220 | /* XXX: not supported */ | |
221 | s->cmos_data[s->cmos_index] = data; | |
222 | break; | |
223 | case RTC_SECONDS: | |
224 | case RTC_MINUTES: | |
225 | case RTC_HOURS: | |
226 | case RTC_DAY_OF_WEEK: | |
227 | case RTC_DAY_OF_MONTH: | |
228 | case RTC_MONTH: | |
229 | case RTC_YEAR: | |
230 | s->cmos_data[s->cmos_index] = data; | |
dff38e7b FB |
231 | /* if in set mode, do not update the time */ |
232 | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { | |
233 | rtc_set_time(s); | |
234 | } | |
80cabfad FB |
235 | break; |
236 | case RTC_REG_A: | |
dff38e7b FB |
237 | /* UIP bit is read only */ |
238 | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | | |
239 | (s->cmos_data[RTC_REG_A] & REG_A_UIP); | |
6875204c | 240 | rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
dff38e7b | 241 | break; |
80cabfad | 242 | case RTC_REG_B: |
dff38e7b FB |
243 | if (data & REG_B_SET) { |
244 | /* set mode: reset UIP mode */ | |
245 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
246 | data &= ~REG_B_UIE; | |
247 | } else { | |
248 | /* if disabling set mode, update the time */ | |
249 | if (s->cmos_data[RTC_REG_B] & REG_B_SET) { | |
250 | rtc_set_time(s); | |
251 | } | |
252 | } | |
253 | s->cmos_data[RTC_REG_B] = data; | |
6875204c | 254 | rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
80cabfad FB |
255 | break; |
256 | case RTC_REG_C: | |
257 | case RTC_REG_D: | |
258 | /* cannot write to them */ | |
259 | break; | |
260 | default: | |
261 | s->cmos_data[s->cmos_index] = data; | |
262 | break; | |
263 | } | |
264 | } | |
265 | } | |
266 | ||
abd0c6bd | 267 | static inline int rtc_to_bcd(RTCState *s, int a) |
80cabfad | 268 | { |
6f1bf24d | 269 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) { |
dff38e7b FB |
270 | return a; |
271 | } else { | |
272 | return ((a / 10) << 4) | (a % 10); | |
273 | } | |
80cabfad FB |
274 | } |
275 | ||
abd0c6bd | 276 | static inline int rtc_from_bcd(RTCState *s, int a) |
80cabfad | 277 | { |
6f1bf24d | 278 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) { |
dff38e7b FB |
279 | return a; |
280 | } else { | |
281 | return ((a >> 4) * 10) + (a & 0x0f); | |
282 | } | |
283 | } | |
284 | ||
285 | static void rtc_set_time(RTCState *s) | |
286 | { | |
43f493af | 287 | struct tm *tm = &s->current_tm; |
dff38e7b | 288 | |
abd0c6bd PB |
289 | tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
290 | tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); | |
291 | tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f); | |
43f493af FB |
292 | if (!(s->cmos_data[RTC_REG_B] & 0x02) && |
293 | (s->cmos_data[RTC_HOURS] & 0x80)) { | |
294 | tm->tm_hour += 12; | |
295 | } | |
abd0c6bd PB |
296 | tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1; |
297 | tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); | |
298 | tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1; | |
299 | tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900; | |
80cd3478 LC |
300 | |
301 | rtc_change_mon_event(tm); | |
43f493af FB |
302 | } |
303 | ||
304 | static void rtc_copy_date(RTCState *s) | |
305 | { | |
306 | const struct tm *tm = &s->current_tm; | |
42fc73a1 | 307 | int year; |
dff38e7b | 308 | |
abd0c6bd PB |
309 | s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec); |
310 | s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min); | |
43f493af FB |
311 | if (s->cmos_data[RTC_REG_B] & 0x02) { |
312 | /* 24 hour format */ | |
abd0c6bd | 313 | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour); |
43f493af FB |
314 | } else { |
315 | /* 12 hour format */ | |
abd0c6bd | 316 | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour % 12); |
43f493af FB |
317 | if (tm->tm_hour >= 12) |
318 | s->cmos_data[RTC_HOURS] |= 0x80; | |
319 | } | |
abd0c6bd PB |
320 | s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1); |
321 | s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday); | |
322 | s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1); | |
42fc73a1 AJ |
323 | year = (tm->tm_year - s->base_year) % 100; |
324 | if (year < 0) | |
325 | year += 100; | |
abd0c6bd | 326 | s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year); |
43f493af FB |
327 | } |
328 | ||
329 | /* month is between 0 and 11. */ | |
330 | static int get_days_in_month(int month, int year) | |
331 | { | |
5fafdf24 TS |
332 | static const int days_tab[12] = { |
333 | 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 | |
43f493af FB |
334 | }; |
335 | int d; | |
336 | if ((unsigned )month >= 12) | |
337 | return 31; | |
338 | d = days_tab[month]; | |
339 | if (month == 1) { | |
340 | if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) | |
341 | d++; | |
342 | } | |
343 | return d; | |
344 | } | |
345 | ||
346 | /* update 'tm' to the next second */ | |
347 | static void rtc_next_second(struct tm *tm) | |
348 | { | |
349 | int days_in_month; | |
350 | ||
351 | tm->tm_sec++; | |
352 | if ((unsigned)tm->tm_sec >= 60) { | |
353 | tm->tm_sec = 0; | |
354 | tm->tm_min++; | |
355 | if ((unsigned)tm->tm_min >= 60) { | |
356 | tm->tm_min = 0; | |
357 | tm->tm_hour++; | |
358 | if ((unsigned)tm->tm_hour >= 24) { | |
359 | tm->tm_hour = 0; | |
360 | /* next day */ | |
361 | tm->tm_wday++; | |
362 | if ((unsigned)tm->tm_wday >= 7) | |
363 | tm->tm_wday = 0; | |
5fafdf24 | 364 | days_in_month = get_days_in_month(tm->tm_mon, |
43f493af FB |
365 | tm->tm_year + 1900); |
366 | tm->tm_mday++; | |
367 | if (tm->tm_mday < 1) { | |
368 | tm->tm_mday = 1; | |
369 | } else if (tm->tm_mday > days_in_month) { | |
370 | tm->tm_mday = 1; | |
371 | tm->tm_mon++; | |
372 | if (tm->tm_mon >= 12) { | |
373 | tm->tm_mon = 0; | |
374 | tm->tm_year++; | |
375 | } | |
376 | } | |
377 | } | |
378 | } | |
379 | } | |
dff38e7b FB |
380 | } |
381 | ||
43f493af | 382 | |
dff38e7b FB |
383 | static void rtc_update_second(void *opaque) |
384 | { | |
385 | RTCState *s = opaque; | |
4721c457 | 386 | int64_t delay; |
dff38e7b FB |
387 | |
388 | /* if the oscillator is not in normal operation, we do not update */ | |
389 | if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { | |
6ee093c9 | 390 | s->next_second_time += get_ticks_per_sec(); |
dff38e7b FB |
391 | qemu_mod_timer(s->second_timer, s->next_second_time); |
392 | } else { | |
43f493af | 393 | rtc_next_second(&s->current_tm); |
3b46e624 | 394 | |
dff38e7b FB |
395 | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { |
396 | /* update in progress bit */ | |
397 | s->cmos_data[RTC_REG_A] |= REG_A_UIP; | |
398 | } | |
4721c457 FB |
399 | /* should be 244 us = 8 / 32768 seconds, but currently the |
400 | timers do not have the necessary resolution. */ | |
6ee093c9 | 401 | delay = (get_ticks_per_sec() * 1) / 100; |
4721c457 FB |
402 | if (delay < 1) |
403 | delay = 1; | |
5fafdf24 | 404 | qemu_mod_timer(s->second_timer2, |
4721c457 | 405 | s->next_second_time + delay); |
dff38e7b FB |
406 | } |
407 | } | |
408 | ||
409 | static void rtc_update_second2(void *opaque) | |
410 | { | |
411 | RTCState *s = opaque; | |
dff38e7b FB |
412 | |
413 | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { | |
414 | rtc_copy_date(s); | |
415 | } | |
416 | ||
417 | /* check alarm */ | |
418 | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) { | |
419 | if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 || | |
43f493af | 420 | s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) && |
dff38e7b | 421 | ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 || |
43f493af | 422 | s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) && |
dff38e7b | 423 | ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 || |
43f493af | 424 | s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) { |
dff38e7b | 425 | |
5fafdf24 | 426 | s->cmos_data[RTC_REG_C] |= 0xa0; |
16b29ae1 | 427 | rtc_irq_raise(s->irq); |
dff38e7b FB |
428 | } |
429 | } | |
430 | ||
431 | /* update ended interrupt */ | |
98815437 | 432 | s->cmos_data[RTC_REG_C] |= REG_C_UF; |
dff38e7b | 433 | if (s->cmos_data[RTC_REG_B] & REG_B_UIE) { |
98815437 BK |
434 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
435 | rtc_irq_raise(s->irq); | |
dff38e7b FB |
436 | } |
437 | ||
438 | /* clear update in progress bit */ | |
439 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
440 | ||
6ee093c9 | 441 | s->next_second_time += get_ticks_per_sec(); |
dff38e7b | 442 | qemu_mod_timer(s->second_timer, s->next_second_time); |
80cabfad FB |
443 | } |
444 | ||
b41a2cd1 | 445 | static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
80cabfad | 446 | { |
b41a2cd1 | 447 | RTCState *s = opaque; |
80cabfad FB |
448 | int ret; |
449 | if ((addr & 1) == 0) { | |
450 | return 0xff; | |
451 | } else { | |
452 | switch(s->cmos_index) { | |
453 | case RTC_SECONDS: | |
454 | case RTC_MINUTES: | |
455 | case RTC_HOURS: | |
456 | case RTC_DAY_OF_WEEK: | |
457 | case RTC_DAY_OF_MONTH: | |
458 | case RTC_MONTH: | |
459 | case RTC_YEAR: | |
80cabfad FB |
460 | ret = s->cmos_data[s->cmos_index]; |
461 | break; | |
462 | case RTC_REG_A: | |
463 | ret = s->cmos_data[s->cmos_index]; | |
80cabfad FB |
464 | break; |
465 | case RTC_REG_C: | |
466 | ret = s->cmos_data[s->cmos_index]; | |
d537cf6c | 467 | qemu_irq_lower(s->irq); |
ba32edab GN |
468 | #ifdef TARGET_I386 |
469 | if(s->irq_coalesced && | |
470 | s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) { | |
471 | s->irq_reinject_on_ack_count++; | |
472 | apic_reset_irq_delivered(); | |
473 | qemu_irq_raise(s->irq); | |
474 | if (apic_get_irq_delivered()) | |
475 | s->irq_coalesced--; | |
476 | break; | |
477 | } | |
478 | #endif | |
479 | ||
5fafdf24 | 480 | s->cmos_data[RTC_REG_C] = 0x00; |
80cabfad FB |
481 | break; |
482 | default: | |
483 | ret = s->cmos_data[s->cmos_index]; | |
484 | break; | |
485 | } | |
486 | #ifdef DEBUG_CMOS | |
487 | printf("cmos: read index=0x%02x val=0x%02x\n", | |
488 | s->cmos_index, ret); | |
489 | #endif | |
490 | return ret; | |
491 | } | |
492 | } | |
493 | ||
dff38e7b FB |
494 | void rtc_set_memory(RTCState *s, int addr, int val) |
495 | { | |
496 | if (addr >= 0 && addr <= 127) | |
497 | s->cmos_data[addr] = val; | |
498 | } | |
499 | ||
500 | void rtc_set_date(RTCState *s, const struct tm *tm) | |
501 | { | |
43f493af | 502 | s->current_tm = *tm; |
dff38e7b FB |
503 | rtc_copy_date(s); |
504 | } | |
505 | ||
ea55ffb3 TS |
506 | /* PC cmos mappings */ |
507 | #define REG_IBM_CENTURY_BYTE 0x32 | |
508 | #define REG_IBM_PS2_CENTURY_BYTE 0x37 | |
509 | ||
9596ebb7 | 510 | static void rtc_set_date_from_host(RTCState *s) |
ea55ffb3 | 511 | { |
f6503059 | 512 | struct tm tm; |
ea55ffb3 TS |
513 | int val; |
514 | ||
515 | /* set the CMOS date */ | |
f6503059 AZ |
516 | qemu_get_timedate(&tm, 0); |
517 | rtc_set_date(s, &tm); | |
ea55ffb3 | 518 | |
abd0c6bd | 519 | val = rtc_to_bcd(s, (tm.tm_year / 100) + 19); |
ea55ffb3 TS |
520 | rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val); |
521 | rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val); | |
522 | } | |
523 | ||
6b075b8a | 524 | static int rtc_post_load(void *opaque, int version_id) |
80cabfad | 525 | { |
6b075b8a | 526 | #ifdef TARGET_I386 |
dff38e7b FB |
527 | RTCState *s = opaque; |
528 | ||
048c74c4 | 529 | if (version_id >= 2) { |
048c74c4 JQ |
530 | if (rtc_td_hack) { |
531 | rtc_coalesced_timer_update(s); | |
532 | } | |
048c74c4 | 533 | } |
6b075b8a | 534 | #endif |
73822ec8 AL |
535 | return 0; |
536 | } | |
73822ec8 | 537 | |
6b075b8a JQ |
538 | static const VMStateDescription vmstate_rtc = { |
539 | .name = "mc146818rtc", | |
540 | .version_id = 2, | |
541 | .minimum_version_id = 1, | |
542 | .minimum_version_id_old = 1, | |
543 | .post_load = rtc_post_load, | |
544 | .fields = (VMStateField []) { | |
545 | VMSTATE_BUFFER(cmos_data, RTCState), | |
546 | VMSTATE_UINT8(cmos_index, RTCState), | |
547 | VMSTATE_INT32(current_tm.tm_sec, RTCState), | |
548 | VMSTATE_INT32(current_tm.tm_min, RTCState), | |
549 | VMSTATE_INT32(current_tm.tm_hour, RTCState), | |
550 | VMSTATE_INT32(current_tm.tm_wday, RTCState), | |
551 | VMSTATE_INT32(current_tm.tm_mday, RTCState), | |
552 | VMSTATE_INT32(current_tm.tm_mon, RTCState), | |
553 | VMSTATE_INT32(current_tm.tm_year, RTCState), | |
554 | VMSTATE_TIMER(periodic_timer, RTCState), | |
555 | VMSTATE_INT64(next_periodic_time, RTCState), | |
556 | VMSTATE_INT64(next_second_time, RTCState), | |
557 | VMSTATE_TIMER(second_timer, RTCState), | |
558 | VMSTATE_TIMER(second_timer2, RTCState), | |
559 | VMSTATE_UINT32_V(irq_coalesced, RTCState, 2), | |
560 | VMSTATE_UINT32_V(period, RTCState, 2), | |
561 | VMSTATE_END_OF_LIST() | |
562 | } | |
563 | }; | |
564 | ||
eeb7c03c GN |
565 | static void rtc_reset(void *opaque) |
566 | { | |
567 | RTCState *s = opaque; | |
568 | ||
72716184 AL |
569 | s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
570 | s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); | |
eeb7c03c | 571 | |
72716184 | 572 | qemu_irq_lower(s->irq); |
eeb7c03c GN |
573 | |
574 | #ifdef TARGET_I386 | |
575 | if (rtc_td_hack) | |
576 | s->irq_coalesced = 0; | |
577 | #endif | |
578 | } | |
579 | ||
32e0c826 | 580 | static int rtc_initfn(ISADevice *dev) |
dff38e7b | 581 | { |
32e0c826 GH |
582 | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
583 | int base = 0x70; | |
584 | int isairq = 8; | |
dff38e7b | 585 | |
32e0c826 | 586 | isa_init_irq(dev, &s->irq, isairq); |
80cabfad | 587 | |
80cabfad FB |
588 | s->cmos_data[RTC_REG_A] = 0x26; |
589 | s->cmos_data[RTC_REG_B] = 0x02; | |
590 | s->cmos_data[RTC_REG_C] = 0x00; | |
591 | s->cmos_data[RTC_REG_D] = 0x80; | |
592 | ||
ea55ffb3 TS |
593 | rtc_set_date_from_host(s); |
594 | ||
6875204c | 595 | s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s); |
93b66569 AL |
596 | #ifdef TARGET_I386 |
597 | if (rtc_td_hack) | |
6875204c JK |
598 | s->coalesced_timer = |
599 | qemu_new_timer(rtc_clock, rtc_coalesced_timer, s); | |
93b66569 | 600 | #endif |
6875204c JK |
601 | s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s); |
602 | s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s); | |
dff38e7b | 603 | |
6875204c JK |
604 | s->next_second_time = |
605 | qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100; | |
dff38e7b FB |
606 | qemu_mod_timer(s->second_timer2, s->next_second_time); |
607 | ||
b41a2cd1 FB |
608 | register_ioport_write(base, 2, 1, cmos_ioport_write, s); |
609 | register_ioport_read(base, 2, 1, cmos_ioport_read, s); | |
dff38e7b | 610 | |
6b075b8a | 611 | vmstate_register(base, &vmstate_rtc, s); |
a08d4367 | 612 | qemu_register_reset(rtc_reset, s); |
32e0c826 GH |
613 | return 0; |
614 | } | |
615 | ||
616 | RTCState *rtc_init(int base_year) | |
617 | { | |
618 | ISADevice *dev; | |
eeb7c03c | 619 | |
32e0c826 GH |
620 | dev = isa_create("mc146818rtc"); |
621 | qdev_prop_set_int32(&dev->qdev, "base_year", base_year); | |
e23a1b33 | 622 | qdev_init_nofail(&dev->qdev); |
32e0c826 | 623 | return DO_UPCAST(RTCState, dev, dev); |
80cabfad FB |
624 | } |
625 | ||
32e0c826 GH |
626 | static ISADeviceInfo mc146818rtc_info = { |
627 | .qdev.name = "mc146818rtc", | |
628 | .qdev.size = sizeof(RTCState), | |
629 | .qdev.no_user = 1, | |
630 | .init = rtc_initfn, | |
631 | .qdev.props = (Property[]) { | |
632 | DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), | |
633 | DEFINE_PROP_END_OF_LIST(), | |
634 | } | |
635 | }; | |
636 | ||
637 | static void mc146818rtc_register(void) | |
100d9891 | 638 | { |
32e0c826 | 639 | isa_qdev_register(&mc146818rtc_info); |
100d9891 | 640 | } |
32e0c826 | 641 | device_init(mc146818rtc_register) |