[mirror_qemu.git] / hw / mcf5208.c

/*
 * Motorola ColdFire MCF5208 SoC emulation.
 *
 * Copyright (c) 2007 CodeSourcery.
 *
 * This code is licenced under the GPL
 */
#include "vl.h"

#define SYS_FREQ 66000000

#define PCSR_EN         0x0001
#define PCSR_RLD        0x0002
#define PCSR_PIF        0x0004
#define PCSR_PIE        0x0008
#define PCSR_OVW        0x0010
#define PCSR_DBG        0x0020
#define PCSR_DOZE       0x0040
#define PCSR_PRE_SHIFT  8
#define PCSR_PRE_MASK   0x0f00

typedef struct {
    qemu_irq irq;
    ptimer_state *timer;
    uint16_t pcsr;
    uint16_t pmr;
    uint16_t pcntr;
} m5208_timer_state;

static void m5208_timer_update(m5208_timer_state *s)
{
    if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF))
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static void m5208_timer_write(m5208_timer_state *s, int offset,
                              uint32_t value)
{
    int prescale;
    int limit;
    switch (offset) {
    case 0:
        /* The PIF bit is set-to-clear.  */
        if (value & PCSR_PIF) {
            s->pcsr &= ~PCSR_PIF;
            value &= ~PCSR_PIF;
        }
        /* Avoid frobbing the timer if we're just twiddling IRQ bits. */
        if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) {
            s->pcsr = value;
            m5208_timer_update(s);
            return;
        }

        if (s->pcsr & PCSR_EN)
            ptimer_stop(s->timer);

        s->pcsr = value;

        prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
        ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
        if (s->pcsr & PCSR_RLD)
            limit = s->pmr;
        else
            limit = 0xffff;
        ptimer_set_limit(s->timer, limit, 0);

        if (s->pcsr & PCSR_EN)
            ptimer_run(s->timer, 0);
        break;
    case 2:
        s->pmr = value;
        s->pcsr &= ~PCSR_PIF;
        if ((s->pcsr & PCSR_RLD) == 0) {
            if (s->pcsr & PCSR_OVW)
                ptimer_set_count(s->timer, value);
        } else {
            ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW);
        }
        break;
    case 4:
        break;
    default:
        /* Should never happen.  */
        abort();
    }
    m5208_timer_update(s);
}

static void m5208_timer_trigger(void *opaque)
{
    m5208_timer_state *s = (m5208_timer_state *)opaque;
    s->pcsr |= PCSR_PIF;
    m5208_timer_update(s);
}

typedef struct {
    m5208_timer_state timer[2];
} m5208_sys_state;

static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
{
    m5208_sys_state *s = (m5208_sys_state *)opaque;
    switch (addr) {
    /* PIT0 */
    case 0xfc080000:
        return s->timer[0].pcsr;
    case 0xfc080002:
        return s->timer[0].pmr;
    case 0xfc080004:
        return ptimer_get_count(s->timer[0].timer);
    /* PIT1 */
    case 0xfc084000:
        return s->timer[1].pcsr;
    case 0xfc084002:
        return s->timer[1].pmr;
    case 0xfc084004:
        return ptimer_get_count(s->timer[1].timer);

    /* SDRAM Controller.  */
    case 0xfc0a8110: /* SDCS0 */
        {
            int n;
            for (n = 0; n < 32; n++) {
                if (ram_size < (2u << n))
                    break;
            }
            return (n - 1)  | 0x40000000;
        }
    case 0xfc0a8114: /* SDCS1 */
        return 0;

    default:
        cpu_abort(cpu_single_env, "m5208_sys_read: Bad offset 0x%x\n",
                  (int)addr);
        return 0;
    }
}

static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
                            uint32_t value)
{
    m5208_sys_state *s = (m5208_sys_state *)opaque;
    switch (addr) {
    /* PIT0 */
    case 0xfc080000:
    case 0xfc080002:
    case 0xfc080004:
        m5208_timer_write(&s->timer[0], addr & 0xf, value);
        return;
    /* PIT1 */
    case 0xfc084000:
    case 0xfc084002:
    case 0xfc084004:
        m5208_timer_write(&s->timer[1], addr & 0xf, value);
        return;
    default:
        cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n",
                  (int)addr);
        break;
    }
}

static CPUReadMemoryFunc *m5208_sys_readfn[] = {
   m5208_sys_read,
   m5208_sys_read,
   m5208_sys_read
};

static CPUWriteMemoryFunc *m5208_sys_writefn[] = {
   m5208_sys_write,
   m5208_sys_write,
   m5208_sys_write
};

static void mcf5208_sys_init(qemu_irq *pic)
{
    int iomemtype;
    m5208_sys_state *s;
    QEMUBH *bh;
    int i;

    s = (m5208_sys_state *)qemu_mallocz(sizeof(m5208_sys_state));
    iomemtype = cpu_register_io_memory(0, m5208_sys_readfn,
                                       m5208_sys_writefn, s);
    /* SDRAMC.  */
    cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype);
    /* Timers.  */
    for (i = 0; i < 2; i++) {
        bh = qemu_bh_new(m5208_timer_trigger, &s->timer[i]);
        s->timer[i].timer = ptimer_init(bh);
        cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000,
                                     iomemtype);
        s->timer[i].irq = pic[4 + i];
    }
}

static void mcf5208evb_init(int ram_size, int vga_ram_size, int boot_device,
                     DisplayState *ds, const char **fd_filename, int snapshot,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    CPUState *env;
    int kernel_size;
    uint64_t elf_entry;
    target_ulong entry;
    qemu_irq *pic;

    env = cpu_init();
    if (!cpu_model)
        cpu_model = "m5208";
    if (cpu_m68k_set_model(env, cpu_model)) {
        cpu_abort(env, "Unable to find m68k CPU definition\n");
    }

    /* Initialize CPU registers.  */
    env->vbr = 0;
    /* TODO: Configure BARs.  */

    /* DRAM at 0x20000000 */
    cpu_register_physical_memory(0x40000000, ram_size,
        qemu_ram_alloc(ram_size) | IO_MEM_RAM);

    /* Internal SRAM.  */
    cpu_register_physical_memory(0x80000000, 16384,
        qemu_ram_alloc(16384) | IO_MEM_RAM);

    /* Internal peripherals.  */
    pic = mcf_intc_init(0xfc048000, env);

    mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]);
    mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]);
    mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]);

    mcf5208_sys_init(pic);

    if (nb_nics > 1) {
        fprintf(stderr, "Too many NICs\n");
        exit(1);
    }
    if (nd_table[0].vlan) {
        if (nd_table[0].model == NULL
            || strcmp(nd_table[0].model, "mcf_fec") == 0) {
            mcf_fec_init(&nd_table[0], 0xfc030000, pic + 36);
        } else if (strcmp(nd_table[0].model, "?") == 0) {
            fprintf(stderr, "qemu: Supported NICs: mcf_fec\n");
            exit (1);
        } else {
            fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
            exit (1);
        }
    }

    /*  0xfc000000 SCM.  */
    /*  0xfc004000 XBS.  */
    /*  0xfc008000 FlexBus CS.  */
    /* 0xfc030000 FEC.  */
    /*  0xfc040000 SCM + Power management.  */
    /*  0xfc044000 eDMA.  */
    /* 0xfc048000 INTC.  */
    /*  0xfc058000 I2C.  */
    /*  0xfc05c000 QSPI.  */
    /* 0xfc060000 UART0.  */
    /* 0xfc064000 UART0.  */
    /* 0xfc068000 UART0.  */
    /*  0xfc070000 DMA timers.  */
    /* 0xfc080000 PIT0.  */
    /* 0xfc084000 PIT1.  */
    /*  0xfc088000 EPORT.  */
    /*  0xfc08c000 Watchdog.  */
    /*  0xfc090000 clock module.  */
    /*  0xfc0a0000 CCM + reset.  */
    /*  0xfc0a4000 GPIO.  */
    /* 0xfc0a8000 SDRAM controller.  */

    /* Load kernel.  */
    if (!kernel_filename) {
        fprintf(stderr, "Kernel image must be specified\n");
        exit(1);
    }

    kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL);
    entry = elf_entry;
    if (kernel_size < 0) {
        kernel_size = load_uboot(kernel_filename, &entry, NULL);
    }
    if (kernel_size < 0) {
        kernel_size = load_image(kernel_filename, phys_ram_base);
        entry = 0x20000000;
    }
    if (kernel_size < 0) {
        fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
        exit(1);
    }

    env->pc = entry;
}

QEMUMachine mcf5208evb_machine = {
    "mcf5208evb",
    "MCF5206EVB",
    mcf5208evb_init,
};
Commit	Line	Data
5fafdf24	1	/*
20dcee94 PB	2	* Motorola ColdFire MCF5208 SoC emulation.
	3	*
	4	* Copyright (c) 2007 CodeSourcery.
	5	*
	6	* This code is licenced under the GPL
	7	*/
	8	#include "vl.h"
	9
	10	#define SYS_FREQ 66000000
	11
	12	#define PCSR_EN 0x0001
	13	#define PCSR_RLD 0x0002
	14	#define PCSR_PIF 0x0004
	15	#define PCSR_PIE 0x0008
	16	#define PCSR_OVW 0x0010
	17	#define PCSR_DBG 0x0020
	18	#define PCSR_DOZE 0x0040
	19	#define PCSR_PRE_SHIFT 8
	20	#define PCSR_PRE_MASK 0x0f00
	21
	22	typedef struct {
	23	qemu_irq irq;
	24	ptimer_state *timer;
	25	uint16_t pcsr;
	26	uint16_t pmr;
	27	uint16_t pcntr;
	28	} m5208_timer_state;
	29
	30	static void m5208_timer_update(m5208_timer_state *s)
	31	{
	32	if ((s->pcsr & (PCSR_PIE \| PCSR_PIF)) == (PCSR_PIE \| PCSR_PIF))
	33	qemu_irq_raise(s->irq);
	34	else
	35	qemu_irq_lower(s->irq);
	36	}
	37
	38	static void m5208_timer_write(m5208_timer_state *s, int offset,
	39	uint32_t value)
	40	{
	41	int prescale;
	42	int limit;
	43	switch (offset) {
	44	case 0:
	45	/* The PIF bit is set-to-clear. */
	46	if (value & PCSR_PIF) {
	47	s->pcsr &= ~PCSR_PIF;
	48	value &= ~PCSR_PIF;
	49	}
	50	/* Avoid frobbing the timer if we're just twiddling IRQ bits. */
	51	if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) {
	52	s->pcsr = value;
	53	m5208_timer_update(s);
	54	return;
	55	}
	56
	57	if (s->pcsr & PCSR_EN)
	58	ptimer_stop(s->timer);
	59
	60	s->pcsr = value;
	61
	62	prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
	63	ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
	64	if (s->pcsr & PCSR_RLD)
20dcee94	65	limit = s->pmr;
6d9db39c PB	66	else
6d9db39c PB	67	limit = 0xffff;
20dcee94 PB	68	ptimer_set_limit(s->timer, limit, 0);
	69
	70	if (s->pcsr & PCSR_EN)
	71	ptimer_run(s->timer, 0);
	72	break;
	73	case 2:
	74	s->pmr = value;
	75	s->pcsr &= ~PCSR_PIF;
6d9db39c PB	76	if ((s->pcsr & PCSR_RLD) == 0) {
	77	if (s->pcsr & PCSR_OVW)
	78	ptimer_set_count(s->timer, value);
	79	} else {
	80	ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW);
	81	}
20dcee94 PB	82	break;
	83	case 4:
	84	break;
	85	default:
	86	/* Should never happen. */
	87	abort();
	88	}
	89	m5208_timer_update(s);
	90	}
	91
	92	static void m5208_timer_trigger(void *opaque)
	93	{
	94	m5208_timer_state s = (m5208_timer_state )opaque;
	95	s->pcsr \|= PCSR_PIF;
	96	m5208_timer_update(s);
	97	}
	98
	99	typedef struct {
	100	m5208_timer_state timer[2];
	101	} m5208_sys_state;
	102
	103	static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
	104	{
	105	m5208_sys_state s = (m5208_sys_state )opaque;
	106	switch (addr) {
	107	/* PIT0 */
	108	case 0xfc080000:
	109	return s->timer[0].pcsr;
	110	case 0xfc080002:
	111	return s->timer[0].pmr;
	112	case 0xfc080004:
	113	return ptimer_get_count(s->timer[0].timer);
	114	/* PIT1 */
	115	case 0xfc084000:
	116	return s->timer[1].pcsr;
	117	case 0xfc084002:
	118	return s->timer[1].pmr;
	119	case 0xfc084004:
	120	return ptimer_get_count(s->timer[1].timer);
	121
	122	/* SDRAM Controller. */
	123	case 0xfc0a8110: /* SDCS0 */
	124	{
	125	int n;
	126	for (n = 0; n < 32; n++) {
	127	if (ram_size < (2u << n))
	128	break;
	129	}
	130	return (n - 1) \| 0x40000000;
	131	}
	132	case 0xfc0a8114: /* SDCS1 */
	133	return 0;
	134
	135	default:
	136	cpu_abort(cpu_single_env, "m5208_sys_read: Bad offset 0x%x\n",
	137	(int)addr);
	138	return 0;
	139	}
	140	}
	141
	142	static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
	143	uint32_t value)
	144	{
	145	m5208_sys_state s = (m5208_sys_state )opaque;
146	switch (addr) {
147	/* PIT0 */
148	case 0xfc080000:
149	case 0xfc080002:
150	case 0xfc080004:
151	m5208_timer_write(&s->timer[0], addr & 0xf, value);
152	return;
153	/* PIT1 */
154	case 0xfc084000:
155	case 0xfc084002:
156	case 0xfc084004:
157	m5208_timer_write(&s->timer[1], addr & 0xf, value);
158	return;
159	default:
160	cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n",
161	(int)addr);
162	break;
163	}
164	}
165
166	static CPUReadMemoryFunc *m5208_sys_readfn[] = {
167	m5208_sys_read,
168	m5208_sys_read,
169	m5208_sys_read
170	};
171
172	static CPUWriteMemoryFunc *m5208_sys_writefn[] = {
173	m5208_sys_write,
174	m5208_sys_write,
175	m5208_sys_write
176	};
177
178	static void mcf5208_sys_init(qemu_irq *pic)
179	{
180	int iomemtype;
181	m5208_sys_state *s;
182	QEMUBH *bh;
183	int i;
184
185	s = (m5208_sys_state *)qemu_mallocz(sizeof(m5208_sys_state));
186	iomemtype = cpu_register_io_memory(0, m5208_sys_readfn,
187	m5208_sys_writefn, s);
188	/* SDRAMC. */
189	cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype);
190	/* Timers. */
191	for (i = 0; i < 2; i++) {
192	bh = qemu_bh_new(m5208_timer_trigger, &s->timer[i]);
193	s->timer[i].timer = ptimer_init(bh);
194	cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000,
195	iomemtype);
196	s->timer[i].irq = pic[4 + i];
197	}
198	}
199
200	static void mcf5208evb_init(int ram_size, int vga_ram_size, int boot_device,
201	DisplayState ds, const char *fd_filename, int snapshot,
202	const char kernel_filename, const char kernel_cmdline,
203	const char initrd_filename, const char cpu_model)
204	{
205	CPUState *env;
206	int kernel_size;
207	uint64_t elf_entry;
208	target_ulong entry;
209	qemu_irq *pic;
210
211	env = cpu_init();
212	if (!cpu_model)
213	cpu_model = "m5208";
214	if (cpu_m68k_set_model(env, cpu_model)) {
215	cpu_abort(env, "Unable to find m68k CPU definition\n");
216	}
217
218	/* Initialize CPU registers. */
219	env->vbr = 0;
220	/* TODO: Configure BARs. */
221
222	/* DRAM at 0x20000000 */
223	cpu_register_physical_memory(0x40000000, ram_size,
224	qemu_ram_alloc(ram_size) \| IO_MEM_RAM);
225
226	/* Internal SRAM. */
227	cpu_register_physical_memory(0x80000000, 16384,
228	qemu_ram_alloc(16384) \| IO_MEM_RAM);
229
230	/* Internal peripherals. */
231	pic = mcf_intc_init(0xfc048000, env);
232
233	mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]);
234	mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]);
235	mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]);
236
237	mcf5208_sys_init(pic);
238
7e049b8a PB	239	if (nb_nics > 1) {
	240	fprintf(stderr, "Too many NICs\n");
	241	exit(1);
	242	}
	243	if (nd_table[0].vlan) {
	244	if (nd_table[0].model == NULL
	245	\|\| strcmp(nd_table[0].model, "mcf_fec") == 0) {
	246	mcf_fec_init(&nd_table[0], 0xfc030000, pic + 36);
	247	} else if (strcmp(nd_table[0].model, "?") == 0) {
	248	fprintf(stderr, "qemu: Supported NICs: mcf_fec\n");
	249	exit (1);
	250	} else {
	251	fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
	252	exit (1);
	253	}
	254	}
	255
20dcee94 PB	256	/* 0xfc000000 SCM. */
	257	/* 0xfc004000 XBS. */
	258	/* 0xfc008000 FlexBus CS. */
7e049b8a	259	/* 0xfc030000 FEC. */
20dcee94 PB	260	/* 0xfc040000 SCM + Power management. */
	261	/* 0xfc044000 eDMA. */
	262	/* 0xfc048000 INTC. */
	263	/* 0xfc058000 I2C. */
	264	/* 0xfc05c000 QSPI. */
	265	/* 0xfc060000 UART0. */
	266	/* 0xfc064000 UART0. */
	267	/* 0xfc068000 UART0. */
	268	/* 0xfc070000 DMA timers. */
	269	/* 0xfc080000 PIT0. */
	270	/* 0xfc084000 PIT1. */
	271	/* 0xfc088000 EPORT. */
	272	/* 0xfc08c000 Watchdog. */
	273	/* 0xfc090000 clock module. */
	274	/* 0xfc0a0000 CCM + reset. */
	275	/* 0xfc0a4000 GPIO. */
	276	/* 0xfc0a8000 SDRAM controller. */
	277
	278	/* Load kernel. */
	279	if (!kernel_filename) {
	280	fprintf(stderr, "Kernel image must be specified\n");
	281	exit(1);
	282	}
	283
	284	kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL);
	285	entry = elf_entry;
	286	if (kernel_size < 0) {
	287	kernel_size = load_uboot(kernel_filename, &entry, NULL);
	288	}
	289	if (kernel_size < 0) {
	290	kernel_size = load_image(kernel_filename, phys_ram_base);
	291	entry = 0x20000000;
	292	}
	293	if (kernel_size < 0) {
	294	fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
	295	exit(1);
	296	}
	297
	298	env->pc = entry;
	299	}
	300
	301	QEMUMachine mcf5208evb_machine = {
	302	"mcf5208evb",
	303	"MCF5206EVB",
	304	mcf5208evb_init,
	305	};