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8e7e8a5b LA |
1 | /* |
2 | * Coherent Processing System emulation. | |
3 | * | |
4 | * Copyright (c) 2016 Imagination Technologies | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
d136ecc0 | 9 | * version 2.1 of the License, or (at your option) any later version. |
8e7e8a5b LA |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qapi/error.h" | |
0b8fa32f | 22 | #include "qemu/module.h" |
8e7e8a5b LA |
23 | #include "hw/mips/cps.h" |
24 | #include "hw/mips/mips.h" | |
e8373c56 | 25 | #include "hw/qdev-clock.h" |
a27bd6c7 | 26 | #include "hw/qdev-properties.h" |
8e7e8a5b | 27 | #include "hw/mips/cpudevs.h" |
40829435 | 28 | #include "sysemu/kvm.h" |
71e8a915 | 29 | #include "sysemu/reset.h" |
8e7e8a5b LA |
30 | |
31 | qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number) | |
32 | { | |
8e7e8a5b | 33 | assert(pin_number < s->num_irq); |
19494f81 | 34 | return s->gic.irq_state[pin_number].irq; |
8e7e8a5b LA |
35 | } |
36 | ||
37 | static void mips_cps_init(Object *obj) | |
38 | { | |
39 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
40 | MIPSCPSState *s = MIPS_CPS(obj); | |
41 | ||
5ee0abed | 42 | s->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, NULL, 0); |
f5c3fbfc AM |
43 | /* |
44 | * Cover entire address space as there do not seem to be any | |
45 | * constraints for the base address of CPC and GIC. | |
46 | */ | |
8e7e8a5b LA |
47 | memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX); |
48 | sysbus_init_mmio(sbd, &s->container); | |
49 | } | |
50 | ||
51 | static void main_cpu_reset(void *opaque) | |
52 | { | |
53 | MIPSCPU *cpu = opaque; | |
54 | CPUState *cs = CPU(cpu); | |
55 | ||
56 | cpu_reset(cs); | |
8e7e8a5b LA |
57 | } |
58 | ||
40829435 LA |
59 | static bool cpu_mips_itu_supported(CPUMIPSState *env) |
60 | { | |
17c2c320 | 61 | bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env); |
40829435 LA |
62 | |
63 | return is_mt && !kvm_enabled(); | |
64 | } | |
65 | ||
8e7e8a5b LA |
66 | static void mips_cps_realize(DeviceState *dev, Error **errp) |
67 | { | |
68 | MIPSCPSState *s = MIPS_CPS(dev); | |
69 | CPUMIPSState *env; | |
70 | MIPSCPU *cpu; | |
71 | int i; | |
a9bd9b5a | 72 | target_ulong gcr_base; |
40829435 | 73 | bool itu_present = false; |
043715d1 | 74 | bool saar_present = false; |
8e7e8a5b | 75 | |
ba25670c PMD |
76 | if (!clock_get(s->clock)) { |
77 | error_setg(errp, "CPS input clock is not connected to an output clock"); | |
78 | return; | |
79 | } | |
80 | ||
8e7e8a5b | 81 | for (i = 0; i < s->num_vp; i++) { |
102ca966 TJB |
82 | cpu = MIPS_CPU(object_new(s->cpu_type)); |
83 | ||
84 | /* All VPs are halted on reset. Leave powering up to CPC. */ | |
85 | if (!object_property_set_bool(OBJECT(cpu), "start-powered-off", true, | |
86 | errp)) { | |
87 | return; | |
88 | } | |
e8373c56 PMD |
89 | /* All cores use the same clock tree */ |
90 | qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock); | |
102ca966 TJB |
91 | |
92 | if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) { | |
93 | return; | |
94 | } | |
8e7e8a5b LA |
95 | |
96 | /* Init internal devices */ | |
5a975d43 PB |
97 | cpu_mips_irq_init_cpu(cpu); |
98 | cpu_mips_clock_init(cpu); | |
99 | ||
100 | env = &cpu->env; | |
40829435 LA |
101 | if (cpu_mips_itu_supported(env)) { |
102 | itu_present = true; | |
103 | /* Attach ITC Tag to the VP */ | |
104 | env->itc_tag = mips_itu_get_tag_region(&s->itu); | |
043715d1 | 105 | env->itu = &s->itu; |
40829435 | 106 | } |
8e7e8a5b LA |
107 | qemu_register_reset(main_cpu_reset, cpu); |
108 | } | |
a9bd9b5a LA |
109 | |
110 | cpu = MIPS_CPU(first_cpu); | |
111 | env = &cpu->env; | |
043715d1 | 112 | saar_present = (bool)env->saarp; |
a9bd9b5a | 113 | |
40829435 LA |
114 | /* Inter-Thread Communication Unit */ |
115 | if (itu_present) { | |
0074fce6 | 116 | object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU); |
5325cc34 | 117 | object_property_set_int(OBJECT(&s->itu), "num-fifo", 16, |
81f66cfd | 118 | &error_abort); |
5325cc34 | 119 | object_property_set_int(OBJECT(&s->itu), "num-semaphores", 16, |
81f66cfd | 120 | &error_abort); |
5325cc34 | 121 | object_property_set_bool(OBJECT(&s->itu), "saar-present", saar_present, |
81f66cfd | 122 | &error_abort); |
043715d1 | 123 | if (saar_present) { |
3cff8173 | 124 | s->itu.saar = &env->CP0_SAAR; |
043715d1 | 125 | } |
668f62ec | 126 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) { |
40829435 LA |
127 | return; |
128 | } | |
129 | ||
130 | memory_region_add_subregion(&s->container, 0, | |
131 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0)); | |
132 | } | |
133 | ||
2edd5261 | 134 | /* Cluster Power Controller */ |
0074fce6 | 135 | object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC); |
5325cc34 | 136 | object_property_set_int(OBJECT(&s->cpc), "num-vp", s->num_vp, |
81f66cfd | 137 | &error_abort); |
5325cc34 | 138 | object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1, |
81f66cfd | 139 | &error_abort); |
668f62ec | 140 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpc), errp)) { |
2edd5261 LA |
141 | return; |
142 | } | |
143 | ||
144 | memory_region_add_subregion(&s->container, 0, | |
145 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0)); | |
146 | ||
19494f81 | 147 | /* Global Interrupt Controller */ |
0074fce6 | 148 | object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC); |
5325cc34 | 149 | object_property_set_int(OBJECT(&s->gic), "num-vp", s->num_vp, |
81f66cfd | 150 | &error_abort); |
5325cc34 | 151 | object_property_set_int(OBJECT(&s->gic), "num-irq", 128, |
81f66cfd | 152 | &error_abort); |
668f62ec | 153 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { |
19494f81 LA |
154 | return; |
155 | } | |
156 | ||
157 | memory_region_add_subregion(&s->container, 0, | |
158 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0)); | |
159 | ||
a9bd9b5a LA |
160 | /* Global Configuration Registers */ |
161 | gcr_base = env->CP0_CMGCRBase << 4; | |
162 | ||
0074fce6 | 163 | object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); |
5325cc34 | 164 | object_property_set_int(OBJECT(&s->gcr), "num-vp", s->num_vp, |
81f66cfd | 165 | &error_abort); |
5325cc34 | 166 | object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800, |
81f66cfd | 167 | &error_abort); |
5325cc34 | 168 | object_property_set_int(OBJECT(&s->gcr), "gcr-base", gcr_base, |
81f66cfd | 169 | &error_abort); |
5325cc34 | 170 | object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr), |
2726dc51 | 171 | &error_abort); |
5325cc34 | 172 | object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr), |
2726dc51 | 173 | &error_abort); |
668f62ec | 174 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { |
a9bd9b5a LA |
175 | return; |
176 | } | |
177 | ||
178 | memory_region_add_subregion(&s->container, gcr_base, | |
179 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0)); | |
8e7e8a5b LA |
180 | } |
181 | ||
182 | static Property mips_cps_properties[] = { | |
183 | DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1), | |
19494f81 | 184 | DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256), |
a7519f2b | 185 | DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type), |
8e7e8a5b LA |
186 | DEFINE_PROP_END_OF_LIST() |
187 | }; | |
188 | ||
189 | static void mips_cps_class_init(ObjectClass *klass, void *data) | |
190 | { | |
191 | DeviceClass *dc = DEVICE_CLASS(klass); | |
192 | ||
193 | dc->realize = mips_cps_realize; | |
4f67d30b | 194 | device_class_set_props(dc, mips_cps_properties); |
8e7e8a5b LA |
195 | } |
196 | ||
197 | static const TypeInfo mips_cps_info = { | |
198 | .name = TYPE_MIPS_CPS, | |
199 | .parent = TYPE_SYS_BUS_DEVICE, | |
200 | .instance_size = sizeof(MIPSCPSState), | |
201 | .instance_init = mips_cps_init, | |
202 | .class_init = mips_cps_class_init, | |
203 | }; | |
204 | ||
205 | static void mips_cps_register_types(void) | |
206 | { | |
207 | type_register_static(&mips_cps_info); | |
208 | } | |
209 | ||
210 | type_init(mips_cps_register_types) |