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Commit | Line | Data |
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4ce7ff6e AJ |
1 | /* |
2 | * QEMU MIPS Jazz support | |
3 | * | |
4 | * Copyright (c) 2007-2008 Hervé Poussineau | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "hw.h" | |
26 | #include "mips.h" | |
b970ea8f | 27 | #include "mips_cpudevs.h" |
4ce7ff6e AJ |
28 | #include "pc.h" |
29 | #include "isa.h" | |
30 | #include "fdc.h" | |
31 | #include "sysemu.h" | |
0dfa5ef9 | 32 | #include "arch_init.h" |
4ce7ff6e AJ |
33 | #include "boards.h" |
34 | #include "net.h" | |
1cd3af54 | 35 | #include "esp.h" |
bba831e8 | 36 | #include "mips-bios.h" |
ca20cf32 | 37 | #include "loader.h" |
1d914fa0 | 38 | #include "mc146818rtc.h" |
b1277b03 | 39 | #include "i8254.h" |
302fe51b | 40 | #include "pcspk.h" |
2446333c | 41 | #include "blockdev.h" |
cd3e2409 | 42 | #include "sysbus.h" |
be20f9e9 | 43 | #include "exec-memory.h" |
4ce7ff6e | 44 | |
4ce7ff6e AJ |
45 | enum jazz_model_e |
46 | { | |
47 | JAZZ_MAGNUM, | |
c171148c | 48 | JAZZ_PICA61, |
4ce7ff6e AJ |
49 | }; |
50 | ||
51 | static void main_cpu_reset(void *opaque) | |
52 | { | |
61c56c8c | 53 | CPUMIPSState *env = opaque; |
1bba0dc9 | 54 | cpu_state_reset(env); |
4ce7ff6e AJ |
55 | } |
56 | ||
60581b37 | 57 | static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size) |
4ce7ff6e | 58 | { |
afcea8cb | 59 | return cpu_inw(0x71); |
4ce7ff6e AJ |
60 | } |
61 | ||
60581b37 AK |
62 | static void rtc_write(void *opaque, target_phys_addr_t addr, |
63 | uint64_t val, unsigned size) | |
4ce7ff6e | 64 | { |
afcea8cb | 65 | cpu_outw(0x71, val & 0xff); |
4ce7ff6e AJ |
66 | } |
67 | ||
60581b37 AK |
68 | static const MemoryRegionOps rtc_ops = { |
69 | .read = rtc_read, | |
70 | .write = rtc_write, | |
71 | .endianness = DEVICE_NATIVE_ENDIAN, | |
4ce7ff6e AJ |
72 | }; |
73 | ||
60581b37 AK |
74 | static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr, |
75 | unsigned size) | |
c6945b15 AJ |
76 | { |
77 | /* Nothing to do. That is only to ensure that | |
78 | * the current DMA acknowledge cycle is completed. */ | |
60581b37 | 79 | return 0xff; |
c6945b15 AJ |
80 | } |
81 | ||
60581b37 AK |
82 | static void dma_dummy_write(void *opaque, target_phys_addr_t addr, |
83 | uint64_t val, unsigned size) | |
84 | { | |
85 | /* Nothing to do. That is only to ensure that | |
86 | * the current DMA acknowledge cycle is completed. */ | |
87 | } | |
c6945b15 | 88 | |
60581b37 AK |
89 | static const MemoryRegionOps dma_dummy_ops = { |
90 | .read = dma_dummy_read, | |
91 | .write = dma_dummy_write, | |
92 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c6945b15 AJ |
93 | }; |
94 | ||
4ce7ff6e AJ |
95 | #define MAGNUM_BIOS_SIZE_MAX 0x7e000 |
96 | #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) | |
97 | ||
4556bd8b BS |
98 | static void cpu_request_exit(void *opaque, int irq, int level) |
99 | { | |
61c56c8c | 100 | CPUMIPSState *env = cpu_single_env; |
4556bd8b BS |
101 | |
102 | if (env && level) { | |
103 | cpu_exit(env); | |
104 | } | |
105 | } | |
106 | ||
c2d0d012 RH |
107 | static void mips_jazz_init(MemoryRegion *address_space, |
108 | MemoryRegion *address_space_io, | |
109 | ram_addr_t ram_size, | |
110 | const char *cpu_model, | |
111 | enum jazz_model_e jazz_model) | |
4ce7ff6e | 112 | { |
5cea8590 | 113 | char *filename; |
4ce7ff6e | 114 | int bios_size, n; |
61c56c8c | 115 | CPUMIPSState *env; |
4ce7ff6e | 116 | qemu_irq *rc4030, *i8259; |
c6945b15 | 117 | rc4030_dma *dmas; |
68238a9e | 118 | void* rc4030_opaque; |
60581b37 | 119 | MemoryRegion *rtc = g_new(MemoryRegion, 1); |
dbff76ac | 120 | MemoryRegion *i8042 = g_new(MemoryRegion, 1); |
60581b37 | 121 | MemoryRegion *dma_dummy = g_new(MemoryRegion, 1); |
a65f56ee | 122 | NICInfo *nd; |
cd3e2409 HP |
123 | DeviceState *dev; |
124 | SysBusDevice *sysbus; | |
48a18b3c | 125 | ISABus *isa_bus; |
64d7e9a4 | 126 | ISADevice *pit; |
fd8014e1 | 127 | DriveInfo *fds[MAX_FD]; |
73d74342 | 128 | qemu_irq esp_reset, dma_enable; |
4556bd8b | 129 | qemu_irq *cpu_exit_irq; |
60581b37 AK |
130 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
131 | MemoryRegion *bios = g_new(MemoryRegion, 1); | |
132 | MemoryRegion *bios2 = g_new(MemoryRegion, 1); | |
4ce7ff6e AJ |
133 | |
134 | /* init CPUs */ | |
135 | if (cpu_model == NULL) { | |
136 | #ifdef TARGET_MIPS64 | |
137 | cpu_model = "R4000"; | |
138 | #else | |
139 | /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */ | |
140 | cpu_model = "24Kf"; | |
141 | #endif | |
142 | } | |
143 | env = cpu_init(cpu_model); | |
144 | if (!env) { | |
145 | fprintf(stderr, "Unable to find CPU definition\n"); | |
146 | exit(1); | |
147 | } | |
a08d4367 | 148 | qemu_register_reset(main_cpu_reset, env); |
4ce7ff6e AJ |
149 | |
150 | /* allocate RAM */ | |
c5705a77 AK |
151 | memory_region_init_ram(ram, "mips_jazz.ram", ram_size); |
152 | vmstate_register_ram_global(ram); | |
60581b37 | 153 | memory_region_add_subregion(address_space, 0, ram); |
dcac9679 | 154 | |
c5705a77 AK |
155 | memory_region_init_ram(bios, "mips_jazz.bios", MAGNUM_BIOS_SIZE); |
156 | vmstate_register_ram_global(bios); | |
60581b37 AK |
157 | memory_region_set_readonly(bios, true); |
158 | memory_region_init_alias(bios2, "mips_jazz.bios", bios, | |
159 | 0, MAGNUM_BIOS_SIZE); | |
160 | memory_region_add_subregion(address_space, 0x1fc00000LL, bios); | |
161 | memory_region_add_subregion(address_space, 0xfff00000LL, bios2); | |
4ce7ff6e AJ |
162 | |
163 | /* load the BIOS image. */ | |
c6945b15 AJ |
164 | if (bios_name == NULL) |
165 | bios_name = BIOS_FILENAME; | |
5cea8590 PB |
166 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
167 | if (filename) { | |
168 | bios_size = load_image_targphys(filename, 0xfff00000LL, | |
169 | MAGNUM_BIOS_SIZE); | |
7267c094 | 170 | g_free(filename); |
5cea8590 PB |
171 | } else { |
172 | bios_size = -1; | |
173 | } | |
4ce7ff6e AJ |
174 | if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) { |
175 | fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n", | |
5cea8590 | 176 | bios_name); |
4ce7ff6e AJ |
177 | exit(1); |
178 | } | |
179 | ||
4ce7ff6e AJ |
180 | /* Init CPU internal devices */ |
181 | cpu_mips_irq_init_cpu(env); | |
182 | cpu_mips_clock_init(env); | |
183 | ||
184 | /* Chipset */ | |
3054434d AK |
185 | rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas, |
186 | address_space); | |
60581b37 AK |
187 | memory_region_init_io(dma_dummy, &dma_dummy_ops, NULL, "dummy_dma", 0x1000); |
188 | memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); | |
4ce7ff6e AJ |
189 | |
190 | /* ISA devices */ | |
48a18b3c HP |
191 | isa_bus = isa_bus_new(NULL, address_space_io); |
192 | i8259 = i8259_init(isa_bus, env->irq[4]); | |
193 | isa_bus_irqs(isa_bus, i8259); | |
4556bd8b BS |
194 | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
195 | DMA_init(0, cpu_exit_irq); | |
319ba9f5 | 196 | pit = pit_init(isa_bus, 0x40, 0, NULL); |
302fe51b | 197 | pcspk_init(isa_bus, pit); |
4ce7ff6e AJ |
198 | |
199 | /* ISA IO space at 0x90000000 */ | |
968d683c | 200 | isa_mmio_init(0x90000000, 0x01000000); |
4ce7ff6e AJ |
201 | isa_mem_base = 0x11000000; |
202 | ||
203 | /* Video card */ | |
204 | switch (jazz_model) { | |
205 | case JAZZ_MAGNUM: | |
97a3f6ff HP |
206 | dev = qdev_create(NULL, "sysbus-g364"); |
207 | qdev_init_nofail(dev); | |
208 | sysbus = sysbus_from_qdev(dev); | |
209 | sysbus_mmio_map(sysbus, 0, 0x60080000); | |
210 | sysbus_mmio_map(sysbus, 1, 0x40000000); | |
211 | sysbus_connect_irq(sysbus, 0, rc4030[3]); | |
212 | { | |
213 | /* Simple ROM, so user doesn't have to provide one */ | |
60581b37 | 214 | MemoryRegion *rom_mr = g_new(MemoryRegion, 1); |
c5705a77 AK |
215 | memory_region_init_ram(rom_mr, "g364fb.rom", 0x80000); |
216 | vmstate_register_ram_global(rom_mr); | |
60581b37 AK |
217 | memory_region_set_readonly(rom_mr, true); |
218 | uint8_t *rom = memory_region_get_ram_ptr(rom_mr); | |
219 | memory_region_add_subregion(address_space, 0x60000000, rom_mr); | |
97a3f6ff HP |
220 | rom[0] = 0x10; /* Mips G364 */ |
221 | } | |
4ce7ff6e | 222 | break; |
c171148c | 223 | case JAZZ_PICA61: |
be20f9e9 | 224 | isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory()); |
c171148c | 225 | break; |
4ce7ff6e AJ |
226 | default: |
227 | break; | |
228 | } | |
229 | ||
230 | /* Network controller */ | |
a65f56ee AJ |
231 | for (n = 0; n < nb_nics; n++) { |
232 | nd = &nd_table[n]; | |
233 | if (!nd->model) | |
7267c094 | 234 | nd->model = g_strdup("dp83932"); |
a65f56ee | 235 | if (strcmp(nd->model, "dp83932") == 0) { |
024e5bb6 | 236 | dp83932_init(nd, 0x80001000, 2, get_system_memory(), rc4030[4], |
a65f56ee AJ |
237 | rc4030_opaque, rc4030_dma_memory_rw); |
238 | break; | |
239 | } else if (strcmp(nd->model, "?") == 0) { | |
240 | fprintf(stderr, "qemu: Supported NICs: dp83932\n"); | |
241 | exit(1); | |
242 | } else { | |
243 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model); | |
244 | exit(1); | |
245 | } | |
246 | } | |
4ce7ff6e AJ |
247 | |
248 | /* SCSI adapter */ | |
cfb9de9c PB |
249 | esp_init(0x80002000, 0, |
250 | rc4030_dma_read, rc4030_dma_write, dmas[0], | |
73d74342 | 251 | rc4030[5], &esp_reset, &dma_enable); |
4ce7ff6e AJ |
252 | |
253 | /* Floppy */ | |
254 | if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) { | |
255 | fprintf(stderr, "qemu: too many floppy drives\n"); | |
256 | exit(1); | |
257 | } | |
258 | for (n = 0; n < MAX_FD; n++) { | |
fd8014e1 | 259 | fds[n] = drive_get(IF_FLOPPY, 0, n); |
4ce7ff6e | 260 | } |
2091ba23 | 261 | fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds); |
4ce7ff6e AJ |
262 | |
263 | /* Real time clock */ | |
48a18b3c | 264 | rtc_init(isa_bus, 1980, NULL); |
60581b37 AK |
265 | memory_region_init_io(rtc, &rtc_ops, NULL, "rtc", 0x1000); |
266 | memory_region_add_subregion(address_space, 0x80004000, rtc); | |
4ce7ff6e AJ |
267 | |
268 | /* Keyboard (i8042) */ | |
dbff76ac RH |
269 | i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1); |
270 | memory_region_add_subregion(address_space, 0x80005000, i8042); | |
4ce7ff6e AJ |
271 | |
272 | /* Serial ports */ | |
2d48377a | 273 | if (serial_hds[0]) { |
39186d8a RH |
274 | serial_mm_init(address_space, 0x80006000, 0, rc4030[8], 8000000/16, |
275 | serial_hds[0], DEVICE_NATIVE_ENDIAN); | |
2d48377a BS |
276 | } |
277 | if (serial_hds[1]) { | |
39186d8a RH |
278 | serial_mm_init(address_space, 0x80007000, 0, rc4030[9], 8000000/16, |
279 | serial_hds[1], DEVICE_NATIVE_ENDIAN); | |
2d48377a | 280 | } |
4ce7ff6e AJ |
281 | |
282 | /* Parallel port */ | |
283 | if (parallel_hds[0]) | |
63858cd9 AK |
284 | parallel_mm_init(address_space, 0x80008000, 0, rc4030[0], |
285 | parallel_hds[0]); | |
4ce7ff6e AJ |
286 | |
287 | /* Sound card */ | |
288 | /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ | |
4a0f031d | 289 | audio_init(isa_bus, NULL); |
4ce7ff6e | 290 | |
cd3e2409 HP |
291 | /* NVRAM */ |
292 | dev = qdev_create(NULL, "ds1225y"); | |
293 | qdev_init_nofail(dev); | |
294 | sysbus = sysbus_from_qdev(dev); | |
295 | sysbus_mmio_map(sysbus, 0, 0x80009000); | |
4ce7ff6e AJ |
296 | |
297 | /* LED indicator */ | |
b39506e4 | 298 | sysbus_create_simple("jazz-led", 0x8000f000, NULL); |
4ce7ff6e AJ |
299 | } |
300 | ||
301 | static | |
c227f099 | 302 | void mips_magnum_init (ram_addr_t ram_size, |
3023f332 | 303 | const char *boot_device, |
4ce7ff6e AJ |
304 | const char *kernel_filename, const char *kernel_cmdline, |
305 | const char *initrd_filename, const char *cpu_model) | |
306 | { | |
c2d0d012 RH |
307 | mips_jazz_init(get_system_memory(), get_system_io(), |
308 | ram_size, cpu_model, JAZZ_MAGNUM); | |
4ce7ff6e AJ |
309 | } |
310 | ||
c171148c | 311 | static |
c227f099 | 312 | void mips_pica61_init (ram_addr_t ram_size, |
3023f332 | 313 | const char *boot_device, |
c171148c AJ |
314 | const char *kernel_filename, const char *kernel_cmdline, |
315 | const char *initrd_filename, const char *cpu_model) | |
316 | { | |
c2d0d012 RH |
317 | mips_jazz_init(get_system_memory(), get_system_io(), |
318 | ram_size, cpu_model, JAZZ_PICA61); | |
c171148c AJ |
319 | } |
320 | ||
f80f9ec9 | 321 | static QEMUMachine mips_magnum_machine = { |
eec2743e TS |
322 | .name = "magnum", |
323 | .desc = "MIPS Magnum", | |
324 | .init = mips_magnum_init, | |
c6945b15 | 325 | .use_scsi = 1, |
4ce7ff6e | 326 | }; |
c171148c | 327 | |
f80f9ec9 | 328 | static QEMUMachine mips_pica61_machine = { |
eec2743e TS |
329 | .name = "pica61", |
330 | .desc = "Acer Pica 61", | |
331 | .init = mips_pica61_init, | |
c6945b15 | 332 | .use_scsi = 1, |
c171148c | 333 | }; |
f80f9ec9 AL |
334 | |
335 | static void mips_jazz_machine_init(void) | |
336 | { | |
337 | qemu_register_machine(&mips_magnum_machine); | |
338 | qemu_register_machine(&mips_pica61_machine); | |
339 | } | |
340 | ||
341 | machine_init(mips_jazz_machine_init); |