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4ce7ff6e AJ |
1 | /* |
2 | * QEMU MIPS Jazz support | |
3 | * | |
4 | * Copyright (c) 2007-2008 Hervé Poussineau | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "hw.h" | |
26 | #include "mips.h" | |
b970ea8f | 27 | #include "mips_cpudevs.h" |
4ce7ff6e AJ |
28 | #include "pc.h" |
29 | #include "isa.h" | |
30 | #include "fdc.h" | |
31 | #include "sysemu.h" | |
0dfa5ef9 | 32 | #include "arch_init.h" |
4ce7ff6e AJ |
33 | #include "boards.h" |
34 | #include "net.h" | |
1cd3af54 | 35 | #include "esp.h" |
bba831e8 | 36 | #include "mips-bios.h" |
ca20cf32 | 37 | #include "loader.h" |
1d914fa0 | 38 | #include "mc146818rtc.h" |
2446333c | 39 | #include "blockdev.h" |
4ce7ff6e | 40 | |
4ce7ff6e AJ |
41 | enum jazz_model_e |
42 | { | |
43 | JAZZ_MAGNUM, | |
c171148c | 44 | JAZZ_PICA61, |
4ce7ff6e AJ |
45 | }; |
46 | ||
47 | static void main_cpu_reset(void *opaque) | |
48 | { | |
49 | CPUState *env = opaque; | |
50 | cpu_reset(env); | |
51 | } | |
52 | ||
c227f099 | 53 | static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr) |
4ce7ff6e | 54 | { |
afcea8cb | 55 | return cpu_inw(0x71); |
4ce7ff6e AJ |
56 | } |
57 | ||
c227f099 | 58 | static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
4ce7ff6e | 59 | { |
afcea8cb | 60 | cpu_outw(0x71, val & 0xff); |
4ce7ff6e AJ |
61 | } |
62 | ||
d60efc6b | 63 | static CPUReadMemoryFunc * const rtc_read[3] = { |
4ce7ff6e AJ |
64 | rtc_readb, |
65 | rtc_readb, | |
66 | rtc_readb, | |
67 | }; | |
68 | ||
d60efc6b | 69 | static CPUWriteMemoryFunc * const rtc_write[3] = { |
4ce7ff6e AJ |
70 | rtc_writeb, |
71 | rtc_writeb, | |
72 | rtc_writeb, | |
73 | }; | |
74 | ||
c227f099 | 75 | static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
c6945b15 AJ |
76 | { |
77 | /* Nothing to do. That is only to ensure that | |
78 | * the current DMA acknowledge cycle is completed. */ | |
79 | } | |
80 | ||
d60efc6b | 81 | static CPUReadMemoryFunc * const dma_dummy_read[3] = { |
c6945b15 AJ |
82 | NULL, |
83 | NULL, | |
84 | NULL, | |
85 | }; | |
86 | ||
d60efc6b | 87 | static CPUWriteMemoryFunc * const dma_dummy_write[3] = { |
c6945b15 AJ |
88 | dma_dummy_writeb, |
89 | dma_dummy_writeb, | |
90 | dma_dummy_writeb, | |
91 | }; | |
92 | ||
4ce7ff6e AJ |
93 | #define MAGNUM_BIOS_SIZE_MAX 0x7e000 |
94 | #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) | |
95 | ||
4556bd8b BS |
96 | static void cpu_request_exit(void *opaque, int irq, int level) |
97 | { | |
98 | CPUState *env = cpu_single_env; | |
99 | ||
100 | if (env && level) { | |
101 | cpu_exit(env); | |
102 | } | |
103 | } | |
104 | ||
4ce7ff6e | 105 | static |
c227f099 | 106 | void mips_jazz_init (ram_addr_t ram_size, |
3023f332 | 107 | const char *cpu_model, |
4ce7ff6e AJ |
108 | enum jazz_model_e jazz_model) |
109 | { | |
5cea8590 | 110 | char *filename; |
4ce7ff6e AJ |
111 | int bios_size, n; |
112 | CPUState *env; | |
113 | qemu_irq *rc4030, *i8259; | |
c6945b15 | 114 | rc4030_dma *dmas; |
68238a9e | 115 | void* rc4030_opaque; |
c6945b15 | 116 | int s_rtc, s_dma_dummy; |
a65f56ee | 117 | NICInfo *nd; |
4ce7ff6e | 118 | PITState *pit; |
fd8014e1 | 119 | DriveInfo *fds[MAX_FD]; |
73d74342 | 120 | qemu_irq esp_reset, dma_enable; |
4556bd8b | 121 | qemu_irq *cpu_exit_irq; |
c227f099 AL |
122 | ram_addr_t ram_offset; |
123 | ram_addr_t bios_offset; | |
4ce7ff6e AJ |
124 | |
125 | /* init CPUs */ | |
126 | if (cpu_model == NULL) { | |
127 | #ifdef TARGET_MIPS64 | |
128 | cpu_model = "R4000"; | |
129 | #else | |
130 | /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */ | |
131 | cpu_model = "24Kf"; | |
132 | #endif | |
133 | } | |
134 | env = cpu_init(cpu_model); | |
135 | if (!env) { | |
136 | fprintf(stderr, "Unable to find CPU definition\n"); | |
137 | exit(1); | |
138 | } | |
a08d4367 | 139 | qemu_register_reset(main_cpu_reset, env); |
4ce7ff6e AJ |
140 | |
141 | /* allocate RAM */ | |
1724f049 | 142 | ram_offset = qemu_ram_alloc(NULL, "mips_jazz.ram", ram_size); |
dcac9679 PB |
143 | cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); |
144 | ||
1724f049 | 145 | bios_offset = qemu_ram_alloc(NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE); |
dcac9679 PB |
146 | cpu_register_physical_memory(0x1fc00000LL, |
147 | MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM); | |
148 | cpu_register_physical_memory(0xfff00000LL, | |
149 | MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM); | |
4ce7ff6e AJ |
150 | |
151 | /* load the BIOS image. */ | |
c6945b15 AJ |
152 | if (bios_name == NULL) |
153 | bios_name = BIOS_FILENAME; | |
5cea8590 PB |
154 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
155 | if (filename) { | |
156 | bios_size = load_image_targphys(filename, 0xfff00000LL, | |
157 | MAGNUM_BIOS_SIZE); | |
158 | qemu_free(filename); | |
159 | } else { | |
160 | bios_size = -1; | |
161 | } | |
4ce7ff6e AJ |
162 | if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) { |
163 | fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n", | |
5cea8590 | 164 | bios_name); |
4ce7ff6e AJ |
165 | exit(1); |
166 | } | |
167 | ||
4ce7ff6e AJ |
168 | /* Init CPU internal devices */ |
169 | cpu_mips_irq_init_cpu(env); | |
170 | cpu_mips_clock_init(env); | |
171 | ||
172 | /* Chipset */ | |
68238a9e | 173 | rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas); |
2507c12a AG |
174 | s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL, |
175 | DEVICE_NATIVE_ENDIAN); | |
c6945b15 | 176 | cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy); |
4ce7ff6e AJ |
177 | |
178 | /* ISA devices */ | |
179 | i8259 = i8259_init(env->irq[4]); | |
5041fccd RT |
180 | isa_bus_new(NULL); |
181 | isa_bus_irqs(i8259); | |
4556bd8b BS |
182 | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
183 | DMA_init(0, cpu_exit_irq); | |
4ce7ff6e AJ |
184 | pit = pit_init(0x40, i8259[0]); |
185 | pcspk_init(pit); | |
186 | ||
187 | /* ISA IO space at 0x90000000 */ | |
968d683c | 188 | isa_mmio_init(0x90000000, 0x01000000); |
4ce7ff6e AJ |
189 | isa_mem_base = 0x11000000; |
190 | ||
191 | /* Video card */ | |
192 | switch (jazz_model) { | |
193 | case JAZZ_MAGNUM: | |
fbe1b595 | 194 | g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]); |
4ce7ff6e | 195 | break; |
c171148c | 196 | case JAZZ_PICA61: |
fbe1b595 | 197 | isa_vga_mm_init(0x40000000, 0x60000000, 0); |
c171148c | 198 | break; |
4ce7ff6e AJ |
199 | default: |
200 | break; | |
201 | } | |
202 | ||
203 | /* Network controller */ | |
a65f56ee AJ |
204 | for (n = 0; n < nb_nics; n++) { |
205 | nd = &nd_table[n]; | |
206 | if (!nd->model) | |
9203f520 | 207 | nd->model = qemu_strdup("dp83932"); |
a65f56ee AJ |
208 | if (strcmp(nd->model, "dp83932") == 0) { |
209 | dp83932_init(nd, 0x80001000, 2, rc4030[4], | |
210 | rc4030_opaque, rc4030_dma_memory_rw); | |
211 | break; | |
212 | } else if (strcmp(nd->model, "?") == 0) { | |
213 | fprintf(stderr, "qemu: Supported NICs: dp83932\n"); | |
214 | exit(1); | |
215 | } else { | |
216 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model); | |
217 | exit(1); | |
218 | } | |
219 | } | |
4ce7ff6e AJ |
220 | |
221 | /* SCSI adapter */ | |
cfb9de9c PB |
222 | esp_init(0x80002000, 0, |
223 | rc4030_dma_read, rc4030_dma_write, dmas[0], | |
73d74342 | 224 | rc4030[5], &esp_reset, &dma_enable); |
4ce7ff6e AJ |
225 | |
226 | /* Floppy */ | |
227 | if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) { | |
228 | fprintf(stderr, "qemu: too many floppy drives\n"); | |
229 | exit(1); | |
230 | } | |
231 | for (n = 0; n < MAX_FD; n++) { | |
fd8014e1 | 232 | fds[n] = drive_get(IF_FLOPPY, 0, n); |
4ce7ff6e | 233 | } |
2091ba23 | 234 | fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds); |
4ce7ff6e AJ |
235 | |
236 | /* Real time clock */ | |
7d932dfd | 237 | rtc_init(1980, NULL); |
2507c12a AG |
238 | s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL, |
239 | DEVICE_NATIVE_ENDIAN); | |
4ce7ff6e AJ |
240 | cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc); |
241 | ||
242 | /* Keyboard (i8042) */ | |
4efbe58f | 243 | i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1); |
4ce7ff6e AJ |
244 | |
245 | /* Serial ports */ | |
2d48377a BS |
246 | if (serial_hds[0]) { |
247 | #ifdef TARGET_WORDS_BIGENDIAN | |
248 | serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 1); | |
249 | #else | |
250 | serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 0); | |
251 | #endif | |
252 | } | |
253 | if (serial_hds[1]) { | |
254 | #ifdef TARGET_WORDS_BIGENDIAN | |
255 | serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 1); | |
256 | #else | |
257 | serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 0); | |
258 | #endif | |
259 | } | |
4ce7ff6e AJ |
260 | |
261 | /* Parallel port */ | |
262 | if (parallel_hds[0]) | |
263 | parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]); | |
264 | ||
265 | /* Sound card */ | |
266 | /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ | |
0dfa5ef9 | 267 | audio_init(i8259, NULL); |
4ce7ff6e AJ |
268 | |
269 | /* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */ | |
270 | ds1225y_init(0x80009000, "nvram"); | |
271 | ||
272 | /* LED indicator */ | |
3023f332 | 273 | jazz_led_init(0x8000f000); |
4ce7ff6e AJ |
274 | } |
275 | ||
276 | static | |
c227f099 | 277 | void mips_magnum_init (ram_addr_t ram_size, |
3023f332 | 278 | const char *boot_device, |
4ce7ff6e AJ |
279 | const char *kernel_filename, const char *kernel_cmdline, |
280 | const char *initrd_filename, const char *cpu_model) | |
281 | { | |
fbe1b595 | 282 | mips_jazz_init(ram_size, cpu_model, JAZZ_MAGNUM); |
4ce7ff6e AJ |
283 | } |
284 | ||
c171148c | 285 | static |
c227f099 | 286 | void mips_pica61_init (ram_addr_t ram_size, |
3023f332 | 287 | const char *boot_device, |
c171148c AJ |
288 | const char *kernel_filename, const char *kernel_cmdline, |
289 | const char *initrd_filename, const char *cpu_model) | |
290 | { | |
fbe1b595 | 291 | mips_jazz_init(ram_size, cpu_model, JAZZ_PICA61); |
c171148c AJ |
292 | } |
293 | ||
f80f9ec9 | 294 | static QEMUMachine mips_magnum_machine = { |
eec2743e TS |
295 | .name = "magnum", |
296 | .desc = "MIPS Magnum", | |
297 | .init = mips_magnum_init, | |
c6945b15 | 298 | .use_scsi = 1, |
4ce7ff6e | 299 | }; |
c171148c | 300 | |
f80f9ec9 | 301 | static QEMUMachine mips_pica61_machine = { |
eec2743e TS |
302 | .name = "pica61", |
303 | .desc = "Acer Pica 61", | |
304 | .init = mips_pica61_init, | |
c6945b15 | 305 | .use_scsi = 1, |
c171148c | 306 | }; |
f80f9ec9 AL |
307 | |
308 | static void mips_jazz_machine_init(void) | |
309 | { | |
310 | qemu_register_machine(&mips_magnum_machine); | |
311 | qemu_register_machine(&mips_pica61_machine); | |
312 | } | |
313 | ||
314 | machine_init(mips_jazz_machine_init); |