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Commit | Line | Data |
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e16fe40c TS |
1 | #include "vl.h" |
2 | ||
3 | void cpu_mips_irqctrl_init (void) | |
4 | { | |
5 | } | |
6 | ||
7 | /* XXX: do not use a global */ | |
8 | uint32_t cpu_mips_get_random (CPUState *env) | |
9 | { | |
10 | static uint32_t seed = 0; | |
11 | uint32_t idx; | |
12 | seed = seed * 314159 + 1; | |
13 | idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired; | |
14 | return idx; | |
15 | } | |
16 | ||
17 | /* MIPS R4K timer */ | |
18 | uint32_t cpu_mips_get_count (CPUState *env) | |
19 | { | |
20 | return env->CP0_Count + | |
21 | (uint32_t)muldiv64(qemu_get_clock(vm_clock), | |
22 | 100 * 1000 * 1000, ticks_per_sec); | |
23 | } | |
24 | ||
3529b538 | 25 | void cpu_mips_store_count (CPUState *env, uint32_t count) |
e16fe40c TS |
26 | { |
27 | uint64_t now, next; | |
28 | uint32_t tmp; | |
3529b538 | 29 | uint32_t compare = env->CP0_Compare; |
39d51eb8 | 30 | |
e16fe40c TS |
31 | tmp = count; |
32 | if (count == compare) | |
33 | tmp++; | |
34 | now = qemu_get_clock(vm_clock); | |
35 | next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000); | |
36 | if (next == now) | |
37 | next++; | |
38 | #if 0 | |
39 | if (logfile) { | |
40 | fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n", | |
41 | __func__, now, count, compare, next - now); | |
42 | } | |
43 | #endif | |
44 | /* Store new count and compare registers */ | |
45 | env->CP0_Compare = compare; | |
46 | env->CP0_Count = | |
47 | count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec); | |
48 | /* Adjust timer */ | |
49 | qemu_mod_timer(env->timer, next); | |
50 | } | |
51 | ||
3529b538 | 52 | static void cpu_mips_update_count (CPUState *env, uint32_t count) |
e16fe40c | 53 | { |
3529b538 TS |
54 | if (env->CP0_Cause & (1 << CP0Ca_DC)) |
55 | return; | |
56 | ||
57 | cpu_mips_store_count(env, count); | |
e16fe40c TS |
58 | } |
59 | ||
60 | void cpu_mips_store_compare (CPUState *env, uint32_t value) | |
61 | { | |
3529b538 TS |
62 | env->CP0_Compare = value; |
63 | cpu_mips_update_count(env, cpu_mips_get_count(env)); | |
39d51eb8 TS |
64 | if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) |
65 | env->CP0_Cause &= ~(1 << CP0Ca_TI); | |
4de9b249 | 66 | cpu_mips_irq_request(env, 7, 0); |
e16fe40c TS |
67 | } |
68 | ||
69 | static void mips_timer_cb (void *opaque) | |
70 | { | |
71 | CPUState *env; | |
72 | ||
73 | env = opaque; | |
74 | #if 0 | |
75 | if (logfile) { | |
76 | fprintf(logfile, "%s\n", __func__); | |
77 | } | |
78 | #endif | |
3529b538 | 79 | cpu_mips_update_count(env, cpu_mips_get_count(env)); |
39d51eb8 TS |
80 | if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) |
81 | env->CP0_Cause |= 1 << CP0Ca_TI; | |
4de9b249 | 82 | cpu_mips_irq_request(env, 7, 1); |
e16fe40c TS |
83 | } |
84 | ||
85 | void cpu_mips_clock_init (CPUState *env) | |
86 | { | |
87 | env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); | |
88 | env->CP0_Compare = 0; | |
3529b538 | 89 | cpu_mips_update_count(env, 1); |
e16fe40c | 90 | } |