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Commit | Line | Data |
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6cbf4c8c CM |
1 | /* |
2 | * Inter-VM Shared Memory PCI device. | |
3 | * | |
4 | * Author: | |
5 | * Cam Macdonell <cam@cs.ualberta.ca> | |
6 | * | |
7 | * Based On: cirrus_vga.c | |
8 | * Copyright (c) 2004 Fabrice Bellard | |
9 | * Copyright (c) 2004 Makoto Suzuki (suzu) | |
10 | * | |
11 | * and rtl8139.c | |
12 | * Copyright (c) 2006 Igor Kovalenko | |
13 | * | |
14 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
15 | * |
16 | * Contributions after 2012-01-13 are licensed under the terms of the | |
17 | * GNU GPL, version 2 or (at your option) any later version. | |
6cbf4c8c | 18 | */ |
83c9f4ca | 19 | #include "hw/hw.h" |
0d09e41a | 20 | #include "hw/i386/pc.h" |
83c9f4ca PB |
21 | #include "hw/pci/pci.h" |
22 | #include "hw/pci/msix.h" | |
9c17d615 | 23 | #include "sysemu/kvm.h" |
caf71f86 | 24 | #include "migration/migration.h" |
7b1b5d19 | 25 | #include "qapi/qmp/qerror.h" |
1de7afc9 | 26 | #include "qemu/event_notifier.h" |
dccfcd0e | 27 | #include "sysemu/char.h" |
6cbf4c8c CM |
28 | |
29 | #include <sys/mman.h> | |
30 | #include <sys/types.h> | |
31 | ||
b8ef62a9 PB |
32 | #define PCI_VENDOR_ID_IVSHMEM PCI_VENDOR_ID_REDHAT_QUMRANET |
33 | #define PCI_DEVICE_ID_IVSHMEM 0x1110 | |
34 | ||
6cbf4c8c CM |
35 | #define IVSHMEM_IOEVENTFD 0 |
36 | #define IVSHMEM_MSI 1 | |
37 | ||
38 | #define IVSHMEM_PEER 0 | |
39 | #define IVSHMEM_MASTER 1 | |
40 | ||
41 | #define IVSHMEM_REG_BAR_SIZE 0x100 | |
42 | ||
43 | //#define DEBUG_IVSHMEM | |
44 | #ifdef DEBUG_IVSHMEM | |
45 | #define IVSHMEM_DPRINTF(fmt, ...) \ | |
46 | do {printf("IVSHMEM: " fmt, ## __VA_ARGS__); } while (0) | |
47 | #else | |
48 | #define IVSHMEM_DPRINTF(fmt, ...) | |
49 | #endif | |
50 | ||
eb3fedf3 PC |
51 | #define TYPE_IVSHMEM "ivshmem" |
52 | #define IVSHMEM(obj) \ | |
53 | OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM) | |
54 | ||
6cbf4c8c CM |
55 | typedef struct Peer { |
56 | int nb_eventfds; | |
563027cc | 57 | EventNotifier *eventfds; |
6cbf4c8c CM |
58 | } Peer; |
59 | ||
60 | typedef struct EventfdEntry { | |
61 | PCIDevice *pdev; | |
62 | int vector; | |
63 | } EventfdEntry; | |
64 | ||
65 | typedef struct IVShmemState { | |
b7578eaa AF |
66 | /*< private >*/ |
67 | PCIDevice parent_obj; | |
68 | /*< public >*/ | |
69 | ||
6cbf4c8c CM |
70 | uint32_t intrmask; |
71 | uint32_t intrstatus; | |
72 | uint32_t doorbell; | |
73 | ||
74 | CharDriverState **eventfd_chr; | |
75 | CharDriverState *server_chr; | |
cb06608e | 76 | MemoryRegion ivshmem_mmio; |
6cbf4c8c | 77 | |
cb06608e AK |
78 | /* We might need to register the BAR before we actually have the memory. |
79 | * So prepare a container MemoryRegion for the BAR immediately and | |
80 | * add a subregion when we have the memory. | |
81 | */ | |
82 | MemoryRegion bar; | |
83 | MemoryRegion ivshmem; | |
6cbf4c8c | 84 | uint64_t ivshmem_size; /* size of shared memory region */ |
c08ba66f GH |
85 | uint32_t ivshmem_attr; |
86 | uint32_t ivshmem_64bit; | |
6cbf4c8c CM |
87 | int shm_fd; /* shared memory file descriptor */ |
88 | ||
89 | Peer *peers; | |
90 | int nb_peers; /* how many guests we have space for */ | |
91 | int max_peer; /* maximum numbered peer */ | |
92 | ||
93 | int vm_id; | |
94 | uint32_t vectors; | |
95 | uint32_t features; | |
96 | EventfdEntry *eventfd_table; | |
97 | ||
38e0735e AL |
98 | Error *migration_blocker; |
99 | ||
6cbf4c8c CM |
100 | char * shmobj; |
101 | char * sizearg; | |
102 | char * role; | |
103 | int role_val; /* scalar to avoid multiple string comparisons */ | |
104 | } IVShmemState; | |
105 | ||
106 | /* registers for the Inter-VM shared memory device */ | |
107 | enum ivshmem_registers { | |
108 | INTRMASK = 0, | |
109 | INTRSTATUS = 4, | |
110 | IVPOSITION = 8, | |
111 | DOORBELL = 12, | |
112 | }; | |
113 | ||
114 | static inline uint32_t ivshmem_has_feature(IVShmemState *ivs, | |
115 | unsigned int feature) { | |
116 | return (ivs->features & (1 << feature)); | |
117 | } | |
118 | ||
119 | static inline bool is_power_of_two(uint64_t x) { | |
120 | return (x & (x - 1)) == 0; | |
121 | } | |
122 | ||
6cbf4c8c CM |
123 | /* accessing registers - based on rtl8139 */ |
124 | static void ivshmem_update_irq(IVShmemState *s, int val) | |
125 | { | |
b7578eaa | 126 | PCIDevice *d = PCI_DEVICE(s); |
6cbf4c8c CM |
127 | int isr; |
128 | isr = (s->intrstatus & s->intrmask) & 0xffffffff; | |
129 | ||
130 | /* don't print ISR resets */ | |
131 | if (isr) { | |
132 | IVSHMEM_DPRINTF("Set IRQ to %d (%04x %04x)\n", | |
133 | isr ? 1 : 0, s->intrstatus, s->intrmask); | |
134 | } | |
135 | ||
b7578eaa | 136 | qemu_set_irq(d->irq[0], (isr != 0)); |
6cbf4c8c CM |
137 | } |
138 | ||
139 | static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val) | |
140 | { | |
141 | IVSHMEM_DPRINTF("IntrMask write(w) val = 0x%04x\n", val); | |
142 | ||
143 | s->intrmask = val; | |
144 | ||
145 | ivshmem_update_irq(s, val); | |
146 | } | |
147 | ||
148 | static uint32_t ivshmem_IntrMask_read(IVShmemState *s) | |
149 | { | |
150 | uint32_t ret = s->intrmask; | |
151 | ||
152 | IVSHMEM_DPRINTF("intrmask read(w) val = 0x%04x\n", ret); | |
153 | ||
154 | return ret; | |
155 | } | |
156 | ||
157 | static void ivshmem_IntrStatus_write(IVShmemState *s, uint32_t val) | |
158 | { | |
159 | IVSHMEM_DPRINTF("IntrStatus write(w) val = 0x%04x\n", val); | |
160 | ||
161 | s->intrstatus = val; | |
162 | ||
163 | ivshmem_update_irq(s, val); | |
6cbf4c8c CM |
164 | } |
165 | ||
166 | static uint32_t ivshmem_IntrStatus_read(IVShmemState *s) | |
167 | { | |
168 | uint32_t ret = s->intrstatus; | |
169 | ||
170 | /* reading ISR clears all interrupts */ | |
171 | s->intrstatus = 0; | |
172 | ||
173 | ivshmem_update_irq(s, 0); | |
174 | ||
175 | return ret; | |
176 | } | |
177 | ||
a8170e5e | 178 | static void ivshmem_io_write(void *opaque, hwaddr addr, |
cb06608e | 179 | uint64_t val, unsigned size) |
6cbf4c8c CM |
180 | { |
181 | IVShmemState *s = opaque; | |
182 | ||
6cbf4c8c CM |
183 | uint16_t dest = val >> 16; |
184 | uint16_t vector = val & 0xff; | |
185 | ||
186 | addr &= 0xfc; | |
187 | ||
188 | IVSHMEM_DPRINTF("writing to addr " TARGET_FMT_plx "\n", addr); | |
189 | switch (addr) | |
190 | { | |
191 | case INTRMASK: | |
192 | ivshmem_IntrMask_write(s, val); | |
193 | break; | |
194 | ||
195 | case INTRSTATUS: | |
196 | ivshmem_IntrStatus_write(s, val); | |
197 | break; | |
198 | ||
199 | case DOORBELL: | |
200 | /* check that dest VM ID is reasonable */ | |
1b27d7a1 | 201 | if (dest > s->max_peer) { |
6cbf4c8c CM |
202 | IVSHMEM_DPRINTF("Invalid destination VM ID (%d)\n", dest); |
203 | break; | |
204 | } | |
205 | ||
206 | /* check doorbell range */ | |
1b27d7a1 | 207 | if (vector < s->peers[dest].nb_eventfds) { |
563027cc PB |
208 | IVSHMEM_DPRINTF("Notifying VM %d on vector %d\n", dest, vector); |
209 | event_notifier_set(&s->peers[dest].eventfds[vector]); | |
6cbf4c8c CM |
210 | } |
211 | break; | |
212 | default: | |
213 | IVSHMEM_DPRINTF("Invalid VM Doorbell VM %d\n", dest); | |
214 | } | |
215 | } | |
216 | ||
a8170e5e | 217 | static uint64_t ivshmem_io_read(void *opaque, hwaddr addr, |
cb06608e | 218 | unsigned size) |
6cbf4c8c CM |
219 | { |
220 | ||
221 | IVShmemState *s = opaque; | |
222 | uint32_t ret; | |
223 | ||
224 | switch (addr) | |
225 | { | |
226 | case INTRMASK: | |
227 | ret = ivshmem_IntrMask_read(s); | |
228 | break; | |
229 | ||
230 | case INTRSTATUS: | |
231 | ret = ivshmem_IntrStatus_read(s); | |
232 | break; | |
233 | ||
234 | case IVPOSITION: | |
235 | /* return my VM ID if the memory is mapped */ | |
236 | if (s->shm_fd > 0) { | |
237 | ret = s->vm_id; | |
238 | } else { | |
239 | ret = -1; | |
240 | } | |
241 | break; | |
242 | ||
243 | default: | |
244 | IVSHMEM_DPRINTF("why are we reading " TARGET_FMT_plx "\n", addr); | |
245 | ret = 0; | |
246 | } | |
247 | ||
248 | return ret; | |
249 | } | |
250 | ||
cb06608e AK |
251 | static const MemoryRegionOps ivshmem_mmio_ops = { |
252 | .read = ivshmem_io_read, | |
253 | .write = ivshmem_io_write, | |
254 | .endianness = DEVICE_NATIVE_ENDIAN, | |
255 | .impl = { | |
256 | .min_access_size = 4, | |
257 | .max_access_size = 4, | |
258 | }, | |
6cbf4c8c CM |
259 | }; |
260 | ||
261 | static void ivshmem_receive(void *opaque, const uint8_t *buf, int size) | |
262 | { | |
263 | IVShmemState *s = opaque; | |
264 | ||
265 | ivshmem_IntrStatus_write(s, *buf); | |
266 | ||
267 | IVSHMEM_DPRINTF("ivshmem_receive 0x%02x\n", *buf); | |
268 | } | |
269 | ||
270 | static int ivshmem_can_receive(void * opaque) | |
271 | { | |
272 | return 8; | |
273 | } | |
274 | ||
275 | static void ivshmem_event(void *opaque, int event) | |
276 | { | |
277 | IVSHMEM_DPRINTF("ivshmem_event %d\n", event); | |
278 | } | |
279 | ||
280 | static void fake_irqfd(void *opaque, const uint8_t *buf, int size) { | |
281 | ||
282 | EventfdEntry *entry = opaque; | |
283 | PCIDevice *pdev = entry->pdev; | |
284 | ||
285 | IVSHMEM_DPRINTF("interrupt on vector %p %d\n", pdev, entry->vector); | |
286 | msix_notify(pdev, entry->vector); | |
287 | } | |
288 | ||
563027cc PB |
289 | static CharDriverState* create_eventfd_chr_device(void * opaque, EventNotifier *n, |
290 | int vector) | |
6cbf4c8c CM |
291 | { |
292 | /* create a event character device based on the passed eventfd */ | |
293 | IVShmemState *s = opaque; | |
294 | CharDriverState * chr; | |
563027cc | 295 | int eventfd = event_notifier_get_fd(n); |
6cbf4c8c CM |
296 | |
297 | chr = qemu_chr_open_eventfd(eventfd); | |
298 | ||
299 | if (chr == NULL) { | |
300 | fprintf(stderr, "creating eventfd for eventfd %d failed\n", eventfd); | |
301 | exit(-1); | |
302 | } | |
456d6069 | 303 | qemu_chr_fe_claim_no_fail(chr); |
6cbf4c8c CM |
304 | |
305 | /* if MSI is supported we need multiple interrupts */ | |
306 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
b7578eaa | 307 | s->eventfd_table[vector].pdev = PCI_DEVICE(s); |
6cbf4c8c CM |
308 | s->eventfd_table[vector].vector = vector; |
309 | ||
310 | qemu_chr_add_handlers(chr, ivshmem_can_receive, fake_irqfd, | |
311 | ivshmem_event, &s->eventfd_table[vector]); | |
312 | } else { | |
313 | qemu_chr_add_handlers(chr, ivshmem_can_receive, ivshmem_receive, | |
314 | ivshmem_event, s); | |
315 | } | |
316 | ||
317 | return chr; | |
318 | ||
319 | } | |
320 | ||
321 | static int check_shm_size(IVShmemState *s, int fd) { | |
322 | /* check that the guest isn't going to try and map more memory than the | |
323 | * the object has allocated return -1 to indicate error */ | |
324 | ||
325 | struct stat buf; | |
326 | ||
327 | fstat(fd, &buf); | |
328 | ||
329 | if (s->ivshmem_size > buf.st_size) { | |
ad0a4ac1 AK |
330 | fprintf(stderr, |
331 | "IVSHMEM ERROR: Requested memory size greater" | |
332 | " than shared object size (%" PRIu64 " > %" PRIu64")\n", | |
333 | s->ivshmem_size, (uint64_t)buf.st_size); | |
6cbf4c8c CM |
334 | return -1; |
335 | } else { | |
336 | return 0; | |
337 | } | |
338 | } | |
339 | ||
340 | /* create the shared memory BAR when we are not using the server, so we can | |
341 | * create the BAR and map the memory immediately */ | |
342 | static void create_shared_memory_BAR(IVShmemState *s, int fd) { | |
343 | ||
344 | void * ptr; | |
345 | ||
346 | s->shm_fd = fd; | |
347 | ||
348 | ptr = mmap(0, s->ivshmem_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); | |
349 | ||
3c161542 | 350 | memory_region_init_ram_ptr(&s->ivshmem, OBJECT(s), "ivshmem.bar2", |
cb06608e | 351 | s->ivshmem_size, ptr); |
eb3fedf3 | 352 | vmstate_register_ram(&s->ivshmem, DEVICE(s)); |
cb06608e | 353 | memory_region_add_subregion(&s->bar, 0, &s->ivshmem); |
6cbf4c8c CM |
354 | |
355 | /* region for shared memory */ | |
b7578eaa | 356 | pci_register_bar(PCI_DEVICE(s), 2, s->ivshmem_attr, &s->bar); |
6cbf4c8c CM |
357 | } |
358 | ||
563027cc PB |
359 | static void ivshmem_add_eventfd(IVShmemState *s, int posn, int i) |
360 | { | |
361 | memory_region_add_eventfd(&s->ivshmem_mmio, | |
362 | DOORBELL, | |
363 | 4, | |
364 | true, | |
365 | (posn << 16) | i, | |
753d5e14 | 366 | &s->peers[posn].eventfds[i]); |
563027cc PB |
367 | } |
368 | ||
369 | static void ivshmem_del_eventfd(IVShmemState *s, int posn, int i) | |
370 | { | |
371 | memory_region_del_eventfd(&s->ivshmem_mmio, | |
372 | DOORBELL, | |
373 | 4, | |
374 | true, | |
375 | (posn << 16) | i, | |
753d5e14 | 376 | &s->peers[posn].eventfds[i]); |
563027cc PB |
377 | } |
378 | ||
6cbf4c8c CM |
379 | static void close_guest_eventfds(IVShmemState *s, int posn) |
380 | { | |
381 | int i, guest_curr_max; | |
382 | ||
98609cd8 PB |
383 | if (!ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { |
384 | return; | |
385 | } | |
386 | ||
6cbf4c8c CM |
387 | guest_curr_max = s->peers[posn].nb_eventfds; |
388 | ||
b6a1f3a5 | 389 | memory_region_transaction_begin(); |
6cbf4c8c | 390 | for (i = 0; i < guest_curr_max; i++) { |
563027cc | 391 | ivshmem_del_eventfd(s, posn, i); |
b6a1f3a5 PB |
392 | } |
393 | memory_region_transaction_commit(); | |
394 | for (i = 0; i < guest_curr_max; i++) { | |
563027cc | 395 | event_notifier_cleanup(&s->peers[posn].eventfds[i]); |
6cbf4c8c CM |
396 | } |
397 | ||
7267c094 | 398 | g_free(s->peers[posn].eventfds); |
6cbf4c8c CM |
399 | s->peers[posn].nb_eventfds = 0; |
400 | } | |
401 | ||
6cbf4c8c CM |
402 | /* this function increase the dynamic storage need to store data about other |
403 | * guests */ | |
404 | static void increase_dynamic_storage(IVShmemState *s, int new_min_size) { | |
405 | ||
406 | int j, old_nb_alloc; | |
407 | ||
408 | old_nb_alloc = s->nb_peers; | |
409 | ||
410 | while (new_min_size >= s->nb_peers) | |
411 | s->nb_peers = s->nb_peers * 2; | |
412 | ||
413 | IVSHMEM_DPRINTF("bumping storage to %d guests\n", s->nb_peers); | |
7267c094 | 414 | s->peers = g_realloc(s->peers, s->nb_peers * sizeof(Peer)); |
6cbf4c8c CM |
415 | |
416 | /* zero out new pointers */ | |
417 | for (j = old_nb_alloc; j < s->nb_peers; j++) { | |
418 | s->peers[j].eventfds = NULL; | |
419 | s->peers[j].nb_eventfds = 0; | |
420 | } | |
421 | } | |
422 | ||
423 | static void ivshmem_read(void *opaque, const uint8_t * buf, int flags) | |
424 | { | |
425 | IVShmemState *s = opaque; | |
426 | int incoming_fd, tmp_fd; | |
427 | int guest_max_eventfd; | |
428 | long incoming_posn; | |
429 | ||
430 | memcpy(&incoming_posn, buf, sizeof(long)); | |
431 | /* pick off s->server_chr->msgfd and store it, posn should accompany msg */ | |
74c0d6f0 | 432 | tmp_fd = qemu_chr_fe_get_msgfd(s->server_chr); |
6cbf4c8c CM |
433 | IVSHMEM_DPRINTF("posn is %ld, fd is %d\n", incoming_posn, tmp_fd); |
434 | ||
435 | /* make sure we have enough space for this guest */ | |
436 | if (incoming_posn >= s->nb_peers) { | |
437 | increase_dynamic_storage(s, incoming_posn); | |
438 | } | |
439 | ||
440 | if (tmp_fd == -1) { | |
441 | /* if posn is positive and unseen before then this is our posn*/ | |
442 | if ((incoming_posn >= 0) && | |
443 | (s->peers[incoming_posn].eventfds == NULL)) { | |
444 | /* receive our posn */ | |
445 | s->vm_id = incoming_posn; | |
446 | return; | |
447 | } else { | |
448 | /* otherwise an fd == -1 means an existing guest has gone away */ | |
449 | IVSHMEM_DPRINTF("posn %ld has gone away\n", incoming_posn); | |
450 | close_guest_eventfds(s, incoming_posn); | |
451 | return; | |
452 | } | |
453 | } | |
454 | ||
455 | /* because of the implementation of get_msgfd, we need a dup */ | |
456 | incoming_fd = dup(tmp_fd); | |
457 | ||
458 | if (incoming_fd == -1) { | |
459 | fprintf(stderr, "could not allocate file descriptor %s\n", | |
460 | strerror(errno)); | |
461 | return; | |
462 | } | |
463 | ||
464 | /* if the position is -1, then it's shared memory region fd */ | |
465 | if (incoming_posn == -1) { | |
466 | ||
467 | void * map_ptr; | |
468 | ||
469 | s->max_peer = 0; | |
470 | ||
471 | if (check_shm_size(s, incoming_fd) == -1) { | |
472 | exit(-1); | |
473 | } | |
474 | ||
475 | /* mmap the region and map into the BAR2 */ | |
476 | map_ptr = mmap(0, s->ivshmem_size, PROT_READ|PROT_WRITE, MAP_SHARED, | |
477 | incoming_fd, 0); | |
3c161542 | 478 | memory_region_init_ram_ptr(&s->ivshmem, OBJECT(s), |
cb06608e | 479 | "ivshmem.bar2", s->ivshmem_size, map_ptr); |
eb3fedf3 | 480 | vmstate_register_ram(&s->ivshmem, DEVICE(s)); |
6cbf4c8c | 481 | |
cb06608e | 482 | IVSHMEM_DPRINTF("guest h/w addr = %" PRIu64 ", size = %" PRIu64 "\n", |
6cbf4c8c CM |
483 | s->ivshmem_offset, s->ivshmem_size); |
484 | ||
cb06608e | 485 | memory_region_add_subregion(&s->bar, 0, &s->ivshmem); |
6cbf4c8c CM |
486 | |
487 | /* only store the fd if it is successfully mapped */ | |
488 | s->shm_fd = incoming_fd; | |
489 | ||
490 | return; | |
491 | } | |
492 | ||
493 | /* each guest has an array of eventfds, and we keep track of how many | |
494 | * guests for each VM */ | |
495 | guest_max_eventfd = s->peers[incoming_posn].nb_eventfds; | |
496 | ||
497 | if (guest_max_eventfd == 0) { | |
498 | /* one eventfd per MSI vector */ | |
563027cc | 499 | s->peers[incoming_posn].eventfds = g_new(EventNotifier, s->vectors); |
6cbf4c8c CM |
500 | } |
501 | ||
502 | /* this is an eventfd for a particular guest VM */ | |
503 | IVSHMEM_DPRINTF("eventfds[%ld][%d] = %d\n", incoming_posn, | |
504 | guest_max_eventfd, incoming_fd); | |
563027cc PB |
505 | event_notifier_init_fd(&s->peers[incoming_posn].eventfds[guest_max_eventfd], |
506 | incoming_fd); | |
6cbf4c8c CM |
507 | |
508 | /* increment count for particular guest */ | |
509 | s->peers[incoming_posn].nb_eventfds++; | |
510 | ||
511 | /* keep track of the maximum VM ID */ | |
512 | if (incoming_posn > s->max_peer) { | |
513 | s->max_peer = incoming_posn; | |
514 | } | |
515 | ||
516 | if (incoming_posn == s->vm_id) { | |
517 | s->eventfd_chr[guest_max_eventfd] = create_eventfd_chr_device(s, | |
563027cc | 518 | &s->peers[s->vm_id].eventfds[guest_max_eventfd], |
6cbf4c8c CM |
519 | guest_max_eventfd); |
520 | } | |
521 | ||
522 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { | |
563027cc | 523 | ivshmem_add_eventfd(s, incoming_posn, guest_max_eventfd); |
6cbf4c8c | 524 | } |
6cbf4c8c CM |
525 | } |
526 | ||
4490c711 MT |
527 | /* Select the MSI-X vectors used by device. |
528 | * ivshmem maps events to vectors statically, so | |
529 | * we just enable all vectors on init and after reset. */ | |
530 | static void ivshmem_use_msix(IVShmemState * s) | |
531 | { | |
b7578eaa | 532 | PCIDevice *d = PCI_DEVICE(s); |
4490c711 MT |
533 | int i; |
534 | ||
b7578eaa | 535 | if (!msix_present(d)) { |
4490c711 MT |
536 | return; |
537 | } | |
538 | ||
539 | for (i = 0; i < s->vectors; i++) { | |
b7578eaa | 540 | msix_vector_use(d, i); |
4490c711 MT |
541 | } |
542 | } | |
543 | ||
6cbf4c8c CM |
544 | static void ivshmem_reset(DeviceState *d) |
545 | { | |
eb3fedf3 | 546 | IVShmemState *s = IVSHMEM(d); |
6cbf4c8c CM |
547 | |
548 | s->intrstatus = 0; | |
4490c711 | 549 | ivshmem_use_msix(s); |
6cbf4c8c CM |
550 | } |
551 | ||
6cbf4c8c CM |
552 | static uint64_t ivshmem_get_size(IVShmemState * s) { |
553 | ||
554 | uint64_t value; | |
555 | char *ptr; | |
556 | ||
557 | value = strtoull(s->sizearg, &ptr, 10); | |
558 | switch (*ptr) { | |
559 | case 0: case 'M': case 'm': | |
560 | value <<= 20; | |
561 | break; | |
562 | case 'G': case 'g': | |
563 | value <<= 30; | |
564 | break; | |
565 | default: | |
566 | fprintf(stderr, "qemu: invalid ram size: %s\n", s->sizearg); | |
567 | exit(1); | |
568 | } | |
569 | ||
570 | /* BARs must be a power of 2 */ | |
571 | if (!is_power_of_two(value)) { | |
572 | fprintf(stderr, "ivshmem: size must be power of 2\n"); | |
573 | exit(1); | |
574 | } | |
575 | ||
576 | return value; | |
577 | } | |
578 | ||
4490c711 MT |
579 | static void ivshmem_setup_msi(IVShmemState * s) |
580 | { | |
b7578eaa | 581 | if (msix_init_exclusive_bar(PCI_DEVICE(s), s->vectors, 1)) { |
6cbf4c8c CM |
582 | IVSHMEM_DPRINTF("msix initialization failed\n"); |
583 | exit(1); | |
584 | } | |
585 | ||
1116b539 AW |
586 | IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors); |
587 | ||
5cbdb3a3 | 588 | /* allocate QEMU char devices for receiving interrupts */ |
7267c094 | 589 | s->eventfd_table = g_malloc0(s->vectors * sizeof(EventfdEntry)); |
4490c711 MT |
590 | |
591 | ivshmem_use_msix(s); | |
6cbf4c8c CM |
592 | } |
593 | ||
594 | static void ivshmem_save(QEMUFile* f, void *opaque) | |
595 | { | |
596 | IVShmemState *proxy = opaque; | |
b7578eaa | 597 | PCIDevice *pci_dev = PCI_DEVICE(proxy); |
6cbf4c8c CM |
598 | |
599 | IVSHMEM_DPRINTF("ivshmem_save\n"); | |
b7578eaa | 600 | pci_device_save(pci_dev, f); |
6cbf4c8c CM |
601 | |
602 | if (ivshmem_has_feature(proxy, IVSHMEM_MSI)) { | |
b7578eaa | 603 | msix_save(pci_dev, f); |
6cbf4c8c CM |
604 | } else { |
605 | qemu_put_be32(f, proxy->intrstatus); | |
606 | qemu_put_be32(f, proxy->intrmask); | |
607 | } | |
608 | ||
609 | } | |
610 | ||
611 | static int ivshmem_load(QEMUFile* f, void *opaque, int version_id) | |
612 | { | |
613 | IVSHMEM_DPRINTF("ivshmem_load\n"); | |
614 | ||
615 | IVShmemState *proxy = opaque; | |
b7578eaa | 616 | PCIDevice *pci_dev = PCI_DEVICE(proxy); |
4490c711 | 617 | int ret; |
6cbf4c8c CM |
618 | |
619 | if (version_id > 0) { | |
620 | return -EINVAL; | |
621 | } | |
622 | ||
623 | if (proxy->role_val == IVSHMEM_PEER) { | |
624 | fprintf(stderr, "ivshmem: 'peer' devices are not migratable\n"); | |
625 | return -EINVAL; | |
626 | } | |
627 | ||
b7578eaa | 628 | ret = pci_device_load(pci_dev, f); |
6cbf4c8c CM |
629 | if (ret) { |
630 | return ret; | |
631 | } | |
632 | ||
633 | if (ivshmem_has_feature(proxy, IVSHMEM_MSI)) { | |
b7578eaa | 634 | msix_load(pci_dev, f); |
4490c711 | 635 | ivshmem_use_msix(proxy); |
6cbf4c8c CM |
636 | } else { |
637 | proxy->intrstatus = qemu_get_be32(f); | |
638 | proxy->intrmask = qemu_get_be32(f); | |
639 | } | |
640 | ||
641 | return 0; | |
642 | } | |
643 | ||
4490c711 MT |
644 | static void ivshmem_write_config(PCIDevice *pci_dev, uint32_t address, |
645 | uint32_t val, int len) | |
646 | { | |
647 | pci_default_write_config(pci_dev, address, val, len); | |
648 | msix_write_config(pci_dev, address, val, len); | |
649 | } | |
650 | ||
6cbf4c8c CM |
651 | static int pci_ivshmem_init(PCIDevice *dev) |
652 | { | |
eb3fedf3 | 653 | IVShmemState *s = IVSHMEM(dev); |
6cbf4c8c CM |
654 | uint8_t *pci_conf; |
655 | ||
656 | if (s->sizearg == NULL) | |
657 | s->ivshmem_size = 4 << 20; /* 4 MB default */ | |
658 | else { | |
659 | s->ivshmem_size = ivshmem_get_size(s); | |
660 | } | |
661 | ||
eb3fedf3 | 662 | register_savevm(DEVICE(dev), "ivshmem", 0, 0, ivshmem_save, ivshmem_load, |
6cbf4c8c CM |
663 | dev); |
664 | ||
665 | /* IRQFD requires MSI */ | |
666 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD) && | |
667 | !ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
668 | fprintf(stderr, "ivshmem: ioeventfd/irqfd requires MSI\n"); | |
669 | exit(1); | |
670 | } | |
671 | ||
672 | /* check that role is reasonable */ | |
673 | if (s->role) { | |
674 | if (strncmp(s->role, "peer", 5) == 0) { | |
675 | s->role_val = IVSHMEM_PEER; | |
676 | } else if (strncmp(s->role, "master", 7) == 0) { | |
677 | s->role_val = IVSHMEM_MASTER; | |
678 | } else { | |
679 | fprintf(stderr, "ivshmem: 'role' must be 'peer' or 'master'\n"); | |
680 | exit(1); | |
681 | } | |
682 | } else { | |
683 | s->role_val = IVSHMEM_MASTER; /* default */ | |
684 | } | |
685 | ||
686 | if (s->role_val == IVSHMEM_PEER) { | |
c3594ed7 AG |
687 | error_set(&s->migration_blocker, QERR_DEVICE_FEATURE_BLOCKS_MIGRATION, |
688 | "peer mode", "ivshmem"); | |
38e0735e | 689 | migrate_add_blocker(s->migration_blocker); |
6cbf4c8c CM |
690 | } |
691 | ||
b7578eaa | 692 | pci_conf = dev->config; |
6cbf4c8c | 693 | pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY; |
6cbf4c8c CM |
694 | |
695 | pci_config_set_interrupt_pin(pci_conf, 1); | |
696 | ||
6cbf4c8c CM |
697 | s->shm_fd = 0; |
698 | ||
3c161542 | 699 | memory_region_init_io(&s->ivshmem_mmio, OBJECT(s), &ivshmem_mmio_ops, s, |
cb06608e AK |
700 | "ivshmem-mmio", IVSHMEM_REG_BAR_SIZE); |
701 | ||
6cbf4c8c | 702 | /* region for registers*/ |
b7578eaa | 703 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, |
e824b2cc | 704 | &s->ivshmem_mmio); |
cb06608e | 705 | |
3c161542 | 706 | memory_region_init(&s->bar, OBJECT(s), "ivshmem-bar2-container", s->ivshmem_size); |
c08ba66f GH |
707 | s->ivshmem_attr = PCI_BASE_ADDRESS_SPACE_MEMORY | |
708 | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
709 | if (s->ivshmem_64bit) { | |
710 | s->ivshmem_attr |= PCI_BASE_ADDRESS_MEM_TYPE_64; | |
711 | } | |
6cbf4c8c CM |
712 | |
713 | if ((s->server_chr != NULL) && | |
714 | (strncmp(s->server_chr->filename, "unix:", 5) == 0)) { | |
715 | /* if we get a UNIX socket as the parameter we will talk | |
716 | * to the ivshmem server to receive the memory region */ | |
717 | ||
718 | if (s->shmobj != NULL) { | |
719 | fprintf(stderr, "WARNING: do not specify both 'chardev' " | |
720 | "and 'shm' with ivshmem\n"); | |
721 | } | |
722 | ||
723 | IVSHMEM_DPRINTF("using shared memory server (socket = %s)\n", | |
724 | s->server_chr->filename); | |
725 | ||
726 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
727 | ivshmem_setup_msi(s); | |
728 | } | |
729 | ||
730 | /* we allocate enough space for 16 guests and grow as needed */ | |
731 | s->nb_peers = 16; | |
732 | s->vm_id = -1; | |
733 | ||
734 | /* allocate/initialize space for interrupt handling */ | |
7267c094 | 735 | s->peers = g_malloc0(s->nb_peers * sizeof(Peer)); |
6cbf4c8c | 736 | |
b7578eaa | 737 | pci_register_bar(dev, 2, s->ivshmem_attr, &s->bar); |
6cbf4c8c | 738 | |
7267c094 | 739 | s->eventfd_chr = g_malloc0(s->vectors * sizeof(CharDriverState *)); |
6cbf4c8c CM |
740 | |
741 | qemu_chr_add_handlers(s->server_chr, ivshmem_can_receive, ivshmem_read, | |
742 | ivshmem_event, s); | |
743 | } else { | |
744 | /* just map the file immediately, we're not using a server */ | |
745 | int fd; | |
746 | ||
747 | if (s->shmobj == NULL) { | |
748 | fprintf(stderr, "Must specify 'chardev' or 'shm' to ivshmem\n"); | |
baefb8bf | 749 | exit(1); |
6cbf4c8c CM |
750 | } |
751 | ||
752 | IVSHMEM_DPRINTF("using shm_open (shm object = %s)\n", s->shmobj); | |
753 | ||
754 | /* try opening with O_EXCL and if it succeeds zero the memory | |
755 | * by truncating to 0 */ | |
756 | if ((fd = shm_open(s->shmobj, O_CREAT|O_RDWR|O_EXCL, | |
757 | S_IRWXU|S_IRWXG|S_IRWXO)) > 0) { | |
758 | /* truncate file to length PCI device's memory */ | |
759 | if (ftruncate(fd, s->ivshmem_size) != 0) { | |
760 | fprintf(stderr, "ivshmem: could not truncate shared file\n"); | |
761 | } | |
762 | ||
763 | } else if ((fd = shm_open(s->shmobj, O_CREAT|O_RDWR, | |
764 | S_IRWXU|S_IRWXG|S_IRWXO)) < 0) { | |
765 | fprintf(stderr, "ivshmem: could not open shared file\n"); | |
766 | exit(-1); | |
767 | ||
768 | } | |
769 | ||
770 | if (check_shm_size(s, fd) == -1) { | |
771 | exit(-1); | |
772 | } | |
773 | ||
774 | create_shared_memory_BAR(s, fd); | |
775 | ||
776 | } | |
777 | ||
b7578eaa | 778 | dev->config_write = ivshmem_write_config; |
4490c711 | 779 | |
6cbf4c8c CM |
780 | return 0; |
781 | } | |
782 | ||
f90c2bcd | 783 | static void pci_ivshmem_uninit(PCIDevice *dev) |
6cbf4c8c | 784 | { |
eb3fedf3 | 785 | IVShmemState *s = IVSHMEM(dev); |
6cbf4c8c | 786 | |
38e0735e AL |
787 | if (s->migration_blocker) { |
788 | migrate_del_blocker(s->migration_blocker); | |
789 | error_free(s->migration_blocker); | |
790 | } | |
791 | ||
cb06608e AK |
792 | memory_region_destroy(&s->ivshmem_mmio); |
793 | memory_region_del_subregion(&s->bar, &s->ivshmem); | |
eb3fedf3 | 794 | vmstate_unregister_ram(&s->ivshmem, DEVICE(dev)); |
cb06608e AK |
795 | memory_region_destroy(&s->ivshmem); |
796 | memory_region_destroy(&s->bar); | |
eb3fedf3 | 797 | unregister_savevm(DEVICE(dev), "ivshmem", s); |
6cbf4c8c CM |
798 | } |
799 | ||
40021f08 AL |
800 | static Property ivshmem_properties[] = { |
801 | DEFINE_PROP_CHR("chardev", IVShmemState, server_chr), | |
802 | DEFINE_PROP_STRING("size", IVShmemState, sizearg), | |
803 | DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1), | |
804 | DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD, false), | |
805 | DEFINE_PROP_BIT("msi", IVShmemState, features, IVSHMEM_MSI, true), | |
806 | DEFINE_PROP_STRING("shm", IVShmemState, shmobj), | |
807 | DEFINE_PROP_STRING("role", IVShmemState, role), | |
c08ba66f | 808 | DEFINE_PROP_UINT32("use64", IVShmemState, ivshmem_64bit, 1), |
40021f08 AL |
809 | DEFINE_PROP_END_OF_LIST(), |
810 | }; | |
811 | ||
812 | static void ivshmem_class_init(ObjectClass *klass, void *data) | |
813 | { | |
39bffca2 | 814 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
815 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
816 | ||
817 | k->init = pci_ivshmem_init; | |
818 | k->exit = pci_ivshmem_uninit; | |
b8ef62a9 PB |
819 | k->vendor_id = PCI_VENDOR_ID_IVSHMEM; |
820 | k->device_id = PCI_DEVICE_ID_IVSHMEM; | |
40021f08 | 821 | k->class_id = PCI_CLASS_MEMORY_RAM; |
39bffca2 AL |
822 | dc->reset = ivshmem_reset; |
823 | dc->props = ivshmem_properties; | |
125ee0ed | 824 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
40021f08 AL |
825 | } |
826 | ||
8c43a6f0 | 827 | static const TypeInfo ivshmem_info = { |
eb3fedf3 | 828 | .name = TYPE_IVSHMEM, |
39bffca2 AL |
829 | .parent = TYPE_PCI_DEVICE, |
830 | .instance_size = sizeof(IVShmemState), | |
831 | .class_init = ivshmem_class_init, | |
6cbf4c8c CM |
832 | }; |
833 | ||
83f7d43a | 834 | static void ivshmem_register_types(void) |
6cbf4c8c | 835 | { |
39bffca2 | 836 | type_register_static(&ivshmem_info); |
6cbf4c8c CM |
837 | } |
838 | ||
83f7d43a | 839 | type_init(ivshmem_register_types) |