[qemu.git] / hw / msix.c

/*
 * MSI-X device support
 *
 * This module includes support for MSI-X in pci devices.
 *
 * Author: Michael S. Tsirkin <mst@redhat.com>
 *
 *  Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 */

#include "hw.h"
#include "msix.h"
#include "pci.h"

/* Declaration from linux/pci_regs.h */
#define  PCI_CAP_ID_MSIX 0x11 /* MSI-X */
#define  PCI_MSIX_FLAGS 2     /* Table at lower 11 bits */
#define  PCI_MSIX_FLAGS_QSIZE	0x7FF
#define  PCI_MSIX_FLAGS_ENABLE	(1 << 15)
#define  PCI_MSIX_FLAGS_BIRMASK	(7 << 0)

/* MSI-X capability structure */
#define MSIX_TABLE_OFFSET 4
#define MSIX_PBA_OFFSET 8
#define MSIX_CAP_LENGTH 12

/* MSI enable bit is in byte 1 in FLAGS register */
#define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1)
#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)

/* MSI-X table format */
#define MSIX_MSG_ADDR 0
#define MSIX_MSG_UPPER_ADDR 4
#define MSIX_MSG_DATA 8
#define MSIX_VECTOR_CTRL 12
#define MSIX_ENTRY_SIZE 16
#define MSIX_VECTOR_MASK 0x1

/* How much space does an MSIX table need. */
/* The spec requires giving the table structure
 * a 4K aligned region all by itself. */
#define MSIX_PAGE_SIZE 0x1000
/* Reserve second half of the page for pending bits */
#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
#define MSIX_MAX_ENTRIES 32


#ifdef MSIX_DEBUG
#define DEBUG(fmt, ...)                                       \
    do {                                                      \
      fprintf(stderr, "%s: " fmt, __func__ , __VA_ARGS__);    \
    } while (0)
#else
#define DEBUG(fmt, ...) do { } while(0)
#endif

/* Flag for interrupt controller to declare MSI-X support */
int msix_supported;

/* Add MSI-X capability to the config space for the device. */
/* Given a bar and its size, add MSI-X table on top of it
 * and fill MSI-X capability in the config space.
 * Original bar size must be a power of 2 or 0.
 * New bar size is returned. */
static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
                           unsigned bar_nr, unsigned bar_size)
{
    int config_offset;
    uint8_t *config;
    uint32_t new_size;

    if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
        return -EINVAL;
    if (bar_size > 0x80000000)
        return -ENOSPC;

    /* Add space for MSI-X structures */
    if (!bar_size) {
        new_size = MSIX_PAGE_SIZE;
    } else if (bar_size < MSIX_PAGE_SIZE) {
        bar_size = MSIX_PAGE_SIZE;
        new_size = MSIX_PAGE_SIZE * 2;
    } else {
        new_size = bar_size * 2;
    }

    pdev->msix_bar_size = new_size;
    config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
    if (config_offset < 0)
        return config_offset;
    config = pdev->config + config_offset;

    pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
    /* Table on top of BAR */
    pci_set_long(config + MSIX_TABLE_OFFSET, bar_size | bar_nr);
    /* Pending bits on top of that */
    pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) |
                 bar_nr);
    pdev->msix_cap = config_offset;
    /* Make flags bit writeable. */
    pdev->wmask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK;
    return 0;
}

static void msix_free_irq_entries(PCIDevice *dev)
{
    int vector;

    for (vector = 0; vector < dev->msix_entries_nr; ++vector)
        dev->msix_entry_used[vector] = 0;
}

/* Handle MSI-X capability config write. */
void msix_write_config(PCIDevice *dev, uint32_t addr,
                       uint32_t val, int len)
{
    unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET;
    if (addr + len <= enable_pos || addr > enable_pos)
        return;

    if (msix_enabled(dev))
        qemu_set_irq(dev->irq[0], 0);
}

static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
{
    PCIDevice *dev = opaque;
    unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
    void *page = dev->msix_table_page;

    return pci_get_long(page + offset);
}

static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
{
    fprintf(stderr, "MSI-X: only dword read is allowed!\n");
    return 0;
}

static uint8_t msix_pending_mask(int vector)
{
    return 1 << (vector % 8);
}

static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
{
    return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
}

static int msix_is_pending(PCIDevice *dev, int vector)
{
    return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
}

static void msix_set_pending(PCIDevice *dev, int vector)
{
    *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
}

static void msix_clr_pending(PCIDevice *dev, int vector)
{
    *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
}

static int msix_is_masked(PCIDevice *dev, int vector)
{
    unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
    return dev->msix_table_page[offset] & MSIX_VECTOR_MASK;
}

static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
                             uint32_t val)
{
    PCIDevice *dev = opaque;
    unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
    int vector = offset / MSIX_ENTRY_SIZE;
    pci_set_long(dev->msix_table_page + offset, val);
    if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
        msix_clr_pending(dev, vector);
        msix_notify(dev, vector);
    }
}

static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr,
                                      uint32_t val)
{
    fprintf(stderr, "MSI-X: only dword write is allowed!\n");
}

static CPUWriteMemoryFunc * const msix_mmio_write[] = {
    msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel
};

static CPUReadMemoryFunc * const msix_mmio_read[] = {
    msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl
};

/* Should be called from device's map method. */
void msix_mmio_map(PCIDevice *d, int region_num,
                   pcibus_t addr, pcibus_t size, int type)
{
    uint8_t *config = d->config + d->msix_cap;
    uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET);
    uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
    /* TODO: for assigned devices, we'll want to make it possible to map
     * pending bits separately in case they are in a separate bar. */
    int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;

    if (table_bir != region_num)
        return;
    if (size <= offset)
        return;
    cpu_register_physical_memory(addr + offset, size - offset,
                                 d->msix_mmio_index);
}

/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
 * modified, it should be retrieved with msix_bar_size. */
int msix_init(struct PCIDevice *dev, unsigned short nentries,
              unsigned bar_nr, unsigned bar_size)
{
    int ret;
    /* Nothing to do if MSI is not supported by interrupt controller */
    if (!msix_supported)
        return -ENOTSUP;

    if (nentries > MSIX_MAX_ENTRIES)
        return -EINVAL;

    dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES *
                                        sizeof *dev->msix_entry_used);

    dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE);

    dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read,
                                                  msix_mmio_write, dev);
    if (dev->msix_mmio_index == -1) {
        ret = -EBUSY;
        goto err_index;
    }

    dev->msix_entries_nr = nentries;
    ret = msix_add_config(dev, nentries, bar_nr, bar_size);
    if (ret)
        goto err_config;

    dev->cap_present |= QEMU_PCI_CAP_MSIX;
    return 0;

err_config:
    dev->msix_entries_nr = 0;
    cpu_unregister_io_memory(dev->msix_mmio_index);
err_index:
    qemu_free(dev->msix_table_page);
    dev->msix_table_page = NULL;
    qemu_free(dev->msix_entry_used);
    dev->msix_entry_used = NULL;
    return ret;
}

/* Clean up resources for the device. */
int msix_uninit(PCIDevice *dev)
{
    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
        return 0;
    pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
    dev->msix_cap = 0;
    msix_free_irq_entries(dev);
    dev->msix_entries_nr = 0;
    cpu_unregister_io_memory(dev->msix_mmio_index);
    qemu_free(dev->msix_table_page);
    dev->msix_table_page = NULL;
    qemu_free(dev->msix_entry_used);
    dev->msix_entry_used = NULL;
    dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
    return 0;
}

void msix_save(PCIDevice *dev, QEMUFile *f)
{
    unsigned n = dev->msix_entries_nr;

    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
        return;
    }

    qemu_put_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
    qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
}

/* Should be called after restoring the config space. */
void msix_load(PCIDevice *dev, QEMUFile *f)
{
    unsigned n = dev->msix_entries_nr;

    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
        return;
    }

    msix_free_irq_entries(dev);
    qemu_get_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
    qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
}

/* Does device support MSI-X? */
int msix_present(PCIDevice *dev)
{
    return dev->cap_present & QEMU_PCI_CAP_MSIX;
}

/* Is MSI-X enabled? */
int msix_enabled(PCIDevice *dev)
{
    return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
        (dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &
         MSIX_ENABLE_MASK);
}

/* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
uint32_t msix_bar_size(PCIDevice *dev)
{
    return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
        dev->msix_bar_size : 0;
}

/* Send an MSI-X message */
void msix_notify(PCIDevice *dev, unsigned vector)
{
    uint8_t *table_entry = dev->msix_table_page + vector * MSIX_ENTRY_SIZE;
    uint64_t address;
    uint32_t data;

    if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
        return;
    if (msix_is_masked(dev, vector)) {
        msix_set_pending(dev, vector);
        return;
    }

    address = pci_get_long(table_entry + MSIX_MSG_UPPER_ADDR);
    address = (address << 32) | pci_get_long(table_entry + MSIX_MSG_ADDR);
    data = pci_get_long(table_entry + MSIX_MSG_DATA);
    stl_phys(address, data);
}

void msix_reset(PCIDevice *dev)
{
    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
        return;
    msix_free_irq_entries(dev);
    dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &= MSIX_ENABLE_MASK;
    memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
}

/* PCI spec suggests that devices make it possible for software to configure
 * less vectors than supported by the device, but does not specify a standard
 * mechanism for devices to do so.
 *
 * We support this by asking devices to declare vectors software is going to
 * actually use, and checking this on the notification path. Devices that
 * don't want to follow the spec suggestion can declare all vectors as used. */

/* Mark vector as used. */
int msix_vector_use(PCIDevice *dev, unsigned vector)
{
    if (vector >= dev->msix_entries_nr)
        return -EINVAL;
    dev->msix_entry_used[vector]++;
    return 0;
}

/* Mark vector as unused. */
void msix_vector_unuse(PCIDevice *dev, unsigned vector)
{
    if (vector < dev->msix_entries_nr && dev->msix_entry_used[vector])
        --dev->msix_entry_used[vector];
}
Commit	Line	Data
02eb84d0 MT	1	/*
	2	* MSI-X device support
	3	*
	4	* This module includes support for MSI-X in pci devices.
	5	*
	6	* Author: Michael S. Tsirkin <mst@redhat.com>
	7	*
	8	* Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
	9	*
	10	* This work is licensed under the terms of the GNU GPL, version 2. See
	11	* the COPYING file in the top-level directory.
	12	*/
	13
	14	#include "hw.h"
	15	#include "msix.h"
	16	#include "pci.h"
	17
	18	/* Declaration from linux/pci_regs.h */
	19	#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
	20	#define PCI_MSIX_FLAGS 2 /* Table at lower 11 bits */
	21	#define PCI_MSIX_FLAGS_QSIZE 0x7FF
	22	#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
	23	#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
	24
	25	/* MSI-X capability structure */
	26	#define MSIX_TABLE_OFFSET 4
	27	#define MSIX_PBA_OFFSET 8
	28	#define MSIX_CAP_LENGTH 12
	29
	30	/* MSI enable bit is in byte 1 in FLAGS register */
	31	#define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1)
	32	#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
	33
	34	/* MSI-X table format */
	35	#define MSIX_MSG_ADDR 0
	36	#define MSIX_MSG_UPPER_ADDR 4
	37	#define MSIX_MSG_DATA 8
	38	#define MSIX_VECTOR_CTRL 12
	39	#define MSIX_ENTRY_SIZE 16
	40	#define MSIX_VECTOR_MASK 0x1
5a1fc5e8 MT	41
	42	/* How much space does an MSIX table need. */
	43	/* The spec requires giving the table structure
	44	* a 4K aligned region all by itself. */
	45	#define MSIX_PAGE_SIZE 0x1000
	46	/* Reserve second half of the page for pending bits */
	47	#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
02eb84d0 MT	48	#define MSIX_MAX_ENTRIES 32
	49
	50
	51	#ifdef MSIX_DEBUG
	52	#define DEBUG(fmt, ...) \
	53	do { \
	54	fprintf(stderr, "%s: " fmt, __func__ , __VA_ARGS__); \
	55	} while (0)
	56	#else
	57	#define DEBUG(fmt, ...) do { } while(0)
	58	#endif
	59
	60	/* Flag for interrupt controller to declare MSI-X support */
	61	int msix_supported;
	62
	63	/* Add MSI-X capability to the config space for the device. */
	64	/* Given a bar and its size, add MSI-X table on top of it
	65	* and fill MSI-X capability in the config space.
	66	* Original bar size must be a power of 2 or 0.
	67	* New bar size is returned. */
	68	static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
	69	unsigned bar_nr, unsigned bar_size)
	70	{
	71	int config_offset;
	72	uint8_t *config;
	73	uint32_t new_size;
	74
	75	if (nentries < 1 \|\| nentries > PCI_MSIX_FLAGS_QSIZE + 1)
	76	return -EINVAL;
	77	if (bar_size > 0x80000000)
	78	return -ENOSPC;
	79
	80	/* Add space for MSI-X structures */
5e520a7d	81	if (!bar_size) {
5a1fc5e8 MT	82	new_size = MSIX_PAGE_SIZE;
	83	} else if (bar_size < MSIX_PAGE_SIZE) {
	84	bar_size = MSIX_PAGE_SIZE;
	85	new_size = MSIX_PAGE_SIZE * 2;
	86	} else {
02eb84d0	87	new_size = bar_size * 2;
5a1fc5e8	88	}
02eb84d0 MT	89
	90	pdev->msix_bar_size = new_size;
	91	config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
	92	if (config_offset < 0)
	93	return config_offset;
	94	config = pdev->config + config_offset;
	95
	96	pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
	97	/* Table on top of BAR */
	98	pci_set_long(config + MSIX_TABLE_OFFSET, bar_size \| bar_nr);
	99	/* Pending bits on top of that */
5a1fc5e8 MT	100	pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) \|
5a1fc5e8 MT	101	bar_nr);
02eb84d0 MT	102	pdev->msix_cap = config_offset;
	103	/* Make flags bit writeable. */
	104	pdev->wmask[config_offset + MSIX_ENABLE_OFFSET] \|= MSIX_ENABLE_MASK;
	105	return 0;
	106	}
	107
	108	static void msix_free_irq_entries(PCIDevice *dev)
	109	{
	110	int vector;
	111
	112	for (vector = 0; vector < dev->msix_entries_nr; ++vector)
	113	dev->msix_entry_used[vector] = 0;
	114	}
	115
	116	/* Handle MSI-X capability config write. */
	117	void msix_write_config(PCIDevice *dev, uint32_t addr,
	118	uint32_t val, int len)
	119	{
	120	unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET;
	121	if (addr + len <= enable_pos \|\| addr > enable_pos)
	122	return;
	123
	124	if (msix_enabled(dev))
	125	qemu_set_irq(dev->irq[0], 0);
	126	}
	127
c227f099	128	static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
02eb84d0 MT	129	{
02eb84d0 MT	130	PCIDevice *dev = opaque;
76f5159d	131	unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
02eb84d0	132	void *page = dev->msix_table_page;
02eb84d0	133
76f5159d	134	return pci_get_long(page + offset);
02eb84d0 MT	135	}
02eb84d0 MT	136
c227f099	137	static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
02eb84d0 MT	138	{
	139	fprintf(stderr, "MSI-X: only dword read is allowed!\n");
	140	return 0;
	141	}
	142
	143	static uint8_t msix_pending_mask(int vector)
	144	{
	145	return 1 << (vector % 8);
	146	}
	147
	148	static uint8_t msix_pending_byte(PCIDevice dev, int vector)
	149	{
5a1fc5e8	150	return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
02eb84d0 MT	151	}
	152
	153	static int msix_is_pending(PCIDevice *dev, int vector)
	154	{
	155	return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
	156	}
	157
	158	static void msix_set_pending(PCIDevice *dev, int vector)
	159	{
	160	*msix_pending_byte(dev, vector) \|= msix_pending_mask(vector);
	161	}
	162
	163	static void msix_clr_pending(PCIDevice *dev, int vector)
	164	{
	165	*msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
	166	}
	167
	168	static int msix_is_masked(PCIDevice *dev, int vector)
	169	{
	170	unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
	171	return dev->msix_table_page[offset] & MSIX_VECTOR_MASK;
	172	}
	173
c227f099	174	static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
02eb84d0 MT	175	uint32_t val)
	176	{
	177	PCIDevice *dev = opaque;
76f5159d	178	unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
02eb84d0	179	int vector = offset / MSIX_ENTRY_SIZE;
76f5159d	180	pci_set_long(dev->msix_table_page + offset, val);
02eb84d0 MT	181	if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
	182	msix_clr_pending(dev, vector);
	183	msix_notify(dev, vector);
	184	}
	185	}
	186
c227f099	187	static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr,
02eb84d0 MT	188	uint32_t val)
	189	{
	190	fprintf(stderr, "MSI-X: only dword write is allowed!\n");
	191	}
	192
d60efc6b	193	static CPUWriteMemoryFunc * const msix_mmio_write[] = {
02eb84d0 MT	194	msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel
	195	};
	196
d60efc6b	197	static CPUReadMemoryFunc * const msix_mmio_read[] = {
02eb84d0 MT	198	msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl
	199	};
	200
	201	/* Should be called from device's map method. */
	202	void msix_mmio_map(PCIDevice *d, int region_num,
6e355d90	203	pcibus_t addr, pcibus_t size, int type)
02eb84d0 MT	204	{
	205	uint8_t *config = d->config + d->msix_cap;
	206	uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET);
5a1fc5e8	207	uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
02eb84d0 MT	208	/* TODO: for assigned devices, we'll want to make it possible to map
	209	* pending bits separately in case they are in a separate bar. */
	210	int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;
	211
	212	if (table_bir != region_num)
	213	return;
	214	if (size <= offset)
	215	return;
	216	cpu_register_physical_memory(addr + offset, size - offset,
	217	d->msix_mmio_index);
	218	}
	219
	220	/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
	221	* modified, it should be retrieved with msix_bar_size. */
	222	int msix_init(struct PCIDevice *dev, unsigned short nentries,
5a1fc5e8	223	unsigned bar_nr, unsigned bar_size)
02eb84d0 MT	224	{
	225	int ret;
	226	/* Nothing to do if MSI is not supported by interrupt controller */
	227	if (!msix_supported)
	228	return -ENOTSUP;
	229
	230	if (nentries > MSIX_MAX_ENTRIES)
	231	return -EINVAL;
	232
	233	dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES *
	234	sizeof *dev->msix_entry_used);
	235
5a1fc5e8	236	dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE);
02eb84d0 MT	237
	238	dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read,
	239	msix_mmio_write, dev);
	240	if (dev->msix_mmio_index == -1) {
	241	ret = -EBUSY;
	242	goto err_index;
	243	}
	244
	245	dev->msix_entries_nr = nentries;
	246	ret = msix_add_config(dev, nentries, bar_nr, bar_size);
	247	if (ret)
	248	goto err_config;
	249
	250	dev->cap_present \|= QEMU_PCI_CAP_MSIX;
	251	return 0;
	252
	253	err_config:
3174ecd1	254	dev->msix_entries_nr = 0;
02eb84d0 MT	255	cpu_unregister_io_memory(dev->msix_mmio_index);
	256	err_index:
	257	qemu_free(dev->msix_table_page);
	258	dev->msix_table_page = NULL;
	259	qemu_free(dev->msix_entry_used);
	260	dev->msix_entry_used = NULL;
	261	return ret;
	262	}
	263
	264	/* Clean up resources for the device. */
	265	int msix_uninit(PCIDevice *dev)
	266	{
	267	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
	268	return 0;
	269	pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
	270	dev->msix_cap = 0;
	271	msix_free_irq_entries(dev);
	272	dev->msix_entries_nr = 0;
	273	cpu_unregister_io_memory(dev->msix_mmio_index);
	274	qemu_free(dev->msix_table_page);
	275	dev->msix_table_page = NULL;
	276	qemu_free(dev->msix_entry_used);
	277	dev->msix_entry_used = NULL;
	278	dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
	279	return 0;
	280	}
	281
	282	void msix_save(PCIDevice dev, QEMUFile f)
	283	{
9a3e12c8 MT	284	unsigned n = dev->msix_entries_nr;
9a3e12c8 MT	285
72755a70	286	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
9a3e12c8	287	return;
72755a70	288	}
9a3e12c8 MT	289
9a3e12c8 MT	290	qemu_put_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
5a1fc5e8	291	qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
02eb84d0 MT	292	}
	293
	294	/* Should be called after restoring the config space. */
	295	void msix_load(PCIDevice dev, QEMUFile f)
	296	{
	297	unsigned n = dev->msix_entries_nr;
	298
98846d73	299	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
02eb84d0	300	return;
98846d73	301	}
02eb84d0	302
4bfd1712	303	msix_free_irq_entries(dev);
02eb84d0	304	qemu_get_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
5a1fc5e8	305	qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
02eb84d0 MT	306	}
	307
	308	/* Does device support MSI-X? */
	309	int msix_present(PCIDevice *dev)
	310	{
	311	return dev->cap_present & QEMU_PCI_CAP_MSIX;
	312	}
	313
	314	/* Is MSI-X enabled? */
	315	int msix_enabled(PCIDevice *dev)
	316	{
	317	return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
	318	(dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &
	319	MSIX_ENABLE_MASK);
	320	}
	321
	322	/* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
	323	uint32_t msix_bar_size(PCIDevice *dev)
	324	{
	325	return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
	326	dev->msix_bar_size : 0;
	327	}
	328
	329	/* Send an MSI-X message */
	330	void msix_notify(PCIDevice *dev, unsigned vector)
	331	{
	332	uint8_t table_entry = dev->msix_table_page + vector MSIX_ENTRY_SIZE;
	333	uint64_t address;
	334	uint32_t data;
	335
	336	if (vector >= dev->msix_entries_nr \|\| !dev->msix_entry_used[vector])
	337	return;
	338	if (msix_is_masked(dev, vector)) {
	339	msix_set_pending(dev, vector);
	340	return;
	341	}
	342
	343	address = pci_get_long(table_entry + MSIX_MSG_UPPER_ADDR);
	344	address = (address << 32) \| pci_get_long(table_entry + MSIX_MSG_ADDR);
	345	data = pci_get_long(table_entry + MSIX_MSG_DATA);
	346	stl_phys(address, data);
	347	}
	348
	349	void msix_reset(PCIDevice *dev)
	350	{
	351	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
	352	return;
	353	msix_free_irq_entries(dev);
	354	dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &= MSIX_ENABLE_MASK;
5a1fc5e8	355	memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
02eb84d0 MT	356	}
	357
	358	/* PCI spec suggests that devices make it possible for software to configure
	359	* less vectors than supported by the device, but does not specify a standard
	360	* mechanism for devices to do so.
	361	*
	362	* We support this by asking devices to declare vectors software is going to
	363	* actually use, and checking this on the notification path. Devices that
	364	* don't want to follow the spec suggestion can declare all vectors as used. */
	365
	366	/* Mark vector as used. */
	367	int msix_vector_use(PCIDevice *dev, unsigned vector)
	368	{
	369	if (vector >= dev->msix_entries_nr)
	370	return -EINVAL;
	371	dev->msix_entry_used[vector]++;
	372	return 0;
	373	}
	374
	375	/* Mark vector as unused. */
	376	void msix_vector_unuse(PCIDevice *dev, unsigned vector)
	377	{
	378	if (vector < dev->msix_entries_nr && dev->msix_entry_used[vector])
	379	--dev->msix_entry_used[vector];
	380	}