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[mirror_qemu.git] / hw / net / vmxnet3.h
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786fd2b0
DF		 1/*
2 * QEMU VMWARE VMXNET3 paravirtual NIC interface definitions
3 *
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
5 *
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
7 *
8 * Authors:
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
15 *
16 */
17
2a6a4076
MA		 18#ifndef QEMU_VMXNET3_H
19#define QEMU_VMXNET3_H
786fd2b0
DF		 20
21#define VMXNET3_DEVICE_MAX_TX_QUEUES 8
22#define VMXNET3_DEVICE_MAX_RX_QUEUES 8 /* Keep this value as a power of 2 */
23
24/*
25 * VMWARE headers we got from Linux kernel do not fully comply QEMU coding
26 * standards in sense of types and defines used.
27 * Since we didn't want to change VMWARE code, following set of typedefs
28 * and defines needed to compile these headers with QEMU introduced.
29 */
30#define u64 uint64_t
31#define u32 uint32_t
32#define u16 uint16_t
33#define u8 uint8_t
34#define __le16 uint16_t
35#define __le32 uint32_t
36#define __le64 uint64_t
786fd2b0
DF		 37
38#if defined(HOST_WORDS_BIGENDIAN)
786fd2b0
DF		 39#define __BIG_ENDIAN_BITFIELD
40#else
786fd2b0
DF		 41#endif
42
43/*
44 * Following is an interface definition for
45 * VMXNET3 device as provided by VMWARE
46 * See original copyright from Linux kernel v3.2.8
47 * header file drivers/net/vmxnet3/vmxnet3_defs.h below.
48 */
49
50/*
51 * Linux driver for VMware's vmxnet3 ethernet NIC.
52 *
53 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
54 *
55 * This program is free software; you can redistribute it and/or modify it
56 * under the terms of the GNU General Public License as published by the
57 * Free Software Foundation; version 2 of the License and no later version.
58 *
59 * This program is distributed in the hope that it will be useful, but
60 * WITHOUT ANY WARRANTY; without even the implied warranty of
61 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
62 * NON INFRINGEMENT. See the GNU General Public License for more
63 * details.
64 *
65 * You should have received a copy of the GNU General Public License
66 * along with this program; if not, write to the Free Software
67 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
68 *
69 * The full GNU General Public License is included in this distribution in
70 * the file called "COPYING".
71 *
72 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
73 *
74 */
75
76struct UPT1_TxStats {
77 u64 TSOPktsTxOK; /* TSO pkts post-segmentation */
78 u64 TSOBytesTxOK;
79 u64 ucastPktsTxOK;
80 u64 ucastBytesTxOK;
81 u64 mcastPktsTxOK;
82 u64 mcastBytesTxOK;
83 u64 bcastPktsTxOK;
84 u64 bcastBytesTxOK;
85 u64 pktsTxError;
86 u64 pktsTxDiscard;
87};
88
89struct UPT1_RxStats {
90 u64 LROPktsRxOK; /* LRO pkts */
91 u64 LROBytesRxOK; /* bytes from LRO pkts */
92 /* the following counters are for pkts from the wire, i.e., pre-LRO */
93 u64 ucastPktsRxOK;
94 u64 ucastBytesRxOK;
95 u64 mcastPktsRxOK;
96 u64 mcastBytesRxOK;
97 u64 bcastPktsRxOK;
98 u64 bcastBytesRxOK;
99 u64 pktsRxOutOfBuf;
100 u64 pktsRxError;
101};
102
103/* interrupt moderation level */
104enum {
105 UPT1_IML_NONE = 0, /* no interrupt moderation */
106 UPT1_IML_HIGHEST = 7, /* least intr generated */
107 UPT1_IML_ADAPTIVE = 8, /* adpative intr moderation */
108};
109/* values for UPT1_RSSConf.hashFunc */
110enum {
111 UPT1_RSS_HASH_TYPE_NONE = 0x0,
112 UPT1_RSS_HASH_TYPE_IPV4 = 0x01,
113 UPT1_RSS_HASH_TYPE_TCP_IPV4 = 0x02,
114 UPT1_RSS_HASH_TYPE_IPV6 = 0x04,
115 UPT1_RSS_HASH_TYPE_TCP_IPV6 = 0x08,
116};
117
118enum {
119 UPT1_RSS_HASH_FUNC_NONE = 0x0,
120 UPT1_RSS_HASH_FUNC_TOEPLITZ = 0x01,
121};
122
123#define UPT1_RSS_MAX_KEY_SIZE 40
124#define UPT1_RSS_MAX_IND_TABLE_SIZE 128
125
126struct UPT1_RSSConf {
127 u16 hashType;
128 u16 hashFunc;
129 u16 hashKeySize;
130 u16 indTableSize;
131 u8 hashKey[UPT1_RSS_MAX_KEY_SIZE];
132 u8 indTable[UPT1_RSS_MAX_IND_TABLE_SIZE];
133};
134
135/* features */
136enum {
389dd807
DF		 137 UPT1_F_RXCSUM = 0x0001, /* rx csum verification */
138 UPT1_F_RSS = 0x0002,
139 UPT1_F_RXVLAN = 0x0004, /* VLAN tag stripping */
140 UPT1_F_LRO = 0x0008,
786fd2b0
DF		 141};
142
143/* all registers are 32 bit wide */
144/* BAR 1 */
145enum {
146 VMXNET3_REG_VRRS = 0x0, /* Vmxnet3 Revision Report Selection */
147 VMXNET3_REG_UVRS = 0x8, /* UPT Version Report Selection */
148 VMXNET3_REG_DSAL = 0x10, /* Driver Shared Address Low */
149 VMXNET3_REG_DSAH = 0x18, /* Driver Shared Address High */
150 VMXNET3_REG_CMD = 0x20, /* Command */
151 VMXNET3_REG_MACL = 0x28, /* MAC Address Low */
152 VMXNET3_REG_MACH = 0x30, /* MAC Address High */
153 VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */
154 VMXNET3_REG_ECR = 0x40 /* Event Cause Register */
155};
156
157/* BAR 0 */
158enum {
159 VMXNET3_REG_IMR = 0x0, /* Interrupt Mask Register */
160 VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */
161 VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */
162 VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */
163};
164
165#define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */
166#define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */
167
168#define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
169#define VMXNET3_REG_ALIGN_MASK 0x7
170
171/* I/O Mapped access to registers */
172#define VMXNET3_IO_TYPE_PT 0
173#define VMXNET3_IO_TYPE_VD 1
174#define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
175#define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
176#define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
177
178enum {
179 VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
180 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET, /* 0xCAFE0000 */
181 VMXNET3_CMD_QUIESCE_DEV, /* 0xCAFE0001 */
182 VMXNET3_CMD_RESET_DEV, /* 0xCAFE0002 */
183 VMXNET3_CMD_UPDATE_RX_MODE, /* 0xCAFE0003 */
184 VMXNET3_CMD_UPDATE_MAC_FILTERS, /* 0xCAFE0004 */
185 VMXNET3_CMD_UPDATE_VLAN_FILTERS, /* 0xCAFE0005 */
186 VMXNET3_CMD_UPDATE_RSSIDT, /* 0xCAFE0006 */
187 VMXNET3_CMD_UPDATE_IML, /* 0xCAFE0007 */
188 VMXNET3_CMD_UPDATE_PMCFG, /* 0xCAFE0008 */
189 VMXNET3_CMD_UPDATE_FEATURE, /* 0xCAFE0009 */
190 VMXNET3_CMD_LOAD_PLUGIN, /* 0xCAFE000A */
191
192 VMXNET3_CMD_FIRST_GET = 0xF00D0000,
193 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET, /* 0xF00D0000 */
194 VMXNET3_CMD_GET_STATS, /* 0xF00D0001 */
195 VMXNET3_CMD_GET_LINK, /* 0xF00D0002 */
196 VMXNET3_CMD_GET_PERM_MAC_LO, /* 0xF00D0003 */
197 VMXNET3_CMD_GET_PERM_MAC_HI, /* 0xF00D0004 */
198 VMXNET3_CMD_GET_DID_LO, /* 0xF00D0005 */
199 VMXNET3_CMD_GET_DID_HI, /* 0xF00D0006 */
200 VMXNET3_CMD_GET_DEV_EXTRA_INFO, /* 0xF00D0007 */
d62241eb
SL		 201 VMXNET3_CMD_GET_CONF_INTR, /* 0xF00D0008 */
202 VMXNET3_CMD_GET_ADAPTIVE_RING_INFO /* 0xF00D0009 */
786fd2b0
DF		 203};
204
d62241eb
SL		 205/* Adaptive Ring Info Flags */
206#define VMXNET3_DISABLE_ADAPTIVE_RING 1
207
786fd2b0
DF		 208/*
209 * Little Endian layout of bitfields -
210 * Byte 0 : 7.....len.....0
211 * Byte 1 : rsvd gen 13.len.8
212 * Byte 2 : 5.msscof.0 ext1 dtype
213 * Byte 3 : 13...msscof...6
214 *
215 * Big Endian layout of bitfields -
216 * Byte 0: 13...msscof...6
217 * Byte 1 : 5.msscof.0 ext1 dtype
218 * Byte 2 : rsvd gen 13.len.8
219 * Byte 3 : 7.....len.....0
220 *
221 * Thus, le32_to_cpu on the dword will allow the big endian driver to read
222 * the bit fields correctly. And cpu_to_le32 will convert bitfields
223 * bit fields written by big endian driver to format required by device.
224 */
225
226struct Vmxnet3_TxDesc {
227 __le64 addr;
228
229#ifdef __BIG_ENDIAN_BITFIELD
230 u32 msscof:14; /* MSS, checksum offset, flags */
231 u32 ext1:1;
232 u32 dtype:1; /* descriptor type */
233 u32 rsvd:1;
234 u32 gen:1; /* generation bit */
235 u32 len:14;
236#else
237 u32 len:14;
238 u32 gen:1; /* generation bit */
239 u32 rsvd:1;
240 u32 dtype:1; /* descriptor type */
241 u32 ext1:1;
242 u32 msscof:14; /* MSS, checksum offset, flags */
243#endif /* __BIG_ENDIAN_BITFIELD */
244
245#ifdef __BIG_ENDIAN_BITFIELD
246 u32 tci:16; /* Tag to Insert */
247 u32 ti:1; /* VLAN Tag Insertion */
248 u32 ext2:1;
249 u32 cq:1; /* completion request */
250 u32 eop:1; /* End Of Packet */
251 u32 om:2; /* offload mode */
252 u32 hlen:10; /* header len */
253#else
254 u32 hlen:10; /* header len */
255 u32 om:2; /* offload mode */
256 u32 eop:1; /* End Of Packet */
257 u32 cq:1; /* completion request */
258 u32 ext2:1;
259 u32 ti:1; /* VLAN Tag Insertion */
260 u32 tci:16; /* Tag to Insert */
261#endif /* __BIG_ENDIAN_BITFIELD */
262};
263
264/* TxDesc.OM values */
265#define VMXNET3_OM_NONE 0
266#define VMXNET3_OM_CSUM 2
267#define VMXNET3_OM_TSO 3
268
269/* fields in TxDesc we access w/o using bit fields */
270#define VMXNET3_TXD_EOP_SHIFT 12
271#define VMXNET3_TXD_CQ_SHIFT 13
272#define VMXNET3_TXD_GEN_SHIFT 14
273#define VMXNET3_TXD_EOP_DWORD_SHIFT 3
274#define VMXNET3_TXD_GEN_DWORD_SHIFT 2
275
276#define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
277#define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
278#define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
279
280#define VMXNET3_HDR_COPY_SIZE 128
281
282
283struct Vmxnet3_TxDataDesc {
284 u8 data[VMXNET3_HDR_COPY_SIZE];
285};
286
287#define VMXNET3_TCD_GEN_SHIFT 31
288#define VMXNET3_TCD_GEN_SIZE 1
289#define VMXNET3_TCD_TXIDX_SHIFT 0
290#define VMXNET3_TCD_TXIDX_SIZE 12
291#define VMXNET3_TCD_GEN_DWORD_SHIFT 3
292
293struct Vmxnet3_TxCompDesc {
294 u32 txdIdx:12; /* Index of the EOP TxDesc */
295 u32 ext1:20;
296
297 __le32 ext2;
298 __le32 ext3;
299
300 u32 rsvd:24;
301 u32 type:7; /* completion type */
302 u32 gen:1; /* generation bit */
303};
304
305struct Vmxnet3_RxDesc {
306 __le64 addr;
307
308#ifdef __BIG_ENDIAN_BITFIELD
309 u32 gen:1; /* Generation bit */
310 u32 rsvd:15;
311 u32 dtype:1; /* Descriptor type */
312 u32 btype:1; /* Buffer Type */
313 u32 len:14;
314#else
315 u32 len:14;
316 u32 btype:1; /* Buffer Type */
317 u32 dtype:1; /* Descriptor type */
318 u32 rsvd:15;
319 u32 gen:1; /* Generation bit */
320#endif
321 u32 ext1;
322};
323
324/* values of RXD.BTYPE */
325#define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */
326#define VMXNET3_RXD_BTYPE_BODY 1 /* body only */
327
328/* fields in RxDesc we access w/o using bit fields */
329#define VMXNET3_RXD_BTYPE_SHIFT 14
330#define VMXNET3_RXD_GEN_SHIFT 31
331
332struct Vmxnet3_RxCompDesc {
333#ifdef __BIG_ENDIAN_BITFIELD
334 u32 ext2:1;
335 u32 cnc:1; /* Checksum Not Calculated */
336 u32 rssType:4; /* RSS hash type used */
337 u32 rqID:10; /* rx queue/ring ID */
338 u32 sop:1; /* Start of Packet */
339 u32 eop:1; /* End of Packet */
340 u32 ext1:2;
341 u32 rxdIdx:12; /* Index of the RxDesc */
342#else
343 u32 rxdIdx:12; /* Index of the RxDesc */
344 u32 ext1:2;
345 u32 eop:1; /* End of Packet */
346 u32 sop:1; /* Start of Packet */
347 u32 rqID:10; /* rx queue/ring ID */
348 u32 rssType:4; /* RSS hash type used */
349 u32 cnc:1; /* Checksum Not Calculated */
350 u32 ext2:1;
351#endif /* __BIG_ENDIAN_BITFIELD */
352
353 __le32 rssHash; /* RSS hash value */
354
355#ifdef __BIG_ENDIAN_BITFIELD
356 u32 tci:16; /* Tag stripped */
357 u32 ts:1; /* Tag is stripped */
358 u32 err:1; /* Error */
359 u32 len:14; /* data length */
360#else
361 u32 len:14; /* data length */
362 u32 err:1; /* Error */
363 u32 ts:1; /* Tag is stripped */
364 u32 tci:16; /* Tag stripped */
365#endif /* __BIG_ENDIAN_BITFIELD */
366
367
368#ifdef __BIG_ENDIAN_BITFIELD
369 u32 gen:1; /* generation bit */
370 u32 type:7; /* completion type */
371 u32 fcs:1; /* Frame CRC correct */
372 u32 frg:1; /* IP Fragment */
373 u32 v4:1; /* IPv4 */
374 u32 v6:1; /* IPv6 */
375 u32 ipc:1; /* IP Checksum Correct */
376 u32 tcp:1; /* TCP packet */
377 u32 udp:1; /* UDP packet */
378 u32 tuc:1; /* TCP/UDP Checksum Correct */
379 u32 csum:16;
380#else
381 u32 csum:16;
382 u32 tuc:1; /* TCP/UDP Checksum Correct */
383 u32 udp:1; /* UDP packet */
384 u32 tcp:1; /* TCP packet */
385 u32 ipc:1; /* IP Checksum Correct */
386 u32 v6:1; /* IPv6 */
387 u32 v4:1; /* IPv4 */
388 u32 frg:1; /* IP Fragment */
389 u32 fcs:1; /* Frame CRC correct */
390 u32 type:7; /* completion type */
391 u32 gen:1; /* generation bit */
392#endif /* __BIG_ENDIAN_BITFIELD */
393};
394
395/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
396#define VMXNET3_RCD_TUC_SHIFT 16
397#define VMXNET3_RCD_IPC_SHIFT 19
398
399/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
400#define VMXNET3_RCD_TYPE_SHIFT 56
401#define VMXNET3_RCD_GEN_SHIFT 63
402
403/* csum OK for TCP/UDP pkts over IP */
404#define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \
405 1 << VMXNET3_RCD_IPC_SHIFT)
406#define VMXNET3_TXD_GEN_SIZE 1
407#define VMXNET3_TXD_EOP_SIZE 1
408
409/* value of RxCompDesc.rssType */
410enum {
411 VMXNET3_RCD_RSS_TYPE_NONE = 0,
412 VMXNET3_RCD_RSS_TYPE_IPV4 = 1,
413 VMXNET3_RCD_RSS_TYPE_TCPIPV4 = 2,
414 VMXNET3_RCD_RSS_TYPE_IPV6 = 3,
415 VMXNET3_RCD_RSS_TYPE_TCPIPV6 = 4,
416};
417
418
419/* a union for accessing all cmd/completion descriptors */
420union Vmxnet3_GenericDesc {
421 __le64 qword[2];
422 __le32 dword[4];
423 __le16 word[8];
424 struct Vmxnet3_TxDesc txd;
425 struct Vmxnet3_RxDesc rxd;
426 struct Vmxnet3_TxCompDesc tcd;
427 struct Vmxnet3_RxCompDesc rcd;
428};
429
430#define VMXNET3_INIT_GEN 1
431
432/* Max size of a single tx buffer */
433#define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)
434
435/* # of tx desc needed for a tx buffer size */
436#define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
437 VMXNET3_MAX_TX_BUF_SIZE)
438
439/* max # of tx descs for a non-tso pkt */
440#define VMXNET3_MAX_TXD_PER_PKT 16
441
442/* Max size of a single rx buffer */
443#define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
444/* Minimum size of a type 0 buffer */
445#define VMXNET3_MIN_T0_BUF_SIZE 128
446#define VMXNET3_MAX_CSUM_OFFSET 1024
447
448/* Ring base address alignment */
449#define VMXNET3_RING_BA_ALIGN 512
450#define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
451
452/* Ring size must be a multiple of 32 */
453#define VMXNET3_RING_SIZE_ALIGN 32
454#define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
455
456/* Max ring size */
457#define VMXNET3_TX_RING_MAX_SIZE 4096
458#define VMXNET3_TC_RING_MAX_SIZE 4096
459#define VMXNET3_RX_RING_MAX_SIZE 4096
460#define VMXNET3_RC_RING_MAX_SIZE 8192
461
462/* a list of reasons for queue stop */
463
464enum {
465 VMXNET3_ERR_NOEOP = 0x80000000, /* cannot find the EOP desc of a pkt */
466 VMXNET3_ERR_TXD_REUSE = 0x80000001, /* reuse TxDesc before tx completion */
467 VMXNET3_ERR_BIG_PKT = 0x80000002, /* too many TxDesc for a pkt */
468 VMXNET3_ERR_DESC_NOT_SPT = 0x80000003, /* descriptor type not supported */
469 VMXNET3_ERR_SMALL_BUF = 0x80000004, /* type 0 buffer too small */
470 VMXNET3_ERR_STRESS = 0x80000005, /* stress option firing in vmkernel */
471 VMXNET3_ERR_SWITCH = 0x80000006, /* mode switch failure */
472 VMXNET3_ERR_TXD_INVALID = 0x80000007, /* invalid TxDesc */
473};
474
475/* completion descriptor types */
476#define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */
477#define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */
478
479enum {
480 VMXNET3_GOS_BITS_UNK = 0, /* unknown */
481 VMXNET3_GOS_BITS_32 = 1,
482 VMXNET3_GOS_BITS_64 = 2,
483};
484
485#define VMXNET3_GOS_TYPE_UNK 0 /* unknown */
486#define VMXNET3_GOS_TYPE_LINUX 1
487#define VMXNET3_GOS_TYPE_WIN 2
488#define VMXNET3_GOS_TYPE_SOLARIS 3
489#define VMXNET3_GOS_TYPE_FREEBSD 4
490#define VMXNET3_GOS_TYPE_PXE 5
491
492struct Vmxnet3_GOSInfo {
493#ifdef __BIG_ENDIAN_BITFIELD
494 u32 gosMisc:10; /* other info about gos */
495 u32 gosVer:16; /* gos version */
496 u32 gosType:4; /* which guest */
497 u32 gosBits:2; /* 32-bit or 64-bit? */
498#else
499 u32 gosBits:2; /* 32-bit or 64-bit? */
500 u32 gosType:4; /* which guest */
501 u32 gosVer:16; /* gos version */
502 u32 gosMisc:10; /* other info about gos */
503#endif /* __BIG_ENDIAN_BITFIELD */
504};
505
506struct Vmxnet3_DriverInfo {
507 __le32 version;
508 struct Vmxnet3_GOSInfo gos;
509 __le32 vmxnet3RevSpt;
510 __le32 uptVerSpt;
511};
512
513
514#define VMXNET3_REV1_MAGIC 0xbabefee1
515
516/*
517 * QueueDescPA must be 128 bytes aligned. It points to an array of
518 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
519 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
520 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
521 */
522#define VMXNET3_QUEUE_DESC_ALIGN 128
523
524
525struct Vmxnet3_MiscConf {
526 struct Vmxnet3_DriverInfo driverInfo;
527 __le64 uptFeatures;
528 __le64 ddPA; /* driver data PA */
529 __le64 queueDescPA; /* queue descriptor table PA */
530 __le32 ddLen; /* driver data len */
531 __le32 queueDescLen; /* queue desc. table len in bytes */
532 __le32 mtu;
533 __le16 maxNumRxSG;
534 u8 numTxQueues;
535 u8 numRxQueues;
536 __le32 reserved[4];
537};
538
539
540struct Vmxnet3_TxQueueConf {
541 __le64 txRingBasePA;
542 __le64 dataRingBasePA;
543 __le64 compRingBasePA;
544 __le64 ddPA; /* driver data */
545 __le64 reserved;
546 __le32 txRingSize; /* # of tx desc */
547 __le32 dataRingSize; /* # of data desc */
548 __le32 compRingSize; /* # of comp desc */
549 __le32 ddLen; /* size of driver data */
550 u8 intrIdx;
551 u8 _pad[7];
552};
553
554
555struct Vmxnet3_RxQueueConf {
556 __le64 rxRingBasePA[2];
557 __le64 compRingBasePA;
558 __le64 ddPA; /* driver data */
559 __le64 reserved;
560 __le32 rxRingSize[2]; /* # of rx desc */
561 __le32 compRingSize; /* # of rx comp desc */
562 __le32 ddLen; /* size of driver data */
563 u8 intrIdx;
564 u8 _pad[7];
565};
566
567
568enum vmxnet3_intr_mask_mode {
569 VMXNET3_IMM_AUTO = 0,
570 VMXNET3_IMM_ACTIVE = 1,
571 VMXNET3_IMM_LAZY = 2
572};
573
574enum vmxnet3_intr_type {
575 VMXNET3_IT_AUTO = 0,
576 VMXNET3_IT_INTX = 1,
577 VMXNET3_IT_MSI = 2,
578 VMXNET3_IT_MSIX = 3
579};
580
581#define VMXNET3_MAX_TX_QUEUES 8
582#define VMXNET3_MAX_RX_QUEUES 16
583/* addition 1 for events */
584#define VMXNET3_MAX_INTRS 25
585
586/* value of intrCtrl */
587#define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */
588
589
590struct Vmxnet3_IntrConf {
591 bool autoMask;
592 u8 numIntrs; /* # of interrupts */
593 u8 eventIntrIdx;
594 u8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for
595 * each intr */
596 __le32 intrCtrl;
597 __le32 reserved[2];
598};
599
600/* one bit per VLAN ID, the size is in the units of u32 */
601#define VMXNET3_VFT_SIZE (4096/(sizeof(uint32_t)*8))
602
603
604struct Vmxnet3_QueueStatus {
605 bool stopped;
606 u8 _pad[3];
607 __le32 error;
608};
609
610
611struct Vmxnet3_TxQueueCtrl {
612 __le32 txNumDeferred;
613 __le32 txThreshold;
614 __le64 reserved;
615};
616
617
618struct Vmxnet3_RxQueueCtrl {
619 bool updateRxProd;
620 u8 _pad[7];
621 __le64 reserved;
622};
623
624enum {
625 VMXNET3_RXM_UCAST = 0x01, /* unicast only */
626 VMXNET3_RXM_MCAST = 0x02, /* multicast passing the filters */
627 VMXNET3_RXM_BCAST = 0x04, /* broadcast only */
628 VMXNET3_RXM_ALL_MULTI = 0x08, /* all multicast */
629 VMXNET3_RXM_PROMISC = 0x10 /* promiscuous */
630};
631
632struct Vmxnet3_RxFilterConf {
633 __le32 rxMode; /* VMXNET3_RXM_xxx */
634 __le16 mfTableLen; /* size of the multicast filter table */
635 __le16 _pad1;
636 __le64 mfTablePA; /* PA of the multicast filters table */
637 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
638};
639
640
641#define VMXNET3_PM_MAX_FILTERS 6
642#define VMXNET3_PM_MAX_PATTERN_SIZE 128
643#define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
644
645#define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01) /* wake up on magic pkts */
646#define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02) /* wake up on pkts matching
647 * filters */
648
649
650struct Vmxnet3_PM_PktFilter {
651 u8 maskSize;
652 u8 patternSize;
653 u8 mask[VMXNET3_PM_MAX_MASK_SIZE];
654 u8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
655 u8 pad[6];
656};
657
658
659struct Vmxnet3_PMConf {
660 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */
661 u8 numFilters;
662 u8 pad[5];
663 struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
664};
665
666
667struct Vmxnet3_VariableLenConfDesc {
668 __le32 confVer;
669 __le32 confLen;
670 __le64 confPA;
671};
672
673
674struct Vmxnet3_TxQueueDesc {
675 struct Vmxnet3_TxQueueCtrl ctrl;
676 struct Vmxnet3_TxQueueConf conf;
677
678 /* Driver read after a GET command */
679 struct Vmxnet3_QueueStatus status;
680 struct UPT1_TxStats stats;
681 u8 _pad[88]; /* 128 aligned */
682};
683
684
685struct Vmxnet3_RxQueueDesc {
686 struct Vmxnet3_RxQueueCtrl ctrl;
687 struct Vmxnet3_RxQueueConf conf;
688 /* Driver read after a GET commad */
689 struct Vmxnet3_QueueStatus status;
690 struct UPT1_RxStats stats;
691 u8 __pad[88]; /* 128 aligned */
692};
693
694
695struct Vmxnet3_DSDevRead {
696 /* read-only region for device, read by dev in response to a SET cmd */
697 struct Vmxnet3_MiscConf misc;
698 struct Vmxnet3_IntrConf intrConf;
699 struct Vmxnet3_RxFilterConf rxFilterConf;
700 struct Vmxnet3_VariableLenConfDesc rssConfDesc;
701 struct Vmxnet3_VariableLenConfDesc pmConfDesc;
702 struct Vmxnet3_VariableLenConfDesc pluginConfDesc;
703};
704
705/* All structures in DriverShared are padded to multiples of 8 bytes */
706struct Vmxnet3_DriverShared {
707 __le32 magic;
708 /* make devRead start at 64bit boundaries */
709 __le32 pad;
710 struct Vmxnet3_DSDevRead devRead;
711 __le32 ecr;
712 __le32 reserved[5];
713};
714
715
716#define VMXNET3_ECR_RQERR (1 << 0)
717#define VMXNET3_ECR_TQERR (1 << 1)
718#define VMXNET3_ECR_LINK (1 << 2)
719#define VMXNET3_ECR_DIC (1 << 3)
720#define VMXNET3_ECR_DEBUG (1 << 4)
721
722/* flip the gen bit of a ring */
723#define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
724
725/* only use this if moving the idx won't affect the gen bit */
726#define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
727 do {\
728 (idx)++;\
729 if (unlikely((idx) == (ring_size))) {\
730 (idx) = 0;\
731 } \
732 } while (0)
733
734#define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
735 (vfTable[vid >> 5] |= (1 << (vid & 31)))
736#define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
737 (vfTable[vid >> 5] &= ~(1 << (vid & 31)))
738
739#define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
740 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
741
742#define VMXNET3_MAX_MTU 9000
743#define VMXNET3_MIN_MTU 60
744
745#define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */
746#define VMXNET3_LINK_DOWN 0
747
748#undef u64
749#undef u32
750#undef u16
751#undef u8
752#undef __le16
753#undef __le32
754#undef __le64
786fd2b0
DF		 755#if defined(HOST_WORDS_BIGENDIAN)
756#undef __BIG_ENDIAN_BITFIELD
757#endif
758
759#endif
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