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VM load/save support for PPC devices
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1/*
2 * OMAP clocks.
3 *
827df9f3 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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5 *
6 * Clocks data comes in part from arch/arm/mach-omap1/clock.h in Linux.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
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23#include "hw.h"
24#include "omap.h"
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25
26struct clk {
27 const char *name;
28 const char *alias;
29 struct clk *parent;
30 struct clk *child1;
31 struct clk *sibling;
32#define ALWAYS_ENABLED (1 << 0)
33#define CLOCK_IN_OMAP310 (1 << 10)
34#define CLOCK_IN_OMAP730 (1 << 11)
35#define CLOCK_IN_OMAP1510 (1 << 12)
36#define CLOCK_IN_OMAP16XX (1 << 13)
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37#define CLOCK_IN_OMAP242X (1 << 14)
38#define CLOCK_IN_OMAP243X (1 << 15)
39#define CLOCK_IN_OMAP343X (1 << 16)
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40 uint32_t flags;
41 int id;
42
43 int running; /* Is currently ticking */
44 int enabled; /* Is enabled, regardless of its input clk */
45 unsigned long rate; /* Current rate (if .running) */
46 unsigned int divisor; /* Rate relative to input (if .enabled) */
47 unsigned int multiplier; /* Rate relative to input (if .enabled) */
48 qemu_irq users[16]; /* Who to notify on change */
49 int usecount; /* Automatically idle when unused */
50};
51
52static struct clk xtal_osc12m = {
53 .name = "xtal_osc_12m",
54 .rate = 12000000,
55 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
56};
57
58static struct clk xtal_osc32k = {
59 .name = "xtal_osc_32k",
60 .rate = 32768,
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61 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
62 CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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63};
64
65static struct clk ck_ref = {
66 .name = "ck_ref",
67 .alias = "clkin",
68 .parent = &xtal_osc12m,
69 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
70 ALWAYS_ENABLED,
71};
72
73/* If a dpll is disabled it becomes a bypass, child clocks don't stop */
74static struct clk dpll1 = {
75 .name = "dpll1",
76 .parent = &ck_ref,
77 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
78 ALWAYS_ENABLED,
79};
80
81static struct clk dpll2 = {
82 .name = "dpll2",
83 .parent = &ck_ref,
84 .flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
85};
86
87static struct clk dpll3 = {
88 .name = "dpll3",
89 .parent = &ck_ref,
90 .flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
91};
92
93static struct clk dpll4 = {
94 .name = "dpll4",
95 .parent = &ck_ref,
96 .multiplier = 4,
97 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
98};
99
100static struct clk apll = {
101 .name = "apll",
102 .parent = &ck_ref,
103 .multiplier = 48,
104 .divisor = 12,
105 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
106};
107
108static struct clk ck_48m = {
109 .name = "ck_48m",
110 .parent = &dpll4, /* either dpll4 or apll */
111 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
112};
113
114static struct clk ck_dpll1out = {
115 .name = "ck_dpll1out",
116 .parent = &dpll1,
117 .flags = CLOCK_IN_OMAP16XX,
118};
119
120static struct clk sossi_ck = {
121 .name = "ck_sossi",
122 .parent = &ck_dpll1out,
123 .flags = CLOCK_IN_OMAP16XX,
124};
125
126static struct clk clkm1 = {
127 .name = "clkm1",
128 .alias = "ck_gen1",
129 .parent = &dpll1,
130 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
131 ALWAYS_ENABLED,
132};
133
134static struct clk clkm2 = {
135 .name = "clkm2",
136 .alias = "ck_gen2",
137 .parent = &dpll1,
138 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
139 ALWAYS_ENABLED,
140};
141
142static struct clk clkm3 = {
143 .name = "clkm3",
144 .alias = "ck_gen3",
145 .parent = &dpll1, /* either dpll1 or ck_ref */
146 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
147 ALWAYS_ENABLED,
148};
149
150static struct clk arm_ck = {
151 .name = "arm_ck",
152 .alias = "mpu_ck",
153 .parent = &clkm1,
154 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
155 ALWAYS_ENABLED,
156};
157
158static struct clk armper_ck = {
159 .name = "armper_ck",
160 .alias = "mpuper_ck",
161 .parent = &clkm1,
162 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
163};
164
165static struct clk arm_gpio_ck = {
166 .name = "arm_gpio_ck",
167 .alias = "mpu_gpio_ck",
168 .parent = &clkm1,
169 .divisor = 1,
170 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
171};
172
173static struct clk armxor_ck = {
174 .name = "armxor_ck",
175 .alias = "mpuxor_ck",
176 .parent = &ck_ref,
177 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
178};
179
180static struct clk armtim_ck = {
181 .name = "armtim_ck",
182 .alias = "mputim_ck",
183 .parent = &ck_ref, /* either CLKIN or DPLL1 */
184 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
185};
186
187static struct clk armwdt_ck = {
188 .name = "armwdt_ck",
189 .alias = "mpuwd_ck",
190 .parent = &clkm1,
191 .divisor = 14,
192 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
193 ALWAYS_ENABLED,
194};
195
196static struct clk arminth_ck16xx = {
197 .name = "arminth_ck",
198 .parent = &arm_ck,
199 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
200 /* Note: On 16xx the frequency can be divided by 2 by programming
201 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
202 *
203 * 1510 version is in TC clocks.
204 */
205};
206
207static struct clk dsp_ck = {
208 .name = "dsp_ck",
209 .parent = &clkm2,
210 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
211};
212
213static struct clk dspmmu_ck = {
214 .name = "dspmmu_ck",
215 .parent = &clkm2,
216 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
217 ALWAYS_ENABLED,
218};
219
220static struct clk dspper_ck = {
221 .name = "dspper_ck",
222 .parent = &clkm2,
223 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
224};
225
226static struct clk dspxor_ck = {
227 .name = "dspxor_ck",
228 .parent = &ck_ref,
229 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
230};
231
232static struct clk dsptim_ck = {
233 .name = "dsptim_ck",
234 .parent = &ck_ref,
235 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
236};
237
238static struct clk tc_ck = {
239 .name = "tc_ck",
240 .parent = &clkm3,
241 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
242 CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
243 ALWAYS_ENABLED,
244};
245
246static struct clk arminth_ck15xx = {
247 .name = "arminth_ck",
248 .parent = &tc_ck,
249 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
250 /* Note: On 1510 the frequency follows TC_CK
251 *
252 * 16xx version is in MPU clocks.
253 */
254};
255
256static struct clk tipb_ck = {
257 /* No-idle controlled by "tc_ck" */
258 .name = "tipb_ck",
259 .parent = &tc_ck,
260 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
261};
262
263static struct clk l3_ocpi_ck = {
264 /* No-idle controlled by "tc_ck" */
265 .name = "l3_ocpi_ck",
266 .parent = &tc_ck,
267 .flags = CLOCK_IN_OMAP16XX,
268};
269
270static struct clk tc1_ck = {
271 .name = "tc1_ck",
272 .parent = &tc_ck,
273 .flags = CLOCK_IN_OMAP16XX,
274};
275
276static struct clk tc2_ck = {
277 .name = "tc2_ck",
278 .parent = &tc_ck,
279 .flags = CLOCK_IN_OMAP16XX,
280};
281
282static struct clk dma_ck = {
283 /* No-idle controlled by "tc_ck" */
284 .name = "dma_ck",
285 .parent = &tc_ck,
286 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
287 ALWAYS_ENABLED,
288};
289
290static struct clk dma_lcdfree_ck = {
291 .name = "dma_lcdfree_ck",
292 .parent = &tc_ck,
293 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
294};
295
296static struct clk api_ck = {
297 .name = "api_ck",
298 .alias = "mpui_ck",
299 .parent = &tc_ck,
300 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
301};
302
303static struct clk lb_ck = {
304 .name = "lb_ck",
305 .parent = &tc_ck,
306 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
307};
308
309static struct clk lbfree_ck = {
310 .name = "lbfree_ck",
311 .parent = &tc_ck,
312 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
313};
314
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315static struct clk hsab_ck = {
316 .name = "hsab_ck",
317 .parent = &tc_ck,
318 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
319};
320
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321static struct clk rhea1_ck = {
322 .name = "rhea1_ck",
323 .parent = &tc_ck,
324 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
325};
326
327static struct clk rhea2_ck = {
328 .name = "rhea2_ck",
329 .parent = &tc_ck,
330 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
331};
332
333static struct clk lcd_ck_16xx = {
334 .name = "lcd_ck",
335 .parent = &clkm3,
336 .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730,
337};
338
339static struct clk lcd_ck_1510 = {
340 .name = "lcd_ck",
341 .parent = &clkm3,
342 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
343};
344
345static struct clk uart1_1510 = {
346 .name = "uart1_ck",
347 /* Direct from ULPD, no real parent */
348 .parent = &armper_ck, /* either armper_ck or dpll4 */
349 .rate = 12000000,
350 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
351};
352
353static struct clk uart1_16xx = {
354 .name = "uart1_ck",
355 /* Direct from ULPD, no real parent */
356 .parent = &armper_ck,
357 .rate = 48000000,
358 .flags = CLOCK_IN_OMAP16XX,
359};
360
361static struct clk uart2_ck = {
362 .name = "uart2_ck",
363 /* Direct from ULPD, no real parent */
364 .parent = &armper_ck, /* either armper_ck or dpll4 */
365 .rate = 12000000,
366 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
367 ALWAYS_ENABLED,
368};
369
370static struct clk uart3_1510 = {
371 .name = "uart3_ck",
372 /* Direct from ULPD, no real parent */
d8f699cb 373 .parent = &armper_ck, /* either armper_ck or dpll4 */
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374 .rate = 12000000,
375 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
376};
377
378static struct clk uart3_16xx = {
379 .name = "uart3_ck",
380 /* Direct from ULPD, no real parent */
381 .parent = &armper_ck,
382 .rate = 48000000,
383 .flags = CLOCK_IN_OMAP16XX,
384};
385
386static struct clk usb_clk0 = { /* 6 MHz output on W4_USB_CLK0 */
387 .name = "usb_clk0",
388 .alias = "usb.clko",
389 /* Direct from ULPD, no parent */
390 .rate = 6000000,
391 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
392};
393
394static struct clk usb_hhc_ck1510 = {
395 .name = "usb_hhc_ck",
396 /* Direct from ULPD, no parent */
397 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
398 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
399};
400
401static struct clk usb_hhc_ck16xx = {
402 .name = "usb_hhc_ck",
403 /* Direct from ULPD, no parent */
404 .rate = 48000000,
405 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
406 .flags = CLOCK_IN_OMAP16XX,
407};
408
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409static struct clk usb_w2fc_mclk = {
410 .name = "usb_w2fc_mclk",
411 .alias = "usb_w2fc_ck",
412 .parent = &ck_48m,
c3d2689d 413 .rate = 48000000,
d8f699cb 414 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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415};
416
417static struct clk mclk_1510 = {
418 .name = "mclk",
419 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
420 .rate = 12000000,
421 .flags = CLOCK_IN_OMAP1510,
422};
423
424static struct clk bclk_310 = {
425 .name = "bt_mclk_out", /* Alias midi_mclk_out? */
426 .parent = &armper_ck,
427 .flags = CLOCK_IN_OMAP310,
428};
429
430static struct clk mclk_310 = {
431 .name = "com_mclk_out",
432 .parent = &armper_ck,
433 .flags = CLOCK_IN_OMAP310,
434};
435
436static struct clk mclk_16xx = {
437 .name = "mclk",
438 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
439 .flags = CLOCK_IN_OMAP16XX,
440};
441
442static struct clk bclk_1510 = {
443 .name = "bclk",
444 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
445 .rate = 12000000,
446 .flags = CLOCK_IN_OMAP1510,
447};
448
449static struct clk bclk_16xx = {
450 .name = "bclk",
451 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
452 .flags = CLOCK_IN_OMAP16XX,
453};
454
455static struct clk mmc1_ck = {
456 .name = "mmc_ck",
457 .id = 1,
458 /* Functional clock is direct from ULPD, interface clock is ARMPER */
459 .parent = &armper_ck, /* either armper_ck or dpll4 */
460 .rate = 48000000,
461 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
462};
463
464static struct clk mmc2_ck = {
465 .name = "mmc_ck",
466 .id = 2,
467 /* Functional clock is direct from ULPD, interface clock is ARMPER */
468 .parent = &armper_ck,
469 .rate = 48000000,
470 .flags = CLOCK_IN_OMAP16XX,
471};
472
473static struct clk cam_mclk = {
474 .name = "cam.mclk",
475 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
476 .rate = 12000000,
477};
478
479static struct clk cam_exclk = {
480 .name = "cam.exclk",
481 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
482 /* Either 12M from cam.mclk or 48M from dpll4 */
483 .parent = &cam_mclk,
484};
485
486static struct clk cam_lclk = {
487 .name = "cam.lclk",
488 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
489};
490
491static struct clk i2c_fck = {
492 .name = "i2c_fck",
493 .id = 1,
494 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
495 ALWAYS_ENABLED,
496 .parent = &armxor_ck,
497};
498
499static struct clk i2c_ick = {
500 .name = "i2c_ick",
501 .id = 1,
502 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
503 .parent = &armper_ck,
504};
505
506static struct clk clk32k = {
507 .name = "clk32-kHz",
508 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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509 CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
510 .parent = &xtal_osc32k,
511};
512
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513static struct clk ref_clk = {
514 .name = "ref_clk",
515 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
516 .rate = 12000000, /* 12 MHz or 13 MHz or 19.2 MHz */
517 /*.parent = sys.xtalin */
518};
519
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520static struct clk apll_96m = {
521 .name = "apll_96m",
522 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
523 .rate = 96000000,
51fec3cc 524 /*.parent = ref_clk */
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525};
526
527static struct clk apll_54m = {
528 .name = "apll_54m",
529 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
530 .rate = 54000000,
51fec3cc 531 /*.parent = ref_clk */
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532};
533
534static struct clk sys_clk = {
535 .name = "sys_clk",
536 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
537 .rate = 32768,
538 /*.parent = sys.xtalin */
539};
540
541static struct clk sleep_clk = {
542 .name = "sleep_clk",
543 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
544 .rate = 32768,
545 /*.parent = sys.xtalin */
546};
547
548static struct clk dpll_ck = {
549 .name = "dpll",
550 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
51fec3cc 551 .parent = &ref_clk,
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552};
553
554static struct clk dpll_x2_ck = {
555 .name = "dpll_x2",
556 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
51fec3cc 557 .parent = &ref_clk,
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558};
559
560static struct clk wdt1_sys_clk = {
561 .name = "wdt1_sys_clk",
562 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
563 .rate = 32768,
564 /*.parent = sys.xtalin */
565};
566
567static struct clk func_96m_clk = {
568 .name = "func_96m_clk",
569 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
570 .divisor = 1,
571 .parent = &apll_96m,
572};
573
574static struct clk func_48m_clk = {
575 .name = "func_48m_clk",
576 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
577 .divisor = 2,
578 .parent = &apll_96m,
579};
580
581static struct clk func_12m_clk = {
582 .name = "func_12m_clk",
583 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
584 .divisor = 8,
585 .parent = &apll_96m,
586};
587
588static struct clk func_54m_clk = {
589 .name = "func_54m_clk",
590 .flags = CLOCK_IN_OMAP242X,
591 .divisor = 1,
592 .parent = &apll_54m,
593};
594
595static struct clk sys_clkout = {
596 .name = "clkout",
597 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
598 .parent = &sys_clk,
599};
600
601static struct clk sys_clkout2 = {
602 .name = "clkout2",
603 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
604 .parent = &sys_clk,
605};
606
607static struct clk core_clk = {
608 .name = "core_clk",
609 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
51fec3cc 610 .parent = &dpll_x2_ck, /* Switchable between dpll_ck and clk32k */
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611};
612
613static struct clk l3_clk = {
614 .name = "l3_clk",
615 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
616 .parent = &core_clk,
617};
618
619static struct clk core_l4_iclk = {
620 .name = "core_l4_iclk",
621 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
622 .parent = &l3_clk,
623};
624
625static struct clk wu_l4_iclk = {
626 .name = "wu_l4_iclk",
627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
628 .parent = &l3_clk,
629};
630
631static struct clk core_l3_iclk = {
632 .name = "core_l3_iclk",
633 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
634 .parent = &core_clk,
635};
636
637static struct clk core_l4_usb_clk = {
638 .name = "core_l4_usb_clk",
639 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
640 .parent = &l3_clk,
641};
642
643static struct clk wu_gpt1_clk = {
644 .name = "wu_gpt1_clk",
645 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
646 .parent = &sys_clk,
647};
648
649static struct clk wu_32k_clk = {
650 .name = "wu_32k_clk",
651 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
652 .parent = &sys_clk,
653};
654
655static struct clk uart1_fclk = {
656 .name = "uart1_fclk",
657 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
658 .parent = &func_48m_clk,
659};
660
661static struct clk uart1_iclk = {
662 .name = "uart1_iclk",
663 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
664 .parent = &core_l4_iclk,
665};
666
667static struct clk uart2_fclk = {
668 .name = "uart2_fclk",
669 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
670 .parent = &func_48m_clk,
671};
672
673static struct clk uart2_iclk = {
674 .name = "uart2_iclk",
675 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
676 .parent = &core_l4_iclk,
677};
678
679static struct clk uart3_fclk = {
680 .name = "uart3_fclk",
681 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
682 .parent = &func_48m_clk,
683};
684
685static struct clk uart3_iclk = {
686 .name = "uart3_iclk",
687 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
688 .parent = &core_l4_iclk,
689};
690
691static struct clk mpu_fclk = {
692 .name = "mpu_fclk",
693 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
694 .parent = &core_clk,
695};
696
697static struct clk mpu_iclk = {
698 .name = "mpu_iclk",
699 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
700 .parent = &core_clk,
701};
702
703static struct clk int_m_fclk = {
704 .name = "int_m_fclk",
705 .alias = "mpu_intc_fclk",
706 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
707 .parent = &core_clk,
708};
709
710static struct clk int_m_iclk = {
711 .name = "int_m_iclk",
712 .alias = "mpu_intc_iclk",
713 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
714 .parent = &core_clk,
715};
716
717static struct clk core_gpt2_clk = {
718 .name = "core_gpt2_clk",
719 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
720 .parent = &sys_clk,
721};
722
723static struct clk core_gpt3_clk = {
724 .name = "core_gpt3_clk",
725 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
726 .parent = &sys_clk,
727};
728
729static struct clk core_gpt4_clk = {
730 .name = "core_gpt4_clk",
731 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
732 .parent = &sys_clk,
733};
734
735static struct clk core_gpt5_clk = {
736 .name = "core_gpt5_clk",
737 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
738 .parent = &sys_clk,
739};
740
741static struct clk core_gpt6_clk = {
742 .name = "core_gpt6_clk",
743 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
744 .parent = &sys_clk,
745};
746
747static struct clk core_gpt7_clk = {
748 .name = "core_gpt7_clk",
749 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
750 .parent = &sys_clk,
751};
752
753static struct clk core_gpt8_clk = {
754 .name = "core_gpt8_clk",
755 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
756 .parent = &sys_clk,
757};
758
759static struct clk core_gpt9_clk = {
760 .name = "core_gpt9_clk",
761 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
762 .parent = &sys_clk,
763};
764
765static struct clk core_gpt10_clk = {
766 .name = "core_gpt10_clk",
767 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
768 .parent = &sys_clk,
769};
770
771static struct clk core_gpt11_clk = {
772 .name = "core_gpt11_clk",
773 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
774 .parent = &sys_clk,
775};
776
777static struct clk core_gpt12_clk = {
778 .name = "core_gpt12_clk",
779 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
780 .parent = &sys_clk,
781};
782
783static struct clk mcbsp1_clk = {
784 .name = "mcbsp1_cg",
785 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
786 .divisor = 2,
787 .parent = &func_96m_clk,
788};
789
790static struct clk mcbsp2_clk = {
791 .name = "mcbsp2_cg",
792 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
793 .divisor = 2,
794 .parent = &func_96m_clk,
795};
796
797static struct clk emul_clk = {
798 .name = "emul_ck",
799 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
800 .parent = &func_54m_clk,
801};
802
803static struct clk sdma_fclk = {
804 .name = "sdma_fclk",
805 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
806 .parent = &l3_clk,
807};
808
809static struct clk sdma_iclk = {
810 .name = "sdma_iclk",
811 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
812 .parent = &core_l3_iclk, /* core_l4_iclk for the configuration port */
813};
814
815static struct clk i2c1_fclk = {
816 .name = "i2c1.fclk",
817 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
818 .parent = &func_12m_clk,
819 .divisor = 1,
820};
821
822static struct clk i2c1_iclk = {
823 .name = "i2c1.iclk",
824 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
825 .parent = &core_l4_iclk,
826};
827
828static struct clk i2c2_fclk = {
829 .name = "i2c2.fclk",
830 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
831 .parent = &func_12m_clk,
832 .divisor = 1,
833};
834
835static struct clk i2c2_iclk = {
836 .name = "i2c2.iclk",
837 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
838 .parent = &core_l4_iclk,
839};
840
841static struct clk gpio_dbclk[4] = {
842 {
843 .name = "gpio1_dbclk",
844 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
845 .parent = &wu_32k_clk,
846 }, {
847 .name = "gpio2_dbclk",
848 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
849 .parent = &wu_32k_clk,
850 }, {
851 .name = "gpio3_dbclk",
852 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
853 .parent = &wu_32k_clk,
854 }, {
855 .name = "gpio4_dbclk",
856 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
857 .parent = &wu_32k_clk,
858 },
859};
860
861static struct clk gpio_iclk = {
862 .name = "gpio_iclk",
863 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
864 .parent = &wu_l4_iclk,
865};
866
867static struct clk mmc_fck = {
868 .name = "mmc_fclk",
869 .flags = CLOCK_IN_OMAP242X,
870 .parent = &func_96m_clk,
871};
872
873static struct clk mmc_ick = {
874 .name = "mmc_iclk",
875 .flags = CLOCK_IN_OMAP242X,
876 .parent = &core_l4_iclk,
877};
878
879static struct clk spi_fclk[3] = {
880 {
881 .name = "spi1_fclk",
882 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
883 .parent = &func_48m_clk,
884 }, {
885 .name = "spi2_fclk",
886 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
887 .parent = &func_48m_clk,
888 }, {
889 .name = "spi3_fclk",
890 .flags = CLOCK_IN_OMAP243X,
891 .parent = &func_48m_clk,
892 },
893};
894
895static struct clk dss_clk[2] = {
896 {
897 .name = "dss_clk1",
898 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
899 .parent = &core_clk,
900 }, {
901 .name = "dss_clk2",
902 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
903 .parent = &sys_clk,
904 },
905};
906
907static struct clk dss_54m_clk = {
908 .name = "dss_54m_clk",
909 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
910 .parent = &func_54m_clk,
911};
912
913static struct clk dss_l3_iclk = {
914 .name = "dss_l3_iclk",
915 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
916 .parent = &core_l3_iclk,
917};
918
919static struct clk dss_l4_iclk = {
920 .name = "dss_l4_iclk",
921 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
922 .parent = &core_l4_iclk,
923};
924
925static struct clk spi_iclk[3] = {
926 {
927 .name = "spi1_iclk",
928 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
929 .parent = &core_l4_iclk,
930 }, {
931 .name = "spi2_iclk",
932 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
933 .parent = &core_l4_iclk,
934 }, {
935 .name = "spi3_iclk",
936 .flags = CLOCK_IN_OMAP243X,
937 .parent = &core_l4_iclk,
938 },
939};
940
941static struct clk omapctrl_clk = {
942 .name = "omapctrl_iclk",
943 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
944 /* XXX Should be in WKUP domain */
945 .parent = &core_l4_iclk,
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946};
947
948static struct clk *onchip_clks[] = {
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949 /* OMAP 1 */
950
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951 /* non-ULPD clocks */
952 &xtal_osc12m,
953 &xtal_osc32k,
954 &ck_ref,
955 &dpll1,
956 &dpll2,
957 &dpll3,
958 &dpll4,
959 &apll,
960 &ck_48m,
961 /* CK_GEN1 clocks */
962 &clkm1,
963 &ck_dpll1out,
964 &sossi_ck,
965 &arm_ck,
966 &armper_ck,
967 &arm_gpio_ck,
968 &armxor_ck,
969 &armtim_ck,
970 &armwdt_ck,
971 &arminth_ck15xx, &arminth_ck16xx,
972 /* CK_GEN2 clocks */
973 &clkm2,
974 &dsp_ck,
975 &dspmmu_ck,
976 &dspper_ck,
977 &dspxor_ck,
978 &dsptim_ck,
979 /* CK_GEN3 clocks */
980 &clkm3,
981 &tc_ck,
982 &tipb_ck,
983 &l3_ocpi_ck,
984 &tc1_ck,
985 &tc2_ck,
986 &dma_ck,
987 &dma_lcdfree_ck,
988 &api_ck,
989 &lb_ck,
990 &lbfree_ck,
d8f699cb 991 &hsab_ck,
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992 &rhea1_ck,
993 &rhea2_ck,
994 &lcd_ck_16xx,
995 &lcd_ck_1510,
996 /* ULPD clocks */
997 &uart1_1510,
998 &uart1_16xx,
999 &uart2_ck,
1000 &uart3_1510,
1001 &uart3_16xx,
1002 &usb_clk0,
1003 &usb_hhc_ck1510, &usb_hhc_ck16xx,
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1004 &mclk_1510, &mclk_16xx, &mclk_310,
1005 &bclk_1510, &bclk_16xx, &bclk_310,
1006 &mmc1_ck,
1007 &mmc2_ck,
1008 &cam_mclk,
1009 &cam_exclk,
1010 &cam_lclk,
1011 &clk32k,
d8f699cb 1012 &usb_w2fc_mclk,
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1013 /* Virtual clocks */
1014 &i2c_fck,
1015 &i2c_ick,
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1016
1017 /* OMAP 2 */
1018
51fec3cc 1019 &ref_clk,
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1020 &apll_96m,
1021 &apll_54m,
1022 &sys_clk,
1023 &sleep_clk,
1024 &dpll_ck,
1025 &dpll_x2_ck,
1026 &wdt1_sys_clk,
1027 &func_96m_clk,
1028 &func_48m_clk,
1029 &func_12m_clk,
1030 &func_54m_clk,
1031 &sys_clkout,
1032 &sys_clkout2,
1033 &core_clk,
1034 &l3_clk,
1035 &core_l4_iclk,
1036 &wu_l4_iclk,
1037 &core_l3_iclk,
1038 &core_l4_usb_clk,
1039 &wu_gpt1_clk,
1040 &wu_32k_clk,
1041 &uart1_fclk,
1042 &uart1_iclk,
1043 &uart2_fclk,
1044 &uart2_iclk,
1045 &uart3_fclk,
1046 &uart3_iclk,
1047 &mpu_fclk,
1048 &mpu_iclk,
1049 &int_m_fclk,
1050 &int_m_iclk,
1051 &core_gpt2_clk,
1052 &core_gpt3_clk,
1053 &core_gpt4_clk,
1054 &core_gpt5_clk,
1055 &core_gpt6_clk,
1056 &core_gpt7_clk,
1057 &core_gpt8_clk,
1058 &core_gpt9_clk,
1059 &core_gpt10_clk,
1060 &core_gpt11_clk,
1061 &core_gpt12_clk,
1062 &mcbsp1_clk,
1063 &mcbsp2_clk,
1064 &emul_clk,
1065 &sdma_fclk,
1066 &sdma_iclk,
1067 &i2c1_fclk,
1068 &i2c1_iclk,
1069 &i2c2_fclk,
1070 &i2c2_iclk,
1071 &gpio_dbclk[0],
1072 &gpio_dbclk[1],
1073 &gpio_dbclk[2],
1074 &gpio_dbclk[3],
1075 &gpio_iclk,
1076 &mmc_fck,
1077 &mmc_ick,
1078 &spi_fclk[0],
1079 &spi_iclk[0],
1080 &spi_fclk[1],
1081 &spi_iclk[1],
1082 &spi_fclk[2],
1083 &spi_iclk[2],
1084 &dss_clk[0],
1085 &dss_clk[1],
1086 &dss_54m_clk,
1087 &dss_l3_iclk,
1088 &dss_l4_iclk,
1089 &omapctrl_clk,
1090
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1091 0
1092};
1093
1094void omap_clk_adduser(struct clk *clk, qemu_irq user)
1095{
1096 qemu_irq *i;
1097
1098 for (i = clk->users; *i; i ++);
1099 *i = user;
1100}
1101
1102/* If a clock is allowed to idle, it is disabled automatically when
1103 * all of clock domains using it are disabled. */
b1d8e52e 1104static int omap_clk_is_idle(struct clk *clk)
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1105{
1106 struct clk *chld;
1107
1108 if (!clk->enabled && (!clk->usecount || !(clk->flags && ALWAYS_ENABLED)))
1109 return 1;
1110 if (clk->usecount)
1111 return 0;
1112
1113 for (chld = clk->child1; chld; chld = chld->sibling)
1114 if (!omap_clk_is_idle(chld))
1115 return 0;
1116 return 1;
1117}
1118
1119struct clk *omap_findclk(struct omap_mpu_state_s *mpu, const char *name)
1120{
1121 struct clk *i;
1122
1123 for (i = mpu->clks; i->name; i ++)
1124 if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias, name)))
1125 return i;
1126 cpu_abort(mpu->env, "%s: %s not found\n", __FUNCTION__, name);
1127}
1128
1129void omap_clk_get(struct clk *clk)
1130{
1131 clk->usecount ++;
1132}
1133
1134void omap_clk_put(struct clk *clk)
1135{
1136 if (!(clk->usecount --))
1137 cpu_abort(cpu_single_env, "%s: %s is not in use\n",
1138 __FUNCTION__, clk->name);
1139}
1140
1141static void omap_clk_update(struct clk *clk)
1142{
1143 int parent, running;
1144 qemu_irq *user;
1145 struct clk *i;
1146
1147 if (clk->parent)
1148 parent = clk->parent->running;
1149 else
1150 parent = 1;
1151
1152 running = parent && (clk->enabled ||
1153 ((clk->flags & ALWAYS_ENABLED) && clk->usecount));
1154 if (clk->running != running) {
1155 clk->running = running;
1156 for (user = clk->users; *user; user ++)
1157 qemu_set_irq(*user, running);
1158 for (i = clk->child1; i; i = i->sibling)
1159 omap_clk_update(i);
1160 }
1161}
1162
1163static void omap_clk_rate_update_full(struct clk *clk, unsigned long int rate,
1164 unsigned long int div, unsigned long int mult)
1165{
1166 struct clk *i;
1167 qemu_irq *user;
1168
1169 clk->rate = muldiv64(rate, mult, div);
1170 if (clk->running)
1171 for (user = clk->users; *user; user ++)
1172 qemu_irq_raise(*user);
1173 for (i = clk->child1; i; i = i->sibling)
1174 omap_clk_rate_update_full(i, rate,
1175 div * i->divisor, mult * i->multiplier);
1176}
1177
1178static void omap_clk_rate_update(struct clk *clk)
1179{
1180 struct clk *i;
1181 unsigned long int div, mult = div = 1;
1182
1183 for (i = clk; i->parent; i = i->parent) {
1184 div *= i->divisor;
1185 mult *= i->multiplier;
1186 }
1187
1188 omap_clk_rate_update_full(clk, i->rate, div, mult);
1189}
1190
1191void omap_clk_reparent(struct clk *clk, struct clk *parent)
1192{
1193 struct clk **p;
1194
1195 if (clk->parent) {
1196 for (p = &clk->parent->child1; *p != clk; p = &(*p)->sibling);
1197 *p = clk->sibling;
1198 }
1199
1200 clk->parent = parent;
1201 if (parent) {
1202 clk->sibling = parent->child1;
1203 parent->child1 = clk;
1204 omap_clk_update(clk);
1205 omap_clk_rate_update(clk);
1206 } else
1207 clk->sibling = 0;
1208}
1209
1210void omap_clk_onoff(struct clk *clk, int on)
1211{
1212 clk->enabled = on;
1213 omap_clk_update(clk);
1214}
1215
1216void omap_clk_canidle(struct clk *clk, int can)
1217{
1218 if (can)
1219 omap_clk_put(clk);
1220 else
1221 omap_clk_get(clk);
1222}
1223
1224void omap_clk_setrate(struct clk *clk, int divide, int multiply)
1225{
1226 clk->divisor = divide;
1227 clk->multiplier = multiply;
1228 omap_clk_rate_update(clk);
1229}
1230
1231int64_t omap_clk_getrate(omap_clk clk)
1232{
1233 return clk->rate;
1234}
1235
1236void omap_clk_init(struct omap_mpu_state_s *mpu)
1237{
1238 struct clk **i, *j, *k;
1239 int count;
1240 int flag;
1241
1242 if (cpu_is_omap310(mpu))
1243 flag = CLOCK_IN_OMAP310;
1244 else if (cpu_is_omap1510(mpu))
1245 flag = CLOCK_IN_OMAP1510;
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1246 else if (cpu_is_omap2410(mpu) || cpu_is_omap2420(mpu))
1247 flag = CLOCK_IN_OMAP242X;
1248 else if (cpu_is_omap2430(mpu))
1249 flag = CLOCK_IN_OMAP243X;
1250 else if (cpu_is_omap3430(mpu))
1251 flag = CLOCK_IN_OMAP243X;
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1252 else
1253 return;
1254
1255 for (i = onchip_clks, count = 0; *i; i ++)
1256 if ((*i)->flags & flag)
1257 count ++;
1258 mpu->clks = (struct clk *) qemu_mallocz(sizeof(struct clk) * (count + 1));
1259 for (i = onchip_clks, j = mpu->clks; *i; i ++)
1260 if ((*i)->flags & flag) {
1261 memcpy(j, *i, sizeof(struct clk));
1262 for (k = mpu->clks; k < j; k ++)
1263 if (j->parent && !strcmp(j->parent->name, k->name)) {
1264 j->parent = k;
1265 j->sibling = k->child1;
1266 k->child1 = j;
1267 } else if (k->parent && !strcmp(k->parent->name, j->name)) {
1268 k->parent = j;
1269 k->sibling = j->child1;
1270 j->child1 = k;
1271 }
1272 j->divisor = j->divisor ?: 1;
1273 j->multiplier = j->multiplier ?: 1;
1274 j ++;
1275 }
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1276 for (j = mpu->clks; count --; j ++) {
1277 omap_clk_update(j);
1278 omap_clk_rate_update(j);
1279 }
c3d2689d 1280}