]>
Commit | Line | Data |
---|---|---|
ce6e1e9e JL |
1 | /* |
2 | * OpenRISC simulator for use as an IIS. | |
3 | * | |
4 | * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> | |
5 | * Feng Gao <gf91597@gmail.com> | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
ed2decc6 | 21 | #include "qemu/osdep.h" |
da34e65c | 22 | #include "qapi/error.h" |
4771d756 PB |
23 | #include "qemu-common.h" |
24 | #include "cpu.h" | |
83c9f4ca PB |
25 | #include "hw/hw.h" |
26 | #include "hw/boards.h" | |
ce6e1e9e | 27 | #include "elf.h" |
0d09e41a | 28 | #include "hw/char/serial.h" |
1422e32d | 29 | #include "net/net.h" |
83c9f4ca | 30 | #include "hw/loader.h" |
022c62cb | 31 | #include "exec/address-spaces.h" |
9c17d615 | 32 | #include "sysemu/sysemu.h" |
83c9f4ca | 33 | #include "hw/sysbus.h" |
9c17d615 | 34 | #include "sysemu/qtest.h" |
ce6e1e9e JL |
35 | |
36 | #define KERNEL_LOAD_ADDR 0x100 | |
37 | ||
13f1c773 SH |
38 | static struct openrisc_boot_info { |
39 | uint32_t bootstrap_pc; | |
40 | } boot_info; | |
41 | ||
ce6e1e9e JL |
42 | static void main_cpu_reset(void *opaque) |
43 | { | |
44 | OpenRISCCPU *cpu = opaque; | |
13f1c773 | 45 | CPUState *cs = CPU(cpu); |
ce6e1e9e JL |
46 | |
47 | cpu_reset(CPU(cpu)); | |
13f1c773 SH |
48 | |
49 | cpu_set_pc(cs, boot_info.bootstrap_pc); | |
ce6e1e9e JL |
50 | } |
51 | ||
13f1c773 SH |
52 | static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors, |
53 | int num_cpus, qemu_irq **cpu_irqs, | |
54 | int irq_pin, NICInfo *nd) | |
ce6e1e9e JL |
55 | { |
56 | DeviceState *dev; | |
57 | SysBusDevice *s; | |
13f1c773 | 58 | int i; |
ce6e1e9e JL |
59 | |
60 | dev = qdev_create(NULL, "open_eth"); | |
61 | qdev_set_nic_properties(dev, nd); | |
62 | qdev_init_nofail(dev); | |
63 | ||
1356b98d | 64 | s = SYS_BUS_DEVICE(dev); |
13f1c773 SH |
65 | for (i = 0; i < num_cpus; i++) { |
66 | sysbus_connect_irq(s, 0, cpu_irqs[i][irq_pin]); | |
67 | } | |
68 | sysbus_mmio_map(s, 0, base); | |
69 | sysbus_mmio_map(s, 1, descriptors); | |
70 | } | |
71 | ||
72 | static void openrisc_sim_ompic_init(hwaddr base, int num_cpus, | |
73 | qemu_irq **cpu_irqs, int irq_pin) | |
74 | { | |
75 | DeviceState *dev; | |
76 | SysBusDevice *s; | |
77 | int i; | |
78 | ||
79 | dev = qdev_create(NULL, "or1k-ompic"); | |
80 | qdev_prop_set_uint32(dev, "num-cpus", num_cpus); | |
81 | qdev_init_nofail(dev); | |
82 | ||
83 | s = SYS_BUS_DEVICE(dev); | |
84 | for (i = 0; i < num_cpus; i++) { | |
85 | sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]); | |
86 | } | |
87 | sysbus_mmio_map(s, 0, base); | |
ce6e1e9e JL |
88 | } |
89 | ||
13f1c773 SH |
90 | static void openrisc_load_kernel(ram_addr_t ram_size, |
91 | const char *kernel_filename) | |
ce6e1e9e JL |
92 | { |
93 | long kernel_size; | |
94 | uint64_t elf_entry; | |
a8170e5e | 95 | hwaddr entry; |
ce6e1e9e JL |
96 | |
97 | if (kernel_filename && !qtest_enabled()) { | |
98 | kernel_size = load_elf(kernel_filename, NULL, NULL, | |
7ef295ea PC |
99 | &elf_entry, NULL, NULL, 1, EM_OPENRISC, |
100 | 1, 0); | |
ce6e1e9e JL |
101 | entry = elf_entry; |
102 | if (kernel_size < 0) { | |
103 | kernel_size = load_uimage(kernel_filename, | |
25bda50a | 104 | &entry, NULL, NULL, NULL, NULL); |
ce6e1e9e JL |
105 | } |
106 | if (kernel_size < 0) { | |
107 | kernel_size = load_image_targphys(kernel_filename, | |
108 | KERNEL_LOAD_ADDR, | |
109 | ram_size - KERNEL_LOAD_ADDR); | |
13f1c773 SH |
110 | } |
111 | ||
112 | if (entry <= 0) { | |
ce6e1e9e JL |
113 | entry = KERNEL_LOAD_ADDR; |
114 | } | |
115 | ||
116 | if (kernel_size < 0) { | |
4284c051 | 117 | fprintf(stderr, "QEMU: couldn't load the kernel '%s'\n", |
ce6e1e9e JL |
118 | kernel_filename); |
119 | exit(1); | |
120 | } | |
13f1c773 | 121 | boot_info.bootstrap_pc = entry; |
ce6e1e9e | 122 | } |
ce6e1e9e JL |
123 | } |
124 | ||
3ef96221 | 125 | static void openrisc_sim_init(MachineState *machine) |
ce6e1e9e | 126 | { |
3ef96221 MA |
127 | ram_addr_t ram_size = machine->ram_size; |
128 | const char *cpu_model = machine->cpu_model; | |
129 | const char *kernel_filename = machine->kernel_filename; | |
68f12828 | 130 | OpenRISCCPU *cpu = NULL; |
ce6e1e9e | 131 | MemoryRegion *ram; |
13f1c773 SH |
132 | qemu_irq *cpu_irqs[2]; |
133 | qemu_irq serial_irq; | |
ce6e1e9e JL |
134 | int n; |
135 | ||
136 | if (!cpu_model) { | |
137 | cpu_model = "or1200"; | |
138 | } | |
139 | ||
140 | for (n = 0; n < smp_cpus; n++) { | |
f6f8b260 | 141 | cpu = OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model)); |
13f1c773 SH |
142 | if (cpu == NULL) { |
143 | fprintf(stderr, "Unable to find CPU definition!\n"); | |
144 | exit(1); | |
145 | } | |
146 | cpu_openrisc_pic_init(cpu); | |
147 | cpu_irqs[n] = (qemu_irq *) cpu->env.irq; | |
148 | ||
149 | cpu_openrisc_clock_init(cpu); | |
150 | ||
ce6e1e9e | 151 | qemu_register_reset(main_cpu_reset, cpu); |
ce6e1e9e JL |
152 | } |
153 | ||
154 | ram = g_malloc(sizeof(*ram)); | |
98a99ce0 | 155 | memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal); |
ce6e1e9e JL |
156 | memory_region_add_subregion(get_system_memory(), 0, ram); |
157 | ||
13f1c773 SH |
158 | if (nd_table[0].used) { |
159 | openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus, | |
160 | cpu_irqs, 4, nd_table); | |
161 | } | |
ce6e1e9e | 162 | |
13f1c773 SH |
163 | if (smp_cpus > 1) { |
164 | openrisc_sim_ompic_init(0x98000000, smp_cpus, cpu_irqs, 1); | |
ce6e1e9e | 165 | |
13f1c773 SH |
166 | serial_irq = qemu_irq_split(cpu_irqs[0][2], cpu_irqs[1][2]); |
167 | } else { | |
168 | serial_irq = cpu_irqs[0][2]; | |
ce6e1e9e JL |
169 | } |
170 | ||
13f1c773 SH |
171 | serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq, |
172 | 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); | |
173 | ||
174 | openrisc_load_kernel(ram_size, kernel_filename); | |
ce6e1e9e JL |
175 | } |
176 | ||
e264d29d | 177 | static void openrisc_sim_machine_init(MachineClass *mc) |
ce6e1e9e | 178 | { |
4a09d0bb | 179 | mc->desc = "or1k simulation"; |
e264d29d | 180 | mc->init = openrisc_sim_init; |
13f1c773 | 181 | mc->max_cpus = 2; |
e264d29d | 182 | mc->is_default = 1; |
ce6e1e9e JL |
183 | } |
184 | ||
4a09d0bb | 185 | DEFINE_MACHINE("or1k-sim", openrisc_sim_machine_init) |