[qemu.git] / hw / parallel.c

/*
 * QEMU Parallel PORT emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 * Copyright (c) 2007 Marko Kohtala
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "qemu-char.h"
#include "isa.h"
#include "pc.h"

//#define DEBUG_PARALLEL

#ifdef DEBUG_PARALLEL
#define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
#else
#define pdebug(fmt, ...) ((void)0)
#endif

#define PARA_REG_DATA 0
#define PARA_REG_STS 1
#define PARA_REG_CTR 2
#define PARA_REG_EPP_ADDR 3
#define PARA_REG_EPP_DATA 4

/*
 * These are the definitions for the Printer Status Register
 */
#define PARA_STS_BUSY	0x80	/* Busy complement */
#define PARA_STS_ACK	0x40	/* Acknowledge */
#define PARA_STS_PAPER	0x20	/* Out of paper */
#define PARA_STS_ONLINE	0x10	/* Online */
#define PARA_STS_ERROR	0x08	/* Error complement */
#define PARA_STS_TMOUT	0x01	/* EPP timeout */

/*
 * These are the definitions for the Printer Control Register
 */
#define PARA_CTR_DIR	0x20	/* Direction (1=read, 0=write) */
#define PARA_CTR_INTEN	0x10	/* IRQ Enable */
#define PARA_CTR_SELECT	0x08	/* Select In complement */
#define PARA_CTR_INIT	0x04	/* Initialize Printer complement */
#define PARA_CTR_AUTOLF	0x02	/* Auto linefeed complement */
#define PARA_CTR_STROBE	0x01	/* Strobe complement */

#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)

struct ParallelState {
    uint8_t dataw;
    uint8_t datar;
    uint8_t status;
    uint8_t control;
    qemu_irq irq;
    int irq_pending;
    CharDriverState *chr;
    int hw_driver;
    int epp_timeout;
    uint32_t last_read_offset; /* For debugging */
    /* Memory-mapped interface */
    int it_shift;
};

typedef struct ISAParallelState {
    ISADevice dev;
    uint32_t index;
    uint32_t iobase;
    uint32_t isairq;
    ParallelState state;
} ISAParallelState;

static void parallel_update_irq(ParallelState *s)
{
    if (s->irq_pending)
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static void
parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;

    pdebug("write addr=0x%02x val=0x%02x\n", addr, val);

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        s->dataw = val;
        parallel_update_irq(s);
        break;
    case PARA_REG_CTR:
        val |= 0xc0;
        if ((val & PARA_CTR_INIT) == 0 ) {
            s->status = PARA_STS_BUSY;
            s->status |= PARA_STS_ACK;
            s->status |= PARA_STS_ONLINE;
            s->status |= PARA_STS_ERROR;
        }
        else if (val & PARA_CTR_SELECT) {
            if (val & PARA_CTR_STROBE) {
                s->status &= ~PARA_STS_BUSY;
                if ((s->control & PARA_CTR_STROBE) == 0)
                    qemu_chr_write(s->chr, &s->dataw, 1);
            } else {
                if (s->control & PARA_CTR_INTEN) {
                    s->irq_pending = 1;
                }
            }
        }
        parallel_update_irq(s);
        s->control = val;
        break;
    }
}

static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint8_t parm = val;
    int dir;

    /* Sometimes programs do several writes for timing purposes on old
       HW. Take care not to waste time on writes that do nothing. */

    s->last_read_offset = ~0U;

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        if (s->dataw == val)
            return;
        pdebug("wd%02x\n", val);
        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
        s->dataw = val;
        break;
    case PARA_REG_STS:
        pdebug("ws%02x\n", val);
        if (val & PARA_STS_TMOUT)
            s->epp_timeout = 0;
        break;
    case PARA_REG_CTR:
        val |= 0xc0;
        if (s->control == val)
            return;
        pdebug("wc%02x\n", val);

        if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
            if (val & PARA_CTR_DIR) {
                dir = 1;
            } else {
                dir = 0;
            }
            qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
            parm &= ~PARA_CTR_DIR;
        }

        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
        s->control = val;
        break;
    case PARA_REG_EPP_ADDR:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
            /* Controls not correct for EPP address cycle, so do nothing */
            pdebug("wa%02x s\n", val);
        else {
            struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("wa%02x t\n", val);
            }
            else
                pdebug("wa%02x\n", val);
        }
        break;
    case PARA_REG_EPP_DATA:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
            /* Controls not correct for EPP data cycle, so do nothing */
            pdebug("we%02x s\n", val);
        else {
            struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("we%02x t\n", val);
            }
            else
                pdebug("we%02x\n", val);
        }
        break;
    }
}

static void
parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint16_t eppdata = cpu_to_le16(val);
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("we%04x s\n", val);
        return;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
    if (err) {
        s->epp_timeout = 1;
        pdebug("we%04x t\n", val);
    }
    else
        pdebug("we%04x\n", val);
}

static void
parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint32_t eppdata = cpu_to_le32(val);
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("we%08x s\n", val);
        return;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
    if (err) {
        s->epp_timeout = 1;
        pdebug("we%08x t\n", val);
    }
    else
        pdebug("we%08x\n", val);
}

static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret = 0xff;

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        if (s->control & PARA_CTR_DIR)
            ret = s->datar;
        else
            ret = s->dataw;
        break;
    case PARA_REG_STS:
        ret = s->status;
        s->irq_pending = 0;
        if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
            /* XXX Fixme: wait 5 microseconds */
            if (s->status & PARA_STS_ACK)
                s->status &= ~PARA_STS_ACK;
            else {
                /* XXX Fixme: wait 5 microseconds */
                s->status |= PARA_STS_ACK;
                s->status |= PARA_STS_BUSY;
            }
        }
        parallel_update_irq(s);
        break;
    case PARA_REG_CTR:
        ret = s->control;
        break;
    }
    pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
    return ret;
}

static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint8_t ret = 0xff;
    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
        if (s->last_read_offset != addr || s->datar != ret)
            pdebug("rd%02x\n", ret);
        s->datar = ret;
        break;
    case PARA_REG_STS:
        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
        ret &= ~PARA_STS_TMOUT;
        if (s->epp_timeout)
            ret |= PARA_STS_TMOUT;
        if (s->last_read_offset != addr || s->status != ret)
            pdebug("rs%02x\n", ret);
        s->status = ret;
        break;
    case PARA_REG_CTR:
        /* s->control has some bits fixed to 1. It is zero only when
           it has not been yet written to.  */
        if (s->control == 0) {
            qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
            if (s->last_read_offset != addr)
                pdebug("rc%02x\n", ret);
            s->control = ret;
        }
        else {
            ret = s->control;
            if (s->last_read_offset != addr)
                pdebug("rc%02x\n", ret);
        }
        break;
    case PARA_REG_EPP_ADDR:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
            /* Controls not correct for EPP addr cycle, so do nothing */
            pdebug("ra%02x s\n", ret);
        else {
            struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("ra%02x t\n", ret);
            }
            else
                pdebug("ra%02x\n", ret);
        }
        break;
    case PARA_REG_EPP_DATA:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
            /* Controls not correct for EPP data cycle, so do nothing */
            pdebug("re%02x s\n", ret);
        else {
            struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("re%02x t\n", ret);
            }
            else
                pdebug("re%02x\n", ret);
        }
        break;
    }
    s->last_read_offset = addr;
    return ret;
}

static uint32_t
parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret;
    uint16_t eppdata = ~0;
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("re%04x s\n", eppdata);
        return eppdata;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
    ret = le16_to_cpu(eppdata);

    if (err) {
        s->epp_timeout = 1;
        pdebug("re%04x t\n", ret);
    }
    else
        pdebug("re%04x\n", ret);
    return ret;
}

static uint32_t
parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret;
    uint32_t eppdata = ~0U;
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("re%08x s\n", eppdata);
        return eppdata;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
    ret = le32_to_cpu(eppdata);

    if (err) {
        s->epp_timeout = 1;
        pdebug("re%08x t\n", ret);
    }
    else
        pdebug("re%08x\n", ret);
    return ret;
}

static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
{
    pdebug("wecp%d=%02x\n", addr & 7, val);
}

static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
{
    uint8_t ret = 0xff;

    pdebug("recp%d:%02x\n", addr & 7, ret);
    return ret;
}

static void parallel_reset(void *opaque)
{
    ParallelState *s = opaque;

    s->datar = ~0;
    s->dataw = ~0;
    s->status = PARA_STS_BUSY;
    s->status |= PARA_STS_ACK;
    s->status |= PARA_STS_ONLINE;
    s->status |= PARA_STS_ERROR;
    s->status |= PARA_STS_TMOUT;
    s->control = PARA_CTR_SELECT;
    s->control |= PARA_CTR_INIT;
    s->control |= 0xc0;
    s->irq_pending = 0;
    s->hw_driver = 0;
    s->epp_timeout = 0;
    s->last_read_offset = ~0U;
}

static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };

static int parallel_isa_initfn(ISADevice *dev)
{
    static int index;
    ISAParallelState *isa = DO_UPCAST(ISAParallelState, dev, dev);
    ParallelState *s = &isa->state;
    int base;
    uint8_t dummy;

    if (!s->chr) {
        fprintf(stderr, "Can't create parallel device, empty char device\n");
        exit(1);
    }

    if (isa->index == -1)
        isa->index = index;
    if (isa->index >= MAX_PARALLEL_PORTS)
        return -1;
    if (isa->iobase == -1)
        isa->iobase = isa_parallel_io[isa->index];
    index++;

    base = isa->iobase;
    isa_init_irq(dev, &s->irq, isa->isairq);
    qemu_register_reset(parallel_reset, s);

    if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
        s->hw_driver = 1;
        s->status = dummy;
    }

    if (s->hw_driver) {
        register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
        register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
        register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
        register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
        register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
        register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
        register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
        register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
    }
    else {
        register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
        register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
    }
    return 0;
}

ParallelState *parallel_init(int index, CharDriverState *chr)
{
    ISADevice *dev;

    dev = isa_create("isa-parallel");
    qdev_prop_set_uint32(&dev->qdev, "index", index);
    qdev_prop_set_chr(&dev->qdev, "chardev", chr);
    if (qdev_init(&dev->qdev) < 0)
        return NULL;
    return &DO_UPCAST(ISAParallelState, dev, dev)->state;
}

/* Memory mapped interface */
static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
}

static void parallel_mm_writeb (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
}

static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
}

static void parallel_mm_writew (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
}

static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, addr >> s->it_shift);
}

static void parallel_mm_writel (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, addr >> s->it_shift, value);
}

static CPUReadMemoryFunc * const parallel_mm_read_sw[] = {
    &parallel_mm_readb,
    &parallel_mm_readw,
    &parallel_mm_readl,
};

static CPUWriteMemoryFunc * const parallel_mm_write_sw[] = {
    &parallel_mm_writeb,
    &parallel_mm_writew,
    &parallel_mm_writel,
};

/* If fd is zero, it means that the parallel device uses the console */
ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr)
{
    ParallelState *s;
    int io_sw;

    s = qemu_mallocz(sizeof(ParallelState));
    s->irq = irq;
    s->chr = chr;
    s->it_shift = it_shift;
    qemu_register_reset(parallel_reset, s);

    io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, s);
    cpu_register_physical_memory(base, 8 << it_shift, io_sw);
    return s;
}

static ISADeviceInfo parallel_isa_info = {
    .qdev.name  = "isa-parallel",
    .qdev.size  = sizeof(ISAParallelState),
    .init       = parallel_isa_initfn,
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("index", ISAParallelState, index,   -1),
        DEFINE_PROP_HEX32("iobase", ISAParallelState, iobase,  -1),
        DEFINE_PROP_UINT32("irq",   ISAParallelState, isairq,  7),
        DEFINE_PROP_CHR("chardev",  ISAParallelState, state.chr),
        DEFINE_PROP_END_OF_LIST(),
    },
};

static void parallel_register_devices(void)
{
    isa_qdev_register(&parallel_isa_info);
}

device_init(parallel_register_devices)
Commit	Line	Data
6508fe59 FB	1	/*
6508fe59 FB	2	* QEMU Parallel PORT emulation
5fafdf24	3	*
e57a8c0e	4	* Copyright (c) 2003-2005 Fabrice Bellard
5867c88a	5	* Copyright (c) 2007 Marko Kohtala
5fafdf24	6	*
6508fe59 FB	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
87ecb68b PB	25	#include "hw.h"
	26	#include "qemu-char.h"
	27	#include "isa.h"
	28	#include "pc.h"
6508fe59 FB	29
	30	//#define DEBUG_PARALLEL
	31
5867c88a	32	#ifdef DEBUG_PARALLEL
001faf32	33	#define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
5867c88a	34	#else
001faf32	35	#define pdebug(fmt, ...) ((void)0)
5867c88a TS	36	#endif
	37
	38	#define PARA_REG_DATA 0
	39	#define PARA_REG_STS 1
	40	#define PARA_REG_CTR 2
	41	#define PARA_REG_EPP_ADDR 3
	42	#define PARA_REG_EPP_DATA 4
	43
6508fe59 FB	44	/*
	45	* These are the definitions for the Printer Status Register
	46	*/
	47	#define PARA_STS_BUSY 0x80 /* Busy complement */
	48	#define PARA_STS_ACK 0x40 /* Acknowledge */
	49	#define PARA_STS_PAPER 0x20 /* Out of paper */
	50	#define PARA_STS_ONLINE 0x10 /* Online */
	51	#define PARA_STS_ERROR 0x08 /* Error complement */
5867c88a	52	#define PARA_STS_TMOUT 0x01 /* EPP timeout */
6508fe59 FB	53
	54	/*
	55	* These are the definitions for the Printer Control Register
	56	*/
5867c88a	57	#define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */
6508fe59 FB	58	#define PARA_CTR_INTEN 0x10 /* IRQ Enable */
	59	#define PARA_CTR_SELECT 0x08 /* Select In complement */
	60	#define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
	61	#define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
	62	#define PARA_CTR_STROBE 0x01 /* Strobe complement */
	63
5867c88a TS	64	#define PARA_CTR_SIGNAL (PARA_CTR_SELECT\|PARA_CTR_INIT\|PARA_CTR_AUTOLF\|PARA_CTR_STROBE)
5867c88a TS	65
6508fe59	66	struct ParallelState {
5867c88a TS	67	uint8_t dataw;
	68	uint8_t datar;
	69	uint8_t status;
6508fe59	70	uint8_t control;
d537cf6c	71	qemu_irq irq;
6508fe59 FB	72	int irq_pending;
6508fe59 FB	73	CharDriverState *chr;
e57a8c0e	74	int hw_driver;
5867c88a TS	75	int epp_timeout;
5867c88a TS	76	uint32_t last_read_offset; /* For debugging */
d60532ca	77	/* Memory-mapped interface */
d60532ca	78	int it_shift;
6508fe59 FB	79	};
6508fe59 FB	80
021f0674 GH	81	typedef struct ISAParallelState {
021f0674 GH	82	ISADevice dev;
e8ee28fb	83	uint32_t index;
021f0674 GH	84	uint32_t iobase;
	85	uint32_t isairq;
	86	ParallelState state;
	87	} ISAParallelState;
	88
6508fe59 FB	89	static void parallel_update_irq(ParallelState *s)
	90	{
	91	if (s->irq_pending)
d537cf6c	92	qemu_irq_raise(s->irq);
6508fe59	93	else
d537cf6c	94	qemu_irq_lower(s->irq);
6508fe59 FB	95	}
6508fe59 FB	96
5867c88a TS	97	static void
5867c88a TS	98	parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
6508fe59 FB	99	{
6508fe59 FB	100	ParallelState *s = opaque;
3b46e624	101
5867c88a TS	102	pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
	103
	104	addr &= 7;
	105	switch(addr) {
	106	case PARA_REG_DATA:
0fa7f157 TS	107	s->dataw = val;
0fa7f157 TS	108	parallel_update_irq(s);
5867c88a TS	109	break;
5867c88a TS	110	case PARA_REG_CTR:
52ccc5e0	111	val \|= 0xc0;
0fa7f157 TS	112	if ((val & PARA_CTR_INIT) == 0 ) {
	113	s->status = PARA_STS_BUSY;
	114	s->status \|= PARA_STS_ACK;
	115	s->status \|= PARA_STS_ONLINE;
	116	s->status \|= PARA_STS_ERROR;
	117	}
	118	else if (val & PARA_CTR_SELECT) {
	119	if (val & PARA_CTR_STROBE) {
	120	s->status &= ~PARA_STS_BUSY;
	121	if ((s->control & PARA_CTR_STROBE) == 0)
	122	qemu_chr_write(s->chr, &s->dataw, 1);
	123	} else {
	124	if (s->control & PARA_CTR_INTEN) {
	125	s->irq_pending = 1;
	126	}
	127	}
	128	}
	129	parallel_update_irq(s);
	130	s->control = val;
5867c88a TS	131	break;
	132	}
	133	}
	134
	135	static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
	136	{
	137	ParallelState *s = opaque;
	138	uint8_t parm = val;
563e3c6e	139	int dir;
5867c88a TS	140
	141	/* Sometimes programs do several writes for timing purposes on old
	142	HW. Take care not to waste time on writes that do nothing. */
	143
	144	s->last_read_offset = ~0U;
	145
6508fe59	146	addr &= 7;
6508fe59	147	switch(addr) {
5867c88a TS	148	case PARA_REG_DATA:
5867c88a TS	149	if (s->dataw == val)
0fa7f157 TS	150	return;
	151	pdebug("wd%02x\n", val);
	152	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
	153	s->dataw = val;
6508fe59	154	break;
5867c88a	155	case PARA_REG_STS:
0fa7f157 TS	156	pdebug("ws%02x\n", val);
	157	if (val & PARA_STS_TMOUT)
	158	s->epp_timeout = 0;
	159	break;
5867c88a TS	160	case PARA_REG_CTR:
	161	val \|= 0xc0;
	162	if (s->control == val)
0fa7f157 TS	163	return;
0fa7f157 TS	164	pdebug("wc%02x\n", val);
563e3c6e AJ	165
	166	if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
	167	if (val & PARA_CTR_DIR) {
	168	dir = 1;
	169	} else {
	170	dir = 0;
	171	}
	172	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
	173	parm &= ~PARA_CTR_DIR;
	174	}
	175
0fa7f157 TS	176	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
0fa7f157 TS	177	s->control = val;
6508fe59	178	break;
5867c88a	179	case PARA_REG_EPP_ADDR:
0fa7f157 TS	180	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	181	/* Controls not correct for EPP address cycle, so do nothing */
	182	pdebug("wa%02x s\n", val);
	183	else {
	184	struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
	185	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
	186	s->epp_timeout = 1;
	187	pdebug("wa%02x t\n", val);
	188	}
	189	else
	190	pdebug("wa%02x\n", val);
	191	}
	192	break;
5867c88a	193	case PARA_REG_EPP_DATA:
0fa7f157 TS	194	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	195	/* Controls not correct for EPP data cycle, so do nothing */
	196	pdebug("we%02x s\n", val);
	197	else {
	198	struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
	199	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
	200	s->epp_timeout = 1;
	201	pdebug("we%02x t\n", val);
	202	}
	203	else
	204	pdebug("we%02x\n", val);
	205	}
	206	break;
5867c88a TS	207	}
	208	}
	209
	210	static void
	211	parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
	212	{
	213	ParallelState *s = opaque;
	214	uint16_t eppdata = cpu_to_le16(val);
	215	int err;
	216	struct ParallelIOArg ioarg = {
0fa7f157	217	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	218	};
5867c88a TS	219	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
0fa7f157 TS	220	/* Controls not correct for EPP data cycle, so do nothing */
	221	pdebug("we%04x s\n", val);
	222	return;
5867c88a TS	223	}
	224	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
	225	if (err) {
0fa7f157 TS	226	s->epp_timeout = 1;
0fa7f157 TS	227	pdebug("we%04x t\n", val);
5867c88a TS	228	}
5867c88a TS	229	else
0fa7f157	230	pdebug("we%04x\n", val);
5867c88a TS	231	}
	232
	233	static void
	234	parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
	235	{
	236	ParallelState *s = opaque;
	237	uint32_t eppdata = cpu_to_le32(val);
	238	int err;
	239	struct ParallelIOArg ioarg = {
0fa7f157	240	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	241	};
5867c88a TS	242	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
0fa7f157 TS	243	/* Controls not correct for EPP data cycle, so do nothing */
	244	pdebug("we%08x s\n", val);
	245	return;
5867c88a TS	246	}
	247	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
	248	if (err) {
0fa7f157 TS	249	s->epp_timeout = 1;
0fa7f157 TS	250	pdebug("we%08x t\n", val);
6508fe59	251	}
5867c88a	252	else
0fa7f157	253	pdebug("we%08x\n", val);
6508fe59 FB	254	}
6508fe59 FB	255
5867c88a	256	static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
6508fe59 FB	257	{
	258	ParallelState *s = opaque;
	259	uint32_t ret = 0xff;
	260
	261	addr &= 7;
	262	switch(addr) {
5867c88a	263	case PARA_REG_DATA:
0fa7f157 TS	264	if (s->control & PARA_CTR_DIR)
	265	ret = s->datar;
	266	else
	267	ret = s->dataw;
6508fe59	268	break;
5867c88a	269	case PARA_REG_STS:
0fa7f157 TS	270	ret = s->status;
	271	s->irq_pending = 0;
	272	if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
	273	/* XXX Fixme: wait 5 microseconds */
	274	if (s->status & PARA_STS_ACK)
	275	s->status &= ~PARA_STS_ACK;
	276	else {
	277	/* XXX Fixme: wait 5 microseconds */
	278	s->status \|= PARA_STS_ACK;
	279	s->status \|= PARA_STS_BUSY;
	280	}
	281	}
	282	parallel_update_irq(s);
6508fe59	283	break;
5867c88a	284	case PARA_REG_CTR:
6508fe59 FB	285	ret = s->control;
	286	break;
	287	}
5867c88a TS	288	pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
	289	return ret;
	290	}
	291
	292	static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
	293	{
	294	ParallelState *s = opaque;
	295	uint8_t ret = 0xff;
	296	addr &= 7;
	297	switch(addr) {
	298	case PARA_REG_DATA:
0fa7f157 TS	299	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
	300	if (s->last_read_offset != addr \|\| s->datar != ret)
	301	pdebug("rd%02x\n", ret);
5867c88a TS	302	s->datar = ret;
	303	break;
	304	case PARA_REG_STS:
0fa7f157 TS	305	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
	306	ret &= ~PARA_STS_TMOUT;
	307	if (s->epp_timeout)
	308	ret \|= PARA_STS_TMOUT;
	309	if (s->last_read_offset != addr \|\| s->status != ret)
	310	pdebug("rs%02x\n", ret);
	311	s->status = ret;
5867c88a TS	312	break;
	313	case PARA_REG_CTR:
	314	/* s->control has some bits fixed to 1. It is zero only when
0fa7f157 TS	315	it has not been yet written to. */
	316	if (s->control == 0) {
	317	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
	318	if (s->last_read_offset != addr)
	319	pdebug("rc%02x\n", ret);
	320	s->control = ret;
	321	}
	322	else {
	323	ret = s->control;
	324	if (s->last_read_offset != addr)
	325	pdebug("rc%02x\n", ret);
	326	}
5867c88a TS	327	break;
5867c88a TS	328	case PARA_REG_EPP_ADDR:
0fa7f157 TS	329	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT))
	330	/* Controls not correct for EPP addr cycle, so do nothing */
	331	pdebug("ra%02x s\n", ret);
	332	else {
	333	struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
	334	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
	335	s->epp_timeout = 1;
	336	pdebug("ra%02x t\n", ret);
	337	}
	338	else
	339	pdebug("ra%02x\n", ret);
	340	}
	341	break;
5867c88a	342	case PARA_REG_EPP_DATA:
0fa7f157 TS	343	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT))
	344	/* Controls not correct for EPP data cycle, so do nothing */
	345	pdebug("re%02x s\n", ret);
	346	else {
	347	struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
	348	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
	349	s->epp_timeout = 1;
	350	pdebug("re%02x t\n", ret);
	351	}
	352	else
	353	pdebug("re%02x\n", ret);
	354	}
	355	break;
5867c88a TS	356	}
	357	s->last_read_offset = addr;
	358	return ret;
	359	}
	360
	361	static uint32_t
	362	parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
	363	{
	364	ParallelState *s = opaque;
	365	uint32_t ret;
	366	uint16_t eppdata = ~0;
	367	int err;
	368	struct ParallelIOArg ioarg = {
0fa7f157	369	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	370	};
5867c88a TS	371	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT)) {
0fa7f157 TS	372	/* Controls not correct for EPP data cycle, so do nothing */
	373	pdebug("re%04x s\n", eppdata);
	374	return eppdata;
5867c88a TS	375	}
	376	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
	377	ret = le16_to_cpu(eppdata);
	378
	379	if (err) {
0fa7f157 TS	380	s->epp_timeout = 1;
0fa7f157 TS	381	pdebug("re%04x t\n", ret);
5867c88a TS	382	}
5867c88a TS	383	else
0fa7f157	384	pdebug("re%04x\n", ret);
5867c88a TS	385	return ret;
	386	}
	387
	388	static uint32_t
	389	parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
	390	{
	391	ParallelState *s = opaque;
	392	uint32_t ret;
	393	uint32_t eppdata = ~0U;
	394	int err;
	395	struct ParallelIOArg ioarg = {
0fa7f157	396	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	397	};
5867c88a TS	398	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT)) {
0fa7f157 TS	399	/* Controls not correct for EPP data cycle, so do nothing */
	400	pdebug("re%08x s\n", eppdata);
	401	return eppdata;
5867c88a TS	402	}
	403	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
	404	ret = le32_to_cpu(eppdata);
	405
	406	if (err) {
0fa7f157 TS	407	s->epp_timeout = 1;
0fa7f157 TS	408	pdebug("re%08x t\n", ret);
5867c88a TS	409	}
5867c88a TS	410	else
0fa7f157	411	pdebug("re%08x\n", ret);
5867c88a TS	412	return ret;
	413	}
	414
	415	static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
	416	{
7f5b7d3e	417	pdebug("wecp%d=%02x\n", addr & 7, val);
5867c88a TS	418	}
	419
	420	static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
	421	{
	422	uint8_t ret = 0xff;
7f5b7d3e BS	423
7f5b7d3e BS	424	pdebug("recp%d:%02x\n", addr & 7, ret);
6508fe59 FB	425	return ret;
	426	}
	427
33093a0a	428	static void parallel_reset(void *opaque)
6508fe59	429	{
33093a0a AJ	430	ParallelState *s = opaque;
33093a0a AJ	431
5867c88a TS	432	s->datar = ~0;
5867c88a TS	433	s->dataw = ~0;
6508fe59 FB	434	s->status = PARA_STS_BUSY;
	435	s->status \|= PARA_STS_ACK;
	436	s->status \|= PARA_STS_ONLINE;
	437	s->status \|= PARA_STS_ERROR;
52ccc5e0	438	s->status \|= PARA_STS_TMOUT;
6508fe59 FB	439	s->control = PARA_CTR_SELECT;
6508fe59 FB	440	s->control \|= PARA_CTR_INIT;
52ccc5e0	441	s->control \|= 0xc0;
5867c88a	442	s->irq_pending = 0;
5867c88a TS	443	s->hw_driver = 0;
	444	s->epp_timeout = 0;
	445	s->last_read_offset = ~0U;
d60532ca TS	446	}
d60532ca TS	447
e8ee28fb GH	448	static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
e8ee28fb GH	449
021f0674	450	static int parallel_isa_initfn(ISADevice *dev)
d60532ca	451	{
e8ee28fb	452	static int index;
021f0674 GH	453	ISAParallelState *isa = DO_UPCAST(ISAParallelState, dev, dev);
021f0674 GH	454	ParallelState *s = &isa->state;
e8ee28fb	455	int base;
d60532ca TS	456	uint8_t dummy;
d60532ca TS	457
021f0674 GH	458	if (!s->chr) {
	459	fprintf(stderr, "Can't create parallel device, empty char device\n");
	460	exit(1);
	461	}
	462
e8ee28fb GH	463	if (isa->index == -1)
	464	isa->index = index;
	465	if (isa->index >= MAX_PARALLEL_PORTS)
	466	return -1;
	467	if (isa->iobase == -1)
	468	isa->iobase = isa_parallel_io[isa->index];
	469	index++;
	470
	471	base = isa->iobase;
021f0674	472	isa_init_irq(dev, &s->irq, isa->isairq);
a08d4367	473	qemu_register_reset(parallel_reset, s);
6508fe59	474
021f0674	475	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
5867c88a	476	s->hw_driver = 1;
0fa7f157	477	s->status = dummy;
5867c88a TS	478	}
	479
	480	if (s->hw_driver) {
0fa7f157 TS	481	register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
	482	register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
	483	register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
	484	register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
	485	register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
	486	register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
	487	register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
	488	register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
5867c88a TS	489	}
5867c88a TS	490	else {
0fa7f157 TS	491	register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
0fa7f157 TS	492	register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
5867c88a	493	}
021f0674 GH	494	return 0;
	495	}
	496
021f0674 GH	497	ParallelState parallel_init(int index, CharDriverState chr)
	498	{
	499	ISADevice *dev;
	500
	501	dev = isa_create("isa-parallel");
e8ee28fb	502	qdev_prop_set_uint32(&dev->qdev, "index", index);
021f0674	503	qdev_prop_set_chr(&dev->qdev, "chardev", chr);
5c17ca25	504	if (qdev_init(&dev->qdev) < 0)
021f0674 GH	505	return NULL;
021f0674 GH	506	return &DO_UPCAST(ISAParallelState, dev, dev)->state;
6508fe59	507	}
d60532ca TS	508
d60532ca TS	509	/* Memory mapped interface */
c227f099	510	static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
d60532ca TS	511	{
	512	ParallelState *s = opaque;
	513
8da3ff18	514	return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
d60532ca TS	515	}
d60532ca TS	516
9596ebb7	517	static void parallel_mm_writeb (void *opaque,
c227f099	518	target_phys_addr_t addr, uint32_t value)
d60532ca TS	519	{
	520	ParallelState *s = opaque;
	521
8da3ff18	522	parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
d60532ca TS	523	}
d60532ca TS	524
c227f099	525	static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
d60532ca TS	526	{
	527	ParallelState *s = opaque;
	528
8da3ff18	529	return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
d60532ca TS	530	}
d60532ca TS	531
9596ebb7	532	static void parallel_mm_writew (void *opaque,
c227f099	533	target_phys_addr_t addr, uint32_t value)
d60532ca TS	534	{
	535	ParallelState *s = opaque;
	536
8da3ff18	537	parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
d60532ca TS	538	}
d60532ca TS	539
c227f099	540	static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
d60532ca TS	541	{
	542	ParallelState *s = opaque;
	543
8da3ff18	544	return parallel_ioport_read_sw(s, addr >> s->it_shift);
d60532ca TS	545	}
d60532ca TS	546
9596ebb7	547	static void parallel_mm_writel (void *opaque,
c227f099	548	target_phys_addr_t addr, uint32_t value)
d60532ca TS	549	{
	550	ParallelState *s = opaque;
	551
8da3ff18	552	parallel_ioport_write_sw(s, addr >> s->it_shift, value);
d60532ca TS	553	}
d60532ca TS	554
d60efc6b	555	static CPUReadMemoryFunc * const parallel_mm_read_sw[] = {
d60532ca TS	556	&parallel_mm_readb,
	557	&parallel_mm_readw,
	558	&parallel_mm_readl,
	559	};
	560
d60efc6b	561	static CPUWriteMemoryFunc * const parallel_mm_write_sw[] = {
d60532ca TS	562	&parallel_mm_writeb,
	563	&parallel_mm_writew,
	564	&parallel_mm_writel,
	565	};
	566
	567	/* If fd is zero, it means that the parallel device uses the console */
c227f099	568	ParallelState parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState chr)
d60532ca TS	569	{
	570	ParallelState *s;
	571	int io_sw;
	572
	573	s = qemu_mallocz(sizeof(ParallelState));
33093a0a AJ	574	s->irq = irq;
33093a0a AJ	575	s->chr = chr;
d60532ca	576	s->it_shift = it_shift;
a08d4367	577	qemu_register_reset(parallel_reset, s);
d60532ca	578
1eed09cb	579	io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, s);
d60532ca TS	580	cpu_register_physical_memory(base, 8 << it_shift, io_sw);
	581	return s;
	582	}
021f0674 GH	583
	584	static ISADeviceInfo parallel_isa_info = {
	585	.qdev.name = "isa-parallel",
	586	.qdev.size = sizeof(ISAParallelState),
	587	.init = parallel_isa_initfn,
	588	.qdev.props = (Property[]) {
51954d56	589	DEFINE_PROP_UINT32("index", ISAParallelState, index, -1),
e8ee28fb	590	DEFINE_PROP_HEX32("iobase", ISAParallelState, iobase, -1),
021f0674 GH	591	DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7),
	592	DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr),
	593	DEFINE_PROP_END_OF_LIST(),
	594	},
	595	};
	596
	597	static void parallel_register_devices(void)
	598	{
	599	isa_qdev_register(&parallel_isa_info);
	600	}
	601
	602	device_init(parallel_register_devices)