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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pc.h" | |
aa28b9bf | 26 | #include "apic.h" |
87ecb68b | 27 | #include "fdc.h" |
c0897e0c | 28 | #include "ide.h" |
87ecb68b | 29 | #include "pci.h" |
18e08a55 | 30 | #include "vmware_vga.h" |
376253ec | 31 | #include "monitor.h" |
3cce6243 | 32 | #include "fw_cfg.h" |
16b29ae1 | 33 | #include "hpet_emul.h" |
b6f6e3d3 | 34 | #include "smbios.h" |
ca20cf32 BS |
35 | #include "loader.h" |
36 | #include "elf.h" | |
52001445 | 37 | #include "multiboot.h" |
1d914fa0 | 38 | #include "mc146818rtc.h" |
b1277b03 | 39 | #include "i8254.h" |
302fe51b | 40 | #include "pcspk.h" |
60ba3cc2 | 41 | #include "msi.h" |
822557eb | 42 | #include "sysbus.h" |
666daa68 | 43 | #include "sysemu.h" |
9b5b76d4 | 44 | #include "kvm.h" |
9468e9c4 | 45 | #include "xen.h" |
2446333c | 46 | #include "blockdev.h" |
2b584959 | 47 | #include "hw/block-common.h" |
a19cbfb3 | 48 | #include "ui/qemu-spice.h" |
00cb2a99 | 49 | #include "memory.h" |
be20f9e9 | 50 | #include "exec-memory.h" |
c2d8d311 | 51 | #include "arch_init.h" |
ee785fed | 52 | #include "bitmap.h" |
80cabfad | 53 | |
b41a2cd1 FB |
54 | /* output Bochs bios info messages */ |
55 | //#define DEBUG_BIOS | |
56 | ||
471fd342 BS |
57 | /* debug PC/ISA interrupts */ |
58 | //#define DEBUG_IRQ | |
59 | ||
60 | #ifdef DEBUG_IRQ | |
61 | #define DPRINTF(fmt, ...) \ | |
62 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
63 | #else | |
64 | #define DPRINTF(fmt, ...) | |
65 | #endif | |
66 | ||
a80274c3 PB |
67 | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ |
68 | #define ACPI_DATA_SIZE 0x10000 | |
3cce6243 | 69 | #define BIOS_CFG_IOPORT 0x510 |
8a92ea2f | 70 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
b6f6e3d3 | 71 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
6b35e7bf | 72 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
4c5b10b7 | 73 | #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
40ac17cd | 74 | #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) |
80cabfad | 75 | |
92a16d7a BS |
76 | #define MSI_ADDR_BASE 0xfee00000 |
77 | ||
4c5b10b7 JS |
78 | #define E820_NR_ENTRIES 16 |
79 | ||
80 | struct e820_entry { | |
81 | uint64_t address; | |
82 | uint64_t length; | |
83 | uint32_t type; | |
541dc0d4 | 84 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 JS |
85 | |
86 | struct e820_table { | |
87 | uint32_t count; | |
88 | struct e820_entry entry[E820_NR_ENTRIES]; | |
541dc0d4 | 89 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 JS |
90 | |
91 | static struct e820_table e820_table; | |
dd703b99 | 92 | struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; |
4c5b10b7 | 93 | |
b881fbe9 | 94 | void gsi_handler(void *opaque, int n, int level) |
1452411b | 95 | { |
b881fbe9 | 96 | GSIState *s = opaque; |
1452411b | 97 | |
b881fbe9 JK |
98 | DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); |
99 | if (n < ISA_NUM_IRQS) { | |
100 | qemu_set_irq(s->i8259_irq[n], level); | |
1632dc6a | 101 | } |
b881fbe9 | 102 | qemu_set_irq(s->ioapic_irq[n], level); |
2e9947d2 | 103 | } |
1452411b | 104 | |
b41a2cd1 | 105 | static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
80cabfad FB |
106 | { |
107 | } | |
108 | ||
f929aad6 | 109 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 110 | static qemu_irq ferr_irq; |
8e78eb28 IY |
111 | |
112 | void pc_register_ferr_irq(qemu_irq irq) | |
113 | { | |
114 | ferr_irq = irq; | |
115 | } | |
116 | ||
f929aad6 FB |
117 | /* XXX: add IGNNE support */ |
118 | void cpu_set_ferr(CPUX86State *s) | |
119 | { | |
d537cf6c | 120 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
121 | } |
122 | ||
123 | static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) | |
124 | { | |
d537cf6c | 125 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
126 | } |
127 | ||
28ab0e2e | 128 | /* TSC handling */ |
28ab0e2e FB |
129 | uint64_t cpu_get_tsc(CPUX86State *env) |
130 | { | |
4a1418e0 | 131 | return cpu_get_ticks(); |
28ab0e2e FB |
132 | } |
133 | ||
a5954d5c | 134 | /* SMM support */ |
f885f1ea IY |
135 | |
136 | static cpu_set_smm_t smm_set; | |
137 | static void *smm_arg; | |
138 | ||
139 | void cpu_smm_register(cpu_set_smm_t callback, void *arg) | |
140 | { | |
141 | assert(smm_set == NULL); | |
142 | assert(smm_arg == NULL); | |
143 | smm_set = callback; | |
144 | smm_arg = arg; | |
145 | } | |
146 | ||
4a8fa5dc | 147 | void cpu_smm_update(CPUX86State *env) |
a5954d5c | 148 | { |
f885f1ea IY |
149 | if (smm_set && smm_arg && env == first_cpu) |
150 | smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); | |
a5954d5c FB |
151 | } |
152 | ||
153 | ||
3de388f6 | 154 | /* IRQ handling */ |
4a8fa5dc | 155 | int cpu_get_pic_interrupt(CPUX86State *env) |
3de388f6 FB |
156 | { |
157 | int intno; | |
158 | ||
cf6d64bf | 159 | intno = apic_get_interrupt(env->apic_state); |
3de388f6 | 160 | if (intno >= 0) { |
3de388f6 FB |
161 | return intno; |
162 | } | |
3de388f6 | 163 | /* read the irq from the PIC */ |
cf6d64bf | 164 | if (!apic_accept_pic_intr(env->apic_state)) { |
0e21e12b | 165 | return -1; |
cf6d64bf | 166 | } |
0e21e12b | 167 | |
3de388f6 FB |
168 | intno = pic_read_irq(isa_pic); |
169 | return intno; | |
170 | } | |
171 | ||
d537cf6c | 172 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 173 | { |
4a8fa5dc | 174 | CPUX86State *env = first_cpu; |
a5b38b51 | 175 | |
471fd342 | 176 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
d5529471 AJ |
177 | if (env->apic_state) { |
178 | while (env) { | |
cf6d64bf BS |
179 | if (apic_accept_pic_intr(env->apic_state)) { |
180 | apic_deliver_pic_intr(env->apic_state, level); | |
181 | } | |
d5529471 AJ |
182 | env = env->next_cpu; |
183 | } | |
184 | } else { | |
b614106a AJ |
185 | if (level) |
186 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
187 | else | |
188 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
a5b38b51 | 189 | } |
3de388f6 FB |
190 | } |
191 | ||
b0a21b53 FB |
192 | /* PC cmos mappings */ |
193 | ||
80cabfad FB |
194 | #define REG_EQUIPMENT_BYTE 0x14 |
195 | ||
d288c7ba | 196 | static int cmos_get_fd_drive_type(FDriveType fd0) |
777428f2 FB |
197 | { |
198 | int val; | |
199 | ||
200 | switch (fd0) { | |
d288c7ba | 201 | case FDRIVE_DRV_144: |
777428f2 FB |
202 | /* 1.44 Mb 3"5 drive */ |
203 | val = 4; | |
204 | break; | |
d288c7ba | 205 | case FDRIVE_DRV_288: |
777428f2 FB |
206 | /* 2.88 Mb 3"5 drive */ |
207 | val = 5; | |
208 | break; | |
d288c7ba | 209 | case FDRIVE_DRV_120: |
777428f2 FB |
210 | /* 1.2 Mb 5"5 drive */ |
211 | val = 2; | |
212 | break; | |
d288c7ba | 213 | case FDRIVE_DRV_NONE: |
777428f2 FB |
214 | default: |
215 | val = 0; | |
216 | break; | |
217 | } | |
218 | return val; | |
219 | } | |
220 | ||
9139046c MA |
221 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, |
222 | int16_t cylinders, int8_t heads, int8_t sectors) | |
ba6c2377 | 223 | { |
ba6c2377 FB |
224 | rtc_set_memory(s, type_ofs, 47); |
225 | rtc_set_memory(s, info_ofs, cylinders); | |
226 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
227 | rtc_set_memory(s, info_ofs + 2, heads); | |
228 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
229 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
230 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
231 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
232 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
233 | rtc_set_memory(s, info_ofs + 8, sectors); | |
234 | } | |
235 | ||
6ac0e82d AZ |
236 | /* convert boot_device letter to something recognizable by the bios */ |
237 | static int boot_device2nibble(char boot_device) | |
238 | { | |
239 | switch(boot_device) { | |
240 | case 'a': | |
241 | case 'b': | |
242 | return 0x01; /* floppy boot */ | |
243 | case 'c': | |
244 | return 0x02; /* hard drive boot */ | |
245 | case 'd': | |
246 | return 0x03; /* CD-ROM boot */ | |
247 | case 'n': | |
248 | return 0x04; /* Network boot */ | |
249 | } | |
250 | return 0; | |
251 | } | |
252 | ||
1d914fa0 | 253 | static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk) |
0ecdffbb AJ |
254 | { |
255 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
256 | int nbds, bds[3] = { 0, }; |
257 | int i; | |
258 | ||
259 | nbds = strlen(boot_device); | |
260 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
1ecda02b | 261 | error_report("Too many boot devices for PC"); |
0ecdffbb AJ |
262 | return(1); |
263 | } | |
264 | for (i = 0; i < nbds; i++) { | |
265 | bds[i] = boot_device2nibble(boot_device[i]); | |
266 | if (bds[i] == 0) { | |
1ecda02b MA |
267 | error_report("Invalid boot device for PC: '%c'", |
268 | boot_device[i]); | |
0ecdffbb AJ |
269 | return(1); |
270 | } | |
271 | } | |
272 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 273 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
274 | return(0); |
275 | } | |
276 | ||
d9346e81 MA |
277 | static int pc_boot_set(void *opaque, const char *boot_device) |
278 | { | |
279 | return set_boot_dev(opaque, boot_device, 0); | |
280 | } | |
281 | ||
c0897e0c MA |
282 | typedef struct pc_cmos_init_late_arg { |
283 | ISADevice *rtc_state; | |
9139046c | 284 | BusState *idebus[2]; |
c0897e0c MA |
285 | } pc_cmos_init_late_arg; |
286 | ||
287 | static void pc_cmos_init_late(void *opaque) | |
288 | { | |
289 | pc_cmos_init_late_arg *arg = opaque; | |
290 | ISADevice *s = arg->rtc_state; | |
9139046c MA |
291 | int16_t cylinders; |
292 | int8_t heads, sectors; | |
c0897e0c | 293 | int val; |
2adc99b2 | 294 | int i, trans; |
c0897e0c | 295 | |
9139046c MA |
296 | val = 0; |
297 | if (ide_get_geometry(arg->idebus[0], 0, | |
298 | &cylinders, &heads, §ors) >= 0) { | |
299 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); | |
300 | val |= 0xf0; | |
301 | } | |
302 | if (ide_get_geometry(arg->idebus[0], 1, | |
303 | &cylinders, &heads, §ors) >= 0) { | |
304 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); | |
305 | val |= 0x0f; | |
306 | } | |
307 | rtc_set_memory(s, 0x12, val); | |
c0897e0c MA |
308 | |
309 | val = 0; | |
310 | for (i = 0; i < 4; i++) { | |
9139046c MA |
311 | /* NOTE: ide_get_geometry() returns the physical |
312 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
313 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
314 | geometry can be different if a translation is done. */ | |
315 | if (ide_get_geometry(arg->idebus[i / 2], i % 2, | |
316 | &cylinders, &heads, §ors) >= 0) { | |
2adc99b2 MA |
317 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; |
318 | assert((trans & ~3) == 0); | |
319 | val |= trans << (i * 2); | |
c0897e0c MA |
320 | } |
321 | } | |
322 | rtc_set_memory(s, 0x39, val); | |
323 | ||
324 | qemu_unregister_reset(pc_cmos_init_late, opaque); | |
325 | } | |
326 | ||
845773ab | 327 | void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
c0897e0c | 328 | const char *boot_device, |
34d4260e | 329 | ISADevice *floppy, BusState *idebus0, BusState *idebus1, |
63ffb564 | 330 | ISADevice *s) |
80cabfad | 331 | { |
61a8d649 | 332 | int val, nb, i; |
980bda8b | 333 | FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; |
c0897e0c | 334 | static pc_cmos_init_late_arg arg; |
b0a21b53 | 335 | |
b0a21b53 | 336 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
337 | |
338 | /* memory size */ | |
333190eb FB |
339 | val = 640; /* base memory in K */ |
340 | rtc_set_memory(s, 0x15, val); | |
341 | rtc_set_memory(s, 0x16, val >> 8); | |
342 | ||
80cabfad FB |
343 | val = (ram_size / 1024) - 1024; |
344 | if (val > 65535) | |
345 | val = 65535; | |
b0a21b53 FB |
346 | rtc_set_memory(s, 0x17, val); |
347 | rtc_set_memory(s, 0x18, val >> 8); | |
348 | rtc_set_memory(s, 0x30, val); | |
349 | rtc_set_memory(s, 0x31, val >> 8); | |
80cabfad | 350 | |
00f82b8a AJ |
351 | if (above_4g_mem_size) { |
352 | rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); | |
353 | rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); | |
354 | rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); | |
355 | } | |
356 | ||
9da98861 FB |
357 | if (ram_size > (16 * 1024 * 1024)) |
358 | val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); | |
359 | else | |
360 | val = 0; | |
80cabfad FB |
361 | if (val > 65535) |
362 | val = 65535; | |
b0a21b53 FB |
363 | rtc_set_memory(s, 0x34, val); |
364 | rtc_set_memory(s, 0x35, val >> 8); | |
3b46e624 | 365 | |
298e01b6 AJ |
366 | /* set the number of CPU */ |
367 | rtc_set_memory(s, 0x5f, smp_cpus - 1); | |
368 | ||
6ac0e82d | 369 | /* set boot devices, and disable floppy signature check if requested */ |
d9346e81 | 370 | if (set_boot_dev(s, boot_device, fd_bootchk)) { |
28c5af54 JM |
371 | exit(1); |
372 | } | |
80cabfad | 373 | |
b41a2cd1 | 374 | /* floppy type */ |
34d4260e | 375 | if (floppy) { |
34d4260e | 376 | for (i = 0; i < 2; i++) { |
61a8d649 | 377 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); |
63ffb564 BS |
378 | } |
379 | } | |
380 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
381 | cmos_get_fd_drive_type(fd_type[1]); | |
b0a21b53 | 382 | rtc_set_memory(s, 0x10, val); |
3b46e624 | 383 | |
b0a21b53 | 384 | val = 0; |
b41a2cd1 | 385 | nb = 0; |
63ffb564 | 386 | if (fd_type[0] < FDRIVE_DRV_NONE) { |
80cabfad | 387 | nb++; |
d288c7ba | 388 | } |
63ffb564 | 389 | if (fd_type[1] < FDRIVE_DRV_NONE) { |
80cabfad | 390 | nb++; |
d288c7ba | 391 | } |
80cabfad FB |
392 | switch (nb) { |
393 | case 0: | |
394 | break; | |
395 | case 1: | |
b0a21b53 | 396 | val |= 0x01; /* 1 drive, ready for boot */ |
80cabfad FB |
397 | break; |
398 | case 2: | |
b0a21b53 | 399 | val |= 0x41; /* 2 drives, ready for boot */ |
80cabfad FB |
400 | break; |
401 | } | |
b0a21b53 FB |
402 | val |= 0x02; /* FPU is there */ |
403 | val |= 0x04; /* PS/2 mouse installed */ | |
404 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
405 | ||
ba6c2377 | 406 | /* hard drives */ |
c0897e0c | 407 | arg.rtc_state = s; |
9139046c MA |
408 | arg.idebus[0] = idebus0; |
409 | arg.idebus[1] = idebus1; | |
c0897e0c | 410 | qemu_register_reset(pc_cmos_init_late, &arg); |
80cabfad FB |
411 | } |
412 | ||
4b78a802 BS |
413 | /* port 92 stuff: could be split off */ |
414 | typedef struct Port92State { | |
415 | ISADevice dev; | |
23af670e | 416 | MemoryRegion io; |
4b78a802 BS |
417 | uint8_t outport; |
418 | qemu_irq *a20_out; | |
419 | } Port92State; | |
420 | ||
421 | static void port92_write(void *opaque, uint32_t addr, uint32_t val) | |
422 | { | |
423 | Port92State *s = opaque; | |
424 | ||
425 | DPRINTF("port92: write 0x%02x\n", val); | |
426 | s->outport = val; | |
427 | qemu_set_irq(*s->a20_out, (val >> 1) & 1); | |
428 | if (val & 1) { | |
429 | qemu_system_reset_request(); | |
430 | } | |
431 | } | |
432 | ||
433 | static uint32_t port92_read(void *opaque, uint32_t addr) | |
434 | { | |
435 | Port92State *s = opaque; | |
436 | uint32_t ret; | |
437 | ||
438 | ret = s->outport; | |
439 | DPRINTF("port92: read 0x%02x\n", ret); | |
440 | return ret; | |
441 | } | |
442 | ||
443 | static void port92_init(ISADevice *dev, qemu_irq *a20_out) | |
444 | { | |
445 | Port92State *s = DO_UPCAST(Port92State, dev, dev); | |
446 | ||
447 | s->a20_out = a20_out; | |
448 | } | |
449 | ||
450 | static const VMStateDescription vmstate_port92_isa = { | |
451 | .name = "port92", | |
452 | .version_id = 1, | |
453 | .minimum_version_id = 1, | |
454 | .minimum_version_id_old = 1, | |
455 | .fields = (VMStateField []) { | |
456 | VMSTATE_UINT8(outport, Port92State), | |
457 | VMSTATE_END_OF_LIST() | |
458 | } | |
459 | }; | |
460 | ||
461 | static void port92_reset(DeviceState *d) | |
462 | { | |
463 | Port92State *s = container_of(d, Port92State, dev.qdev); | |
464 | ||
465 | s->outport &= ~1; | |
466 | } | |
467 | ||
23af670e RH |
468 | static const MemoryRegionPortio port92_portio[] = { |
469 | { 0, 1, 1, .read = port92_read, .write = port92_write }, | |
470 | PORTIO_END_OF_LIST(), | |
471 | }; | |
472 | ||
473 | static const MemoryRegionOps port92_ops = { | |
474 | .old_portio = port92_portio | |
475 | }; | |
476 | ||
4b78a802 BS |
477 | static int port92_initfn(ISADevice *dev) |
478 | { | |
479 | Port92State *s = DO_UPCAST(Port92State, dev, dev); | |
480 | ||
23af670e RH |
481 | memory_region_init_io(&s->io, &port92_ops, s, "port92", 1); |
482 | isa_register_ioport(dev, &s->io, 0x92); | |
483 | ||
4b78a802 BS |
484 | s->outport = 0; |
485 | return 0; | |
486 | } | |
487 | ||
8f04ee08 AL |
488 | static void port92_class_initfn(ObjectClass *klass, void *data) |
489 | { | |
39bffca2 | 490 | DeviceClass *dc = DEVICE_CLASS(klass); |
8f04ee08 AL |
491 | ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); |
492 | ic->init = port92_initfn; | |
39bffca2 AL |
493 | dc->no_user = 1; |
494 | dc->reset = port92_reset; | |
495 | dc->vmsd = &vmstate_port92_isa; | |
8f04ee08 AL |
496 | } |
497 | ||
39bffca2 AL |
498 | static TypeInfo port92_info = { |
499 | .name = "port92", | |
500 | .parent = TYPE_ISA_DEVICE, | |
501 | .instance_size = sizeof(Port92State), | |
502 | .class_init = port92_class_initfn, | |
4b78a802 BS |
503 | }; |
504 | ||
83f7d43a | 505 | static void port92_register_types(void) |
4b78a802 | 506 | { |
39bffca2 | 507 | type_register_static(&port92_info); |
4b78a802 | 508 | } |
83f7d43a AF |
509 | |
510 | type_init(port92_register_types) | |
4b78a802 | 511 | |
956a3e6b | 512 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 513 | { |
4a8fa5dc | 514 | CPUX86State *cpu = opaque; |
e1a23744 | 515 | |
956a3e6b | 516 | /* XXX: send to all CPUs ? */ |
4b78a802 | 517 | /* XXX: add logic to handle multiple A20 line sources */ |
956a3e6b | 518 | cpu_x86_set_a20(cpu, level); |
e1a23744 FB |
519 | } |
520 | ||
80cabfad FB |
521 | /***********************************************************/ |
522 | /* Bochs BIOS debug ports */ | |
523 | ||
9596ebb7 | 524 | static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
80cabfad | 525 | { |
a2f659ee FB |
526 | static const char shutdown_str[8] = "Shutdown"; |
527 | static int shutdown_index = 0; | |
3b46e624 | 528 | |
80cabfad FB |
529 | switch(addr) { |
530 | /* Bochs BIOS messages */ | |
531 | case 0x400: | |
532 | case 0x401: | |
0550f9c1 BK |
533 | /* used to be panic, now unused */ |
534 | break; | |
80cabfad FB |
535 | case 0x402: |
536 | case 0x403: | |
537 | #ifdef DEBUG_BIOS | |
538 | fprintf(stderr, "%c", val); | |
539 | #endif | |
540 | break; | |
a2f659ee FB |
541 | case 0x8900: |
542 | /* same as Bochs power off */ | |
543 | if (val == shutdown_str[shutdown_index]) { | |
544 | shutdown_index++; | |
545 | if (shutdown_index == 8) { | |
546 | shutdown_index = 0; | |
547 | qemu_system_shutdown_request(); | |
548 | } | |
549 | } else { | |
550 | shutdown_index = 0; | |
551 | } | |
552 | break; | |
80cabfad FB |
553 | |
554 | /* LGPL'ed VGA BIOS messages */ | |
555 | case 0x501: | |
556 | case 0x502: | |
4333979e | 557 | exit((val << 1) | 1); |
80cabfad FB |
558 | case 0x500: |
559 | case 0x503: | |
560 | #ifdef DEBUG_BIOS | |
561 | fprintf(stderr, "%c", val); | |
562 | #endif | |
563 | break; | |
564 | } | |
565 | } | |
566 | ||
4c5b10b7 JS |
567 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) |
568 | { | |
8ca209ad | 569 | int index = le32_to_cpu(e820_table.count); |
4c5b10b7 JS |
570 | struct e820_entry *entry; |
571 | ||
572 | if (index >= E820_NR_ENTRIES) | |
573 | return -EBUSY; | |
8ca209ad | 574 | entry = &e820_table.entry[index++]; |
4c5b10b7 | 575 | |
8ca209ad AW |
576 | entry->address = cpu_to_le64(address); |
577 | entry->length = cpu_to_le64(length); | |
578 | entry->type = cpu_to_le32(type); | |
4c5b10b7 | 579 | |
8ca209ad AW |
580 | e820_table.count = cpu_to_le32(index); |
581 | return index; | |
4c5b10b7 JS |
582 | } |
583 | ||
bf483392 | 584 | static void *bochs_bios_init(void) |
80cabfad | 585 | { |
3cce6243 | 586 | void *fw_cfg; |
b6f6e3d3 AL |
587 | uint8_t *smbios_table; |
588 | size_t smbios_len; | |
11c2fd3e AL |
589 | uint64_t *numa_fw_cfg; |
590 | int i, j; | |
3cce6243 | 591 | |
b41a2cd1 FB |
592 | register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
593 | register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); | |
594 | register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); | |
595 | register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); | |
a2f659ee | 596 | register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
b41a2cd1 | 597 | |
4333979e | 598 | register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL); |
b41a2cd1 FB |
599 | register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); |
600 | register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); | |
601 | register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); | |
602 | register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); | |
3cce6243 BS |
603 | |
604 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); | |
bf483392 | 605 | |
3cce6243 | 606 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); |
905fdcb5 | 607 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
80deece2 BS |
608 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, |
609 | acpi_tables_len); | |
9b5b76d4 | 610 | fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); |
b6f6e3d3 AL |
611 | |
612 | smbios_table = smbios_get_table(&smbios_len); | |
613 | if (smbios_table) | |
614 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, | |
615 | smbios_table, smbios_len); | |
4c5b10b7 JS |
616 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table, |
617 | sizeof(struct e820_table)); | |
11c2fd3e | 618 | |
40ac17cd GN |
619 | fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg, |
620 | sizeof(struct hpet_fw_config)); | |
11c2fd3e AL |
621 | /* allocate memory for the NUMA channel: one (64bit) word for the number |
622 | * of nodes, one word for each VCPU->node and one word for each node to | |
623 | * hold the amount of memory. | |
624 | */ | |
991dfefd | 625 | numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8); |
11c2fd3e | 626 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); |
991dfefd | 627 | for (i = 0; i < max_cpus; i++) { |
11c2fd3e | 628 | for (j = 0; j < nb_numa_nodes; j++) { |
ee785fed | 629 | if (test_bit(i, node_cpumask[j])) { |
11c2fd3e AL |
630 | numa_fw_cfg[i + 1] = cpu_to_le64(j); |
631 | break; | |
632 | } | |
633 | } | |
634 | } | |
635 | for (i = 0; i < nb_numa_nodes; i++) { | |
991dfefd | 636 | numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]); |
11c2fd3e AL |
637 | } |
638 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, | |
991dfefd | 639 | (1 + max_cpus + nb_numa_nodes) * 8); |
bf483392 AG |
640 | |
641 | return fw_cfg; | |
80cabfad FB |
642 | } |
643 | ||
642a4f96 TS |
644 | static long get_file_size(FILE *f) |
645 | { | |
646 | long where, size; | |
647 | ||
648 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
649 | ||
650 | where = ftell(f); | |
651 | fseek(f, 0, SEEK_END); | |
652 | size = ftell(f); | |
653 | fseek(f, where, SEEK_SET); | |
654 | ||
655 | return size; | |
656 | } | |
657 | ||
f16408df | 658 | static void load_linux(void *fw_cfg, |
4fc9af53 | 659 | const char *kernel_filename, |
642a4f96 | 660 | const char *initrd_filename, |
e6ade764 | 661 | const char *kernel_cmdline, |
45a50b16 | 662 | target_phys_addr_t max_ram_size) |
642a4f96 TS |
663 | { |
664 | uint16_t protocol; | |
5cea8590 | 665 | int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
642a4f96 | 666 | uint32_t initrd_max; |
57a46d05 | 667 | uint8_t header[8192], *setup, *kernel, *initrd_data; |
c227f099 | 668 | target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0; |
45a50b16 | 669 | FILE *f; |
bf4e5d92 | 670 | char *vmode; |
642a4f96 TS |
671 | |
672 | /* Align to 16 bytes as a paranoia measure */ | |
673 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
674 | ||
675 | /* load the kernel header */ | |
676 | f = fopen(kernel_filename, "rb"); | |
677 | if (!f || !(kernel_size = get_file_size(f)) || | |
f16408df AG |
678 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != |
679 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
850810d0 JF |
680 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", |
681 | kernel_filename, strerror(errno)); | |
642a4f96 TS |
682 | exit(1); |
683 | } | |
684 | ||
685 | /* kernel protocol version */ | |
bc4edd79 | 686 | #if 0 |
642a4f96 | 687 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 688 | #endif |
642a4f96 TS |
689 | if (ldl_p(header+0x202) == 0x53726448) |
690 | protocol = lduw_p(header+0x206); | |
f16408df AG |
691 | else { |
692 | /* This looks like a multiboot kernel. If it is, let's stop | |
693 | treating it like a Linux kernel. */ | |
52001445 AL |
694 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, |
695 | kernel_cmdline, kernel_size, header)) | |
82663ee2 | 696 | return; |
642a4f96 | 697 | protocol = 0; |
f16408df | 698 | } |
642a4f96 TS |
699 | |
700 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
701 | /* Low kernel */ | |
a37af289 BS |
702 | real_addr = 0x90000; |
703 | cmdline_addr = 0x9a000 - cmdline_size; | |
704 | prot_addr = 0x10000; | |
642a4f96 TS |
705 | } else if (protocol < 0x202) { |
706 | /* High but ancient kernel */ | |
a37af289 BS |
707 | real_addr = 0x90000; |
708 | cmdline_addr = 0x9a000 - cmdline_size; | |
709 | prot_addr = 0x100000; | |
642a4f96 TS |
710 | } else { |
711 | /* High and recent kernel */ | |
a37af289 BS |
712 | real_addr = 0x10000; |
713 | cmdline_addr = 0x20000; | |
714 | prot_addr = 0x100000; | |
642a4f96 TS |
715 | } |
716 | ||
bc4edd79 | 717 | #if 0 |
642a4f96 | 718 | fprintf(stderr, |
526ccb7a AZ |
719 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" |
720 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
721 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
a37af289 BS |
722 | real_addr, |
723 | cmdline_addr, | |
724 | prot_addr); | |
bc4edd79 | 725 | #endif |
642a4f96 TS |
726 | |
727 | /* highest address for loading the initrd */ | |
728 | if (protocol >= 0x203) | |
729 | initrd_max = ldl_p(header+0x22c); | |
730 | else | |
731 | initrd_max = 0x37ffffff; | |
732 | ||
e6ade764 GC |
733 | if (initrd_max >= max_ram_size-ACPI_DATA_SIZE) |
734 | initrd_max = max_ram_size-ACPI_DATA_SIZE-1; | |
642a4f96 | 735 | |
57a46d05 AG |
736 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
737 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
738 | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, | |
739 | (uint8_t*)strdup(kernel_cmdline), | |
740 | strlen(kernel_cmdline)+1); | |
642a4f96 TS |
741 | |
742 | if (protocol >= 0x202) { | |
a37af289 | 743 | stl_p(header+0x228, cmdline_addr); |
642a4f96 TS |
744 | } else { |
745 | stw_p(header+0x20, 0xA33F); | |
746 | stw_p(header+0x22, cmdline_addr-real_addr); | |
747 | } | |
748 | ||
bf4e5d92 PT |
749 | /* handle vga= parameter */ |
750 | vmode = strstr(kernel_cmdline, "vga="); | |
751 | if (vmode) { | |
752 | unsigned int video_mode; | |
753 | /* skip "vga=" */ | |
754 | vmode += 4; | |
755 | if (!strncmp(vmode, "normal", 6)) { | |
756 | video_mode = 0xffff; | |
757 | } else if (!strncmp(vmode, "ext", 3)) { | |
758 | video_mode = 0xfffe; | |
759 | } else if (!strncmp(vmode, "ask", 3)) { | |
760 | video_mode = 0xfffd; | |
761 | } else { | |
762 | video_mode = strtol(vmode, NULL, 0); | |
763 | } | |
764 | stw_p(header+0x1fa, video_mode); | |
765 | } | |
766 | ||
642a4f96 | 767 | /* loader type */ |
5cbdb3a3 | 768 | /* High nybble = B reserved for QEMU; low nybble is revision number. |
642a4f96 TS |
769 | If this code is substantially changed, you may want to consider |
770 | incrementing the revision. */ | |
771 | if (protocol >= 0x200) | |
772 | header[0x210] = 0xB0; | |
773 | ||
774 | /* heap */ | |
775 | if (protocol >= 0x201) { | |
776 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ | |
777 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
778 | } | |
779 | ||
780 | /* load initrd */ | |
781 | if (initrd_filename) { | |
782 | if (protocol < 0x200) { | |
783 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
784 | exit(1); | |
785 | } | |
786 | ||
45a50b16 | 787 | initrd_size = get_image_size(initrd_filename); |
d6fa4b77 MK |
788 | if (initrd_size < 0) { |
789 | fprintf(stderr, "qemu: error reading initrd %s\n", | |
790 | initrd_filename); | |
791 | exit(1); | |
792 | } | |
793 | ||
45a50b16 | 794 | initrd_addr = (initrd_max-initrd_size) & ~4095; |
57a46d05 | 795 | |
7267c094 | 796 | initrd_data = g_malloc(initrd_size); |
57a46d05 AG |
797 | load_image(initrd_filename, initrd_data); |
798 | ||
799 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
800 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
801 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
642a4f96 | 802 | |
a37af289 | 803 | stl_p(header+0x218, initrd_addr); |
642a4f96 TS |
804 | stl_p(header+0x21c, initrd_size); |
805 | } | |
806 | ||
45a50b16 | 807 | /* load kernel and setup */ |
642a4f96 TS |
808 | setup_size = header[0x1f1]; |
809 | if (setup_size == 0) | |
810 | setup_size = 4; | |
642a4f96 | 811 | setup_size = (setup_size+1)*512; |
45a50b16 | 812 | kernel_size -= setup_size; |
642a4f96 | 813 | |
7267c094 AL |
814 | setup = g_malloc(setup_size); |
815 | kernel = g_malloc(kernel_size); | |
45a50b16 | 816 | fseek(f, 0, SEEK_SET); |
5a41ecc5 KS |
817 | if (fread(setup, 1, setup_size, f) != setup_size) { |
818 | fprintf(stderr, "fread() failed\n"); | |
819 | exit(1); | |
820 | } | |
821 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
822 | fprintf(stderr, "fread() failed\n"); | |
823 | exit(1); | |
824 | } | |
642a4f96 | 825 | fclose(f); |
45a50b16 | 826 | memcpy(setup, header, MIN(sizeof(header), setup_size)); |
57a46d05 AG |
827 | |
828 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
829 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
830 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
831 | ||
832 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
833 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
834 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
835 | ||
2e55e842 GN |
836 | option_rom[nb_option_roms].name = "linuxboot.bin"; |
837 | option_rom[nb_option_roms].bootindex = 0; | |
57a46d05 | 838 | nb_option_roms++; |
642a4f96 TS |
839 | } |
840 | ||
b41a2cd1 FB |
841 | #define NE2000_NB_MAX 6 |
842 | ||
675d6f82 BS |
843 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
844 | 0x280, 0x380 }; | |
845 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 846 | |
675d6f82 BS |
847 | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
848 | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
6508fe59 | 849 | |
48a18b3c | 850 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
851 | { |
852 | static int nb_ne2k = 0; | |
853 | ||
854 | if (nb_ne2k == NE2000_NB_MAX) | |
855 | return; | |
48a18b3c | 856 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 857 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
858 | nb_ne2k++; |
859 | } | |
860 | ||
92a16d7a | 861 | DeviceState *cpu_get_current_apic(void) |
0e26b7b8 BS |
862 | { |
863 | if (cpu_single_env) { | |
864 | return cpu_single_env->apic_state; | |
865 | } else { | |
866 | return NULL; | |
867 | } | |
868 | } | |
869 | ||
92a16d7a BS |
870 | static DeviceState *apic_init(void *env, uint8_t apic_id) |
871 | { | |
872 | DeviceState *dev; | |
92a16d7a BS |
873 | static int apic_mapped; |
874 | ||
3d4b2649 | 875 | if (kvm_irqchip_in_kernel()) { |
680c1c6f | 876 | dev = qdev_create(NULL, "kvm-apic"); |
9468e9c4 WL |
877 | } else if (xen_enabled()) { |
878 | dev = qdev_create(NULL, "xen-apic"); | |
680c1c6f JK |
879 | } else { |
880 | dev = qdev_create(NULL, "apic"); | |
881 | } | |
9468e9c4 | 882 | |
92a16d7a BS |
883 | qdev_prop_set_uint8(dev, "id", apic_id); |
884 | qdev_prop_set_ptr(dev, "cpu_env", env); | |
885 | qdev_init_nofail(dev); | |
92a16d7a BS |
886 | |
887 | /* XXX: mapping more APICs at the same memory location */ | |
888 | if (apic_mapped == 0) { | |
889 | /* NOTE: the APIC is directly connected to the CPU - it is not | |
890 | on the global memory bus. */ | |
891 | /* XXX: what if the base changes? */ | |
680c1c6f | 892 | sysbus_mmio_map(sysbus_from_qdev(dev), 0, MSI_ADDR_BASE); |
92a16d7a BS |
893 | apic_mapped = 1; |
894 | } | |
895 | ||
92a16d7a BS |
896 | return dev; |
897 | } | |
898 | ||
845773ab | 899 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 | 900 | { |
4a8fa5dc | 901 | CPUX86State *s = opaque; |
53b67b30 BS |
902 | |
903 | if (level) { | |
904 | cpu_interrupt(s, CPU_INTERRUPT_SMI); | |
905 | } | |
906 | } | |
907 | ||
608911ac | 908 | static X86CPU *pc_new_cpu(const char *cpu_model) |
3a31f36a | 909 | { |
608911ac | 910 | X86CPU *cpu; |
4a8fa5dc | 911 | CPUX86State *env; |
3a31f36a | 912 | |
608911ac AF |
913 | cpu = cpu_x86_init(cpu_model); |
914 | if (cpu == NULL) { | |
3a31f36a JK |
915 | fprintf(stderr, "Unable to find x86 CPU definition\n"); |
916 | exit(1); | |
917 | } | |
608911ac | 918 | env = &cpu->env; |
3a31f36a | 919 | if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { |
0e26b7b8 BS |
920 | env->apic_state = apic_init(env, env->cpuid_apic_id); |
921 | } | |
65dee380 | 922 | cpu_reset(CPU(cpu)); |
608911ac | 923 | return cpu; |
3a31f36a JK |
924 | } |
925 | ||
845773ab | 926 | void pc_cpus_init(const char *cpu_model) |
70166477 IY |
927 | { |
928 | int i; | |
929 | ||
930 | /* init CPUs */ | |
931 | if (cpu_model == NULL) { | |
932 | #ifdef TARGET_X86_64 | |
933 | cpu_model = "qemu64"; | |
934 | #else | |
935 | cpu_model = "qemu32"; | |
936 | #endif | |
937 | } | |
938 | ||
939 | for(i = 0; i < smp_cpus; i++) { | |
940 | pc_new_cpu(cpu_model); | |
941 | } | |
942 | } | |
943 | ||
459ae5ea | 944 | void *pc_memory_init(MemoryRegion *system_memory, |
4aa63af1 | 945 | const char *kernel_filename, |
845773ab IY |
946 | const char *kernel_cmdline, |
947 | const char *initrd_filename, | |
e0e7e67b | 948 | ram_addr_t below_4g_mem_size, |
ae0a5466 | 949 | ram_addr_t above_4g_mem_size, |
4463aee6 | 950 | MemoryRegion *rom_memory, |
ae0a5466 | 951 | MemoryRegion **ram_memory) |
80cabfad | 952 | { |
cbc5b5f3 JJ |
953 | int linux_boot, i; |
954 | MemoryRegion *ram, *option_rom_mr; | |
00cb2a99 | 955 | MemoryRegion *ram_below_4g, *ram_above_4g; |
81a204e4 | 956 | void *fw_cfg; |
d592d303 | 957 | |
80cabfad FB |
958 | linux_boot = (kernel_filename != NULL); |
959 | ||
00cb2a99 | 960 | /* Allocate RAM. We allocate it as a single memory region and use |
66a0a2cb | 961 | * aliases to address portions of it, mostly for backwards compatibility |
00cb2a99 AK |
962 | * with older qemus that used qemu_ram_alloc(). |
963 | */ | |
7267c094 | 964 | ram = g_malloc(sizeof(*ram)); |
c5705a77 | 965 | memory_region_init_ram(ram, "pc.ram", |
00cb2a99 | 966 | below_4g_mem_size + above_4g_mem_size); |
c5705a77 | 967 | vmstate_register_ram_global(ram); |
ae0a5466 | 968 | *ram_memory = ram; |
7267c094 | 969 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
00cb2a99 AK |
970 | memory_region_init_alias(ram_below_4g, "ram-below-4g", ram, |
971 | 0, below_4g_mem_size); | |
972 | memory_region_add_subregion(system_memory, 0, ram_below_4g); | |
bbe80adf | 973 | if (above_4g_mem_size > 0) { |
7267c094 | 974 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
00cb2a99 AK |
975 | memory_region_init_alias(ram_above_4g, "ram-above-4g", ram, |
976 | below_4g_mem_size, above_4g_mem_size); | |
977 | memory_region_add_subregion(system_memory, 0x100000000ULL, | |
978 | ram_above_4g); | |
bbe80adf | 979 | } |
82b36dc3 | 980 | |
cbc5b5f3 JJ |
981 | |
982 | /* Initialize PC system firmware */ | |
983 | pc_system_firmware_init(rom_memory); | |
00cb2a99 | 984 | |
7267c094 | 985 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
c5705a77 AK |
986 | memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE); |
987 | vmstate_register_ram_global(option_rom_mr); | |
4463aee6 | 988 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
989 | PC_ROM_MIN_VGA, |
990 | option_rom_mr, | |
991 | 1); | |
f753ff16 | 992 | |
bf483392 | 993 | fw_cfg = bochs_bios_init(); |
8832cb80 | 994 | rom_set_fw(fw_cfg); |
1d108d97 | 995 | |
f753ff16 | 996 | if (linux_boot) { |
81a204e4 | 997 | load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); |
f753ff16 PB |
998 | } |
999 | ||
1000 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 1001 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 1002 | } |
459ae5ea | 1003 | return fw_cfg; |
3d53f5c3 IY |
1004 | } |
1005 | ||
845773ab IY |
1006 | qemu_irq *pc_allocate_cpu_irq(void) |
1007 | { | |
1008 | return qemu_allocate_irqs(pic_irq_request, NULL, 1); | |
1009 | } | |
1010 | ||
48a18b3c | 1011 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 1012 | { |
ad6d45fa AL |
1013 | DeviceState *dev = NULL; |
1014 | ||
765d7908 IY |
1015 | if (cirrus_vga_enabled) { |
1016 | if (pci_bus) { | |
ad6d45fa | 1017 | dev = pci_cirrus_vga_init(pci_bus); |
765d7908 | 1018 | } else { |
3d402831 | 1019 | dev = &isa_create_simple(isa_bus, "isa-cirrus-vga")->qdev; |
765d7908 IY |
1020 | } |
1021 | } else if (vmsvga_enabled) { | |
7ba7e49e | 1022 | if (pci_bus) { |
ad6d45fa | 1023 | dev = pci_vmsvga_init(pci_bus); |
7ba7e49e | 1024 | } else { |
765d7908 | 1025 | fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__); |
7ba7e49e | 1026 | } |
a19cbfb3 GH |
1027 | #ifdef CONFIG_SPICE |
1028 | } else if (qxl_enabled) { | |
ad6d45fa AL |
1029 | if (pci_bus) { |
1030 | dev = &pci_create_simple(pci_bus, -1, "qxl-vga")->qdev; | |
1031 | } else { | |
a19cbfb3 | 1032 | fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__); |
ad6d45fa | 1033 | } |
a19cbfb3 | 1034 | #endif |
765d7908 IY |
1035 | } else if (std_vga_enabled) { |
1036 | if (pci_bus) { | |
ad6d45fa | 1037 | dev = pci_vga_init(pci_bus); |
765d7908 | 1038 | } else { |
48a18b3c | 1039 | dev = isa_vga_init(isa_bus); |
765d7908 IY |
1040 | } |
1041 | } | |
ad6d45fa AL |
1042 | |
1043 | return dev; | |
765d7908 IY |
1044 | } |
1045 | ||
4556bd8b BS |
1046 | static void cpu_request_exit(void *opaque, int irq, int level) |
1047 | { | |
4a8fa5dc | 1048 | CPUX86State *env = cpu_single_env; |
4556bd8b BS |
1049 | |
1050 | if (env && level) { | |
1051 | cpu_exit(env); | |
1052 | } | |
1053 | } | |
1054 | ||
48a18b3c | 1055 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, |
1611977c | 1056 | ISADevice **rtc_state, |
34d4260e | 1057 | ISADevice **floppy, |
1611977c | 1058 | bool no_vmport) |
ffe513da IY |
1059 | { |
1060 | int i; | |
1061 | DriveInfo *fd[MAX_FD]; | |
ce967e2f JK |
1062 | DeviceState *hpet = NULL; |
1063 | int pit_isa_irq = 0; | |
1064 | qemu_irq pit_alt_irq = NULL; | |
7d932dfd | 1065 | qemu_irq rtc_irq = NULL; |
956a3e6b | 1066 | qemu_irq *a20_line; |
c2d8d311 | 1067 | ISADevice *i8042, *port92, *vmmouse, *pit = NULL; |
4556bd8b | 1068 | qemu_irq *cpu_exit_irq; |
ffe513da IY |
1069 | |
1070 | register_ioport_write(0x80, 1, 1, ioport80_write, NULL); | |
1071 | ||
1072 | register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); | |
1073 | ||
5d17c0d2 JK |
1074 | /* |
1075 | * Check if an HPET shall be created. | |
1076 | * | |
1077 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1078 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1079 | */ | |
1080 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
ce967e2f | 1081 | hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL); |
822557eb | 1082 | |
dd703b99 | 1083 | if (hpet) { |
b881fbe9 JK |
1084 | for (i = 0; i < GSI_NUM_PINS; i++) { |
1085 | sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]); | |
dd703b99 | 1086 | } |
ce967e2f JK |
1087 | pit_isa_irq = -1; |
1088 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1089 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
822557eb | 1090 | } |
ffe513da | 1091 | } |
48a18b3c | 1092 | *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); |
7d932dfd JK |
1093 | |
1094 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1095 | ||
c2d8d311 SS |
1096 | if (!xen_enabled()) { |
1097 | if (kvm_irqchip_in_kernel()) { | |
1098 | pit = kvm_pit_init(isa_bus, 0x40); | |
1099 | } else { | |
1100 | pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); | |
1101 | } | |
1102 | if (hpet) { | |
1103 | /* connect PIT to output control line of the HPET */ | |
1104 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0)); | |
1105 | } | |
1106 | pcspk_init(isa_bus, pit); | |
ce967e2f | 1107 | } |
ffe513da IY |
1108 | |
1109 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
1110 | if (serial_hds[i]) { | |
48a18b3c | 1111 | serial_isa_init(isa_bus, i, serial_hds[i]); |
ffe513da IY |
1112 | } |
1113 | } | |
1114 | ||
1115 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
1116 | if (parallel_hds[i]) { | |
48a18b3c | 1117 | parallel_init(isa_bus, i, parallel_hds[i]); |
ffe513da IY |
1118 | } |
1119 | } | |
1120 | ||
4b78a802 | 1121 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); |
48a18b3c | 1122 | i8042 = isa_create_simple(isa_bus, "i8042"); |
4b78a802 | 1123 | i8042_setup_a20_line(i8042, &a20_line[0]); |
1611977c | 1124 | if (!no_vmport) { |
48a18b3c HP |
1125 | vmport_init(isa_bus); |
1126 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1611977c AP |
1127 | } else { |
1128 | vmmouse = NULL; | |
1129 | } | |
86d86414 BS |
1130 | if (vmmouse) { |
1131 | qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042); | |
43f20196 | 1132 | qdev_init_nofail(&vmmouse->qdev); |
86d86414 | 1133 | } |
48a18b3c | 1134 | port92 = isa_create_simple(isa_bus, "port92"); |
4b78a802 | 1135 | port92_init(port92, &a20_line[1]); |
956a3e6b | 1136 | |
4556bd8b BS |
1137 | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
1138 | DMA_init(0, cpu_exit_irq); | |
ffe513da IY |
1139 | |
1140 | for(i = 0; i < MAX_FD; i++) { | |
1141 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1142 | } | |
48a18b3c | 1143 | *floppy = fdctrl_init_isa(isa_bus, fd); |
ffe513da IY |
1144 | } |
1145 | ||
845773ab | 1146 | void pc_pci_device_init(PCIBus *pci_bus) |
e3a5cf42 IY |
1147 | { |
1148 | int max_bus; | |
1149 | int bus; | |
1150 | ||
1151 | max_bus = drive_get_max_bus(IF_SCSI); | |
1152 | for (bus = 0; bus <= max_bus; bus++) { | |
1153 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
1154 | } | |
1155 | } |