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Commit | Line | Data |
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69b91039 FB |
1 | /* |
2 | * QEMU PCI bus manager | |
3 | * | |
4 | * Copyright (c) 2004 Fabrice Bellard | |
5fafdf24 | 5 | * |
69b91039 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
c759b24f MT |
24 | #include "hw/hw.h" |
25 | #include "hw/pci/pci.h" | |
26 | #include "hw/pci/pci_bridge.h" | |
06aac7bd | 27 | #include "hw/pci/pci_bus.h" |
568f0690 | 28 | #include "hw/pci/pci_host.h" |
83c9089e | 29 | #include "monitor/monitor.h" |
1422e32d | 30 | #include "net/net.h" |
9c17d615 | 31 | #include "sysemu/sysemu.h" |
c759b24f | 32 | #include "hw/loader.h" |
1de7afc9 | 33 | #include "qemu/range.h" |
79627472 | 34 | #include "qmp-commands.h" |
c759b24f MT |
35 | #include "hw/pci/msi.h" |
36 | #include "hw/pci/msix.h" | |
022c62cb | 37 | #include "exec/address-spaces.h" |
69b91039 FB |
38 | |
39 | //#define DEBUG_PCI | |
d8d2e079 | 40 | #ifdef DEBUG_PCI |
2e49d64a | 41 | # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
d8d2e079 IY |
42 | #else |
43 | # define PCI_DPRINTF(format, ...) do { } while (0) | |
44 | #endif | |
69b91039 | 45 | |
10c4c98a | 46 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); |
4f43c1ff | 47 | static char *pcibus_get_dev_path(DeviceState *dev); |
5e0259e7 | 48 | static char *pcibus_get_fw_dev_path(DeviceState *dev); |
dcc20931 | 49 | static void pcibus_reset(BusState *qbus); |
5c397242 | 50 | static void pci_bus_finalize(Object *obj); |
10c4c98a | 51 | |
3cb75a7c PB |
52 | static Property pci_props[] = { |
53 | DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), | |
54 | DEFINE_PROP_STRING("romfile", PCIDevice, romfile), | |
55 | DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), | |
56 | DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, | |
57 | QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), | |
58 | DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, | |
59 | QEMU_PCI_CAP_SERR_BITNR, true), | |
60 | DEFINE_PROP_END_OF_LIST() | |
61 | }; | |
62 | ||
0d936928 AL |
63 | static void pci_bus_class_init(ObjectClass *klass, void *data) |
64 | { | |
65 | BusClass *k = BUS_CLASS(klass); | |
66 | ||
67 | k->print_dev = pcibus_dev_print; | |
68 | k->get_dev_path = pcibus_get_dev_path; | |
69 | k->get_fw_dev_path = pcibus_get_fw_dev_path; | |
70 | k->reset = pcibus_reset; | |
71 | } | |
72 | ||
73 | static const TypeInfo pci_bus_info = { | |
74 | .name = TYPE_PCI_BUS, | |
75 | .parent = TYPE_BUS, | |
76 | .instance_size = sizeof(PCIBus), | |
5c397242 | 77 | .instance_finalize = pci_bus_finalize, |
0d936928 | 78 | .class_init = pci_bus_class_init, |
30468f78 | 79 | }; |
69b91039 | 80 | |
3a861c46 AW |
81 | static const TypeInfo pcie_bus_info = { |
82 | .name = TYPE_PCIE_BUS, | |
83 | .parent = TYPE_PCI_BUS, | |
84 | }; | |
85 | ||
d662210a | 86 | static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); |
1941d19c | 87 | static void pci_update_mappings(PCIDevice *d); |
d98f08f5 | 88 | static void pci_irq_handler(void *opaque, int irq_num, int level); |
ab85ceb1 | 89 | static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom); |
230741dc | 90 | static void pci_del_option_rom(PCIDevice *pdev); |
1941d19c | 91 | |
d350d97d AL |
92 | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; |
93 | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; | |
e822a52a | 94 | |
7588e2b0 | 95 | static QLIST_HEAD(, PCIHostState) pci_host_bridges; |
30468f78 | 96 | |
2d1e9f96 JQ |
97 | static const VMStateDescription vmstate_pcibus = { |
98 | .name = "PCIBUS", | |
99 | .version_id = 1, | |
100 | .minimum_version_id = 1, | |
101 | .minimum_version_id_old = 1, | |
102 | .fields = (VMStateField []) { | |
103 | VMSTATE_INT32_EQUAL(nirq, PCIBus), | |
c7bde572 | 104 | VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t), |
2d1e9f96 | 105 | VMSTATE_END_OF_LIST() |
52fc1d83 | 106 | } |
2d1e9f96 | 107 | }; |
b3b11697 | 108 | static int pci_bar(PCIDevice *d, int reg) |
5330de09 | 109 | { |
b3b11697 IY |
110 | uint8_t type; |
111 | ||
112 | if (reg != PCI_ROM_SLOT) | |
113 | return PCI_BASE_ADDRESS_0 + reg * 4; | |
114 | ||
115 | type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
116 | return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; | |
5330de09 MT |
117 | } |
118 | ||
d036bb21 MT |
119 | static inline int pci_irq_state(PCIDevice *d, int irq_num) |
120 | { | |
121 | return (d->irq_state >> irq_num) & 0x1; | |
122 | } | |
123 | ||
124 | static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) | |
125 | { | |
126 | d->irq_state &= ~(0x1 << irq_num); | |
127 | d->irq_state |= level << irq_num; | |
128 | } | |
129 | ||
130 | static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) | |
131 | { | |
132 | PCIBus *bus; | |
133 | for (;;) { | |
134 | bus = pci_dev->bus; | |
135 | irq_num = bus->map_irq(pci_dev, irq_num); | |
136 | if (bus->set_irq) | |
137 | break; | |
138 | pci_dev = bus->parent_dev; | |
139 | } | |
140 | bus->irq_count[irq_num] += change; | |
141 | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); | |
142 | } | |
143 | ||
9ddf8437 IY |
144 | int pci_bus_get_irq_level(PCIBus *bus, int irq_num) |
145 | { | |
146 | assert(irq_num >= 0); | |
147 | assert(irq_num < bus->nirq); | |
148 | return !!bus->irq_count[irq_num]; | |
149 | } | |
150 | ||
f9bf77dd MT |
151 | /* Update interrupt status bit in config space on interrupt |
152 | * state change. */ | |
153 | static void pci_update_irq_status(PCIDevice *dev) | |
154 | { | |
155 | if (dev->irq_state) { | |
156 | dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; | |
157 | } else { | |
158 | dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
159 | } | |
160 | } | |
161 | ||
4c92325b IY |
162 | void pci_device_deassert_intx(PCIDevice *dev) |
163 | { | |
164 | int i; | |
165 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
d98f08f5 | 166 | pci_irq_handler(dev, i, 0); |
4c92325b IY |
167 | } |
168 | } | |
169 | ||
dcc20931 | 170 | static void pci_do_device_reset(PCIDevice *dev) |
5330de09 | 171 | { |
c0b1905b | 172 | int r; |
6fc4925b | 173 | |
d036bb21 | 174 | dev->irq_state = 0; |
f9bf77dd | 175 | pci_update_irq_status(dev); |
4c92325b | 176 | pci_device_deassert_intx(dev); |
ebabb67a | 177 | /* Clear all writable bits */ |
99443c21 | 178 | pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, |
f9aebe2e MT |
179 | pci_get_word(dev->wmask + PCI_COMMAND) | |
180 | pci_get_word(dev->w1cmask + PCI_COMMAND)); | |
89d437df IY |
181 | pci_word_test_and_clear_mask(dev->config + PCI_STATUS, |
182 | pci_get_word(dev->wmask + PCI_STATUS) | | |
183 | pci_get_word(dev->w1cmask + PCI_STATUS)); | |
c0b1905b MT |
184 | dev->config[PCI_CACHE_LINE_SIZE] = 0x0; |
185 | dev->config[PCI_INTERRUPT_LINE] = 0x0; | |
186 | for (r = 0; r < PCI_NUM_REGIONS; ++r) { | |
71ebd6dc IY |
187 | PCIIORegion *region = &dev->io_regions[r]; |
188 | if (!region->size) { | |
c0b1905b MT |
189 | continue; |
190 | } | |
71ebd6dc IY |
191 | |
192 | if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && | |
193 | region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
194 | pci_set_quad(dev->config + pci_bar(dev, r), region->type); | |
195 | } else { | |
196 | pci_set_long(dev->config + pci_bar(dev, r), region->type); | |
197 | } | |
c0b1905b MT |
198 | } |
199 | pci_update_mappings(dev); | |
cbd2d434 JK |
200 | |
201 | msi_reset(dev); | |
202 | msix_reset(dev); | |
5330de09 MT |
203 | } |
204 | ||
dcc20931 PB |
205 | /* |
206 | * This function is called on #RST and FLR. | |
207 | * FLR if PCI_EXP_DEVCTL_BCR_FLR is set | |
208 | */ | |
209 | void pci_device_reset(PCIDevice *dev) | |
210 | { | |
211 | qdev_reset_all(&dev->qdev); | |
212 | pci_do_device_reset(dev); | |
213 | } | |
214 | ||
9bb33586 IY |
215 | /* |
216 | * Trigger pci bus reset under a given bus. | |
dcc20931 PB |
217 | * Called via qbus_reset_all on RST# assert, after the devices |
218 | * have been reset qdev_reset_all-ed already. | |
9bb33586 | 219 | */ |
dcc20931 | 220 | static void pcibus_reset(BusState *qbus) |
6eaa6847 | 221 | { |
81e3e75b | 222 | PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); |
6eaa6847 GN |
223 | int i; |
224 | ||
5330de09 MT |
225 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
226 | if (bus->devices[i]) { | |
dcc20931 | 227 | pci_do_device_reset(bus->devices[i]); |
5330de09 | 228 | } |
6eaa6847 | 229 | } |
9bb33586 | 230 | |
9bdbbfc3 PB |
231 | for (i = 0; i < bus->nirq; i++) { |
232 | assert(bus->irq_count[i] == 0); | |
233 | } | |
9bb33586 IY |
234 | } |
235 | ||
7588e2b0 | 236 | static void pci_host_bus_register(PCIBus *bus, DeviceState *parent) |
e822a52a | 237 | { |
7588e2b0 DG |
238 | PCIHostState *host_bridge = PCI_HOST_BRIDGE(parent); |
239 | ||
240 | QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); | |
e822a52a IY |
241 | } |
242 | ||
1ef7a2a2 | 243 | PCIBus *pci_find_primary_bus(void) |
e822a52a | 244 | { |
9bc47305 | 245 | PCIBus *primary_bus = NULL; |
7588e2b0 | 246 | PCIHostState *host; |
e822a52a | 247 | |
7588e2b0 | 248 | QLIST_FOREACH(host, &pci_host_bridges, next) { |
9bc47305 DG |
249 | if (primary_bus) { |
250 | /* We have multiple root buses, refuse to select a primary */ | |
251 | return NULL; | |
e822a52a | 252 | } |
9bc47305 | 253 | primary_bus = host->bus; |
e822a52a IY |
254 | } |
255 | ||
9bc47305 | 256 | return primary_bus; |
e822a52a IY |
257 | } |
258 | ||
c473d18d | 259 | PCIBus *pci_device_root_bus(const PCIDevice *d) |
e075e788 | 260 | { |
c473d18d | 261 | PCIBus *bus = d->bus; |
e075e788 | 262 | |
e075e788 IY |
263 | while ((d = bus->parent_dev) != NULL) { |
264 | bus = d->bus; | |
265 | } | |
266 | ||
c473d18d DG |
267 | return bus; |
268 | } | |
269 | ||
568f0690 | 270 | const char *pci_root_bus_path(PCIDevice *dev) |
c473d18d | 271 | { |
568f0690 DG |
272 | PCIBus *rootbus = pci_device_root_bus(dev); |
273 | PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); | |
274 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); | |
c473d18d | 275 | |
568f0690 DG |
276 | assert(!rootbus->parent_dev); |
277 | assert(host_bridge->bus == rootbus); | |
278 | ||
279 | if (hc->root_bus_path) { | |
280 | return (*hc->root_bus_path)(host_bridge, rootbus); | |
e075e788 IY |
281 | } |
282 | ||
568f0690 | 283 | return rootbus->qbus.name; |
e075e788 IY |
284 | } |
285 | ||
4fec6404 | 286 | static void pci_bus_init(PCIBus *bus, DeviceState *parent, |
1e39101c | 287 | const char *name, |
aee97b84 AK |
288 | MemoryRegion *address_space_mem, |
289 | MemoryRegion *address_space_io, | |
1e39101c | 290 | uint8_t devfn_min) |
30468f78 | 291 | { |
6fa84913 | 292 | assert(PCI_FUNC(devfn_min) == 0); |
502a5395 | 293 | bus->devfn_min = devfn_min; |
5968eca3 AK |
294 | bus->address_space_mem = address_space_mem; |
295 | bus->address_space_io = address_space_io; | |
e822a52a IY |
296 | |
297 | /* host bridge */ | |
298 | QLIST_INIT(&bus->child); | |
2b8cc89a | 299 | |
7588e2b0 | 300 | pci_host_bus_register(bus, parent); |
e822a52a | 301 | |
0be71e32 | 302 | vmstate_register(NULL, -1, &vmstate_pcibus, bus); |
21eea4b3 GH |
303 | } |
304 | ||
8c0bf9e2 AW |
305 | bool pci_bus_is_express(PCIBus *bus) |
306 | { | |
307 | return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); | |
308 | } | |
309 | ||
0889464a AW |
310 | bool pci_bus_is_root(PCIBus *bus) |
311 | { | |
312 | return !bus->parent_dev; | |
313 | } | |
314 | ||
dd301ca6 | 315 | void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, |
4fec6404 PB |
316 | const char *name, |
317 | MemoryRegion *address_space_mem, | |
318 | MemoryRegion *address_space_io, | |
60a0e443 | 319 | uint8_t devfn_min, const char *typename) |
4fec6404 | 320 | { |
fb17dfe0 | 321 | qbus_create_inplace(bus, bus_size, typename, parent, name); |
4fec6404 PB |
322 | pci_bus_init(bus, parent, name, address_space_mem, |
323 | address_space_io, devfn_min); | |
324 | } | |
325 | ||
1e39101c | 326 | PCIBus *pci_bus_new(DeviceState *parent, const char *name, |
aee97b84 AK |
327 | MemoryRegion *address_space_mem, |
328 | MemoryRegion *address_space_io, | |
60a0e443 | 329 | uint8_t devfn_min, const char *typename) |
21eea4b3 GH |
330 | { |
331 | PCIBus *bus; | |
332 | ||
60a0e443 | 333 | bus = PCI_BUS(qbus_create(typename, parent, name)); |
4fec6404 PB |
334 | pci_bus_init(bus, parent, name, address_space_mem, |
335 | address_space_io, devfn_min); | |
21eea4b3 GH |
336 | return bus; |
337 | } | |
338 | ||
339 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
340 | void *irq_opaque, int nirq) | |
341 | { | |
342 | bus->set_irq = set_irq; | |
343 | bus->map_irq = map_irq; | |
344 | bus->irq_opaque = irq_opaque; | |
345 | bus->nirq = nirq; | |
7267c094 | 346 | bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); |
21eea4b3 GH |
347 | } |
348 | ||
87c30546 | 349 | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev) |
ee995ffb GH |
350 | { |
351 | bus->qbus.allow_hotplug = 1; | |
352 | bus->hotplug = hotplug; | |
87c30546 | 353 | bus->hotplug_qdev = qdev; |
ee995ffb GH |
354 | } |
355 | ||
21eea4b3 GH |
356 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
357 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
1e39101c | 358 | void *irq_opaque, |
aee97b84 AK |
359 | MemoryRegion *address_space_mem, |
360 | MemoryRegion *address_space_io, | |
60a0e443 | 361 | uint8_t devfn_min, int nirq, const char *typename) |
21eea4b3 GH |
362 | { |
363 | PCIBus *bus; | |
364 | ||
aee97b84 | 365 | bus = pci_bus_new(parent, name, address_space_mem, |
60a0e443 | 366 | address_space_io, devfn_min, typename); |
21eea4b3 | 367 | pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); |
30468f78 FB |
368 | return bus; |
369 | } | |
69b91039 | 370 | |
502a5395 PB |
371 | int pci_bus_num(PCIBus *s) |
372 | { | |
0889464a | 373 | if (pci_bus_is_root(s)) |
e94ff650 IY |
374 | return 0; /* pci host bridge */ |
375 | return s->parent_dev->config[PCI_SECONDARY_BUS]; | |
502a5395 PB |
376 | } |
377 | ||
5c397242 BD |
378 | static void pci_bus_finalize(Object *obj) |
379 | { | |
380 | PCIBus *bus = PCI_BUS(obj); | |
381 | vmstate_unregister(NULL, &vmstate_pcibus, bus); | |
382 | } | |
383 | ||
73534f2f | 384 | static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) |
30ca2aab | 385 | { |
73534f2f | 386 | PCIDevice *s = container_of(pv, PCIDevice, config); |
e78e9ae4 | 387 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); |
a9f49946 | 388 | uint8_t *config; |
52fc1d83 AZ |
389 | int i; |
390 | ||
a9f49946 | 391 | assert(size == pci_config_size(s)); |
7267c094 | 392 | config = g_malloc(size); |
a9f49946 IY |
393 | |
394 | qemu_get_buffer(f, config, size); | |
395 | for (i = 0; i < size; ++i) { | |
f9aebe2e MT |
396 | if ((config[i] ^ s->config[i]) & |
397 | s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { | |
7267c094 | 398 | g_free(config); |
bd4b65ee | 399 | return -EINVAL; |
a9f49946 IY |
400 | } |
401 | } | |
402 | memcpy(s->config, config, size); | |
bd4b65ee | 403 | |
1941d19c | 404 | pci_update_mappings(s); |
e78e9ae4 | 405 | if (pc->is_bridge) { |
f055e96b | 406 | PCIBridge *b = PCI_BRIDGE(s); |
e78e9ae4 DK |
407 | pci_bridge_update_mappings(b); |
408 | } | |
52fc1d83 | 409 | |
4ea375bf GH |
410 | memory_region_set_enabled(&s->bus_master_enable_region, |
411 | pci_get_word(s->config + PCI_COMMAND) | |
412 | & PCI_COMMAND_MASTER); | |
413 | ||
7267c094 | 414 | g_free(config); |
30ca2aab FB |
415 | return 0; |
416 | } | |
417 | ||
73534f2f | 418 | /* just put buffer */ |
84e2e3eb | 419 | static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) |
73534f2f | 420 | { |
dbe73d7f | 421 | const uint8_t **v = pv; |
a9f49946 | 422 | assert(size == pci_config_size(container_of(pv, PCIDevice, config))); |
dbe73d7f | 423 | qemu_put_buffer(f, *v, size); |
73534f2f JQ |
424 | } |
425 | ||
426 | static VMStateInfo vmstate_info_pci_config = { | |
427 | .name = "pci config", | |
428 | .get = get_pci_config_device, | |
429 | .put = put_pci_config_device, | |
430 | }; | |
431 | ||
d036bb21 MT |
432 | static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) |
433 | { | |
c3f8f611 | 434 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
435 | uint32_t irq_state[PCI_NUM_PINS]; |
436 | int i; | |
437 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
438 | irq_state[i] = qemu_get_be32(f); | |
439 | if (irq_state[i] != 0x1 && irq_state[i] != 0) { | |
440 | fprintf(stderr, "irq state %d: must be 0 or 1.\n", | |
441 | irq_state[i]); | |
442 | return -EINVAL; | |
443 | } | |
444 | } | |
445 | ||
446 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
447 | pci_set_irq_state(s, i, irq_state[i]); | |
448 | } | |
449 | ||
450 | return 0; | |
451 | } | |
452 | ||
453 | static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) | |
454 | { | |
455 | int i; | |
c3f8f611 | 456 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
457 | |
458 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
459 | qemu_put_be32(f, pci_irq_state(s, i)); | |
460 | } | |
461 | } | |
462 | ||
463 | static VMStateInfo vmstate_info_pci_irq_state = { | |
464 | .name = "pci irq state", | |
465 | .get = get_pci_irq_state, | |
466 | .put = put_pci_irq_state, | |
467 | }; | |
468 | ||
73534f2f JQ |
469 | const VMStateDescription vmstate_pci_device = { |
470 | .name = "PCIDevice", | |
471 | .version_id = 2, | |
472 | .minimum_version_id = 1, | |
473 | .minimum_version_id_old = 1, | |
474 | .fields = (VMStateField []) { | |
475 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
a9f49946 IY |
476 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, |
477 | vmstate_info_pci_config, | |
478 | PCI_CONFIG_SPACE_SIZE), | |
d036bb21 MT |
479 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
480 | vmstate_info_pci_irq_state, | |
481 | PCI_NUM_PINS * sizeof(int32_t)), | |
a9f49946 IY |
482 | VMSTATE_END_OF_LIST() |
483 | } | |
484 | }; | |
485 | ||
486 | const VMStateDescription vmstate_pcie_device = { | |
1de53459 | 487 | .name = "PCIEDevice", |
a9f49946 IY |
488 | .version_id = 2, |
489 | .minimum_version_id = 1, | |
490 | .minimum_version_id_old = 1, | |
491 | .fields = (VMStateField []) { | |
492 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
493 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, | |
494 | vmstate_info_pci_config, | |
495 | PCIE_CONFIG_SPACE_SIZE), | |
d036bb21 MT |
496 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
497 | vmstate_info_pci_irq_state, | |
498 | PCI_NUM_PINS * sizeof(int32_t)), | |
73534f2f JQ |
499 | VMSTATE_END_OF_LIST() |
500 | } | |
501 | }; | |
502 | ||
a9f49946 IY |
503 | static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) |
504 | { | |
505 | return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; | |
506 | } | |
507 | ||
73534f2f JQ |
508 | void pci_device_save(PCIDevice *s, QEMUFile *f) |
509 | { | |
f9bf77dd MT |
510 | /* Clear interrupt status bit: it is implicit |
511 | * in irq_state which we are saving. | |
512 | * This makes us compatible with old devices | |
513 | * which never set or clear this bit. */ | |
514 | s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
a9f49946 | 515 | vmstate_save_state(f, pci_get_vmstate(s), s); |
f9bf77dd MT |
516 | /* Restore the interrupt status bit. */ |
517 | pci_update_irq_status(s); | |
73534f2f JQ |
518 | } |
519 | ||
520 | int pci_device_load(PCIDevice *s, QEMUFile *f) | |
521 | { | |
f9bf77dd MT |
522 | int ret; |
523 | ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); | |
524 | /* Restore the interrupt status bit. */ | |
525 | pci_update_irq_status(s); | |
526 | return ret; | |
73534f2f JQ |
527 | } |
528 | ||
5e434f4e | 529 | static void pci_set_default_subsystem_id(PCIDevice *pci_dev) |
d350d97d | 530 | { |
5e434f4e IY |
531 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
532 | pci_default_sub_vendor_id); | |
533 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, | |
534 | pci_default_sub_device_id); | |
d350d97d AL |
535 | } |
536 | ||
880345c4 | 537 | /* |
43c945f1 IY |
538 | * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL |
539 | * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error | |
880345c4 | 540 | */ |
6ac363b5 | 541 | int pci_parse_devaddr(const char *addr, int *domp, int *busp, |
43c945f1 | 542 | unsigned int *slotp, unsigned int *funcp) |
880345c4 AL |
543 | { |
544 | const char *p; | |
545 | char *e; | |
546 | unsigned long val; | |
547 | unsigned long dom = 0, bus = 0; | |
43c945f1 IY |
548 | unsigned int slot = 0; |
549 | unsigned int func = 0; | |
880345c4 AL |
550 | |
551 | p = addr; | |
552 | val = strtoul(p, &e, 16); | |
553 | if (e == p) | |
554 | return -1; | |
555 | if (*e == ':') { | |
556 | bus = val; | |
557 | p = e + 1; | |
558 | val = strtoul(p, &e, 16); | |
559 | if (e == p) | |
560 | return -1; | |
561 | if (*e == ':') { | |
562 | dom = bus; | |
563 | bus = val; | |
564 | p = e + 1; | |
565 | val = strtoul(p, &e, 16); | |
566 | if (e == p) | |
567 | return -1; | |
568 | } | |
569 | } | |
570 | ||
880345c4 AL |
571 | slot = val; |
572 | ||
43c945f1 IY |
573 | if (funcp != NULL) { |
574 | if (*e != '.') | |
575 | return -1; | |
576 | ||
577 | p = e + 1; | |
578 | val = strtoul(p, &e, 16); | |
579 | if (e == p) | |
580 | return -1; | |
581 | ||
582 | func = val; | |
583 | } | |
584 | ||
585 | /* if funcp == NULL func is 0 */ | |
586 | if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) | |
587 | return -1; | |
588 | ||
880345c4 AL |
589 | if (*e) |
590 | return -1; | |
591 | ||
880345c4 AL |
592 | *domp = dom; |
593 | *busp = bus; | |
594 | *slotp = slot; | |
43c945f1 IY |
595 | if (funcp != NULL) |
596 | *funcp = func; | |
880345c4 AL |
597 | return 0; |
598 | } | |
599 | ||
85c6e4fa | 600 | PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr) |
5607c388 MA |
601 | { |
602 | int dom, bus; | |
603 | unsigned slot; | |
604 | ||
85c6e4fa DG |
605 | assert(!root->parent_dev); |
606 | ||
1ef7a2a2 DG |
607 | if (!root) { |
608 | fprintf(stderr, "No primary PCI bus\n"); | |
609 | return NULL; | |
610 | } | |
611 | ||
5607c388 MA |
612 | if (!devaddr) { |
613 | *devfnp = -1; | |
1ef7a2a2 | 614 | return pci_find_bus_nr(root, 0); |
5607c388 MA |
615 | } |
616 | ||
43c945f1 | 617 | if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { |
5607c388 MA |
618 | return NULL; |
619 | } | |
620 | ||
1ef7a2a2 DG |
621 | if (dom != 0) { |
622 | fprintf(stderr, "No support for non-zero PCI domains\n"); | |
623 | return NULL; | |
624 | } | |
625 | ||
6ff534b6 | 626 | *devfnp = PCI_DEVFN(slot, 0); |
1ef7a2a2 | 627 | return pci_find_bus_nr(root, bus); |
5607c388 MA |
628 | } |
629 | ||
bd4b65ee MT |
630 | static void pci_init_cmask(PCIDevice *dev) |
631 | { | |
632 | pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); | |
633 | pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); | |
634 | dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; | |
635 | dev->cmask[PCI_REVISION_ID] = 0xff; | |
636 | dev->cmask[PCI_CLASS_PROG] = 0xff; | |
637 | pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); | |
638 | dev->cmask[PCI_HEADER_TYPE] = 0xff; | |
639 | dev->cmask[PCI_CAPABILITY_LIST] = 0xff; | |
640 | } | |
641 | ||
b7ee1603 MT |
642 | static void pci_init_wmask(PCIDevice *dev) |
643 | { | |
a9f49946 IY |
644 | int config_size = pci_config_size(dev); |
645 | ||
b7ee1603 MT |
646 | dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; |
647 | dev->wmask[PCI_INTERRUPT_LINE] = 0xff; | |
67a51b48 | 648 | pci_set_word(dev->wmask + PCI_COMMAND, |
a7b15a5c MT |
649 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |
650 | PCI_COMMAND_INTX_DISABLE); | |
b1aeb926 IY |
651 | if (dev->cap_present & QEMU_PCI_CAP_SERR) { |
652 | pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); | |
653 | } | |
3e21ffc9 IY |
654 | |
655 | memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, | |
656 | config_size - PCI_CONFIG_HEADER_SIZE); | |
b7ee1603 MT |
657 | } |
658 | ||
89d437df IY |
659 | static void pci_init_w1cmask(PCIDevice *dev) |
660 | { | |
661 | /* | |
f6bdfcc9 | 662 | * Note: It's okay to set w1cmask even for readonly bits as |
89d437df IY |
663 | * long as their value is hardwired to 0. |
664 | */ | |
665 | pci_set_word(dev->w1cmask + PCI_STATUS, | |
666 | PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | | |
667 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | | |
668 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); | |
669 | } | |
670 | ||
d5f27e88 | 671 | static void pci_init_mask_bridge(PCIDevice *d) |
fb231628 IY |
672 | { |
673 | /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and | |
674 | PCI_SEC_LETENCY_TIMER */ | |
675 | memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); | |
676 | ||
677 | /* base and limit */ | |
678 | d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; | |
679 | d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; | |
680 | pci_set_word(d->wmask + PCI_MEMORY_BASE, | |
681 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
682 | pci_set_word(d->wmask + PCI_MEMORY_LIMIT, | |
683 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
684 | pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, | |
685 | PCI_PREF_RANGE_MASK & 0xffff); | |
686 | pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, | |
687 | PCI_PREF_RANGE_MASK & 0xffff); | |
688 | ||
689 | /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ | |
690 | memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); | |
691 | ||
d5f27e88 | 692 | /* Supported memory and i/o types */ |
68917102 MT |
693 | d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; |
694 | d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; | |
d5f27e88 MT |
695 | pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, |
696 | PCI_PREF_RANGE_TYPE_64); | |
697 | pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, | |
698 | PCI_PREF_RANGE_TYPE_64); | |
699 | ||
45eb768c MT |
700 | /* |
701 | * TODO: Bridges default to 10-bit VGA decoding but we currently only | |
702 | * implement 16-bit decoding (no alias support). | |
703 | */ | |
f6bdfcc9 MT |
704 | pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, |
705 | PCI_BRIDGE_CTL_PARITY | | |
706 | PCI_BRIDGE_CTL_SERR | | |
707 | PCI_BRIDGE_CTL_ISA | | |
708 | PCI_BRIDGE_CTL_VGA | | |
709 | PCI_BRIDGE_CTL_VGA_16BIT | | |
710 | PCI_BRIDGE_CTL_MASTER_ABORT | | |
711 | PCI_BRIDGE_CTL_BUS_RESET | | |
712 | PCI_BRIDGE_CTL_FAST_BACK | | |
713 | PCI_BRIDGE_CTL_DISCARD | | |
714 | PCI_BRIDGE_CTL_SEC_DISCARD | | |
f6bdfcc9 MT |
715 | PCI_BRIDGE_CTL_DISCARD_SERR); |
716 | /* Below does not do anything as we never set this bit, put here for | |
717 | * completeness. */ | |
718 | pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, | |
719 | PCI_BRIDGE_CTL_DISCARD_STATUS); | |
d5f27e88 | 720 | d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; |
15ab7a75 | 721 | d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; |
d5f27e88 MT |
722 | pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, |
723 | PCI_PREF_RANGE_TYPE_MASK); | |
15ab7a75 MT |
724 | pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, |
725 | PCI_PREF_RANGE_TYPE_MASK); | |
fb231628 IY |
726 | } |
727 | ||
6eab3de1 IY |
728 | static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) |
729 | { | |
730 | uint8_t slot = PCI_SLOT(dev->devfn); | |
731 | uint8_t func; | |
732 | ||
733 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
734 | dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; | |
735 | } | |
736 | ||
737 | /* | |
b0cd712c | 738 | * multifunction bit is interpreted in two ways as follows. |
6eab3de1 IY |
739 | * - all functions must set the bit to 1. |
740 | * Example: Intel X53 | |
741 | * - function 0 must set the bit, but the rest function (> 0) | |
742 | * is allowed to leave the bit to 0. | |
743 | * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, | |
744 | * | |
745 | * So OS (at least Linux) checks the bit of only function 0, | |
746 | * and doesn't see the bit of function > 0. | |
747 | * | |
748 | * The below check allows both interpretation. | |
749 | */ | |
750 | if (PCI_FUNC(dev->devfn)) { | |
751 | PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; | |
752 | if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { | |
753 | /* function 0 should set multifunction bit */ | |
754 | error_report("PCI: single function device can't be populated " | |
755 | "in function %x.%x", slot, PCI_FUNC(dev->devfn)); | |
756 | return -1; | |
757 | } | |
758 | return 0; | |
759 | } | |
760 | ||
761 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
762 | return 0; | |
763 | } | |
764 | /* function 0 indicates single function, so function > 0 must be NULL */ | |
765 | for (func = 1; func < PCI_FUNC_MAX; ++func) { | |
766 | if (bus->devices[PCI_DEVFN(slot, func)]) { | |
767 | error_report("PCI: %x.0 indicates single function, " | |
768 | "but %x.%x is already populated.", | |
769 | slot, slot, func); | |
770 | return -1; | |
771 | } | |
772 | } | |
773 | return 0; | |
774 | } | |
775 | ||
a9f49946 IY |
776 | static void pci_config_alloc(PCIDevice *pci_dev) |
777 | { | |
778 | int config_size = pci_config_size(pci_dev); | |
779 | ||
7267c094 AL |
780 | pci_dev->config = g_malloc0(config_size); |
781 | pci_dev->cmask = g_malloc0(config_size); | |
782 | pci_dev->wmask = g_malloc0(config_size); | |
783 | pci_dev->w1cmask = g_malloc0(config_size); | |
784 | pci_dev->used = g_malloc0(config_size); | |
a9f49946 IY |
785 | } |
786 | ||
787 | static void pci_config_free(PCIDevice *pci_dev) | |
788 | { | |
7267c094 AL |
789 | g_free(pci_dev->config); |
790 | g_free(pci_dev->cmask); | |
791 | g_free(pci_dev->wmask); | |
792 | g_free(pci_dev->w1cmask); | |
793 | g_free(pci_dev->used); | |
a9f49946 IY |
794 | } |
795 | ||
69b91039 | 796 | /* -1 for devfn means auto assign */ |
6b1b92d3 | 797 | static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, |
40021f08 | 798 | const char *name, int devfn) |
69b91039 | 799 | { |
40021f08 AL |
800 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
801 | PCIConfigReadFunc *config_read = pc->config_read; | |
802 | PCIConfigWriteFunc *config_write = pc->config_write; | |
e00387d5 | 803 | AddressSpace *dma_as; |
113f89df | 804 | |
69b91039 | 805 | if (devfn < 0) { |
b47b0706 | 806 | for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); |
6fa84913 | 807 | devfn += PCI_FUNC_MAX) { |
30468f78 | 808 | if (!bus->devices[devfn]) |
69b91039 FB |
809 | goto found; |
810 | } | |
3709c1b7 | 811 | error_report("PCI: no slot/function available for %s, all in use", name); |
09e3acc6 | 812 | return NULL; |
69b91039 | 813 | found: ; |
07b7d053 | 814 | } else if (bus->devices[devfn]) { |
3709c1b7 DB |
815 | error_report("PCI: slot %d function %d not available for %s, in use by %s", |
816 | PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name); | |
09e3acc6 | 817 | return NULL; |
69b91039 | 818 | } |
e00387d5 | 819 | |
30468f78 | 820 | pci_dev->bus = bus; |
9eda7d37 | 821 | dma_as = pci_device_iommu_address_space(pci_dev); |
24addbc7 | 822 | |
40c5dce9 PB |
823 | memory_region_init_alias(&pci_dev->bus_master_enable_region, |
824 | OBJECT(pci_dev), "bus master", | |
e00387d5 AK |
825 | dma_as->root, 0, memory_region_size(dma_as->root)); |
826 | memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); | |
7dca8043 AK |
827 | address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region, |
828 | name); | |
e00387d5 | 829 | |
69b91039 FB |
830 | pci_dev->devfn = devfn; |
831 | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); | |
d036bb21 | 832 | pci_dev->irq_state = 0; |
a9f49946 | 833 | pci_config_alloc(pci_dev); |
fb231628 | 834 | |
40021f08 AL |
835 | pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); |
836 | pci_config_set_device_id(pci_dev->config, pc->device_id); | |
837 | pci_config_set_revision(pci_dev->config, pc->revision); | |
838 | pci_config_set_class(pci_dev->config, pc->class_id); | |
113f89df | 839 | |
40021f08 AL |
840 | if (!pc->is_bridge) { |
841 | if (pc->subsystem_vendor_id || pc->subsystem_id) { | |
113f89df | 842 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
40021f08 | 843 | pc->subsystem_vendor_id); |
113f89df | 844 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, |
40021f08 | 845 | pc->subsystem_id); |
113f89df IY |
846 | } else { |
847 | pci_set_default_subsystem_id(pci_dev); | |
848 | } | |
849 | } else { | |
850 | /* subsystem_vendor_id/subsystem_id are only for header type 0 */ | |
40021f08 AL |
851 | assert(!pc->subsystem_vendor_id); |
852 | assert(!pc->subsystem_id); | |
fb231628 | 853 | } |
bd4b65ee | 854 | pci_init_cmask(pci_dev); |
b7ee1603 | 855 | pci_init_wmask(pci_dev); |
89d437df | 856 | pci_init_w1cmask(pci_dev); |
40021f08 | 857 | if (pc->is_bridge) { |
d5f27e88 | 858 | pci_init_mask_bridge(pci_dev); |
fb231628 | 859 | } |
6eab3de1 IY |
860 | if (pci_init_multifunction(bus, pci_dev)) { |
861 | pci_config_free(pci_dev); | |
862 | return NULL; | |
863 | } | |
0ac32c83 FB |
864 | |
865 | if (!config_read) | |
866 | config_read = pci_default_read_config; | |
867 | if (!config_write) | |
868 | config_write = pci_default_write_config; | |
69b91039 FB |
869 | pci_dev->config_read = config_read; |
870 | pci_dev->config_write = config_write; | |
30468f78 | 871 | bus->devices[devfn] = pci_dev; |
f16c4abf | 872 | pci_dev->version_id = 2; /* Current pci device vmstate version */ |
69b91039 FB |
873 | return pci_dev; |
874 | } | |
875 | ||
925fe64a AW |
876 | static void do_pci_unregister_device(PCIDevice *pci_dev) |
877 | { | |
925fe64a AW |
878 | pci_dev->bus->devices[pci_dev->devfn] = NULL; |
879 | pci_config_free(pci_dev); | |
817dcc53 | 880 | |
e00387d5 AK |
881 | address_space_destroy(&pci_dev->bus_master_as); |
882 | memory_region_destroy(&pci_dev->bus_master_enable_region); | |
925fe64a AW |
883 | } |
884 | ||
5851e08c AL |
885 | static void pci_unregister_io_regions(PCIDevice *pci_dev) |
886 | { | |
887 | PCIIORegion *r; | |
888 | int i; | |
889 | ||
890 | for(i = 0; i < PCI_NUM_REGIONS; i++) { | |
891 | r = &pci_dev->io_regions[i]; | |
182f9c8a | 892 | if (!r->size || r->addr == PCI_BAR_UNMAPPED) |
5851e08c | 893 | continue; |
03952339 | 894 | memory_region_del_subregion(r->address_space, r->memory); |
5851e08c | 895 | } |
e01fd687 AW |
896 | |
897 | pci_unregister_vga(pci_dev); | |
5851e08c AL |
898 | } |
899 | ||
a36a344d | 900 | static int pci_unregister_device(DeviceState *dev) |
5851e08c | 901 | { |
40021f08 AL |
902 | PCIDevice *pci_dev = PCI_DEVICE(dev); |
903 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); | |
5851e08c AL |
904 | |
905 | pci_unregister_io_regions(pci_dev); | |
230741dc | 906 | pci_del_option_rom(pci_dev); |
7cf1b0fd | 907 | |
f90c2bcd AW |
908 | if (pc->exit) { |
909 | pc->exit(pci_dev); | |
910 | } | |
5851e08c | 911 | |
925fe64a | 912 | do_pci_unregister_device(pci_dev); |
5851e08c AL |
913 | return 0; |
914 | } | |
915 | ||
e824b2cc AK |
916 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
917 | uint8_t type, MemoryRegion *memory) | |
69b91039 FB |
918 | { |
919 | PCIIORegion *r; | |
d7ce493a | 920 | uint32_t addr; |
5a9ff381 | 921 | uint64_t wmask; |
cfc0be25 | 922 | pcibus_t size = memory_region_size(memory); |
a4c20c6a | 923 | |
2bbb9c2f IY |
924 | assert(region_num >= 0); |
925 | assert(region_num < PCI_NUM_REGIONS); | |
a4c20c6a AL |
926 | if (size & (size-1)) { |
927 | fprintf(stderr, "ERROR: PCI region size must be pow2 " | |
89e8b13c | 928 | "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); |
a4c20c6a AL |
929 | exit(1); |
930 | } | |
931 | ||
69b91039 | 932 | r = &pci_dev->io_regions[region_num]; |
182f9c8a | 933 | r->addr = PCI_BAR_UNMAPPED; |
69b91039 FB |
934 | r->size = size; |
935 | r->type = type; | |
79ff8cb0 | 936 | r->memory = NULL; |
b7ee1603 MT |
937 | |
938 | wmask = ~(size - 1); | |
b3b11697 | 939 | addr = pci_bar(pci_dev, region_num); |
d7ce493a | 940 | if (region_num == PCI_ROM_SLOT) { |
ebabb67a | 941 | /* ROM enable bit is writable */ |
5330de09 | 942 | wmask |= PCI_ROM_ADDRESS_ENABLE; |
d7ce493a | 943 | } |
b0ff8eb2 | 944 | pci_set_long(pci_dev->config + addr, type); |
14421258 IY |
945 | if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && |
946 | r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
947 | pci_set_quad(pci_dev->wmask + addr, wmask); | |
948 | pci_set_quad(pci_dev->cmask + addr, ~0ULL); | |
949 | } else { | |
950 | pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); | |
951 | pci_set_long(pci_dev->cmask + addr, 0xffffffff); | |
952 | } | |
79ff8cb0 | 953 | pci_dev->io_regions[region_num].memory = memory; |
5968eca3 | 954 | pci_dev->io_regions[region_num].address_space |
cfc0be25 | 955 | = type & PCI_BASE_ADDRESS_SPACE_IO |
5968eca3 AK |
956 | ? pci_dev->bus->address_space_io |
957 | : pci_dev->bus->address_space_mem; | |
79ff8cb0 AK |
958 | } |
959 | ||
e01fd687 AW |
960 | static void pci_update_vga(PCIDevice *pci_dev) |
961 | { | |
962 | uint16_t cmd; | |
963 | ||
964 | if (!pci_dev->has_vga) { | |
965 | return; | |
966 | } | |
967 | ||
968 | cmd = pci_get_word(pci_dev->config + PCI_COMMAND); | |
969 | ||
970 | memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], | |
971 | cmd & PCI_COMMAND_MEMORY); | |
972 | memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], | |
973 | cmd & PCI_COMMAND_IO); | |
974 | memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], | |
975 | cmd & PCI_COMMAND_IO); | |
976 | } | |
977 | ||
978 | void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, | |
979 | MemoryRegion *io_lo, MemoryRegion *io_hi) | |
980 | { | |
981 | assert(!pci_dev->has_vga); | |
982 | ||
983 | assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); | |
984 | pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; | |
985 | memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem, | |
986 | QEMU_PCI_VGA_MEM_BASE, mem, 1); | |
987 | ||
988 | assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); | |
989 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; | |
990 | memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, | |
991 | QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); | |
992 | ||
993 | assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); | |
994 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; | |
995 | memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, | |
996 | QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); | |
997 | pci_dev->has_vga = true; | |
998 | ||
999 | pci_update_vga(pci_dev); | |
1000 | } | |
1001 | ||
1002 | void pci_unregister_vga(PCIDevice *pci_dev) | |
1003 | { | |
1004 | if (!pci_dev->has_vga) { | |
1005 | return; | |
1006 | } | |
1007 | ||
1008 | memory_region_del_subregion(pci_dev->bus->address_space_mem, | |
1009 | pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); | |
1010 | memory_region_del_subregion(pci_dev->bus->address_space_io, | |
1011 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); | |
1012 | memory_region_del_subregion(pci_dev->bus->address_space_io, | |
1013 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); | |
1014 | pci_dev->has_vga = false; | |
1015 | } | |
1016 | ||
16a96f28 AK |
1017 | pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) |
1018 | { | |
1019 | return pci_dev->io_regions[region_num].addr; | |
1020 | } | |
1021 | ||
876a350d MT |
1022 | static pcibus_t pci_bar_address(PCIDevice *d, |
1023 | int reg, uint8_t type, pcibus_t size) | |
1024 | { | |
1025 | pcibus_t new_addr, last_addr; | |
1026 | int bar = pci_bar(d, reg); | |
1027 | uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); | |
1028 | ||
1029 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
1030 | if (!(cmd & PCI_COMMAND_IO)) { | |
1031 | return PCI_BAR_UNMAPPED; | |
1032 | } | |
1033 | new_addr = pci_get_long(d->config + bar) & ~(size - 1); | |
1034 | last_addr = new_addr + size - 1; | |
9f1a029a HP |
1035 | /* Check if 32 bit BAR wraps around explicitly. |
1036 | * TODO: make priorities correct and remove this work around. | |
1037 | */ | |
1038 | if (last_addr <= new_addr || new_addr == 0 || last_addr >= UINT32_MAX) { | |
876a350d MT |
1039 | return PCI_BAR_UNMAPPED; |
1040 | } | |
1041 | return new_addr; | |
1042 | } | |
1043 | ||
1044 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
1045 | return PCI_BAR_UNMAPPED; | |
1046 | } | |
1047 | if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
1048 | new_addr = pci_get_quad(d->config + bar); | |
1049 | } else { | |
1050 | new_addr = pci_get_long(d->config + bar); | |
1051 | } | |
1052 | /* the ROM slot has a specific enable bit */ | |
1053 | if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { | |
1054 | return PCI_BAR_UNMAPPED; | |
1055 | } | |
1056 | new_addr &= ~(size - 1); | |
1057 | last_addr = new_addr + size - 1; | |
1058 | /* NOTE: we do not support wrapping */ | |
1059 | /* XXX: as we cannot support really dynamic | |
1060 | mappings, we handle specific values as invalid | |
1061 | mappings. */ | |
1062 | if (last_addr <= new_addr || new_addr == 0 || | |
1063 | last_addr == PCI_BAR_UNMAPPED) { | |
1064 | return PCI_BAR_UNMAPPED; | |
1065 | } | |
1066 | ||
1067 | /* Now pcibus_t is 64bit. | |
1068 | * Check if 32 bit BAR wraps around explicitly. | |
1069 | * Without this, PC ide doesn't work well. | |
1070 | * TODO: remove this work around. | |
1071 | */ | |
1072 | if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { | |
1073 | return PCI_BAR_UNMAPPED; | |
1074 | } | |
1075 | ||
1076 | /* | |
1077 | * OS is allowed to set BAR beyond its addressable | |
1078 | * bits. For example, 32 bit OS can set 64bit bar | |
1079 | * to >4G. Check it. TODO: we might need to support | |
1080 | * it in the future for e.g. PAE. | |
1081 | */ | |
a8170e5e | 1082 | if (last_addr >= HWADDR_MAX) { |
876a350d MT |
1083 | return PCI_BAR_UNMAPPED; |
1084 | } | |
1085 | ||
1086 | return new_addr; | |
1087 | } | |
1088 | ||
0ac32c83 FB |
1089 | static void pci_update_mappings(PCIDevice *d) |
1090 | { | |
1091 | PCIIORegion *r; | |
876a350d | 1092 | int i; |
7df32ca0 | 1093 | pcibus_t new_addr; |
3b46e624 | 1094 | |
8a8696a3 | 1095 | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
0ac32c83 | 1096 | r = &d->io_regions[i]; |
a9688570 IY |
1097 | |
1098 | /* this region isn't registered */ | |
ec503442 | 1099 | if (!r->size) |
a9688570 IY |
1100 | continue; |
1101 | ||
876a350d | 1102 | new_addr = pci_bar_address(d, i, r->type, r->size); |
a9688570 IY |
1103 | |
1104 | /* This bar isn't changed */ | |
7df32ca0 | 1105 | if (new_addr == r->addr) |
a9688570 IY |
1106 | continue; |
1107 | ||
1108 | /* now do the real mapping */ | |
1109 | if (r->addr != PCI_BAR_UNMAPPED) { | |
03952339 | 1110 | memory_region_del_subregion(r->address_space, r->memory); |
0ac32c83 | 1111 | } |
a9688570 IY |
1112 | r->addr = new_addr; |
1113 | if (r->addr != PCI_BAR_UNMAPPED) { | |
8b881e77 AK |
1114 | memory_region_add_subregion_overlap(r->address_space, |
1115 | r->addr, r->memory, 1); | |
a9688570 | 1116 | } |
0ac32c83 | 1117 | } |
e01fd687 AW |
1118 | |
1119 | pci_update_vga(d); | |
0ac32c83 FB |
1120 | } |
1121 | ||
a7b15a5c MT |
1122 | static inline int pci_irq_disabled(PCIDevice *d) |
1123 | { | |
1124 | return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; | |
1125 | } | |
1126 | ||
1127 | /* Called after interrupt disabled field update in config space, | |
1128 | * assert/deassert interrupts if necessary. | |
1129 | * Gets original interrupt disable bit value (before update). */ | |
1130 | static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) | |
1131 | { | |
1132 | int i, disabled = pci_irq_disabled(d); | |
1133 | if (disabled == was_irq_disabled) | |
1134 | return; | |
1135 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
1136 | int state = pci_irq_state(d, i); | |
1137 | pci_change_irq_level(d, i, disabled ? -state : state); | |
1138 | } | |
1139 | } | |
1140 | ||
5fafdf24 | 1141 | uint32_t pci_default_read_config(PCIDevice *d, |
0ac32c83 | 1142 | uint32_t address, int len) |
69b91039 | 1143 | { |
5029fe12 | 1144 | uint32_t val = 0; |
42e4126b | 1145 | |
5029fe12 IY |
1146 | memcpy(&val, d->config + address, len); |
1147 | return le32_to_cpu(val); | |
0ac32c83 FB |
1148 | } |
1149 | ||
b7ee1603 | 1150 | void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
0ac32c83 | 1151 | { |
a7b15a5c | 1152 | int i, was_irq_disabled = pci_irq_disabled(d); |
0ac32c83 | 1153 | |
42e4126b | 1154 | for (i = 0; i < l; val >>= 8, ++i) { |
91011d4f | 1155 | uint8_t wmask = d->wmask[addr + i]; |
92ba5f51 IY |
1156 | uint8_t w1cmask = d->w1cmask[addr + i]; |
1157 | assert(!(wmask & w1cmask)); | |
91011d4f | 1158 | d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); |
92ba5f51 | 1159 | d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ |
0ac32c83 | 1160 | } |
260c0cd3 | 1161 | if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || |
edb00035 IY |
1162 | ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || |
1163 | ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || | |
260c0cd3 | 1164 | range_covers_byte(addr, l, PCI_COMMAND)) |
0ac32c83 | 1165 | pci_update_mappings(d); |
a7b15a5c | 1166 | |
1c380f94 | 1167 | if (range_covers_byte(addr, l, PCI_COMMAND)) { |
a7b15a5c | 1168 | pci_update_irq_disabled(d, was_irq_disabled); |
1c380f94 AK |
1169 | memory_region_set_enabled(&d->bus_master_enable_region, |
1170 | pci_get_word(d->config + PCI_COMMAND) | |
1171 | & PCI_COMMAND_MASTER); | |
1172 | } | |
95d65800 JK |
1173 | |
1174 | msi_write_config(d, addr, val, l); | |
1175 | msix_write_config(d, addr, val, l); | |
69b91039 FB |
1176 | } |
1177 | ||
502a5395 PB |
1178 | /***********************************************************/ |
1179 | /* generic PCI irq support */ | |
30468f78 | 1180 | |
502a5395 | 1181 | /* 0 <= irq_num <= 3. level must be 0 or 1 */ |
d98f08f5 | 1182 | static void pci_irq_handler(void *opaque, int irq_num, int level) |
69b91039 | 1183 | { |
a60380a5 | 1184 | PCIDevice *pci_dev = opaque; |
80b3ada7 | 1185 | int change; |
3b46e624 | 1186 | |
d036bb21 | 1187 | change = level - pci_irq_state(pci_dev, irq_num); |
80b3ada7 PB |
1188 | if (!change) |
1189 | return; | |
d2b59317 | 1190 | |
d036bb21 | 1191 | pci_set_irq_state(pci_dev, irq_num, level); |
f9bf77dd | 1192 | pci_update_irq_status(pci_dev); |
a7b15a5c MT |
1193 | if (pci_irq_disabled(pci_dev)) |
1194 | return; | |
d036bb21 | 1195 | pci_change_irq_level(pci_dev, irq_num, change); |
69b91039 FB |
1196 | } |
1197 | ||
d98f08f5 MA |
1198 | static inline int pci_intx(PCIDevice *pci_dev) |
1199 | { | |
1200 | return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; | |
1201 | } | |
1202 | ||
1203 | qemu_irq pci_allocate_irq(PCIDevice *pci_dev) | |
1204 | { | |
1205 | int intx = pci_intx(pci_dev); | |
1206 | ||
1207 | return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); | |
1208 | } | |
1209 | ||
1210 | void pci_set_irq(PCIDevice *pci_dev, int level) | |
1211 | { | |
1212 | int intx = pci_intx(pci_dev); | |
1213 | pci_irq_handler(pci_dev, intx, level); | |
1214 | } | |
1215 | ||
3afa9bb4 MT |
1216 | /* Special hooks used by device assignment */ |
1217 | void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) | |
1218 | { | |
0889464a | 1219 | assert(pci_bus_is_root(bus)); |
3afa9bb4 MT |
1220 | bus->route_intx_to_irq = route_intx_to_irq; |
1221 | } | |
1222 | ||
1223 | PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) | |
1224 | { | |
1225 | PCIBus *bus; | |
1226 | ||
1227 | do { | |
1228 | bus = dev->bus; | |
1229 | pin = bus->map_irq(dev, pin); | |
1230 | dev = bus->parent_dev; | |
1231 | } while (dev); | |
05c0621e AW |
1232 | |
1233 | if (!bus->route_intx_to_irq) { | |
312fd5f2 | 1234 | error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", |
05c0621e AW |
1235 | object_get_typename(OBJECT(bus->qbus.parent))); |
1236 | return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; | |
1237 | } | |
1238 | ||
3afa9bb4 | 1239 | return bus->route_intx_to_irq(bus->irq_opaque, pin); |
0ae16251 JK |
1240 | } |
1241 | ||
d6e65d54 AW |
1242 | bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) |
1243 | { | |
1244 | return old->mode != new->mode || old->irq != new->irq; | |
1245 | } | |
1246 | ||
0ae16251 JK |
1247 | void pci_bus_fire_intx_routing_notifier(PCIBus *bus) |
1248 | { | |
1249 | PCIDevice *dev; | |
1250 | PCIBus *sec; | |
1251 | int i; | |
1252 | ||
1253 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { | |
1254 | dev = bus->devices[i]; | |
1255 | if (dev && dev->intx_routing_notifier) { | |
1256 | dev->intx_routing_notifier(dev); | |
1257 | } | |
e5368f0d AW |
1258 | } |
1259 | ||
1260 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
1261 | pci_bus_fire_intx_routing_notifier(sec); | |
0ae16251 JK |
1262 | } |
1263 | } | |
1264 | ||
1265 | void pci_device_set_intx_routing_notifier(PCIDevice *dev, | |
1266 | PCIINTxRoutingNotifier notifier) | |
1267 | { | |
1268 | dev->intx_routing_notifier = notifier; | |
69b91039 FB |
1269 | } |
1270 | ||
91e56159 IY |
1271 | /* |
1272 | * PCI-to-PCI bridge specification | |
1273 | * 9.1: Interrupt routing. Table 9-1 | |
1274 | * | |
1275 | * the PCI Express Base Specification, Revision 2.1 | |
1276 | * 2.2.8.1: INTx interrutp signaling - Rules | |
1277 | * the Implementation Note | |
1278 | * Table 2-20 | |
1279 | */ | |
1280 | /* | |
1281 | * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD | |
1282 | * 0-origin unlike PCI interrupt pin register. | |
1283 | */ | |
1284 | int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) | |
1285 | { | |
1286 | return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; | |
1287 | } | |
1288 | ||
502a5395 PB |
1289 | /***********************************************************/ |
1290 | /* monitor info on PCI */ | |
0ac32c83 | 1291 | |
6650ee6d PB |
1292 | typedef struct { |
1293 | uint16_t class; | |
1294 | const char *desc; | |
5e0259e7 GN |
1295 | const char *fw_name; |
1296 | uint16_t fw_ign_bits; | |
6650ee6d PB |
1297 | } pci_class_desc; |
1298 | ||
09bc878a | 1299 | static const pci_class_desc pci_class_descriptions[] = |
6650ee6d | 1300 | { |
5e0259e7 GN |
1301 | { 0x0001, "VGA controller", "display"}, |
1302 | { 0x0100, "SCSI controller", "scsi"}, | |
1303 | { 0x0101, "IDE controller", "ide"}, | |
1304 | { 0x0102, "Floppy controller", "fdc"}, | |
1305 | { 0x0103, "IPI controller", "ipi"}, | |
1306 | { 0x0104, "RAID controller", "raid"}, | |
dcb5b19a TS |
1307 | { 0x0106, "SATA controller"}, |
1308 | { 0x0107, "SAS controller"}, | |
1309 | { 0x0180, "Storage controller"}, | |
5e0259e7 GN |
1310 | { 0x0200, "Ethernet controller", "ethernet"}, |
1311 | { 0x0201, "Token Ring controller", "token-ring"}, | |
1312 | { 0x0202, "FDDI controller", "fddi"}, | |
1313 | { 0x0203, "ATM controller", "atm"}, | |
dcb5b19a | 1314 | { 0x0280, "Network controller"}, |
5e0259e7 | 1315 | { 0x0300, "VGA controller", "display", 0x00ff}, |
dcb5b19a TS |
1316 | { 0x0301, "XGA controller"}, |
1317 | { 0x0302, "3D controller"}, | |
1318 | { 0x0380, "Display controller"}, | |
5e0259e7 GN |
1319 | { 0x0400, "Video controller", "video"}, |
1320 | { 0x0401, "Audio controller", "sound"}, | |
dcb5b19a | 1321 | { 0x0402, "Phone"}, |
602ef4d9 | 1322 | { 0x0403, "Audio controller", "sound"}, |
dcb5b19a | 1323 | { 0x0480, "Multimedia controller"}, |
5e0259e7 GN |
1324 | { 0x0500, "RAM controller", "memory"}, |
1325 | { 0x0501, "Flash controller", "flash"}, | |
dcb5b19a | 1326 | { 0x0580, "Memory controller"}, |
5e0259e7 GN |
1327 | { 0x0600, "Host bridge", "host"}, |
1328 | { 0x0601, "ISA bridge", "isa"}, | |
1329 | { 0x0602, "EISA bridge", "eisa"}, | |
1330 | { 0x0603, "MC bridge", "mca"}, | |
4c41425d | 1331 | { 0x0604, "PCI bridge", "pci-bridge"}, |
5e0259e7 GN |
1332 | { 0x0605, "PCMCIA bridge", "pcmcia"}, |
1333 | { 0x0606, "NUBUS bridge", "nubus"}, | |
1334 | { 0x0607, "CARDBUS bridge", "cardbus"}, | |
dcb5b19a TS |
1335 | { 0x0608, "RACEWAY bridge"}, |
1336 | { 0x0680, "Bridge"}, | |
5e0259e7 GN |
1337 | { 0x0700, "Serial port", "serial"}, |
1338 | { 0x0701, "Parallel port", "parallel"}, | |
1339 | { 0x0800, "Interrupt controller", "interrupt-controller"}, | |
1340 | { 0x0801, "DMA controller", "dma-controller"}, | |
1341 | { 0x0802, "Timer", "timer"}, | |
1342 | { 0x0803, "RTC", "rtc"}, | |
1343 | { 0x0900, "Keyboard", "keyboard"}, | |
1344 | { 0x0901, "Pen", "pen"}, | |
1345 | { 0x0902, "Mouse", "mouse"}, | |
1346 | { 0x0A00, "Dock station", "dock", 0x00ff}, | |
1347 | { 0x0B00, "i386 cpu", "cpu", 0x00ff}, | |
1348 | { 0x0c00, "Fireware contorller", "fireware"}, | |
1349 | { 0x0c01, "Access bus controller", "access-bus"}, | |
1350 | { 0x0c02, "SSA controller", "ssa"}, | |
1351 | { 0x0c03, "USB controller", "usb"}, | |
1352 | { 0x0c04, "Fibre channel controller", "fibre-channel"}, | |
f7748569 | 1353 | { 0x0c05, "SMBus"}, |
6650ee6d PB |
1354 | { 0, NULL} |
1355 | }; | |
1356 | ||
163c8a59 | 1357 | static void pci_for_each_device_under_bus(PCIBus *bus, |
7aa8cbb9 AP |
1358 | void (*fn)(PCIBus *b, PCIDevice *d, |
1359 | void *opaque), | |
1360 | void *opaque) | |
30468f78 | 1361 | { |
163c8a59 LC |
1362 | PCIDevice *d; |
1363 | int devfn; | |
30468f78 | 1364 | |
163c8a59 LC |
1365 | for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1366 | d = bus->devices[devfn]; | |
1367 | if (d) { | |
7aa8cbb9 | 1368 | fn(bus, d, opaque); |
163c8a59 LC |
1369 | } |
1370 | } | |
1371 | } | |
1372 | ||
1373 | void pci_for_each_device(PCIBus *bus, int bus_num, | |
7aa8cbb9 AP |
1374 | void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), |
1375 | void *opaque) | |
163c8a59 | 1376 | { |
d662210a | 1377 | bus = pci_find_bus_nr(bus, bus_num); |
163c8a59 LC |
1378 | |
1379 | if (bus) { | |
7aa8cbb9 | 1380 | pci_for_each_device_under_bus(bus, fn, opaque); |
163c8a59 LC |
1381 | } |
1382 | } | |
1383 | ||
79627472 | 1384 | static const pci_class_desc *get_class_desc(int class) |
163c8a59 | 1385 | { |
79627472 | 1386 | const pci_class_desc *desc; |
163c8a59 | 1387 | |
79627472 LC |
1388 | desc = pci_class_descriptions; |
1389 | while (desc->desc && class != desc->class) { | |
1390 | desc++; | |
30468f78 | 1391 | } |
b4dccd8d | 1392 | |
79627472 LC |
1393 | return desc; |
1394 | } | |
14421258 | 1395 | |
79627472 | 1396 | static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); |
163c8a59 | 1397 | |
79627472 LC |
1398 | static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) |
1399 | { | |
1400 | PciMemoryRegionList *head = NULL, *cur_item = NULL; | |
1401 | int i; | |
163c8a59 | 1402 | |
79627472 LC |
1403 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1404 | const PCIIORegion *r = &dev->io_regions[i]; | |
1405 | PciMemoryRegionList *region; | |
1406 | ||
1407 | if (!r->size) { | |
1408 | continue; | |
502a5395 | 1409 | } |
163c8a59 | 1410 | |
79627472 LC |
1411 | region = g_malloc0(sizeof(*region)); |
1412 | region->value = g_malloc0(sizeof(*region->value)); | |
163c8a59 | 1413 | |
79627472 LC |
1414 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { |
1415 | region->value->type = g_strdup("io"); | |
1416 | } else { | |
1417 | region->value->type = g_strdup("memory"); | |
1418 | region->value->has_prefetch = true; | |
1419 | region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); | |
1420 | region->value->has_mem_type_64 = true; | |
1421 | region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); | |
d5e4acf7 | 1422 | } |
163c8a59 | 1423 | |
79627472 LC |
1424 | region->value->bar = i; |
1425 | region->value->address = r->addr; | |
1426 | region->value->size = r->size; | |
163c8a59 | 1427 | |
79627472 LC |
1428 | /* XXX: waiting for the qapi to support GSList */ |
1429 | if (!cur_item) { | |
1430 | head = cur_item = region; | |
1431 | } else { | |
1432 | cur_item->next = region; | |
1433 | cur_item = region; | |
163c8a59 | 1434 | } |
80b3ada7 | 1435 | } |
384d8876 | 1436 | |
79627472 | 1437 | return head; |
163c8a59 LC |
1438 | } |
1439 | ||
79627472 LC |
1440 | static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, |
1441 | int bus_num) | |
163c8a59 | 1442 | { |
79627472 | 1443 | PciBridgeInfo *info; |
163c8a59 | 1444 | |
79627472 | 1445 | info = g_malloc0(sizeof(*info)); |
163c8a59 | 1446 | |
79627472 LC |
1447 | info->bus.number = dev->config[PCI_PRIMARY_BUS]; |
1448 | info->bus.secondary = dev->config[PCI_SECONDARY_BUS]; | |
1449 | info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS]; | |
163c8a59 | 1450 | |
79627472 LC |
1451 | info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range)); |
1452 | info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); | |
1453 | info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); | |
163c8a59 | 1454 | |
79627472 LC |
1455 | info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range)); |
1456 | info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
1457 | info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
163c8a59 | 1458 | |
79627472 LC |
1459 | info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range)); |
1460 | info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
1461 | info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
163c8a59 | 1462 | |
79627472 | 1463 | if (dev->config[PCI_SECONDARY_BUS] != 0) { |
d662210a | 1464 | PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); |
79627472 LC |
1465 | if (child_bus) { |
1466 | info->has_devices = true; | |
1467 | info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); | |
1468 | } | |
163c8a59 LC |
1469 | } |
1470 | ||
79627472 | 1471 | return info; |
163c8a59 LC |
1472 | } |
1473 | ||
79627472 LC |
1474 | static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, |
1475 | int bus_num) | |
163c8a59 | 1476 | { |
79627472 LC |
1477 | const pci_class_desc *desc; |
1478 | PciDeviceInfo *info; | |
b5937f29 | 1479 | uint8_t type; |
79627472 | 1480 | int class; |
163c8a59 | 1481 | |
79627472 LC |
1482 | info = g_malloc0(sizeof(*info)); |
1483 | info->bus = bus_num; | |
1484 | info->slot = PCI_SLOT(dev->devfn); | |
1485 | info->function = PCI_FUNC(dev->devfn); | |
1486 | ||
1487 | class = pci_get_word(dev->config + PCI_CLASS_DEVICE); | |
6f88009e | 1488 | info->class_info.q_class = class; |
79627472 LC |
1489 | desc = get_class_desc(class); |
1490 | if (desc->desc) { | |
1491 | info->class_info.has_desc = true; | |
1492 | info->class_info.desc = g_strdup(desc->desc); | |
1493 | } | |
1494 | ||
1495 | info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID); | |
1496 | info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID); | |
1497 | info->regions = qmp_query_pci_regions(dev); | |
1498 | info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); | |
163c8a59 LC |
1499 | |
1500 | if (dev->config[PCI_INTERRUPT_PIN] != 0) { | |
79627472 LC |
1501 | info->has_irq = true; |
1502 | info->irq = dev->config[PCI_INTERRUPT_LINE]; | |
163c8a59 LC |
1503 | } |
1504 | ||
b5937f29 IY |
1505 | type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
1506 | if (type == PCI_HEADER_TYPE_BRIDGE) { | |
79627472 LC |
1507 | info->has_pci_bridge = true; |
1508 | info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); | |
163c8a59 LC |
1509 | } |
1510 | ||
79627472 | 1511 | return info; |
163c8a59 LC |
1512 | } |
1513 | ||
79627472 | 1514 | static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) |
384d8876 | 1515 | { |
79627472 | 1516 | PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; |
163c8a59 | 1517 | PCIDevice *dev; |
79627472 | 1518 | int devfn; |
163c8a59 LC |
1519 | |
1520 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { | |
1521 | dev = bus->devices[devfn]; | |
1522 | if (dev) { | |
79627472 LC |
1523 | info = g_malloc0(sizeof(*info)); |
1524 | info->value = qmp_query_pci_device(dev, bus, bus_num); | |
1525 | ||
1526 | /* XXX: waiting for the qapi to support GSList */ | |
1527 | if (!cur_item) { | |
1528 | head = cur_item = info; | |
1529 | } else { | |
1530 | cur_item->next = info; | |
1531 | cur_item = info; | |
1532 | } | |
163c8a59 | 1533 | } |
1074df4f | 1534 | } |
163c8a59 | 1535 | |
79627472 | 1536 | return head; |
1074df4f IY |
1537 | } |
1538 | ||
79627472 | 1539 | static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) |
1074df4f | 1540 | { |
79627472 LC |
1541 | PciInfo *info = NULL; |
1542 | ||
d662210a | 1543 | bus = pci_find_bus_nr(bus, bus_num); |
502a5395 | 1544 | if (bus) { |
79627472 LC |
1545 | info = g_malloc0(sizeof(*info)); |
1546 | info->bus = bus_num; | |
1547 | info->devices = qmp_query_pci_devices(bus, bus_num); | |
f2aa58c6 | 1548 | } |
163c8a59 | 1549 | |
79627472 | 1550 | return info; |
f2aa58c6 FB |
1551 | } |
1552 | ||
79627472 | 1553 | PciInfoList *qmp_query_pci(Error **errp) |
f2aa58c6 | 1554 | { |
79627472 | 1555 | PciInfoList *info, *head = NULL, *cur_item = NULL; |
7588e2b0 | 1556 | PCIHostState *host_bridge; |
163c8a59 | 1557 | |
7588e2b0 | 1558 | QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { |
79627472 | 1559 | info = g_malloc0(sizeof(*info)); |
7588e2b0 | 1560 | info->value = qmp_query_pci_bus(host_bridge->bus, 0); |
79627472 LC |
1561 | |
1562 | /* XXX: waiting for the qapi to support GSList */ | |
1563 | if (!cur_item) { | |
1564 | head = cur_item = info; | |
1565 | } else { | |
1566 | cur_item->next = info; | |
1567 | cur_item = info; | |
163c8a59 | 1568 | } |
e822a52a | 1569 | } |
163c8a59 | 1570 | |
79627472 | 1571 | return head; |
77d4bc34 | 1572 | } |
a41b2ff2 | 1573 | |
cb457d76 AL |
1574 | static const char * const pci_nic_models[] = { |
1575 | "ne2k_pci", | |
1576 | "i82551", | |
1577 | "i82557b", | |
1578 | "i82559er", | |
1579 | "rtl8139", | |
1580 | "e1000", | |
1581 | "pcnet", | |
1582 | "virtio", | |
1583 | NULL | |
1584 | }; | |
1585 | ||
9d07d757 PB |
1586 | static const char * const pci_nic_names[] = { |
1587 | "ne2k_pci", | |
1588 | "i82551", | |
1589 | "i82557b", | |
1590 | "i82559er", | |
1591 | "rtl8139", | |
1592 | "e1000", | |
1593 | "pcnet", | |
53c25cea | 1594 | "virtio-net-pci", |
cb457d76 AL |
1595 | NULL |
1596 | }; | |
1597 | ||
a41b2ff2 | 1598 | /* Initialize a PCI NIC. */ |
33e66b86 | 1599 | /* FIXME callers should check for failure, but don't */ |
29b358f9 DG |
1600 | PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus, |
1601 | const char *default_model, | |
5607c388 | 1602 | const char *default_devaddr) |
a41b2ff2 | 1603 | { |
5607c388 | 1604 | const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
07caea31 MA |
1605 | PCIBus *bus; |
1606 | int devfn; | |
5607c388 | 1607 | PCIDevice *pci_dev; |
9d07d757 | 1608 | DeviceState *dev; |
cb457d76 AL |
1609 | int i; |
1610 | ||
07caea31 MA |
1611 | i = qemu_find_nic_model(nd, pci_nic_models, default_model); |
1612 | if (i < 0) | |
1613 | return NULL; | |
1614 | ||
29b358f9 | 1615 | bus = pci_get_bus_devfn(&devfn, rootbus, devaddr); |
07caea31 | 1616 | if (!bus) { |
1ecda02b MA |
1617 | error_report("Invalid PCI device address %s for device %s", |
1618 | devaddr, pci_nic_names[i]); | |
07caea31 MA |
1619 | return NULL; |
1620 | } | |
1621 | ||
499cf102 | 1622 | pci_dev = pci_create(bus, devfn, pci_nic_names[i]); |
9ee05825 | 1623 | dev = &pci_dev->qdev; |
1cc33683 | 1624 | qdev_set_nic_properties(dev, nd); |
07caea31 MA |
1625 | if (qdev_init(dev) < 0) |
1626 | return NULL; | |
9ee05825 | 1627 | return pci_dev; |
a41b2ff2 PB |
1628 | } |
1629 | ||
29b358f9 DG |
1630 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, |
1631 | const char *default_model, | |
07caea31 MA |
1632 | const char *default_devaddr) |
1633 | { | |
1634 | PCIDevice *res; | |
1635 | ||
1636 | if (qemu_show_nic_models(nd->model, pci_nic_models)) | |
1637 | exit(0); | |
1638 | ||
29b358f9 | 1639 | res = pci_nic_init(nd, rootbus, default_model, default_devaddr); |
07caea31 MA |
1640 | if (!res) |
1641 | exit(1); | |
1642 | return res; | |
1643 | } | |
1644 | ||
129d42fb AJ |
1645 | PCIDevice *pci_vga_init(PCIBus *bus) |
1646 | { | |
1647 | switch (vga_interface_type) { | |
1648 | case VGA_CIRRUS: | |
1649 | return pci_create_simple(bus, -1, "cirrus-vga"); | |
1650 | case VGA_QXL: | |
1651 | return pci_create_simple(bus, -1, "qxl-vga"); | |
1652 | case VGA_STD: | |
1653 | return pci_create_simple(bus, -1, "VGA"); | |
1654 | case VGA_VMWARE: | |
1655 | return pci_create_simple(bus, -1, "vmware-svga"); | |
1656 | case VGA_NONE: | |
1657 | default: /* Other non-PCI types. Checking for unsupported types is already | |
1658 | done in vl.c. */ | |
1659 | return NULL; | |
1660 | } | |
1661 | } | |
1662 | ||
929176c3 MT |
1663 | /* Whether a given bus number is in range of the secondary |
1664 | * bus of the given bridge device. */ | |
1665 | static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) | |
1666 | { | |
1667 | return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & | |
1668 | PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && | |
1669 | dev->config[PCI_SECONDARY_BUS] < bus_num && | |
1670 | bus_num <= dev->config[PCI_SUBORDINATE_BUS]; | |
1671 | } | |
1672 | ||
d662210a | 1673 | static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) |
3ae80618 | 1674 | { |
470e6363 | 1675 | PCIBus *sec; |
3ae80618 | 1676 | |
470e6363 | 1677 | if (!bus) { |
e822a52a | 1678 | return NULL; |
470e6363 | 1679 | } |
3ae80618 | 1680 | |
e822a52a IY |
1681 | if (pci_bus_num(bus) == bus_num) { |
1682 | return bus; | |
1683 | } | |
1684 | ||
929176c3 | 1685 | /* Consider all bus numbers in range for the host pci bridge. */ |
0889464a | 1686 | if (!pci_bus_is_root(bus) && |
929176c3 MT |
1687 | !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { |
1688 | return NULL; | |
1689 | } | |
1690 | ||
e822a52a | 1691 | /* try child bus */ |
929176c3 MT |
1692 | for (; bus; bus = sec) { |
1693 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
0889464a | 1694 | assert(!pci_bus_is_root(sec)); |
929176c3 MT |
1695 | if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) { |
1696 | return sec; | |
1697 | } | |
1698 | if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { | |
1699 | break; | |
c021f8e6 | 1700 | } |
e822a52a IY |
1701 | } |
1702 | } | |
1703 | ||
1704 | return NULL; | |
3ae80618 AL |
1705 | } |
1706 | ||
eb0acfdd MT |
1707 | void pci_for_each_bus_depth_first(PCIBus *bus, |
1708 | void *(*begin)(PCIBus *bus, void *parent_state), | |
1709 | void (*end)(PCIBus *bus, void *state), | |
1710 | void *parent_state) | |
1711 | { | |
1712 | PCIBus *sec; | |
1713 | void *state; | |
1714 | ||
1715 | if (!bus) { | |
1716 | return; | |
1717 | } | |
1718 | ||
1719 | if (begin) { | |
1720 | state = begin(bus, parent_state); | |
1721 | } else { | |
1722 | state = parent_state; | |
1723 | } | |
1724 | ||
1725 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
1726 | pci_for_each_bus_depth_first(sec, begin, end, state); | |
1727 | } | |
1728 | ||
1729 | if (end) { | |
1730 | end(bus, state); | |
1731 | } | |
1732 | } | |
1733 | ||
1734 | ||
5256d8bf | 1735 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) |
3ae80618 | 1736 | { |
d662210a | 1737 | bus = pci_find_bus_nr(bus, bus_num); |
3ae80618 AL |
1738 | |
1739 | if (!bus) | |
1740 | return NULL; | |
1741 | ||
5256d8bf | 1742 | return bus->devices[devfn]; |
3ae80618 AL |
1743 | } |
1744 | ||
d307af79 | 1745 | static int pci_qdev_init(DeviceState *qdev) |
6b1b92d3 PB |
1746 | { |
1747 | PCIDevice *pci_dev = (PCIDevice *)qdev; | |
40021f08 | 1748 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
6b1b92d3 | 1749 | PCIBus *bus; |
113f89df | 1750 | int rc; |
ab85ceb1 | 1751 | bool is_default_rom; |
6b1b92d3 | 1752 | |
a9f49946 | 1753 | /* initialize cap_present for pci_is_express() and pci_config_size() */ |
40021f08 | 1754 | if (pc->is_express) { |
a9f49946 IY |
1755 | pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; |
1756 | } | |
1757 | ||
fef7fbc9 | 1758 | bus = PCI_BUS(qdev_get_parent_bus(qdev)); |
6e008585 AL |
1759 | pci_dev = do_pci_register_device(pci_dev, bus, |
1760 | object_get_typename(OBJECT(qdev)), | |
1761 | pci_dev->devfn); | |
09e3acc6 GH |
1762 | if (pci_dev == NULL) |
1763 | return -1; | |
40021f08 | 1764 | if (qdev->hotplugged && pc->no_hotplug) { |
f79f2bfc | 1765 | qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(pci_dev))); |
180c22e1 GH |
1766 | do_pci_unregister_device(pci_dev); |
1767 | return -1; | |
1768 | } | |
40021f08 AL |
1769 | if (pc->init) { |
1770 | rc = pc->init(pci_dev); | |
c2afc922 IY |
1771 | if (rc != 0) { |
1772 | do_pci_unregister_device(pci_dev); | |
1773 | return rc; | |
1774 | } | |
925fe64a | 1775 | } |
8c52c8f3 GH |
1776 | |
1777 | /* rom loading */ | |
ab85ceb1 | 1778 | is_default_rom = false; |
40021f08 AL |
1779 | if (pci_dev->romfile == NULL && pc->romfile != NULL) { |
1780 | pci_dev->romfile = g_strdup(pc->romfile); | |
ab85ceb1 SW |
1781 | is_default_rom = true; |
1782 | } | |
1783 | pci_add_option_rom(pci_dev, is_default_rom); | |
8c52c8f3 | 1784 | |
5beb8ad5 | 1785 | if (bus->hotplug) { |
e927d487 MT |
1786 | /* Let buses differentiate between hotplug and when device is |
1787 | * enabled during qemu machine creation. */ | |
1788 | rc = bus->hotplug(bus->hotplug_qdev, pci_dev, | |
1789 | qdev->hotplugged ? PCI_HOTPLUG_ENABLED: | |
1790 | PCI_COLDPLUG_ENABLED); | |
a213ff63 IY |
1791 | if (rc != 0) { |
1792 | int r = pci_unregister_device(&pci_dev->qdev); | |
1793 | assert(!r); | |
1794 | return rc; | |
1795 | } | |
1796 | } | |
ee995ffb GH |
1797 | return 0; |
1798 | } | |
1799 | ||
1800 | static int pci_unplug_device(DeviceState *qdev) | |
1801 | { | |
40021f08 AL |
1802 | PCIDevice *dev = PCI_DEVICE(qdev); |
1803 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); | |
ee995ffb | 1804 | |
40021f08 | 1805 | if (pc->no_hotplug) { |
f79f2bfc | 1806 | qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(dev))); |
180c22e1 GH |
1807 | return -1; |
1808 | } | |
e927d487 MT |
1809 | return dev->bus->hotplug(dev->bus->hotplug_qdev, dev, |
1810 | PCI_HOTPLUG_DISABLED); | |
6b1b92d3 PB |
1811 | } |
1812 | ||
49823868 IY |
1813 | PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
1814 | const char *name) | |
6b1b92d3 PB |
1815 | { |
1816 | DeviceState *dev; | |
1817 | ||
02e2da45 | 1818 | dev = qdev_create(&bus->qbus, name); |
09f1bbcd | 1819 | qdev_prop_set_int32(dev, "addr", devfn); |
49823868 | 1820 | qdev_prop_set_bit(dev, "multifunction", multifunction); |
40021f08 | 1821 | return PCI_DEVICE(dev); |
71077c1c | 1822 | } |
6b1b92d3 | 1823 | |
49823868 IY |
1824 | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, |
1825 | bool multifunction, | |
1826 | const char *name) | |
71077c1c | 1827 | { |
49823868 | 1828 | PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); |
e23a1b33 | 1829 | qdev_init_nofail(&dev->qdev); |
71077c1c | 1830 | return dev; |
6b1b92d3 | 1831 | } |
6f4cbd39 | 1832 | |
49823868 IY |
1833 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) |
1834 | { | |
1835 | return pci_create_multifunction(bus, devfn, false, name); | |
1836 | } | |
1837 | ||
1838 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) | |
1839 | { | |
1840 | return pci_create_simple_multifunction(bus, devfn, false, name); | |
1841 | } | |
1842 | ||
b56d701f | 1843 | static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) |
6f4cbd39 MT |
1844 | { |
1845 | int offset = PCI_CONFIG_HEADER_SIZE; | |
1846 | int i; | |
b56d701f | 1847 | for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { |
6f4cbd39 MT |
1848 | if (pdev->used[i]) |
1849 | offset = i + 1; | |
1850 | else if (i - offset + 1 == size) | |
1851 | return offset; | |
b56d701f | 1852 | } |
6f4cbd39 MT |
1853 | return 0; |
1854 | } | |
1855 | ||
1856 | static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, | |
1857 | uint8_t *prev_p) | |
1858 | { | |
1859 | uint8_t next, prev; | |
1860 | ||
1861 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) | |
1862 | return 0; | |
1863 | ||
1864 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
1865 | prev = next + PCI_CAP_LIST_NEXT) | |
1866 | if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) | |
1867 | break; | |
1868 | ||
1869 | if (prev_p) | |
1870 | *prev_p = prev; | |
1871 | return next; | |
1872 | } | |
1873 | ||
c9abe111 JK |
1874 | static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) |
1875 | { | |
1876 | uint8_t next, prev, found = 0; | |
1877 | ||
1878 | if (!(pdev->used[offset])) { | |
1879 | return 0; | |
1880 | } | |
1881 | ||
1882 | assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); | |
1883 | ||
1884 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
1885 | prev = next + PCI_CAP_LIST_NEXT) { | |
1886 | if (next <= offset && next > found) { | |
1887 | found = next; | |
1888 | } | |
1889 | } | |
1890 | return found; | |
1891 | } | |
1892 | ||
ab85ceb1 SW |
1893 | /* Patch the PCI vendor and device ids in a PCI rom image if necessary. |
1894 | This is needed for an option rom which is used for more than one device. */ | |
1895 | static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) | |
1896 | { | |
1897 | uint16_t vendor_id; | |
1898 | uint16_t device_id; | |
1899 | uint16_t rom_vendor_id; | |
1900 | uint16_t rom_device_id; | |
1901 | uint16_t rom_magic; | |
1902 | uint16_t pcir_offset; | |
1903 | uint8_t checksum; | |
1904 | ||
1905 | /* Words in rom data are little endian (like in PCI configuration), | |
1906 | so they can be read / written with pci_get_word / pci_set_word. */ | |
1907 | ||
1908 | /* Only a valid rom will be patched. */ | |
1909 | rom_magic = pci_get_word(ptr); | |
1910 | if (rom_magic != 0xaa55) { | |
1911 | PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); | |
1912 | return; | |
1913 | } | |
1914 | pcir_offset = pci_get_word(ptr + 0x18); | |
1915 | if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { | |
1916 | PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); | |
1917 | return; | |
1918 | } | |
1919 | ||
1920 | vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); | |
1921 | device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); | |
1922 | rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); | |
1923 | rom_device_id = pci_get_word(ptr + pcir_offset + 6); | |
1924 | ||
1925 | PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, | |
1926 | vendor_id, device_id, rom_vendor_id, rom_device_id); | |
1927 | ||
1928 | checksum = ptr[6]; | |
1929 | ||
1930 | if (vendor_id != rom_vendor_id) { | |
1931 | /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ | |
1932 | checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); | |
1933 | checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); | |
1934 | PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); | |
1935 | ptr[6] = checksum; | |
1936 | pci_set_word(ptr + pcir_offset + 4, vendor_id); | |
1937 | } | |
1938 | ||
1939 | if (device_id != rom_device_id) { | |
1940 | /* Patch device id and checksum (at offset 6 for etherboot roms). */ | |
1941 | checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); | |
1942 | checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); | |
1943 | PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); | |
1944 | ptr[6] = checksum; | |
1945 | pci_set_word(ptr + pcir_offset + 6, device_id); | |
1946 | } | |
1947 | } | |
1948 | ||
c2039bd0 | 1949 | /* Add an option rom for the device */ |
ab85ceb1 | 1950 | static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom) |
c2039bd0 AL |
1951 | { |
1952 | int size; | |
1953 | char *path; | |
1954 | void *ptr; | |
1724f049 | 1955 | char name[32]; |
4be9f0d1 | 1956 | const VMStateDescription *vmsd; |
c2039bd0 | 1957 | |
8c52c8f3 GH |
1958 | if (!pdev->romfile) |
1959 | return 0; | |
1960 | if (strlen(pdev->romfile) == 0) | |
1961 | return 0; | |
1962 | ||
88169ddf GH |
1963 | if (!pdev->rom_bar) { |
1964 | /* | |
1965 | * Load rom via fw_cfg instead of creating a rom bar, | |
1966 | * for 0.11 compatibility. | |
1967 | */ | |
1968 | int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); | |
1969 | if (class == 0x0300) { | |
1970 | rom_add_vga(pdev->romfile); | |
1971 | } else { | |
2e55e842 | 1972 | rom_add_option(pdev->romfile, -1); |
88169ddf GH |
1973 | } |
1974 | return 0; | |
1975 | } | |
1976 | ||
8c52c8f3 | 1977 | path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); |
c2039bd0 | 1978 | if (path == NULL) { |
7267c094 | 1979 | path = g_strdup(pdev->romfile); |
c2039bd0 AL |
1980 | } |
1981 | ||
1982 | size = get_image_size(path); | |
8c52c8f3 | 1983 | if (size < 0) { |
1ecda02b | 1984 | error_report("%s: failed to find romfile \"%s\"", |
8c7f3dd0 SH |
1985 | __func__, pdev->romfile); |
1986 | g_free(path); | |
1987 | return -1; | |
1988 | } else if (size == 0) { | |
1989 | error_report("%s: ignoring empty romfile \"%s\"", | |
1990 | __func__, pdev->romfile); | |
7267c094 | 1991 | g_free(path); |
8c52c8f3 GH |
1992 | return -1; |
1993 | } | |
c2039bd0 AL |
1994 | if (size & (size - 1)) { |
1995 | size = 1 << qemu_fls(size); | |
1996 | } | |
1997 | ||
4be9f0d1 AL |
1998 | vmsd = qdev_get_vmsd(DEVICE(pdev)); |
1999 | ||
2000 | if (vmsd) { | |
2001 | snprintf(name, sizeof(name), "%s.rom", vmsd->name); | |
2002 | } else { | |
f79f2bfc | 2003 | snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); |
4be9f0d1 | 2004 | } |
14caaf7f | 2005 | pdev->has_rom = true; |
40c5dce9 | 2006 | memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size); |
c5705a77 | 2007 | vmstate_register_ram(&pdev->rom, &pdev->qdev); |
14caaf7f | 2008 | ptr = memory_region_get_ram_ptr(&pdev->rom); |
c2039bd0 | 2009 | load_image(path, ptr); |
7267c094 | 2010 | g_free(path); |
c2039bd0 | 2011 | |
ab85ceb1 SW |
2012 | if (is_default_rom) { |
2013 | /* Only the default rom images will be patched (if needed). */ | |
2014 | pci_patch_ids(pdev, ptr, size); | |
2015 | } | |
2016 | ||
e824b2cc | 2017 | pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); |
c2039bd0 AL |
2018 | |
2019 | return 0; | |
2020 | } | |
2021 | ||
230741dc AW |
2022 | static void pci_del_option_rom(PCIDevice *pdev) |
2023 | { | |
14caaf7f | 2024 | if (!pdev->has_rom) |
230741dc AW |
2025 | return; |
2026 | ||
c5705a77 | 2027 | vmstate_unregister_ram(&pdev->rom, &pdev->qdev); |
14caaf7f AK |
2028 | memory_region_destroy(&pdev->rom); |
2029 | pdev->has_rom = false; | |
230741dc AW |
2030 | } |
2031 | ||
ca77089d IY |
2032 | /* |
2033 | * if !offset | |
2034 | * Reserve space and add capability to the linked list in pci config space | |
2035 | * | |
2036 | * if offset = 0, | |
2037 | * Find and reserve space and add capability to the linked list | |
2038 | * in pci config space */ | |
2039 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, | |
2040 | uint8_t offset, uint8_t size) | |
6f4cbd39 | 2041 | { |
ca77089d | 2042 | uint8_t *config; |
c9abe111 JK |
2043 | int i, overlapping_cap; |
2044 | ||
ca77089d IY |
2045 | if (!offset) { |
2046 | offset = pci_find_space(pdev, size); | |
2047 | if (!offset) { | |
2048 | return -ENOSPC; | |
2049 | } | |
c9abe111 JK |
2050 | } else { |
2051 | /* Verify that capabilities don't overlap. Note: device assignment | |
2052 | * depends on this check to verify that the device is not broken. | |
2053 | * Should never trigger for emulated devices, but it's helpful | |
2054 | * for debugging these. */ | |
2055 | for (i = offset; i < offset + size; i++) { | |
2056 | overlapping_cap = pci_find_capability_at_offset(pdev, i); | |
2057 | if (overlapping_cap) { | |
568f0690 | 2058 | fprintf(stderr, "ERROR: %s:%02x:%02x.%x " |
c9abe111 JK |
2059 | "Attempt to add PCI capability %x at offset " |
2060 | "%x overlaps existing capability %x at offset %x\n", | |
568f0690 | 2061 | pci_root_bus_path(pdev), pci_bus_num(pdev->bus), |
c9abe111 JK |
2062 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
2063 | cap_id, offset, overlapping_cap, i); | |
2064 | return -EINVAL; | |
2065 | } | |
2066 | } | |
ca77089d IY |
2067 | } |
2068 | ||
2069 | config = pdev->config + offset; | |
6f4cbd39 MT |
2070 | config[PCI_CAP_LIST_ID] = cap_id; |
2071 | config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; | |
2072 | pdev->config[PCI_CAPABILITY_LIST] = offset; | |
2073 | pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; | |
e26631b7 | 2074 | memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); |
6f4cbd39 MT |
2075 | /* Make capability read-only by default */ |
2076 | memset(pdev->wmask + offset, 0, size); | |
bd4b65ee MT |
2077 | /* Check capability by default */ |
2078 | memset(pdev->cmask + offset, 0xFF, size); | |
6f4cbd39 MT |
2079 | return offset; |
2080 | } | |
2081 | ||
2082 | /* Unlink capability from the pci config space. */ | |
2083 | void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
2084 | { | |
2085 | uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); | |
2086 | if (!offset) | |
2087 | return; | |
2088 | pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; | |
ebabb67a | 2089 | /* Make capability writable again */ |
6f4cbd39 | 2090 | memset(pdev->wmask + offset, 0xff, size); |
1a4f5971 | 2091 | memset(pdev->w1cmask + offset, 0, size); |
bd4b65ee MT |
2092 | /* Clear cmask as device-specific registers can't be checked */ |
2093 | memset(pdev->cmask + offset, 0, size); | |
e26631b7 | 2094 | memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); |
6f4cbd39 MT |
2095 | |
2096 | if (!pdev->config[PCI_CAPABILITY_LIST]) | |
2097 | pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; | |
2098 | } | |
2099 | ||
6f4cbd39 MT |
2100 | uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) |
2101 | { | |
2102 | return pci_find_capability_list(pdev, cap_id, NULL); | |
2103 | } | |
10c4c98a GH |
2104 | |
2105 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) | |
2106 | { | |
2107 | PCIDevice *d = (PCIDevice *)dev; | |
2108 | const pci_class_desc *desc; | |
2109 | char ctxt[64]; | |
2110 | PCIIORegion *r; | |
2111 | int i, class; | |
2112 | ||
b0ff8eb2 | 2113 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
10c4c98a GH |
2114 | desc = pci_class_descriptions; |
2115 | while (desc->desc && class != desc->class) | |
2116 | desc++; | |
2117 | if (desc->desc) { | |
2118 | snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); | |
2119 | } else { | |
2120 | snprintf(ctxt, sizeof(ctxt), "Class %04x", class); | |
2121 | } | |
2122 | ||
2123 | monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " | |
2124 | "pci id %04x:%04x (sub %04x:%04x)\n", | |
7f5feab4 | 2125 | indent, "", ctxt, pci_bus_num(d->bus), |
e822a52a | 2126 | PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), |
b0ff8eb2 IY |
2127 | pci_get_word(d->config + PCI_VENDOR_ID), |
2128 | pci_get_word(d->config + PCI_DEVICE_ID), | |
2129 | pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), | |
2130 | pci_get_word(d->config + PCI_SUBSYSTEM_ID)); | |
10c4c98a GH |
2131 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
2132 | r = &d->io_regions[i]; | |
2133 | if (!r->size) | |
2134 | continue; | |
89e8b13c IY |
2135 | monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS |
2136 | " [0x%"FMT_PCIBUS"]\n", | |
2137 | indent, "", | |
0392a017 | 2138 | i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", |
10c4c98a GH |
2139 | r->addr, r->addr + r->size - 1); |
2140 | } | |
2141 | } | |
03587182 | 2142 | |
5e0259e7 GN |
2143 | static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) |
2144 | { | |
2145 | PCIDevice *d = (PCIDevice *)dev; | |
2146 | const char *name = NULL; | |
2147 | const pci_class_desc *desc = pci_class_descriptions; | |
2148 | int class = pci_get_word(d->config + PCI_CLASS_DEVICE); | |
2149 | ||
2150 | while (desc->desc && | |
2151 | (class & ~desc->fw_ign_bits) != | |
2152 | (desc->class & ~desc->fw_ign_bits)) { | |
2153 | desc++; | |
2154 | } | |
2155 | ||
2156 | if (desc->desc) { | |
2157 | name = desc->fw_name; | |
2158 | } | |
2159 | ||
2160 | if (name) { | |
2161 | pstrcpy(buf, len, name); | |
2162 | } else { | |
2163 | snprintf(buf, len, "pci%04x,%04x", | |
2164 | pci_get_word(d->config + PCI_VENDOR_ID), | |
2165 | pci_get_word(d->config + PCI_DEVICE_ID)); | |
2166 | } | |
2167 | ||
2168 | return buf; | |
2169 | } | |
2170 | ||
2171 | static char *pcibus_get_fw_dev_path(DeviceState *dev) | |
2172 | { | |
2173 | PCIDevice *d = (PCIDevice *)dev; | |
2174 | char path[50], name[33]; | |
2175 | int off; | |
2176 | ||
2177 | off = snprintf(path, sizeof(path), "%s@%x", | |
2178 | pci_dev_fw_name(dev, name, sizeof name), | |
2179 | PCI_SLOT(d->devfn)); | |
2180 | if (PCI_FUNC(d->devfn)) | |
2181 | snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); | |
a5cf8262 | 2182 | return g_strdup(path); |
5e0259e7 GN |
2183 | } |
2184 | ||
4f43c1ff AW |
2185 | static char *pcibus_get_dev_path(DeviceState *dev) |
2186 | { | |
a6a7005d MT |
2187 | PCIDevice *d = container_of(dev, PCIDevice, qdev); |
2188 | PCIDevice *t; | |
2189 | int slot_depth; | |
2190 | /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. | |
2191 | * 00 is added here to make this format compatible with | |
2192 | * domain:Bus:Slot.Func for systems without nested PCI bridges. | |
2193 | * Slot.Function list specifies the slot and function numbers for all | |
2194 | * devices on the path from root to the specific device. */ | |
568f0690 DG |
2195 | const char *root_bus_path; |
2196 | int root_bus_len; | |
2991181a | 2197 | char slot[] = ":SS.F"; |
2991181a | 2198 | int slot_len = sizeof slot - 1 /* For '\0' */; |
a6a7005d MT |
2199 | int path_len; |
2200 | char *path, *p; | |
2991181a | 2201 | int s; |
a6a7005d | 2202 | |
568f0690 DG |
2203 | root_bus_path = pci_root_bus_path(d); |
2204 | root_bus_len = strlen(root_bus_path); | |
2205 | ||
a6a7005d MT |
2206 | /* Calculate # of slots on path between device and root. */; |
2207 | slot_depth = 0; | |
2208 | for (t = d; t; t = t->bus->parent_dev) { | |
2209 | ++slot_depth; | |
2210 | } | |
2211 | ||
568f0690 | 2212 | path_len = root_bus_len + slot_len * slot_depth; |
a6a7005d MT |
2213 | |
2214 | /* Allocate memory, fill in the terminating null byte. */ | |
7267c094 | 2215 | path = g_malloc(path_len + 1 /* For '\0' */); |
a6a7005d MT |
2216 | path[path_len] = '\0'; |
2217 | ||
568f0690 | 2218 | memcpy(path, root_bus_path, root_bus_len); |
a6a7005d MT |
2219 | |
2220 | /* Fill in slot numbers. We walk up from device to root, so need to print | |
2221 | * them in the reverse order, last to first. */ | |
2222 | p = path + path_len; | |
2223 | for (t = d; t; t = t->bus->parent_dev) { | |
2224 | p -= slot_len; | |
2991181a | 2225 | s = snprintf(slot, sizeof slot, ":%02x.%x", |
4c900518 | 2226 | PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); |
2991181a MT |
2227 | assert(s == slot_len); |
2228 | memcpy(p, slot, slot_len); | |
a6a7005d MT |
2229 | } |
2230 | ||
2231 | return path; | |
4f43c1ff AW |
2232 | } |
2233 | ||
f3006dd1 IY |
2234 | static int pci_qdev_find_recursive(PCIBus *bus, |
2235 | const char *id, PCIDevice **pdev) | |
2236 | { | |
2237 | DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); | |
2238 | if (!qdev) { | |
2239 | return -ENODEV; | |
2240 | } | |
2241 | ||
2242 | /* roughly check if given qdev is pci device */ | |
4be9f0d1 | 2243 | if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { |
40021f08 | 2244 | *pdev = PCI_DEVICE(qdev); |
f3006dd1 IY |
2245 | return 0; |
2246 | } | |
2247 | return -EINVAL; | |
2248 | } | |
2249 | ||
2250 | int pci_qdev_find_device(const char *id, PCIDevice **pdev) | |
2251 | { | |
7588e2b0 | 2252 | PCIHostState *host_bridge; |
f3006dd1 IY |
2253 | int rc = -ENODEV; |
2254 | ||
7588e2b0 DG |
2255 | QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { |
2256 | int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); | |
f3006dd1 IY |
2257 | if (!tmp) { |
2258 | rc = 0; | |
2259 | break; | |
2260 | } | |
2261 | if (tmp != -ENODEV) { | |
2262 | rc = tmp; | |
2263 | } | |
2264 | } | |
2265 | ||
2266 | return rc; | |
2267 | } | |
f5e6fed8 AK |
2268 | |
2269 | MemoryRegion *pci_address_space(PCIDevice *dev) | |
2270 | { | |
2271 | return dev->bus->address_space_mem; | |
2272 | } | |
e11d6439 RH |
2273 | |
2274 | MemoryRegion *pci_address_space_io(PCIDevice *dev) | |
2275 | { | |
2276 | return dev->bus->address_space_io; | |
2277 | } | |
40021f08 | 2278 | |
39bffca2 AL |
2279 | static void pci_device_class_init(ObjectClass *klass, void *data) |
2280 | { | |
2281 | DeviceClass *k = DEVICE_CLASS(klass); | |
2282 | k->init = pci_qdev_init; | |
2283 | k->unplug = pci_unplug_device; | |
2284 | k->exit = pci_unregister_device; | |
0d936928 | 2285 | k->bus_type = TYPE_PCI_BUS; |
bce54474 | 2286 | k->props = pci_props; |
39bffca2 AL |
2287 | } |
2288 | ||
9eda7d37 AK |
2289 | AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) |
2290 | { | |
2291 | PCIBus *bus = PCI_BUS(dev->bus); | |
2292 | ||
2293 | if (bus->iommu_fn) { | |
2294 | return bus->iommu_fn(bus, bus->iommu_opaque, dev->devfn); | |
2295 | } | |
2296 | ||
2297 | if (bus->parent_dev) { | |
2298 | /** We are ignoring the bus master DMA bit of the bridge | |
2299 | * as it would complicate things such as VFIO for no good reason */ | |
2300 | return pci_device_iommu_address_space(bus->parent_dev); | |
2301 | } | |
2302 | ||
2303 | return &address_space_memory; | |
2304 | } | |
2305 | ||
e00387d5 | 2306 | void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) |
5fa45de5 | 2307 | { |
e00387d5 AK |
2308 | bus->iommu_fn = fn; |
2309 | bus->iommu_opaque = opaque; | |
5fa45de5 DG |
2310 | } |
2311 | ||
43864069 MT |
2312 | static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) |
2313 | { | |
2314 | Range *range = opaque; | |
2315 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); | |
2316 | uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); | |
77d6f4ea | 2317 | int i; |
43864069 MT |
2318 | |
2319 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
2320 | return; | |
2321 | } | |
2322 | ||
2323 | if (pc->is_bridge) { | |
2324 | pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
2325 | pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
2326 | ||
2327 | base = MAX(base, 0x1ULL << 32); | |
2328 | ||
2329 | if (limit >= base) { | |
2330 | Range pref_range; | |
2331 | pref_range.begin = base; | |
2332 | pref_range.end = limit + 1; | |
2333 | range_extend(range, &pref_range); | |
2334 | } | |
2335 | } | |
77d6f4ea MT |
2336 | for (i = 0; i < PCI_NUM_REGIONS; ++i) { |
2337 | PCIIORegion *r = &dev->io_regions[i]; | |
43864069 MT |
2338 | Range region_range; |
2339 | ||
77d6f4ea MT |
2340 | if (!r->size || |
2341 | (r->type & PCI_BASE_ADDRESS_SPACE_IO) || | |
2342 | !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { | |
2343 | continue; | |
2344 | } | |
2345 | region_range.begin = pci_bar_address(dev, i, r->type, r->size); | |
2346 | region_range.end = region_range.begin + r->size; | |
2347 | ||
2348 | if (region_range.begin == PCI_BAR_UNMAPPED) { | |
43864069 MT |
2349 | continue; |
2350 | } | |
43864069 MT |
2351 | |
2352 | region_range.begin = MAX(region_range.begin, 0x1ULL << 32); | |
2353 | ||
2354 | if (region_range.end - 1 >= region_range.begin) { | |
2355 | range_extend(range, ®ion_range); | |
2356 | } | |
2357 | } | |
2358 | } | |
2359 | ||
2360 | void pci_bus_get_w64_range(PCIBus *bus, Range *range) | |
2361 | { | |
2362 | range->begin = range->end = 0; | |
2363 | pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); | |
2364 | } | |
2365 | ||
8c43a6f0 | 2366 | static const TypeInfo pci_device_type_info = { |
40021f08 AL |
2367 | .name = TYPE_PCI_DEVICE, |
2368 | .parent = TYPE_DEVICE, | |
2369 | .instance_size = sizeof(PCIDevice), | |
2370 | .abstract = true, | |
2371 | .class_size = sizeof(PCIDeviceClass), | |
39bffca2 | 2372 | .class_init = pci_device_class_init, |
40021f08 AL |
2373 | }; |
2374 | ||
83f7d43a | 2375 | static void pci_register_types(void) |
40021f08 | 2376 | { |
0d936928 | 2377 | type_register_static(&pci_bus_info); |
3a861c46 | 2378 | type_register_static(&pcie_bus_info); |
40021f08 AL |
2379 | type_register_static(&pci_device_type_info); |
2380 | } | |
2381 | ||
83f7d43a | 2382 | type_init(pci_register_types) |