[mirror_qemu.git] / hw / pci / pci_bridge.c

/*
 * QEMU PCI bus manager
 *
 * Copyright (c) 2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to dea

 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
/*
 * split out from pci.c
 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
 *                    VA Linux Systems Japan K.K.
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_bus.h"
#include "qemu/module.h"
#include "qemu/range.h"
#include "qapi/error.h"
#include "hw/acpi/acpi_aml_interface.h"
#include "hw/acpi/pci.h"
#include "hw/qdev-properties.h"

/* PCI bridge subsystem vendor ID helper functions */
#define PCI_SSVID_SIZEOF        8
#define PCI_SSVID_SVID          4
#define PCI_SSVID_SSID          6

int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
                          uint16_t svid, uint16_t ssid,
                          Error **errp)
{
    int pos;

    pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset,
                             PCI_SSVID_SIZEOF, errp);
    if (pos < 0) {
        return pos;
    }

    pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid);
    pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid);
    return pos;
}

/* Accessor function to get parent bridge device from pci bus. */
PCIDevice *pci_bridge_get_device(PCIBus *bus)
{
    return bus->parent_dev;
}

/* Accessor function to get secondary bus from pci-to-pci bridge device */
PCIBus *pci_bridge_get_sec_bus(PCIBridge *br)
{
    return &br->sec_bus;
}

static uint32_t pci_config_get_io_base(const PCIDevice *d,
                                       uint32_t base, uint32_t base_upper16)
{
    uint32_t val;

    val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
    if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
        val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
    }
    return val;
}

static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base)
{
    return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
        << 16;
}

static pcibus_t pci_config_get_pref_base(const PCIDevice *d,
                                         uint32_t base, uint32_t upper)
{
    pcibus_t tmp;
    pcibus_t val;

    tmp = (pcibus_t)pci_get_word(d->config + base);
    val = (tmp & PCI_PREF_RANGE_MASK) << 16;
    if (tmp & PCI_PREF_RANGE_TYPE_64) {
        val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
    }
    return val;
}

/* accessor function to get bridge filtering base address */
pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type)
{
    pcibus_t base;
    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
        base = pci_config_get_io_base(bridge,
                                      PCI_IO_BASE, PCI_IO_BASE_UPPER16);
    } else {
        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
            base = pci_config_get_pref_base(
                bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
        } else {
            base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
        }
    }

    return base;
}

/* accessor function to get bridge filtering limit */
pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type)
{
    pcibus_t limit;
    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
        limit = pci_config_get_io_base(bridge,
                                      PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
        limit |= 0xfff;         /* PCI bridge spec 3.2.5.6. */
    } else {
        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
            limit = pci_config_get_pref_base(
                bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
        } else {
            limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
        }
        limit |= 0xfffff;       /* PCI bridge spec 3.2.5.{1, 8}. */
    }
    return limit;
}

static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias,
                                  uint8_t type, const char *name,
                                  MemoryRegion *space,
                                  MemoryRegion *parent_space,
                                  bool enabled)
{
    PCIDevice *bridge_dev = PCI_DEVICE(bridge);
    pcibus_t base = pci_bridge_get_base(bridge_dev, type);
    pcibus_t limit = pci_bridge_get_limit(bridge_dev, type);
    /* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly.
     * Apparently no way to do this with existing memory APIs. */
    pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0;

    memory_region_init_alias(alias, OBJECT(bridge), name, space, base, size);
    memory_region_add_subregion_overlap(parent_space, base, alias, 1);
}

static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent,
                                        MemoryRegion *alias_vga)
{
    PCIDevice *pd = PCI_DEVICE(br);
    uint16_t brctl = pci_get_word(pd->config + PCI_BRIDGE_CONTROL);

    memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br),
                             "pci_bridge_vga_io_lo", &br->address_space_io,
                             QEMU_PCI_VGA_IO_LO_BASE, QEMU_PCI_VGA_IO_LO_SIZE);
    memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_HI], OBJECT(br),
                             "pci_bridge_vga_io_hi", &br->address_space_io,
                             QEMU_PCI_VGA_IO_HI_BASE, QEMU_PCI_VGA_IO_HI_SIZE);
    memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_MEM], OBJECT(br),
                             "pci_bridge_vga_mem", &br->address_space_mem,
                             QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE);

    if (brctl & PCI_BRIDGE_CTL_VGA) {
        pci_register_vga(pd, &alias_vga[QEMU_PCI_VGA_MEM],
                         &alias_vga[QEMU_PCI_VGA_IO_LO],
                         &alias_vga[QEMU_PCI_VGA_IO_HI]);
    }
}

static void pci_bridge_region_init(PCIBridge *br)
{
    PCIDevice *pd = PCI_DEVICE(br);
    PCIBus *parent = pci_get_bus(pd);
    PCIBridgeWindows *w = &br->windows;
    uint16_t cmd = pci_get_word(pd->config + PCI_COMMAND);

    pci_bridge_init_alias(br, &w->alias_pref_mem,
                          PCI_BASE_ADDRESS_MEM_PREFETCH,
                          "pci_bridge_pref_mem",
                          &br->address_space_mem,
                          parent->address_space_mem,
                          cmd & PCI_COMMAND_MEMORY);
    pci_bridge_init_alias(br, &w->alias_mem,
                          PCI_BASE_ADDRESS_SPACE_MEMORY,
                          "pci_bridge_mem",
                          &br->address_space_mem,
                          parent->address_space_mem,
                          cmd & PCI_COMMAND_MEMORY);
    pci_bridge_init_alias(br, &w->alias_io,
                          PCI_BASE_ADDRESS_SPACE_IO,
                          "pci_bridge_io",
                          &br->address_space_io,
                          parent->address_space_io,
                          cmd & PCI_COMMAND_IO);

    pci_bridge_init_vga_aliases(br, parent, w->alias_vga);
}

static void pci_bridge_region_del(PCIBridge *br, PCIBridgeWindows *w)
{
    PCIDevice *pd = PCI_DEVICE(br);
    PCIBus *parent = pci_get_bus(pd);

    memory_region_del_subregion(parent->address_space_io, &w->alias_io);
    memory_region_del_subregion(parent->address_space_mem, &w->alias_mem);
    memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem);
    pci_unregister_vga(pd);
}

static void pci_bridge_region_cleanup(PCIBridge *br, PCIBridgeWindows *w)
{
    object_unparent(OBJECT(&w->alias_io));
    object_unparent(OBJECT(&w->alias_mem));
    object_unparent(OBJECT(&w->alias_pref_mem));
    object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_LO]));
    object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_HI]));
    object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_MEM]));
}

void pci_bridge_update_mappings(PCIBridge *br)
{
    PCIBridgeWindows *w = &br->windows;

    /* Make updates atomic to: handle the case of one VCPU updating the bridge
     * while another accesses an unaffected region. */
    memory_region_transaction_begin();
    pci_bridge_region_del(br, w);
    pci_bridge_region_cleanup(br, w);
    pci_bridge_region_init(br);
    memory_region_transaction_commit();
}

/* default write_config function for PCI-to-PCI bridge */
void pci_bridge_write_config(PCIDevice *d,
                             uint32_t address, uint32_t val, int len)
{
    PCIBridge *s = PCI_BRIDGE(d);
    uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
    uint16_t newctl;

    pci_default_write_config(d, address, val, len);

    if (ranges_overlap(address, len, PCI_COMMAND, 2) ||

        /* io base/limit */
        ranges_overlap(address, len, PCI_IO_BASE, 2) ||

        /* memory base/limit, prefetchable base/limit and
           io base/limit upper 16 */
        ranges_overlap(address, len, PCI_MEMORY_BASE, 20) ||

        /* vga enable */
        ranges_overlap(address, len, PCI_BRIDGE_CONTROL, 2)) {
        pci_bridge_update_mappings(s);
    }

    newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
    if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {
        /* Trigger hot reset on 0->1 transition. */
        bus_cold_reset(BUS(&s->sec_bus));
    }
}

void pci_bridge_disable_base_limit(PCIDevice *dev)
{
    uint8_t *conf = dev->config;

    pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
                               PCI_IO_RANGE_MASK & 0xff);
    pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
                                 PCI_IO_RANGE_MASK & 0xff);
    pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE,
                               PCI_MEMORY_RANGE_MASK & 0xffff);
    pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
                                 PCI_MEMORY_RANGE_MASK & 0xffff);
    pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE,
                               PCI_PREF_RANGE_MASK & 0xffff);
    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
                                 PCI_PREF_RANGE_MASK & 0xffff);
    pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
    pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
}

/* reset bridge specific configuration registers */
void pci_bridge_reset(DeviceState *qdev)
{
    PCIDevice *dev = PCI_DEVICE(qdev);
    uint8_t *conf = dev->config;

    conf[PCI_PRIMARY_BUS] = 0;
    conf[PCI_SECONDARY_BUS] = 0;
    conf[PCI_SUBORDINATE_BUS] = 0;
    conf[PCI_SEC_LATENCY_TIMER] = 0;

    /*
     * the default values for base/limit registers aren't specified
     * in the PCI-to-PCI-bridge spec. So we don't touch them here.
     * Each implementation can override it.
     * typical implementation does
     * zero base/limit registers or
     * disable forwarding: pci_bridge_disable_base_limit()
     * If disable forwarding is wanted, call pci_bridge_disable_base_limit()
     * after this function.
     */
    pci_byte_test_and_clear_mask(conf + PCI_IO_BASE,
                                 PCI_IO_RANGE_MASK & 0xff);
    pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
                                 PCI_IO_RANGE_MASK & 0xff);
    pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE,
                                 PCI_MEMORY_RANGE_MASK & 0xffff);
    pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
                                 PCI_MEMORY_RANGE_MASK & 0xffff);
    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE,
                                 PCI_PREF_RANGE_MASK & 0xffff);
    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
                                 PCI_PREF_RANGE_MASK & 0xffff);
    pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
    pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);

    pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
}

/* default qdev initialization function for PCI-to-PCI bridge */
void pci_bridge_initfn(PCIDevice *dev, const char *typename)
{
    PCIBus *parent = pci_get_bus(dev);
    PCIBridge *br = PCI_BRIDGE(dev);
    PCIBus *sec_bus = &br->sec_bus;

    pci_word_test_and_set_mask(dev->config + PCI_STATUS,
                               PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);

    /*
     * TODO: We implement VGA Enable in the Bridge Control Register
     * therefore per the PCI to PCI bridge spec we must also implement
     * VGA Palette Snooping.  When done, set this bit writable:
     *
     * pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND,
     *                            PCI_COMMAND_VGA_PALETTE);
     */

    pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
    dev->config[PCI_HEADER_TYPE] =
        (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
        PCI_HEADER_TYPE_BRIDGE;
    pci_set_word(dev->config + PCI_SEC_STATUS,
                 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);

    /*
     * If we don't specify the name, the bus will be addressed as <id>.0, where
     * id is the device id.
     * Since PCI Bridge devices have a single bus each, we don't need the index:
     * let users address the bus using the device name.
     */
    if (!br->bus_name && dev->qdev.id && *dev->qdev.id) {
            br->bus_name = dev->qdev.id;
    }

    qbus_init(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
              br->bus_name);
    sec_bus->parent_dev = dev;
    sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
    sec_bus->address_space_mem = &br->address_space_mem;
    memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX);
    sec_bus->address_space_io = &br->address_space_io;
    memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io",
                       4 * GiB);
    pci_bridge_region_init(br);
    QLIST_INIT(&sec_bus->child);
    QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);

    /* For express secondary buses, secondary latency timer is RO 0 */
    if (pci_bus_is_express(sec_bus) && !br->pcie_writeable_slt_bug) {
        dev->wmask[PCI_SEC_LATENCY_TIMER] = 0;
    }
}

/* default qdev clean up function for PCI-to-PCI bridge */
void pci_bridge_exitfn(PCIDevice *pci_dev)
{
    PCIBridge *s = PCI_BRIDGE(pci_dev);
    assert(QLIST_EMPTY(&s->sec_bus.child));
    QLIST_REMOVE(&s->sec_bus, sibling);
    pci_bridge_region_del(s, &s->windows);
    pci_bridge_region_cleanup(s, &s->windows);
    /* object_unparent() is called automatically during device deletion */
}

/*
 * before qdev initialization(qdev_init()), this function sets bus_name and
 * map_irq callback which are necessary for pci_bridge_initfn() to
 * initialize bus.
 */
void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
                        pci_map_irq_fn map_irq)
{
    br->map_irq = map_irq;
    br->bus_name = bus_name;
}


int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
                                     PCIResReserve res_reserve, Error **errp)
{
    if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
        res_reserve.mem_pref_64 != (uint64_t)-1) {
        error_setg(errp,
                   "PCI resource reserve cap: PREF32 and PREF64 conflict");
        return -EINVAL;
    }

    if (res_reserve.mem_non_pref != (uint64_t)-1 &&
        res_reserve.mem_non_pref >= 4 * GiB) {
        error_setg(errp,
                   "PCI resource reserve cap: mem-reserve must be less than 4G");
        return -EINVAL;
    }

    if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
        res_reserve.mem_pref_32 >= 4 * GiB) {
        error_setg(errp,
                   "PCI resource reserve cap: pref32-reserve  must be less than 4G");
        return -EINVAL;
    }

    if (res_reserve.bus == (uint32_t)-1 &&
        res_reserve.io == (uint64_t)-1 &&
        res_reserve.mem_non_pref == (uint64_t)-1 &&
        res_reserve.mem_pref_32 == (uint64_t)-1 &&
        res_reserve.mem_pref_64 == (uint64_t)-1) {
        return 0;
    }

    size_t cap_len = sizeof(PCIBridgeQemuCap);
    PCIBridgeQemuCap cap = {
            .len = cap_len,
            .type = REDHAT_PCI_CAP_RESOURCE_RESERVE,
            .bus_res = cpu_to_le32(res_reserve.bus),
            .io = cpu_to_le64(res_reserve.io),
            .mem = cpu_to_le32(res_reserve.mem_non_pref),
            .mem_pref_32 = cpu_to_le32(res_reserve.mem_pref_32),
            .mem_pref_64 = cpu_to_le64(res_reserve.mem_pref_64)
    };

    int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,
                                    cap_offset, cap_len, errp);
    if (offset < 0) {
        return offset;
    }

    memcpy(dev->config + offset + PCI_CAP_FLAGS,
           (char *)&cap + PCI_CAP_FLAGS,
           cap_len - PCI_CAP_FLAGS);
    return 0;
}

static Property pci_bridge_properties[] = {
    DEFINE_PROP_BOOL("x-pci-express-writeable-slt-bug", PCIBridge,
                     pcie_writeable_slt_bug, false),
    DEFINE_PROP_END_OF_LIST(),
};

static void pci_bridge_class_init(ObjectClass *klass, void *data)
{
    AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
    DeviceClass *k = DEVICE_CLASS(klass);

    device_class_set_props(k, pci_bridge_properties);
    adevc->build_dev_aml = build_pci_bridge_aml;
}

static const TypeInfo pci_bridge_type_info = {
    .name = TYPE_PCI_BRIDGE,
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIBridge),
    .class_init = pci_bridge_class_init,
    .abstract = true,
    .interfaces = (InterfaceInfo[]) {
        { TYPE_ACPI_DEV_AML_IF },
        { },
    },
};

static void pci_bridge_register_types(void)
{
    type_register_static(&pci_bridge_type_info);
}

type_init(pci_bridge_register_types)
Commit	Line	Data
783753fd IY	1	/*
	2	* QEMU PCI bus manager
	3	*
	4	* Copyright (c) 2004 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to dea
	8
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM
	22
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*/
	26	/*
	27	* split out from pci.c
	28	* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
	29	* VA Linux Systems Japan K.K.
	30	*/
	31
97d5408f	32	#include "qemu/osdep.h"
2dc48da2	33	#include "qemu/units.h"
c759b24f	34	#include "hw/pci/pci_bridge.h"
06aac7bd	35	#include "hw/pci/pci_bus.h"
0b8fa32f	36	#include "qemu/module.h"
1de7afc9	37	#include "qemu/range.h"
9a7c2a59	38	#include "qapi/error.h"
d78644c7	39	#include "hw/acpi/acpi_aml_interface.h"
6c36ec46	40	#include "hw/acpi/pci.h"
4565917b	41	#include "hw/qdev-properties.h"
783753fd	42
f4c817e0 IY	43	/* PCI bridge subsystem vendor ID helper functions */
	44	#define PCI_SSVID_SIZEOF 8
	45	#define PCI_SSVID_SVID 4
	46	#define PCI_SSVID_SSID 6
	47
	48	int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
f8cd1b02 MZ	49	uint16_t svid, uint16_t ssid,
f8cd1b02 MZ	50	Error **errp)
f4c817e0 IY	51	{
f4c817e0 IY	52	int pos;
9a7c2a59 MZ	53
9a7c2a59 MZ	54	pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset,
f8cd1b02	55	PCI_SSVID_SIZEOF, errp);
f4c817e0 IY	56	if (pos < 0) {
	57	return pos;
	58	}
	59
	60	pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid);
	61	pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid);
	62	return pos;
	63	}
	64
68f79994	65	/* Accessor function to get parent bridge device from pci bus. */
783753fd IY	66	PCIDevice pci_bridge_get_device(PCIBus bus)
	67	{
	68	return bus->parent_dev;
	69	}
	70
68f79994 IY	71	/* Accessor function to get secondary bus from pci-to-pci bridge device */
	72	PCIBus pci_bridge_get_sec_bus(PCIBridge br)
	73	{
	74	return &br->sec_bus;
	75	}
	76
	77	static uint32_t pci_config_get_io_base(const PCIDevice *d,
783753fd IY	78	uint32_t base, uint32_t base_upper16)
	79	{
	80	uint32_t val;
	81
	82	val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
	83	if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
	84	val \|= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
	85	}
	86	return val;
	87	}
	88
68f79994	89	static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base)
783753fd IY	90	{
	91	return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
	92	<< 16;
	93	}
	94
68f79994	95	static pcibus_t pci_config_get_pref_base(const PCIDevice *d,
783753fd IY	96	uint32_t base, uint32_t upper)
	97	{
	98	pcibus_t tmp;
	99	pcibus_t val;
	100
	101	tmp = (pcibus_t)pci_get_word(d->config + base);
	102	val = (tmp & PCI_PREF_RANGE_MASK) << 16;
	103	if (tmp & PCI_PREF_RANGE_TYPE_64) {
	104	val \|= (pcibus_t)pci_get_long(d->config + upper) << 32;
	105	}
	106	return val;
	107	}
	108
68f79994 IY	109	/* accessor function to get bridge filtering base address */
68f79994 IY	110	pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type)
783753fd IY	111	{
	112	pcibus_t base;
	113	if (type & PCI_BASE_ADDRESS_SPACE_IO) {
	114	base = pci_config_get_io_base(bridge,
	115	PCI_IO_BASE, PCI_IO_BASE_UPPER16);
	116	} else {
	117	if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
	118	base = pci_config_get_pref_base(
	119	bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
	120	} else {
	121	base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
	122	}
	123	}
	124
	125	return base;
	126	}
	127
cb8d4c8f	128	/* accessor function to get bridge filtering limit */
68f79994	129	pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type)
783753fd IY	130	{
	131	pcibus_t limit;
	132	if (type & PCI_BASE_ADDRESS_SPACE_IO) {
	133	limit = pci_config_get_io_base(bridge,
	134	PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
	135	limit \|= 0xfff; /* PCI bridge spec 3.2.5.6. */
	136	} else {
	137	if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
	138	limit = pci_config_get_pref_base(
	139	bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
	140	} else {
	141	limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
	142	}
	143	limit \|= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
	144	}
	145	return limit;
	146	}
	147
7df32ca0 MT	148	static void pci_bridge_init_alias(PCIBridge bridge, MemoryRegion alias,
	149	uint8_t type, const char *name,
	150	MemoryRegion *space,
	151	MemoryRegion *parent_space,
	152	bool enabled)
	153	{
f055e96b AF	154	PCIDevice *bridge_dev = PCI_DEVICE(bridge);
	155	pcibus_t base = pci_bridge_get_base(bridge_dev, type);
	156	pcibus_t limit = pci_bridge_get_limit(bridge_dev, type);
7df32ca0 MT	157	/* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly.
	158	* Apparently no way to do this with existing memory APIs. */
	159	pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0;
	160
40c5dce9	161	memory_region_init_alias(alias, OBJECT(bridge), name, space, base, size);
7df32ca0 MT	162	memory_region_add_subregion_overlap(parent_space, base, alias, 1);
	163	}
	164
ba7d8515 AW	165	static void pci_bridge_init_vga_aliases(PCIBridge br, PCIBus parent,
	166	MemoryRegion *alias_vga)
	167	{
f055e96b AF	168	PCIDevice *pd = PCI_DEVICE(br);
f055e96b AF	169	uint16_t brctl = pci_get_word(pd->config + PCI_BRIDGE_CONTROL);
ba7d8515	170
40c5dce9	171	memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br),
ba7d8515 AW	172	"pci_bridge_vga_io_lo", &br->address_space_io,
ba7d8515 AW	173	QEMU_PCI_VGA_IO_LO_BASE, QEMU_PCI_VGA_IO_LO_SIZE);
40c5dce9	174	memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_HI], OBJECT(br),
ba7d8515 AW	175	"pci_bridge_vga_io_hi", &br->address_space_io,
ba7d8515 AW	176	QEMU_PCI_VGA_IO_HI_BASE, QEMU_PCI_VGA_IO_HI_SIZE);
40c5dce9	177	memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_MEM], OBJECT(br),
ba7d8515 AW	178	"pci_bridge_vga_mem", &br->address_space_mem,
	179	QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE);
	180
	181	if (brctl & PCI_BRIDGE_CTL_VGA) {
f055e96b	182	pci_register_vga(pd, &alias_vga[QEMU_PCI_VGA_MEM],
ba7d8515 AW	183	&alias_vga[QEMU_PCI_VGA_IO_LO],
	184	&alias_vga[QEMU_PCI_VGA_IO_HI]);
	185	}
	186	}
	187
b2999ed8	188	static void pci_bridge_region_init(PCIBridge *br)
7df32ca0	189	{
f055e96b	190	PCIDevice *pd = PCI_DEVICE(br);
fd56e061	191	PCIBus *parent = pci_get_bus(pd);
b2999ed8	192	PCIBridgeWindows *w = &br->windows;
f055e96b	193	uint16_t cmd = pci_get_word(pd->config + PCI_COMMAND);
7df32ca0	194
b308c82c	195	pci_bridge_init_alias(br, &w->alias_pref_mem,
7df32ca0 MT	196	PCI_BASE_ADDRESS_MEM_PREFETCH,
7df32ca0 MT	197	"pci_bridge_pref_mem",
336411ca	198	&br->address_space_mem,
7df32ca0 MT	199	parent->address_space_mem,
7df32ca0 MT	200	cmd & PCI_COMMAND_MEMORY);
b308c82c	201	pci_bridge_init_alias(br, &w->alias_mem,
7df32ca0 MT	202	PCI_BASE_ADDRESS_SPACE_MEMORY,
7df32ca0 MT	203	"pci_bridge_mem",
336411ca	204	&br->address_space_mem,
7df32ca0 MT	205	parent->address_space_mem,
7df32ca0 MT	206	cmd & PCI_COMMAND_MEMORY);
b308c82c	207	pci_bridge_init_alias(br, &w->alias_io,
7df32ca0 MT	208	PCI_BASE_ADDRESS_SPACE_IO,
7df32ca0 MT	209	"pci_bridge_io",
336411ca	210	&br->address_space_io,
7df32ca0 MT	211	parent->address_space_io,
7df32ca0 MT	212	cmd & PCI_COMMAND_IO);
ba7d8515 AW	213
ba7d8515 AW	214	pci_bridge_init_vga_aliases(br, parent, w->alias_vga);
7df32ca0 MT	215	}
7df32ca0 MT	216
b308c82c	217	static void pci_bridge_region_del(PCIBridge br, PCIBridgeWindows w)
7df32ca0	218	{
f055e96b	219	PCIDevice *pd = PCI_DEVICE(br);
fd56e061	220	PCIBus *parent = pci_get_bus(pd);
b308c82c AK	221
	222	memory_region_del_subregion(parent->address_space_io, &w->alias_io);
	223	memory_region_del_subregion(parent->address_space_mem, &w->alias_mem);
	224	memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem);
f055e96b	225	pci_unregister_vga(pd);
b308c82c AK	226	}
	227
	228	static void pci_bridge_region_cleanup(PCIBridge br, PCIBridgeWindows w)
	229	{
9f6b2f1c PB	230	object_unparent(OBJECT(&w->alias_io));
	231	object_unparent(OBJECT(&w->alias_mem));
	232	object_unparent(OBJECT(&w->alias_pref_mem));
	233	object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_LO]));
	234	object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_HI]));
	235	object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_MEM]));
7df32ca0 MT	236	}
7df32ca0 MT	237
e78e9ae4	238	void pci_bridge_update_mappings(PCIBridge *br)
7df32ca0	239	{
b2999ed8	240	PCIBridgeWindows *w = &br->windows;
b308c82c	241
7df32ca0 MT	242	/* Make updates atomic to: handle the case of one VCPU updating the bridge
	243	* while another accesses an unaffected region. */
	244	memory_region_transaction_begin();
b2999ed8	245	pci_bridge_region_del(br, w);
e7176cdb	246	pci_bridge_region_cleanup(br, w);
b2999ed8	247	pci_bridge_region_init(br);
7df32ca0 MT	248	memory_region_transaction_commit();
	249	}
	250
68f79994 IY	251	/* default write_config function for PCI-to-PCI bridge */
68f79994 IY	252	void pci_bridge_write_config(PCIDevice *d,
783753fd IY	253	uint32_t address, uint32_t val, int len)
783753fd IY	254	{
f055e96b	255	PCIBridge *s = PCI_BRIDGE(d);
a5fce077 IY	256	uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
	257	uint16_t newctl;
	258
783753fd IY	259	pci_default_write_config(d, address, val, len);
783753fd IY	260
7df32ca0 MT	261	if (ranges_overlap(address, len, PCI_COMMAND, 2) \|\|
	262
	263	/* io base/limit */
783753fd IY	264	ranges_overlap(address, len, PCI_IO_BASE, 2) \|\|
	265
	266	/* memory base/limit, prefetchable base/limit and
	267	io base/limit upper 16 */
ba7d8515 AW	268	ranges_overlap(address, len, PCI_MEMORY_BASE, 20) \|\|
	269
	270	/* vga enable */
	271	ranges_overlap(address, len, PCI_BRIDGE_CONTROL, 2)) {
7df32ca0	272	pci_bridge_update_mappings(s);
783753fd	273	}
a5fce077 IY	274
	275	newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
	276	if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {
	277	/* Trigger hot reset on 0->1 transition. */
78e4d5cb	278	bus_cold_reset(BUS(&s->sec_bus));
a5fce077	279	}
783753fd IY	280	}
783753fd IY	281
0208def1 IY	282	void pci_bridge_disable_base_limit(PCIDevice *dev)
	283	{
	284	uint8_t *conf = dev->config;
	285
	286	pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
	287	PCI_IO_RANGE_MASK & 0xff);
	288	pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
	289	PCI_IO_RANGE_MASK & 0xff);
	290	pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE,
	291	PCI_MEMORY_RANGE_MASK & 0xffff);
	292	pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
	293	PCI_MEMORY_RANGE_MASK & 0xffff);
	294	pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE,
	295	PCI_PREF_RANGE_MASK & 0xffff);
	296	pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
	297	PCI_PREF_RANGE_MASK & 0xffff);
cd7898f7 MT	298	pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
cd7898f7 MT	299	pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
0208def1 IY	300	}
0208def1 IY	301
68f79994	302	/* reset bridge specific configuration registers */
cbd2d434	303	void pci_bridge_reset(DeviceState *qdev)
68f79994	304	{
cbd2d434	305	PCIDevice *dev = PCI_DEVICE(qdev);
68f79994 IY	306	uint8_t *conf = dev->config;
	307
	308	conf[PCI_PRIMARY_BUS] = 0;
	309	conf[PCI_SECONDARY_BUS] = 0;
	310	conf[PCI_SUBORDINATE_BUS] = 0;
	311	conf[PCI_SEC_LATENCY_TIMER] = 0;
	312
0208def1 IY	313	/*
0208def1 IY	314	* the default values for base/limit registers aren't specified
5892cfc7	315	* in the PCI-to-PCI-bridge spec. So we don't touch them here.
0208def1 IY	316	* Each implementation can override it.
	317	* typical implementation does
	318	* zero base/limit registers or
	319	* disable forwarding: pci_bridge_disable_base_limit()
	320	* If disable forwarding is wanted, call pci_bridge_disable_base_limit()
	321	* after this function.
	322	*/
	323	pci_byte_test_and_clear_mask(conf + PCI_IO_BASE,
	324	PCI_IO_RANGE_MASK & 0xff);
	325	pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
	326	PCI_IO_RANGE_MASK & 0xff);
	327	pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE,
	328	PCI_MEMORY_RANGE_MASK & 0xffff);
	329	pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
	330	PCI_MEMORY_RANGE_MASK & 0xffff);
	331	pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE,
	332	PCI_PREF_RANGE_MASK & 0xffff);
	333	pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
	334	PCI_PREF_RANGE_MASK & 0xffff);
cd7898f7 MT	335	pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
cd7898f7 MT	336	pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
68f79994 IY	337
	338	pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
	339	}
	340
68f79994	341	/* default qdev initialization function for PCI-to-PCI bridge */
9cfaa007	342	void pci_bridge_initfn(PCIDevice dev, const char typename)
68f79994	343	{
fd56e061	344	PCIBus *parent = pci_get_bus(dev);
f055e96b	345	PCIBridge *br = PCI_BRIDGE(dev);
68f79994	346	PCIBus *sec_bus = &br->sec_bus;
783753fd	347
95be1196 MT	348	pci_word_test_and_set_mask(dev->config + PCI_STATUS,
95be1196 MT	349	PCI_STATUS_66MHZ \| PCI_STATUS_FAST_BACK);
ba7d8515 AW	350
	351	/*
	352	* TODO: We implement VGA Enable in the Bridge Control Register
	353	* therefore per the PCI to PCI bridge spec we must also implement
	354	* VGA Palette Snooping. When done, set this bit writable:
	355	*
	356	* pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND,
	357	* PCI_COMMAND_VGA_PALETTE);
	358	*/
	359
783753fd IY	360	pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
	361	dev->config[PCI_HEADER_TYPE] =
	362	(dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) \|
	363	PCI_HEADER_TYPE_BRIDGE;
	364	pci_set_word(dev->config + PCI_SEC_STATUS,
	365	PCI_STATUS_66MHZ \| PCI_STATUS_FAST_BACK);
68f79994	366
8a3d80fa MT	367	/*
	368	* If we don't specify the name, the bus will be addressed as <id>.0, where
	369	* id is the device id.
	370	* Since PCI Bridge devices have a single bus each, we don't need the index:
	371	* let users address the bus using the device name.
	372	*/
	373	if (!br->bus_name && dev->qdev.id && *dev->qdev.id) {
7d37435b	374	br->bus_name = dev->qdev.id;
8a3d80fa MT	375	}
8a3d80fa MT	376
d637e1dc PM	377	qbus_init(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
d637e1dc PM	378	br->bus_name);
68f79994	379	sec_bus->parent_dev = dev;
659fefee	380	sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
336411ca	381	sec_bus->address_space_mem = &br->address_space_mem;
cf252e51	382	memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX);
336411ca	383	sec_bus->address_space_io = &br->address_space_io;
9cd1e97a	384	memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io",
2dc48da2	385	4 * GiB);
b2999ed8	386	pci_bridge_region_init(br);
68f79994 IY	387	QLIST_INIT(&sec_bus->child);
68f79994 IY	388	QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);
4565917b MT	389
	390	/* For express secondary buses, secondary latency timer is RO 0 */
	391	if (pci_bus_is_express(sec_bus) && !br->pcie_writeable_slt_bug) {
	392	dev->wmask[PCI_SEC_LATENCY_TIMER] = 0;
	393	}
783753fd IY	394	}
783753fd IY	395
68f79994	396	/* default qdev clean up function for PCI-to-PCI bridge */
f90c2bcd	397	void pci_bridge_exitfn(PCIDevice *pci_dev)
783753fd	398	{
f055e96b	399	PCIBridge *s = PCI_BRIDGE(pci_dev);
51a92333 IY	400	assert(QLIST_EMPTY(&s->sec_bus.child));
51a92333 IY	401	QLIST_REMOVE(&s->sec_bus, sibling);
b2999ed8 JC	402	pci_bridge_region_del(s, &s->windows);
b2999ed8 JC	403	pci_bridge_region_cleanup(s, &s->windows);
6780a22c	404	/* object_unparent() is called automatically during device deletion */
783753fd IY	405	}
783753fd IY	406
68f79994 IY	407	/*
68f79994 IY	408	* before qdev initialization(qdev_init()), this function sets bus_name and
d05eec73	409	* map_irq callback which are necessary for pci_bridge_initfn() to
68f79994 IY	410	* initialize bus.
	411	*/
	412	void pci_bridge_map_irq(PCIBridge br, const char bus_name,
	413	pci_map_irq_fn map_irq)
783753fd	414	{
68f79994 IY	415	br->map_irq = map_irq;
68f79994 IY	416	br->bus_name = bus_name;
783753fd	417	}
f055e96b	418
70e1ee59 AB	419
70e1ee59 AB	420	int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
9e899399	421	PCIResReserve res_reserve, Error **errp)
70e1ee59	422	{
9e899399 JL	423	if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
9e899399 JL	424	res_reserve.mem_pref_64 != (uint64_t)-1) {
70e1ee59 AB	425	error_setg(errp,
	426	"PCI resource reserve cap: PREF32 and PREF64 conflict");
	427	return -EINVAL;
	428	}
	429
9e899399	430	if (res_reserve.mem_non_pref != (uint64_t)-1 &&
37e7211c	431	res_reserve.mem_non_pref >= 4 * GiB) {
fc67208f MA	432	error_setg(errp,
	433	"PCI resource reserve cap: mem-reserve must be less than 4G");
	434	return -EINVAL;
	435	}
	436
9e899399	437	if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
37e7211c	438	res_reserve.mem_pref_32 >= 4 * GiB) {
fc67208f MA	439	error_setg(errp,
	440	"PCI resource reserve cap: pref32-reserve must be less than 4G");
	441	return -EINVAL;
	442	}
	443
9e899399 JL	444	if (res_reserve.bus == (uint32_t)-1 &&
	445	res_reserve.io == (uint64_t)-1 &&
	446	res_reserve.mem_non_pref == (uint64_t)-1 &&
	447	res_reserve.mem_pref_32 == (uint64_t)-1 &&
	448	res_reserve.mem_pref_64 == (uint64_t)-1) {
70e1ee59 AB	449	return 0;
	450	}
	451
	452	size_t cap_len = sizeof(PCIBridgeQemuCap);
	453	PCIBridgeQemuCap cap = {
	454	.len = cap_len,
	455	.type = REDHAT_PCI_CAP_RESOURCE_RESERVE,
0e464f7d MT	456	.bus_res = cpu_to_le32(res_reserve.bus),
	457	.io = cpu_to_le64(res_reserve.io),
	458	.mem = cpu_to_le32(res_reserve.mem_non_pref),
	459	.mem_pref_32 = cpu_to_le32(res_reserve.mem_pref_32),
	460	.mem_pref_64 = cpu_to_le64(res_reserve.mem_pref_64)
70e1ee59 AB	461	};
	462
	463	int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,
	464	cap_offset, cap_len, errp);
	465	if (offset < 0) {
	466	return offset;
	467	}
	468
	469	memcpy(dev->config + offset + PCI_CAP_FLAGS,
	470	(char *)&cap + PCI_CAP_FLAGS,
	471	cap_len - PCI_CAP_FLAGS);
	472	return 0;
	473	}
	474
4565917b MT	475	static Property pci_bridge_properties[] = {
	476	DEFINE_PROP_BOOL("x-pci-express-writeable-slt-bug", PCIBridge,
	477	pcie_writeable_slt_bug, false),
	478	DEFINE_PROP_END_OF_LIST(),
	479	};
	480
6c36ec46 IM	481	static void pci_bridge_class_init(ObjectClass klass, void data)
	482	{
	483	AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
4565917b	484	DeviceClass *k = DEVICE_CLASS(klass);
6c36ec46	485
4565917b	486	device_class_set_props(k, pci_bridge_properties);
6c36ec46 IM	487	adevc->build_dev_aml = build_pci_bridge_aml;
	488	}
	489
f055e96b AF	490	static const TypeInfo pci_bridge_type_info = {
	491	.name = TYPE_PCI_BRIDGE,
	492	.parent = TYPE_PCI_DEVICE,
	493	.instance_size = sizeof(PCIBridge),
6c36ec46	494	.class_init = pci_bridge_class_init,
f055e96b	495	.abstract = true,
d78644c7 IM	496	.interfaces = (InterfaceInfo[]) {
	497	{ TYPE_ACPI_DEV_AML_IF },
	498	{ },
	499	},
f055e96b AF	500	};
	501
	502	static void pci_bridge_register_types(void)
	503	{
	504	type_register_static(&pci_bridge_type_info);
	505	}
	506
	507	type_init(pci_bridge_register_types)