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faf1e708 IY |
1 | /* |
2 | * xio3130_upstream.c | |
3 | * TI X3130 pci express upstream port switch | |
4 | * | |
5 | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> | |
6 | * VA Linux Systems Japan K.K. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along | |
19 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
97d5408f | 22 | #include "qemu/osdep.h" |
83c9f4ca PB |
23 | #include "hw/pci/pci_ids.h" |
24 | #include "hw/pci/msi.h" | |
25 | #include "hw/pci/pcie.h" | |
47b43a1f | 26 | #include "xio3130_upstream.h" |
1108b2f8 | 27 | #include "qapi/error.h" |
faf1e708 IY |
28 | |
29 | #define PCI_DEVICE_ID_TI_XIO3130U 0x8232 /* upstream port */ | |
30 | #define XIO3130_REVISION 0x2 | |
31 | #define XIO3130_MSI_OFFSET 0x70 | |
32 | #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT | |
33 | #define XIO3130_MSI_NR_VECTOR 1 | |
34 | #define XIO3130_SSVID_OFFSET 0x80 | |
35 | #define XIO3130_SSVID_SVID 0 | |
36 | #define XIO3130_SSVID_SSID 0 | |
37 | #define XIO3130_EXP_OFFSET 0x90 | |
38 | #define XIO3130_AER_OFFSET 0x100 | |
39 | ||
40 | static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address, | |
41 | uint32_t val, int len) | |
42 | { | |
43 | pci_bridge_write_config(d, address, val, len); | |
44 | pcie_cap_flr_write_config(d, address, val, len); | |
a158f92f | 45 | pcie_aer_write_config(d, address, val, len); |
faf1e708 IY |
46 | } |
47 | ||
48 | static void xio3130_upstream_reset(DeviceState *qdev) | |
49 | { | |
40021f08 | 50 | PCIDevice *d = PCI_DEVICE(qdev); |
cbd2d434 | 51 | |
faf1e708 IY |
52 | pci_bridge_reset(qdev); |
53 | pcie_cap_deverr_reset(d); | |
54 | } | |
55 | ||
56 | static int xio3130_upstream_initfn(PCIDevice *d) | |
57 | { | |
bcb75750 | 58 | PCIEPort *p = PCIE_PORT(d); |
faf1e708 | 59 | int rc; |
1108b2f8 | 60 | Error *err = NULL; |
faf1e708 | 61 | |
9cfaa007 | 62 | pci_bridge_initfn(d, TYPE_PCIE_BUS); |
faf1e708 | 63 | pcie_port_init_reg(d); |
faf1e708 IY |
64 | |
65 | rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, | |
66 | XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, | |
1108b2f8 | 67 | XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, &err); |
faf1e708 | 68 | if (rc < 0) { |
1108b2f8 C |
69 | assert(rc == -ENOTSUP); |
70 | error_report_err(err); | |
a158f92f | 71 | goto err_bridge; |
faf1e708 | 72 | } |
52ea63de | 73 | |
faf1e708 IY |
74 | rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, |
75 | XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); | |
76 | if (rc < 0) { | |
a158f92f | 77 | goto err_bridge; |
faf1e708 | 78 | } |
52ea63de | 79 | |
faf1e708 IY |
80 | rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, |
81 | p->port); | |
82 | if (rc < 0) { | |
a158f92f | 83 | goto err_msi; |
faf1e708 | 84 | } |
faf1e708 | 85 | pcie_cap_flr_init(d); |
faf1e708 | 86 | pcie_cap_deverr_init(d); |
52ea63de | 87 | |
f18c697b DL |
88 | rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET, |
89 | PCI_ERR_SIZEOF, &err); | |
a158f92f | 90 | if (rc < 0) { |
33848cee | 91 | error_report_err(err); |
a158f92f IY |
92 | goto err; |
93 | } | |
faf1e708 IY |
94 | |
95 | return 0; | |
a158f92f IY |
96 | |
97 | err: | |
98 | pcie_cap_exit(d); | |
99 | err_msi: | |
100 | msi_uninit(d); | |
101 | err_bridge: | |
f90c2bcd | 102 | pci_bridge_exitfn(d); |
a158f92f | 103 | return rc; |
faf1e708 IY |
104 | } |
105 | ||
f90c2bcd | 106 | static void xio3130_upstream_exitfn(PCIDevice *d) |
faf1e708 | 107 | { |
a158f92f | 108 | pcie_aer_exit(d); |
faf1e708 | 109 | pcie_cap_exit(d); |
a158f92f | 110 | msi_uninit(d); |
f90c2bcd | 111 | pci_bridge_exitfn(d); |
faf1e708 IY |
112 | } |
113 | ||
114 | PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction, | |
115 | const char *bus_name, pci_map_irq_fn map_irq, | |
116 | uint8_t port) | |
117 | { | |
118 | PCIDevice *d; | |
119 | PCIBridge *br; | |
120 | DeviceState *qdev; | |
121 | ||
122 | d = pci_create_multifunction(bus, devfn, multifunction, "x3130-upstream"); | |
123 | if (!d) { | |
124 | return NULL; | |
125 | } | |
f055e96b | 126 | br = PCI_BRIDGE(d); |
faf1e708 | 127 | |
f055e96b | 128 | qdev = DEVICE(d); |
faf1e708 IY |
129 | pci_bridge_map_irq(br, bus_name, map_irq); |
130 | qdev_prop_set_uint8(qdev, "port", port); | |
131 | qdev_init_nofail(qdev); | |
132 | ||
bcb75750 | 133 | return PCIE_PORT(d); |
faf1e708 IY |
134 | } |
135 | ||
136 | static const VMStateDescription vmstate_xio3130_upstream = { | |
137 | .name = "xio3130-express-upstream-port", | |
138 | .version_id = 1, | |
139 | .minimum_version_id = 1, | |
faf1e708 | 140 | .fields = (VMStateField[]) { |
20daa90a | 141 | VMSTATE_PCI_DEVICE(parent_obj.parent_obj, PCIEPort), |
bcb75750 | 142 | VMSTATE_STRUCT(parent_obj.parent_obj.exp.aer_log, PCIEPort, 0, |
f055e96b | 143 | vmstate_pcie_aer_log, PCIEAERLog), |
faf1e708 IY |
144 | VMSTATE_END_OF_LIST() |
145 | } | |
146 | }; | |
147 | ||
40021f08 AL |
148 | static void xio3130_upstream_class_init(ObjectClass *klass, void *data) |
149 | { | |
39bffca2 | 150 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
151 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
152 | ||
153 | k->is_express = 1; | |
154 | k->is_bridge = 1; | |
155 | k->config_write = xio3130_upstream_write_config; | |
156 | k->init = xio3130_upstream_initfn; | |
157 | k->exit = xio3130_upstream_exitfn; | |
158 | k->vendor_id = PCI_VENDOR_ID_TI; | |
159 | k->device_id = PCI_DEVICE_ID_TI_XIO3130U; | |
160 | k->revision = XIO3130_REVISION; | |
125ee0ed | 161 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
39bffca2 AL |
162 | dc->desc = "TI X3130 Upstream Port of PCI Express Switch"; |
163 | dc->reset = xio3130_upstream_reset; | |
164 | dc->vmsd = &vmstate_xio3130_upstream; | |
40021f08 AL |
165 | } |
166 | ||
8c43a6f0 | 167 | static const TypeInfo xio3130_upstream_info = { |
39bffca2 | 168 | .name = "x3130-upstream", |
bcb75750 | 169 | .parent = TYPE_PCIE_PORT, |
39bffca2 | 170 | .class_init = xio3130_upstream_class_init, |
faf1e708 IY |
171 | }; |
172 | ||
83f7d43a | 173 | static void xio3130_upstream_register_types(void) |
faf1e708 | 174 | { |
39bffca2 | 175 | type_register_static(&xio3130_upstream_info); |
faf1e708 IY |
176 | } |
177 | ||
83f7d43a | 178 | type_init(xio3130_upstream_register_types) |