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Commit | Line | Data |
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69b91039 FB |
1 | /* |
2 | * QEMU PCI bus manager | |
3 | * | |
4 | * Copyright (c) 2004 Fabrice Bellard | |
5fafdf24 | 5 | * |
69b91039 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
376253ec | 26 | #include "monitor.h" |
87ecb68b | 27 | #include "net.h" |
880345c4 | 28 | #include "sysemu.h" |
69b91039 FB |
29 | |
30 | //#define DEBUG_PCI | |
31 | ||
30468f78 | 32 | struct PCIBus { |
02e2da45 | 33 | BusState qbus; |
30468f78 FB |
34 | int bus_num; |
35 | int devfn_min; | |
502a5395 | 36 | pci_set_irq_fn set_irq; |
d2b59317 | 37 | pci_map_irq_fn map_irq; |
30468f78 | 38 | uint32_t config_reg; /* XXX: suppress */ |
384d8876 FB |
39 | /* low level pic */ |
40 | SetIRQFunc *low_set_irq; | |
d537cf6c | 41 | qemu_irq *irq_opaque; |
30468f78 | 42 | PCIDevice *devices[256]; |
80b3ada7 PB |
43 | PCIDevice *parent_dev; |
44 | PCIBus *next; | |
d2b59317 PB |
45 | /* The bus IRQ state is the logical OR of the connected devices. |
46 | Keep a count of the number of devices with raised IRQs. */ | |
52fc1d83 | 47 | int nirq; |
80b3ada7 | 48 | int irq_count[]; |
30468f78 | 49 | }; |
69b91039 | 50 | |
1941d19c | 51 | static void pci_update_mappings(PCIDevice *d); |
d537cf6c | 52 | static void pci_set_irq(void *opaque, int irq_num, int level); |
1941d19c | 53 | |
69b91039 | 54 | target_phys_addr_t pci_mem_base; |
d350d97d AL |
55 | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; |
56 | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; | |
30468f78 FB |
57 | static PCIBus *first_bus; |
58 | ||
52fc1d83 AZ |
59 | static void pcibus_save(QEMUFile *f, void *opaque) |
60 | { | |
61 | PCIBus *bus = (PCIBus *)opaque; | |
62 | int i; | |
63 | ||
64 | qemu_put_be32(f, bus->nirq); | |
65 | for (i = 0; i < bus->nirq; i++) | |
66 | qemu_put_be32(f, bus->irq_count[i]); | |
67 | } | |
68 | ||
69 | static int pcibus_load(QEMUFile *f, void *opaque, int version_id) | |
70 | { | |
71 | PCIBus *bus = (PCIBus *)opaque; | |
72 | int i, nirq; | |
73 | ||
74 | if (version_id != 1) | |
75 | return -EINVAL; | |
76 | ||
77 | nirq = qemu_get_be32(f); | |
78 | if (bus->nirq != nirq) { | |
79 | fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n", | |
80 | nirq, bus->nirq); | |
81 | return -EINVAL; | |
82 | } | |
83 | ||
84 | for (i = 0; i < nirq; i++) | |
85 | bus->irq_count[i] = qemu_get_be32(f); | |
86 | ||
87 | return 0; | |
88 | } | |
89 | ||
6eaa6847 GN |
90 | static void pci_bus_reset(void *opaque) |
91 | { | |
92 | PCIBus *bus = (PCIBus *)opaque; | |
93 | int i; | |
94 | ||
95 | for (i = 0; i < bus->nirq; i++) { | |
96 | bus->irq_count[i] = 0; | |
97 | } | |
98 | for (i = 0; i < 256; i++) { | |
99 | if (bus->devices[i]) | |
100 | memset(bus->devices[i]->irq_state, 0, | |
101 | sizeof(bus->devices[i]->irq_state)); | |
102 | } | |
103 | } | |
104 | ||
02e2da45 PB |
105 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
106 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
d537cf6c | 107 | qemu_irq *pic, int devfn_min, int nirq) |
30468f78 FB |
108 | { |
109 | PCIBus *bus; | |
52fc1d83 AZ |
110 | static int nbus = 0; |
111 | ||
02e2da45 PB |
112 | bus = FROM_QBUS(PCIBus, qbus_create(BUS_TYPE_PCI, |
113 | sizeof(PCIBus) + (nirq * sizeof(int)), | |
114 | parent, name)); | |
502a5395 | 115 | bus->set_irq = set_irq; |
d2b59317 | 116 | bus->map_irq = map_irq; |
502a5395 PB |
117 | bus->irq_opaque = pic; |
118 | bus->devfn_min = devfn_min; | |
52fc1d83 | 119 | bus->nirq = nirq; |
425c608c | 120 | bus->next = first_bus; |
30468f78 | 121 | first_bus = bus; |
52fc1d83 | 122 | register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus); |
a08d4367 | 123 | qemu_register_reset(pci_bus_reset, bus); |
30468f78 FB |
124 | return bus; |
125 | } | |
69b91039 | 126 | |
9596ebb7 | 127 | static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq) |
80b3ada7 PB |
128 | { |
129 | PCIBus *bus; | |
130 | bus = qemu_mallocz(sizeof(PCIBus)); | |
131 | bus->map_irq = map_irq; | |
132 | bus->parent_dev = dev; | |
133 | bus->next = dev->bus->next; | |
134 | dev->bus->next = bus; | |
135 | return bus; | |
136 | } | |
137 | ||
502a5395 PB |
138 | int pci_bus_num(PCIBus *s) |
139 | { | |
140 | return s->bus_num; | |
141 | } | |
142 | ||
1941d19c | 143 | void pci_device_save(PCIDevice *s, QEMUFile *f) |
30ca2aab | 144 | { |
52fc1d83 AZ |
145 | int i; |
146 | ||
147 | qemu_put_be32(f, 2); /* PCI device version */ | |
30ca2aab | 148 | qemu_put_buffer(f, s->config, 256); |
52fc1d83 AZ |
149 | for (i = 0; i < 4; i++) |
150 | qemu_put_be32(f, s->irq_state[i]); | |
30ca2aab FB |
151 | } |
152 | ||
1941d19c | 153 | int pci_device_load(PCIDevice *s, QEMUFile *f) |
30ca2aab | 154 | { |
bd4b65ee | 155 | uint8_t config[PCI_CONFIG_SPACE_SIZE]; |
1941d19c | 156 | uint32_t version_id; |
52fc1d83 AZ |
157 | int i; |
158 | ||
1941d19c | 159 | version_id = qemu_get_be32(f); |
52fc1d83 | 160 | if (version_id > 2) |
30ca2aab | 161 | return -EINVAL; |
bd4b65ee MT |
162 | qemu_get_buffer(f, config, sizeof config); |
163 | for (i = 0; i < sizeof config; ++i) | |
164 | if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) | |
165 | return -EINVAL; | |
166 | memcpy(s->config, config, sizeof config); | |
167 | ||
1941d19c | 168 | pci_update_mappings(s); |
52fc1d83 AZ |
169 | |
170 | if (version_id >= 2) | |
171 | for (i = 0; i < 4; i ++) | |
172 | s->irq_state[i] = qemu_get_be32(f); | |
30ca2aab FB |
173 | return 0; |
174 | } | |
175 | ||
d350d97d AL |
176 | static int pci_set_default_subsystem_id(PCIDevice *pci_dev) |
177 | { | |
178 | uint16_t *id; | |
179 | ||
180 | id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]); | |
181 | id[0] = cpu_to_le16(pci_default_sub_vendor_id); | |
182 | id[1] = cpu_to_le16(pci_default_sub_device_id); | |
183 | return 0; | |
184 | } | |
185 | ||
880345c4 AL |
186 | /* |
187 | * Parse [[<domain>:]<bus>:]<slot>, return -1 on error | |
188 | */ | |
189 | static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) | |
190 | { | |
191 | const char *p; | |
192 | char *e; | |
193 | unsigned long val; | |
194 | unsigned long dom = 0, bus = 0; | |
195 | unsigned slot = 0; | |
196 | ||
197 | p = addr; | |
198 | val = strtoul(p, &e, 16); | |
199 | if (e == p) | |
200 | return -1; | |
201 | if (*e == ':') { | |
202 | bus = val; | |
203 | p = e + 1; | |
204 | val = strtoul(p, &e, 16); | |
205 | if (e == p) | |
206 | return -1; | |
207 | if (*e == ':') { | |
208 | dom = bus; | |
209 | bus = val; | |
210 | p = e + 1; | |
211 | val = strtoul(p, &e, 16); | |
212 | if (e == p) | |
213 | return -1; | |
214 | } | |
215 | } | |
216 | ||
217 | if (dom > 0xffff || bus > 0xff || val > 0x1f) | |
218 | return -1; | |
219 | ||
220 | slot = val; | |
221 | ||
222 | if (*e) | |
223 | return -1; | |
224 | ||
225 | /* Note: QEMU doesn't implement domains other than 0 */ | |
226 | if (dom != 0 || pci_find_bus(bus) == NULL) | |
227 | return -1; | |
228 | ||
229 | *domp = dom; | |
230 | *busp = bus; | |
231 | *slotp = slot; | |
232 | return 0; | |
233 | } | |
234 | ||
e9283f8b JK |
235 | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
236 | unsigned *slotp) | |
880345c4 | 237 | { |
e9283f8b JK |
238 | /* strip legacy tag */ |
239 | if (!strncmp(addr, "pci_addr=", 9)) { | |
240 | addr += 9; | |
241 | } | |
242 | if (pci_parse_devaddr(addr, domp, busp, slotp)) { | |
243 | monitor_printf(mon, "Invalid pci address\n"); | |
880345c4 | 244 | return -1; |
e9283f8b JK |
245 | } |
246 | return 0; | |
880345c4 AL |
247 | } |
248 | ||
5607c388 MA |
249 | static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
250 | { | |
251 | int dom, bus; | |
252 | unsigned slot; | |
253 | ||
254 | if (!devaddr) { | |
255 | *devfnp = -1; | |
256 | return pci_find_bus(0); | |
257 | } | |
258 | ||
259 | if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) { | |
260 | return NULL; | |
261 | } | |
262 | ||
263 | *devfnp = slot << 3; | |
264 | return pci_find_bus(bus); | |
265 | } | |
266 | ||
bd4b65ee MT |
267 | static void pci_init_cmask(PCIDevice *dev) |
268 | { | |
269 | pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); | |
270 | pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); | |
271 | dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; | |
272 | dev->cmask[PCI_REVISION_ID] = 0xff; | |
273 | dev->cmask[PCI_CLASS_PROG] = 0xff; | |
274 | pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); | |
275 | dev->cmask[PCI_HEADER_TYPE] = 0xff; | |
276 | dev->cmask[PCI_CAPABILITY_LIST] = 0xff; | |
277 | } | |
278 | ||
b7ee1603 MT |
279 | static void pci_init_wmask(PCIDevice *dev) |
280 | { | |
281 | int i; | |
282 | dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; | |
283 | dev->wmask[PCI_INTERRUPT_LINE] = 0xff; | |
284 | dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
285 | | PCI_COMMAND_MASTER; | |
286 | for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) | |
287 | dev->wmask[i] = 0xff; | |
288 | } | |
289 | ||
69b91039 | 290 | /* -1 for devfn means auto assign */ |
6b1b92d3 PB |
291 | static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, |
292 | const char *name, int devfn, | |
293 | PCIConfigReadFunc *config_read, | |
294 | PCIConfigWriteFunc *config_write) | |
69b91039 | 295 | { |
69b91039 | 296 | if (devfn < 0) { |
30468f78 FB |
297 | for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
298 | if (!bus->devices[devfn]) | |
69b91039 FB |
299 | goto found; |
300 | } | |
301 | return NULL; | |
302 | found: ; | |
07b7d053 MA |
303 | } else if (bus->devices[devfn]) { |
304 | return NULL; | |
69b91039 | 305 | } |
30468f78 | 306 | pci_dev->bus = bus; |
69b91039 FB |
307 | pci_dev->devfn = devfn; |
308 | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); | |
d2b59317 | 309 | memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); |
d350d97d | 310 | pci_set_default_subsystem_id(pci_dev); |
bd4b65ee | 311 | pci_init_cmask(pci_dev); |
b7ee1603 | 312 | pci_init_wmask(pci_dev); |
0ac32c83 FB |
313 | |
314 | if (!config_read) | |
315 | config_read = pci_default_read_config; | |
316 | if (!config_write) | |
317 | config_write = pci_default_write_config; | |
69b91039 FB |
318 | pci_dev->config_read = config_read; |
319 | pci_dev->config_write = config_write; | |
30468f78 | 320 | bus->devices[devfn] = pci_dev; |
d537cf6c | 321 | pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4); |
69b91039 FB |
322 | return pci_dev; |
323 | } | |
324 | ||
6b1b92d3 PB |
325 | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
326 | int instance_size, int devfn, | |
327 | PCIConfigReadFunc *config_read, | |
328 | PCIConfigWriteFunc *config_write) | |
329 | { | |
330 | PCIDevice *pci_dev; | |
331 | ||
332 | pci_dev = qemu_mallocz(instance_size); | |
333 | pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, | |
334 | config_read, config_write); | |
335 | return pci_dev; | |
336 | } | |
5851e08c AL |
337 | static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr) |
338 | { | |
339 | return addr + pci_mem_base; | |
340 | } | |
341 | ||
342 | static void pci_unregister_io_regions(PCIDevice *pci_dev) | |
343 | { | |
344 | PCIIORegion *r; | |
345 | int i; | |
346 | ||
347 | for(i = 0; i < PCI_NUM_REGIONS; i++) { | |
348 | r = &pci_dev->io_regions[i]; | |
349 | if (!r->size || r->addr == -1) | |
350 | continue; | |
351 | if (r->type == PCI_ADDRESS_SPACE_IO) { | |
352 | isa_unassign_ioport(r->addr, r->size); | |
353 | } else { | |
354 | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), | |
355 | r->size, | |
356 | IO_MEM_UNASSIGNED); | |
357 | } | |
358 | } | |
359 | } | |
360 | ||
361 | int pci_unregister_device(PCIDevice *pci_dev) | |
362 | { | |
363 | int ret = 0; | |
364 | ||
365 | if (pci_dev->unregister) | |
366 | ret = pci_dev->unregister(pci_dev); | |
367 | if (ret) | |
368 | return ret; | |
369 | ||
370 | pci_unregister_io_regions(pci_dev); | |
371 | ||
372 | qemu_free_irqs(pci_dev->irq); | |
5851e08c | 373 | pci_dev->bus->devices[pci_dev->devfn] = NULL; |
02e2da45 | 374 | qdev_free(&pci_dev->qdev); |
5851e08c AL |
375 | return 0; |
376 | } | |
377 | ||
28c2c264 | 378 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
5fafdf24 | 379 | uint32_t size, int type, |
69b91039 FB |
380 | PCIMapIORegionFunc *map_func) |
381 | { | |
382 | PCIIORegion *r; | |
d7ce493a | 383 | uint32_t addr; |
b7ee1603 | 384 | uint32_t wmask; |
69b91039 | 385 | |
8a8696a3 | 386 | if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
69b91039 | 387 | return; |
a4c20c6a AL |
388 | |
389 | if (size & (size-1)) { | |
390 | fprintf(stderr, "ERROR: PCI region size must be pow2 " | |
391 | "type=0x%x, size=0x%x\n", type, size); | |
392 | exit(1); | |
393 | } | |
394 | ||
69b91039 FB |
395 | r = &pci_dev->io_regions[region_num]; |
396 | r->addr = -1; | |
397 | r->size = size; | |
398 | r->type = type; | |
399 | r->map_func = map_func; | |
b7ee1603 MT |
400 | |
401 | wmask = ~(size - 1); | |
d7ce493a PB |
402 | if (region_num == PCI_ROM_SLOT) { |
403 | addr = 0x30; | |
b7ee1603 MT |
404 | /* ROM enable bit is writeable */ |
405 | wmask |= 1; | |
d7ce493a PB |
406 | } else { |
407 | addr = 0x10 + region_num * 4; | |
408 | } | |
409 | *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type); | |
b7ee1603 | 410 | *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask); |
bd4b65ee | 411 | *(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff; |
69b91039 FB |
412 | } |
413 | ||
0ac32c83 FB |
414 | static void pci_update_mappings(PCIDevice *d) |
415 | { | |
416 | PCIIORegion *r; | |
417 | int cmd, i; | |
8a8696a3 | 418 | uint32_t last_addr, new_addr, config_ofs; |
3b46e624 | 419 | |
0ac32c83 | 420 | cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
8a8696a3 | 421 | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
0ac32c83 | 422 | r = &d->io_regions[i]; |
8a8696a3 FB |
423 | if (i == PCI_ROM_SLOT) { |
424 | config_ofs = 0x30; | |
425 | } else { | |
426 | config_ofs = 0x10 + i * 4; | |
427 | } | |
0ac32c83 FB |
428 | if (r->size != 0) { |
429 | if (r->type & PCI_ADDRESS_SPACE_IO) { | |
430 | if (cmd & PCI_COMMAND_IO) { | |
5fafdf24 | 431 | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
8a8696a3 | 432 | config_ofs)); |
0ac32c83 FB |
433 | new_addr = new_addr & ~(r->size - 1); |
434 | last_addr = new_addr + r->size - 1; | |
435 | /* NOTE: we have only 64K ioports on PC */ | |
436 | if (last_addr <= new_addr || new_addr == 0 || | |
437 | last_addr >= 0x10000) { | |
438 | new_addr = -1; | |
439 | } | |
440 | } else { | |
441 | new_addr = -1; | |
442 | } | |
443 | } else { | |
444 | if (cmd & PCI_COMMAND_MEMORY) { | |
5fafdf24 | 445 | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
8a8696a3 FB |
446 | config_ofs)); |
447 | /* the ROM slot has a specific enable bit */ | |
448 | if (i == PCI_ROM_SLOT && !(new_addr & 1)) | |
449 | goto no_mem_map; | |
0ac32c83 FB |
450 | new_addr = new_addr & ~(r->size - 1); |
451 | last_addr = new_addr + r->size - 1; | |
452 | /* NOTE: we do not support wrapping */ | |
453 | /* XXX: as we cannot support really dynamic | |
454 | mappings, we handle specific values as invalid | |
455 | mappings. */ | |
456 | if (last_addr <= new_addr || new_addr == 0 || | |
457 | last_addr == -1) { | |
458 | new_addr = -1; | |
459 | } | |
460 | } else { | |
8a8696a3 | 461 | no_mem_map: |
0ac32c83 FB |
462 | new_addr = -1; |
463 | } | |
464 | } | |
465 | /* now do the real mapping */ | |
466 | if (new_addr != r->addr) { | |
467 | if (r->addr != -1) { | |
468 | if (r->type & PCI_ADDRESS_SPACE_IO) { | |
469 | int class; | |
470 | /* NOTE: specific hack for IDE in PC case: | |
471 | only one byte must be mapped. */ | |
472 | class = d->config[0x0a] | (d->config[0x0b] << 8); | |
473 | if (class == 0x0101 && r->size == 4) { | |
474 | isa_unassign_ioport(r->addr + 2, 1); | |
475 | } else { | |
476 | isa_unassign_ioport(r->addr, r->size); | |
477 | } | |
478 | } else { | |
502a5395 | 479 | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
5fafdf24 | 480 | r->size, |
0ac32c83 | 481 | IO_MEM_UNASSIGNED); |
f65ed4c1 | 482 | qemu_unregister_coalesced_mmio(r->addr, r->size); |
0ac32c83 FB |
483 | } |
484 | } | |
485 | r->addr = new_addr; | |
486 | if (r->addr != -1) { | |
487 | r->map_func(d, i, r->addr, r->size, r->type); | |
488 | } | |
489 | } | |
490 | } | |
491 | } | |
492 | } | |
493 | ||
5fafdf24 | 494 | uint32_t pci_default_read_config(PCIDevice *d, |
0ac32c83 | 495 | uint32_t address, int len) |
69b91039 | 496 | { |
0ac32c83 | 497 | uint32_t val; |
a2d4e44b | 498 | |
0ac32c83 | 499 | switch(len) { |
0ac32c83 FB |
500 | default: |
501 | case 4: | |
a2d4e44b TS |
502 | if (address <= 0xfc) { |
503 | val = le32_to_cpu(*(uint32_t *)(d->config + address)); | |
504 | break; | |
505 | } | |
506 | /* fall through */ | |
507 | case 2: | |
508 | if (address <= 0xfe) { | |
509 | val = le16_to_cpu(*(uint16_t *)(d->config + address)); | |
510 | break; | |
511 | } | |
512 | /* fall through */ | |
513 | case 1: | |
514 | val = d->config[address]; | |
0ac32c83 FB |
515 | break; |
516 | } | |
517 | return val; | |
518 | } | |
519 | ||
b7ee1603 | 520 | void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
0ac32c83 | 521 | { |
b7ee1603 MT |
522 | uint8_t orig[PCI_CONFIG_SPACE_SIZE]; |
523 | int i; | |
0ac32c83 | 524 | |
0ac32c83 | 525 | /* not efficient, but simple */ |
b7ee1603 MT |
526 | memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE); |
527 | for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) { | |
528 | uint8_t wmask = d->wmask[addr]; | |
529 | d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask); | |
0ac32c83 | 530 | } |
b7ee1603 MT |
531 | if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24) |
532 | || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND]) | |
533 | & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO))) | |
0ac32c83 | 534 | pci_update_mappings(d); |
69b91039 FB |
535 | } |
536 | ||
502a5395 | 537 | void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) |
69b91039 | 538 | { |
30468f78 FB |
539 | PCIBus *s = opaque; |
540 | PCIDevice *pci_dev; | |
541 | int config_addr, bus_num; | |
3b46e624 | 542 | |
69b91039 FB |
543 | #if defined(DEBUG_PCI) && 0 |
544 | printf("pci_data_write: addr=%08x val=%08x len=%d\n", | |
502a5395 | 545 | addr, val, len); |
69b91039 | 546 | #endif |
502a5395 | 547 | bus_num = (addr >> 16) & 0xff; |
80b3ada7 PB |
548 | while (s && s->bus_num != bus_num) |
549 | s = s->next; | |
550 | if (!s) | |
69b91039 | 551 | return; |
502a5395 | 552 | pci_dev = s->devices[(addr >> 8) & 0xff]; |
69b91039 FB |
553 | if (!pci_dev) |
554 | return; | |
502a5395 | 555 | config_addr = addr & 0xff; |
69b91039 FB |
556 | #if defined(DEBUG_PCI) |
557 | printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n", | |
558 | pci_dev->name, config_addr, val, len); | |
559 | #endif | |
0ac32c83 | 560 | pci_dev->config_write(pci_dev, config_addr, val, len); |
69b91039 FB |
561 | } |
562 | ||
502a5395 | 563 | uint32_t pci_data_read(void *opaque, uint32_t addr, int len) |
69b91039 | 564 | { |
30468f78 FB |
565 | PCIBus *s = opaque; |
566 | PCIDevice *pci_dev; | |
567 | int config_addr, bus_num; | |
69b91039 FB |
568 | uint32_t val; |
569 | ||
502a5395 | 570 | bus_num = (addr >> 16) & 0xff; |
80b3ada7 PB |
571 | while (s && s->bus_num != bus_num) |
572 | s= s->next; | |
573 | if (!s) | |
69b91039 | 574 | goto fail; |
502a5395 | 575 | pci_dev = s->devices[(addr >> 8) & 0xff]; |
69b91039 FB |
576 | if (!pci_dev) { |
577 | fail: | |
63ce9e0a FB |
578 | switch(len) { |
579 | case 1: | |
580 | val = 0xff; | |
581 | break; | |
582 | case 2: | |
583 | val = 0xffff; | |
584 | break; | |
585 | default: | |
586 | case 4: | |
587 | val = 0xffffffff; | |
588 | break; | |
589 | } | |
69b91039 FB |
590 | goto the_end; |
591 | } | |
502a5395 | 592 | config_addr = addr & 0xff; |
69b91039 FB |
593 | val = pci_dev->config_read(pci_dev, config_addr, len); |
594 | #if defined(DEBUG_PCI) | |
595 | printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n", | |
596 | pci_dev->name, config_addr, val, len); | |
597 | #endif | |
598 | the_end: | |
599 | #if defined(DEBUG_PCI) && 0 | |
600 | printf("pci_data_read: addr=%08x val=%08x len=%d\n", | |
502a5395 | 601 | addr, val, len); |
69b91039 FB |
602 | #endif |
603 | return val; | |
604 | } | |
605 | ||
502a5395 PB |
606 | /***********************************************************/ |
607 | /* generic PCI irq support */ | |
30468f78 | 608 | |
502a5395 | 609 | /* 0 <= irq_num <= 3. level must be 0 or 1 */ |
d537cf6c | 610 | static void pci_set_irq(void *opaque, int irq_num, int level) |
69b91039 | 611 | { |
d537cf6c | 612 | PCIDevice *pci_dev = (PCIDevice *)opaque; |
80b3ada7 PB |
613 | PCIBus *bus; |
614 | int change; | |
3b46e624 | 615 | |
80b3ada7 PB |
616 | change = level - pci_dev->irq_state[irq_num]; |
617 | if (!change) | |
618 | return; | |
d2b59317 | 619 | |
d2b59317 | 620 | pci_dev->irq_state[irq_num] = level; |
5e966ce6 PB |
621 | for (;;) { |
622 | bus = pci_dev->bus; | |
80b3ada7 | 623 | irq_num = bus->map_irq(pci_dev, irq_num); |
5e966ce6 PB |
624 | if (bus->set_irq) |
625 | break; | |
80b3ada7 | 626 | pci_dev = bus->parent_dev; |
80b3ada7 PB |
627 | } |
628 | bus->irq_count[irq_num] += change; | |
d2b59317 | 629 | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); |
69b91039 FB |
630 | } |
631 | ||
502a5395 PB |
632 | /***********************************************************/ |
633 | /* monitor info on PCI */ | |
0ac32c83 | 634 | |
6650ee6d PB |
635 | typedef struct { |
636 | uint16_t class; | |
637 | const char *desc; | |
638 | } pci_class_desc; | |
639 | ||
09bc878a | 640 | static const pci_class_desc pci_class_descriptions[] = |
6650ee6d | 641 | { |
4ca9c76f | 642 | { 0x0100, "SCSI controller"}, |
6650ee6d | 643 | { 0x0101, "IDE controller"}, |
dcb5b19a TS |
644 | { 0x0102, "Floppy controller"}, |
645 | { 0x0103, "IPI controller"}, | |
646 | { 0x0104, "RAID controller"}, | |
647 | { 0x0106, "SATA controller"}, | |
648 | { 0x0107, "SAS controller"}, | |
649 | { 0x0180, "Storage controller"}, | |
6650ee6d | 650 | { 0x0200, "Ethernet controller"}, |
dcb5b19a TS |
651 | { 0x0201, "Token Ring controller"}, |
652 | { 0x0202, "FDDI controller"}, | |
653 | { 0x0203, "ATM controller"}, | |
654 | { 0x0280, "Network controller"}, | |
6650ee6d | 655 | { 0x0300, "VGA controller"}, |
dcb5b19a TS |
656 | { 0x0301, "XGA controller"}, |
657 | { 0x0302, "3D controller"}, | |
658 | { 0x0380, "Display controller"}, | |
659 | { 0x0400, "Video controller"}, | |
660 | { 0x0401, "Audio controller"}, | |
661 | { 0x0402, "Phone"}, | |
662 | { 0x0480, "Multimedia controller"}, | |
663 | { 0x0500, "RAM controller"}, | |
664 | { 0x0501, "Flash controller"}, | |
665 | { 0x0580, "Memory controller"}, | |
6650ee6d PB |
666 | { 0x0600, "Host bridge"}, |
667 | { 0x0601, "ISA bridge"}, | |
dcb5b19a TS |
668 | { 0x0602, "EISA bridge"}, |
669 | { 0x0603, "MC bridge"}, | |
6650ee6d | 670 | { 0x0604, "PCI bridge"}, |
dcb5b19a TS |
671 | { 0x0605, "PCMCIA bridge"}, |
672 | { 0x0606, "NUBUS bridge"}, | |
673 | { 0x0607, "CARDBUS bridge"}, | |
674 | { 0x0608, "RACEWAY bridge"}, | |
675 | { 0x0680, "Bridge"}, | |
6650ee6d PB |
676 | { 0x0c03, "USB controller"}, |
677 | { 0, NULL} | |
678 | }; | |
679 | ||
502a5395 | 680 | static void pci_info_device(PCIDevice *d) |
30468f78 | 681 | { |
376253ec | 682 | Monitor *mon = cur_mon; |
502a5395 PB |
683 | int i, class; |
684 | PCIIORegion *r; | |
09bc878a | 685 | const pci_class_desc *desc; |
30468f78 | 686 | |
376253ec AL |
687 | monitor_printf(mon, " Bus %2d, device %3d, function %d:\n", |
688 | d->bus->bus_num, d->devfn >> 3, d->devfn & 7); | |
502a5395 | 689 | class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
376253ec | 690 | monitor_printf(mon, " "); |
6650ee6d PB |
691 | desc = pci_class_descriptions; |
692 | while (desc->desc && class != desc->class) | |
693 | desc++; | |
694 | if (desc->desc) { | |
376253ec | 695 | monitor_printf(mon, "%s", desc->desc); |
6650ee6d | 696 | } else { |
376253ec | 697 | monitor_printf(mon, "Class %04x", class); |
72cc6cfe | 698 | } |
376253ec | 699 | monitor_printf(mon, ": PCI device %04x:%04x\n", |
502a5395 PB |
700 | le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
701 | le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); | |
30468f78 | 702 | |
502a5395 | 703 | if (d->config[PCI_INTERRUPT_PIN] != 0) { |
376253ec AL |
704 | monitor_printf(mon, " IRQ %d.\n", |
705 | d->config[PCI_INTERRUPT_LINE]); | |
30468f78 | 706 | } |
80b3ada7 | 707 | if (class == 0x0604) { |
376253ec | 708 | monitor_printf(mon, " BUS %d.\n", d->config[0x19]); |
80b3ada7 | 709 | } |
502a5395 PB |
710 | for(i = 0;i < PCI_NUM_REGIONS; i++) { |
711 | r = &d->io_regions[i]; | |
712 | if (r->size != 0) { | |
376253ec | 713 | monitor_printf(mon, " BAR%d: ", i); |
502a5395 | 714 | if (r->type & PCI_ADDRESS_SPACE_IO) { |
376253ec AL |
715 | monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n", |
716 | r->addr, r->addr + r->size - 1); | |
502a5395 | 717 | } else { |
376253ec AL |
718 | monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n", |
719 | r->addr, r->addr + r->size - 1); | |
502a5395 PB |
720 | } |
721 | } | |
77d4bc34 | 722 | } |
80b3ada7 PB |
723 | if (class == 0x0604 && d->config[0x19] != 0) { |
724 | pci_for_each_device(d->config[0x19], pci_info_device); | |
725 | } | |
384d8876 FB |
726 | } |
727 | ||
80b3ada7 | 728 | void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)) |
384d8876 | 729 | { |
502a5395 | 730 | PCIBus *bus = first_bus; |
384d8876 | 731 | PCIDevice *d; |
502a5395 | 732 | int devfn; |
3b46e624 | 733 | |
80b3ada7 PB |
734 | while (bus && bus->bus_num != bus_num) |
735 | bus = bus->next; | |
502a5395 PB |
736 | if (bus) { |
737 | for(devfn = 0; devfn < 256; devfn++) { | |
738 | d = bus->devices[devfn]; | |
739 | if (d) | |
740 | fn(d); | |
741 | } | |
f2aa58c6 | 742 | } |
f2aa58c6 FB |
743 | } |
744 | ||
376253ec | 745 | void pci_info(Monitor *mon) |
f2aa58c6 | 746 | { |
80b3ada7 | 747 | pci_for_each_device(0, pci_info_device); |
77d4bc34 | 748 | } |
a41b2ff2 | 749 | |
1f5f6638 | 750 | PCIDevice *pci_create(const char *name, const char *devaddr) |
5607c388 MA |
751 | { |
752 | PCIBus *bus; | |
753 | int devfn; | |
754 | DeviceState *dev; | |
755 | ||
756 | bus = pci_get_bus_devfn(&devfn, devaddr); | |
757 | if (!bus) { | |
758 | fprintf(stderr, "Invalid PCI device address %s for device %s\n", | |
759 | devaddr, name); | |
760 | exit(1); | |
761 | } | |
762 | ||
763 | dev = qdev_create(&bus->qbus, name); | |
764 | qdev_set_prop_int(dev, "devfn", devfn); | |
765 | return (PCIDevice *)dev; | |
766 | } | |
767 | ||
cb457d76 AL |
768 | static const char * const pci_nic_models[] = { |
769 | "ne2k_pci", | |
770 | "i82551", | |
771 | "i82557b", | |
772 | "i82559er", | |
773 | "rtl8139", | |
774 | "e1000", | |
775 | "pcnet", | |
776 | "virtio", | |
777 | NULL | |
778 | }; | |
779 | ||
9d07d757 PB |
780 | static const char * const pci_nic_names[] = { |
781 | "ne2k_pci", | |
782 | "i82551", | |
783 | "i82557b", | |
784 | "i82559er", | |
785 | "rtl8139", | |
786 | "e1000", | |
787 | "pcnet", | |
53c25cea | 788 | "virtio-net-pci", |
cb457d76 AL |
789 | NULL |
790 | }; | |
791 | ||
a41b2ff2 | 792 | /* Initialize a PCI NIC. */ |
5607c388 MA |
793 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
794 | const char *default_devaddr) | |
a41b2ff2 | 795 | { |
5607c388 MA |
796 | const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
797 | PCIDevice *pci_dev; | |
9d07d757 | 798 | DeviceState *dev; |
cb457d76 AL |
799 | int i; |
800 | ||
801 | qemu_check_nic_model_list(nd, pci_nic_models, default_model); | |
802 | ||
9d07d757 | 803 | for (i = 0; pci_nic_models[i]; i++) { |
72da4208 | 804 | if (strcmp(nd->model, pci_nic_models[i]) == 0) { |
5607c388 MA |
805 | pci_dev = pci_create(pci_nic_names[i], devaddr); |
806 | dev = &pci_dev->qdev; | |
9d07d757 PB |
807 | qdev_set_netdev(dev, nd); |
808 | qdev_init(dev); | |
809 | nd->private = dev; | |
5607c388 | 810 | return pci_dev; |
72da4208 | 811 | } |
9d07d757 | 812 | } |
72da4208 AL |
813 | |
814 | return NULL; | |
a41b2ff2 PB |
815 | } |
816 | ||
80b3ada7 PB |
817 | typedef struct { |
818 | PCIDevice dev; | |
819 | PCIBus *bus; | |
820 | } PCIBridge; | |
821 | ||
9596ebb7 | 822 | static void pci_bridge_write_config(PCIDevice *d, |
80b3ada7 PB |
823 | uint32_t address, uint32_t val, int len) |
824 | { | |
825 | PCIBridge *s = (PCIBridge *)d; | |
826 | ||
80b3ada7 | 827 | pci_default_write_config(d, address, val, len); |
b7ee1603 | 828 | s->bus->bus_num = d->config[PCI_SECONDARY_BUS]; |
80b3ada7 PB |
829 | } |
830 | ||
3ae80618 AL |
831 | PCIBus *pci_find_bus(int bus_num) |
832 | { | |
833 | PCIBus *bus = first_bus; | |
834 | ||
835 | while (bus && bus->bus_num != bus_num) | |
836 | bus = bus->next; | |
837 | ||
838 | return bus; | |
839 | } | |
840 | ||
841 | PCIDevice *pci_find_device(int bus_num, int slot, int function) | |
842 | { | |
843 | PCIBus *bus = pci_find_bus(bus_num); | |
844 | ||
845 | if (!bus) | |
846 | return NULL; | |
847 | ||
848 | return bus->devices[PCI_DEVFN(slot, function)]; | |
849 | } | |
850 | ||
480b9f24 | 851 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did, |
80b3ada7 PB |
852 | pci_map_irq_fn map_irq, const char *name) |
853 | { | |
854 | PCIBridge *s; | |
5fafdf24 | 855 | s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge), |
80b3ada7 | 856 | devfn, NULL, pci_bridge_write_config); |
480b9f24 BS |
857 | |
858 | pci_config_set_vendor_id(s->dev.config, vid); | |
859 | pci_config_set_device_id(s->dev.config, did); | |
860 | ||
80b3ada7 PB |
861 | s->dev.config[0x04] = 0x06; // command = bus master, pci mem |
862 | s->dev.config[0x05] = 0x00; | |
863 | s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
864 | s->dev.config[0x07] = 0x00; // status = fast devsel | |
865 | s->dev.config[0x08] = 0x00; // revision | |
866 | s->dev.config[0x09] = 0x00; // programming i/f | |
173a543b | 867 | pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI); |
80b3ada7 | 868 | s->dev.config[0x0D] = 0x10; // latency_timer |
6407f373 IY |
869 | s->dev.config[PCI_HEADER_TYPE] = |
870 | PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type | |
80b3ada7 PB |
871 | s->dev.config[0x1E] = 0xa0; // secondary status |
872 | ||
873 | s->bus = pci_register_secondary_bus(&s->dev, map_irq); | |
874 | return s->bus; | |
875 | } | |
6b1b92d3 | 876 | |
02e2da45 PB |
877 | typedef struct { |
878 | DeviceInfo qdev; | |
879 | pci_qdev_initfn init; | |
880 | } PCIDeviceInfo; | |
881 | ||
882 | static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base) | |
6b1b92d3 PB |
883 | { |
884 | PCIDevice *pci_dev = (PCIDevice *)qdev; | |
02e2da45 | 885 | PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev); |
6b1b92d3 PB |
886 | PCIBus *bus; |
887 | int devfn; | |
888 | ||
02e2da45 | 889 | bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
6b1b92d3 PB |
890 | devfn = qdev_get_prop_int(qdev, "devfn", -1); |
891 | pci_dev = do_pci_register_device(pci_dev, bus, "FIXME", devfn, | |
892 | NULL, NULL);//FIXME:config_read, config_write); | |
893 | assert(pci_dev); | |
02e2da45 | 894 | info->init(pci_dev); |
6b1b92d3 PB |
895 | } |
896 | ||
897 | void pci_qdev_register(const char *name, int size, pci_qdev_initfn init) | |
898 | { | |
02e2da45 PB |
899 | PCIDeviceInfo *info; |
900 | ||
901 | info = qemu_mallocz(sizeof(*info)); | |
074f2fff GH |
902 | info->qdev.name = qemu_strdup(name); |
903 | info->qdev.size = size; | |
02e2da45 PB |
904 | info->init = init; |
905 | info->qdev.init = pci_qdev_init; | |
906 | info->qdev.bus_type = BUS_TYPE_PCI; | |
907 | ||
074f2fff | 908 | qdev_register(&info->qdev); |
6b1b92d3 PB |
909 | } |
910 | ||
911 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) | |
912 | { | |
913 | DeviceState *dev; | |
914 | ||
02e2da45 | 915 | dev = qdev_create(&bus->qbus, name); |
6b1b92d3 PB |
916 | qdev_set_prop_int(dev, "devfn", devfn); |
917 | qdev_init(dev); | |
918 | ||
919 | return (PCIDevice *)dev; | |
920 | } | |
6f4cbd39 MT |
921 | |
922 | static int pci_find_space(PCIDevice *pdev, uint8_t size) | |
923 | { | |
924 | int offset = PCI_CONFIG_HEADER_SIZE; | |
925 | int i; | |
926 | for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) | |
927 | if (pdev->used[i]) | |
928 | offset = i + 1; | |
929 | else if (i - offset + 1 == size) | |
930 | return offset; | |
931 | return 0; | |
932 | } | |
933 | ||
934 | static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, | |
935 | uint8_t *prev_p) | |
936 | { | |
937 | uint8_t next, prev; | |
938 | ||
939 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) | |
940 | return 0; | |
941 | ||
942 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
943 | prev = next + PCI_CAP_LIST_NEXT) | |
944 | if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) | |
945 | break; | |
946 | ||
947 | if (prev_p) | |
948 | *prev_p = prev; | |
949 | return next; | |
950 | } | |
951 | ||
952 | /* Reserve space and add capability to the linked list in pci config space */ | |
953 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
954 | { | |
955 | uint8_t offset = pci_find_space(pdev, size); | |
956 | uint8_t *config = pdev->config + offset; | |
957 | if (!offset) | |
958 | return -ENOSPC; | |
959 | config[PCI_CAP_LIST_ID] = cap_id; | |
960 | config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; | |
961 | pdev->config[PCI_CAPABILITY_LIST] = offset; | |
962 | pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; | |
963 | memset(pdev->used + offset, 0xFF, size); | |
964 | /* Make capability read-only by default */ | |
965 | memset(pdev->wmask + offset, 0, size); | |
bd4b65ee MT |
966 | /* Check capability by default */ |
967 | memset(pdev->cmask + offset, 0xFF, size); | |
6f4cbd39 MT |
968 | return offset; |
969 | } | |
970 | ||
971 | /* Unlink capability from the pci config space. */ | |
972 | void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
973 | { | |
974 | uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); | |
975 | if (!offset) | |
976 | return; | |
977 | pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; | |
978 | /* Make capability writeable again */ | |
979 | memset(pdev->wmask + offset, 0xff, size); | |
bd4b65ee MT |
980 | /* Clear cmask as device-specific registers can't be checked */ |
981 | memset(pdev->cmask + offset, 0, size); | |
6f4cbd39 MT |
982 | memset(pdev->used + offset, 0, size); |
983 | ||
984 | if (!pdev->config[PCI_CAPABILITY_LIST]) | |
985 | pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; | |
986 | } | |
987 | ||
988 | /* Reserve space for capability at a known offset (to call after load). */ | |
989 | void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size) | |
990 | { | |
991 | memset(pdev->used + offset, 0xff, size); | |
992 | } | |
993 | ||
994 | uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) | |
995 | { | |
996 | return pci_find_capability_list(pdev, cap_id, NULL); | |
997 | } |