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Commit | Line | Data |
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05ee37eb AZ |
1 | /* |
2 | * CFI parallel flash with Intel command set emulation | |
3 | * | |
4 | * Copyright (c) 2006 Thorsten Zitterell | |
5 | * Copyright (c) 2005 Jocelyn Mayer | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
05ee37eb AZ |
19 | */ |
20 | ||
21 | /* | |
22 | * For now, this code can emulate flashes of 1, 2 or 4 bytes width. | |
23 | * Supported commands/modes are: | |
24 | * - flash read | |
25 | * - flash write | |
26 | * - flash ID read | |
27 | * - sector erase | |
28 | * - CFI queries | |
29 | * | |
30 | * It does not support timings | |
31 | * It does not support flash interleaving | |
32 | * It does not implement software data protection as found in many real chips | |
33 | * It does not implement erase suspend/resume commands | |
34 | * It does not implement multiple sectors erase | |
35 | * | |
36 | * It does not implement much more ... | |
37 | */ | |
38 | ||
87ecb68b PB |
39 | #include "hw.h" |
40 | #include "flash.h" | |
737e150e | 41 | #include "block/block.h" |
1de7afc9 | 42 | #include "qemu/timer.h" |
022c62cb | 43 | #include "exec/address-spaces.h" |
1de7afc9 | 44 | #include "qemu/host-utils.h" |
368a354f | 45 | #include "sysbus.h" |
05ee37eb | 46 | |
001faf32 | 47 | #define PFLASH_BUG(fmt, ...) \ |
05ee37eb | 48 | do { \ |
ec9ea489 | 49 | fprintf(stderr, "PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \ |
05ee37eb AZ |
50 | exit(1); \ |
51 | } while(0) | |
52 | ||
53 | /* #define PFLASH_DEBUG */ | |
54 | #ifdef PFLASH_DEBUG | |
ec9ea489 PC |
55 | #define DPRINTF(fmt, ...) \ |
56 | do { \ | |
57 | fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \ | |
05ee37eb AZ |
58 | } while (0) |
59 | #else | |
001faf32 | 60 | #define DPRINTF(fmt, ...) do { } while (0) |
05ee37eb AZ |
61 | #endif |
62 | ||
c227f099 | 63 | struct pflash_t { |
368a354f | 64 | SysBusDevice busdev; |
05ee37eb | 65 | BlockDriverState *bs; |
368a354f PC |
66 | uint32_t nb_blocs; |
67 | uint64_t sector_len; | |
68 | uint8_t width; | |
69 | uint8_t be; | |
05ee37eb AZ |
70 | int wcycle; /* if 0, the flash is read normally */ |
71 | int bypass; | |
72 | int ro; | |
73 | uint8_t cmd; | |
74 | uint8_t status; | |
368a354f PC |
75 | uint16_t ident0; |
76 | uint16_t ident1; | |
77 | uint16_t ident2; | |
78 | uint16_t ident3; | |
05ee37eb AZ |
79 | uint8_t cfi_len; |
80 | uint8_t cfi_table[0x52]; | |
a8170e5e | 81 | hwaddr counter; |
b4bf0a9a | 82 | unsigned int writeblock_size; |
05ee37eb | 83 | QEMUTimer *timer; |
cfe5f011 | 84 | MemoryRegion mem; |
368a354f | 85 | char *name; |
05ee37eb AZ |
86 | void *storage; |
87 | }; | |
88 | ||
89 | static void pflash_timer (void *opaque) | |
90 | { | |
c227f099 | 91 | pflash_t *pfl = opaque; |
05ee37eb AZ |
92 | |
93 | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd); | |
94 | /* Reset flash */ | |
95 | pfl->status ^= 0x80; | |
96 | if (pfl->bypass) { | |
97 | pfl->wcycle = 2; | |
98 | } else { | |
cfe5f011 | 99 | memory_region_rom_device_set_readable(&pfl->mem, true); |
05ee37eb AZ |
100 | pfl->wcycle = 0; |
101 | } | |
102 | pfl->cmd = 0; | |
103 | } | |
104 | ||
a8170e5e | 105 | static uint32_t pflash_read (pflash_t *pfl, hwaddr offset, |
3d08ff69 | 106 | int width, int be) |
05ee37eb | 107 | { |
a8170e5e | 108 | hwaddr boff; |
05ee37eb AZ |
109 | uint32_t ret; |
110 | uint8_t *p; | |
111 | ||
112 | ret = -1; | |
05ee37eb AZ |
113 | boff = offset & 0xFF; /* why this here ?? */ |
114 | ||
115 | if (pfl->width == 2) | |
116 | boff = boff >> 1; | |
117 | else if (pfl->width == 4) | |
118 | boff = boff >> 2; | |
119 | ||
fad8c772 EI |
120 | #if 0 |
121 | DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n", | |
06adb549 | 122 | __func__, offset, pfl->cmd, width); |
fad8c772 | 123 | #endif |
05ee37eb AZ |
124 | switch (pfl->cmd) { |
125 | case 0x00: | |
126 | /* Flash area read */ | |
127 | p = pfl->storage; | |
128 | switch (width) { | |
129 | case 1: | |
130 | ret = p[offset]; | |
fad8c772 | 131 | DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n", |
c8b153d7 | 132 | __func__, offset, ret); |
05ee37eb AZ |
133 | break; |
134 | case 2: | |
3d08ff69 BS |
135 | if (be) { |
136 | ret = p[offset] << 8; | |
137 | ret |= p[offset + 1]; | |
138 | } else { | |
139 | ret = p[offset]; | |
140 | ret |= p[offset + 1] << 8; | |
141 | } | |
fad8c772 | 142 | DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n", |
c8b153d7 | 143 | __func__, offset, ret); |
05ee37eb AZ |
144 | break; |
145 | case 4: | |
3d08ff69 BS |
146 | if (be) { |
147 | ret = p[offset] << 24; | |
148 | ret |= p[offset + 1] << 16; | |
149 | ret |= p[offset + 2] << 8; | |
150 | ret |= p[offset + 3]; | |
151 | } else { | |
152 | ret = p[offset]; | |
153 | ret |= p[offset + 1] << 8; | |
3d08ff69 BS |
154 | ret |= p[offset + 2] << 16; |
155 | ret |= p[offset + 3] << 24; | |
156 | } | |
fad8c772 | 157 | DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n", |
c8b153d7 | 158 | __func__, offset, ret); |
05ee37eb AZ |
159 | break; |
160 | default: | |
161 | DPRINTF("BUG in %s\n", __func__); | |
162 | } | |
163 | ||
164 | break; | |
165 | case 0x20: /* Block erase */ | |
166 | case 0x50: /* Clear status register */ | |
167 | case 0x60: /* Block /un)lock */ | |
168 | case 0x70: /* Status Register */ | |
169 | case 0xe8: /* Write block */ | |
170 | /* Status register read */ | |
171 | ret = pfl->status; | |
172 | DPRINTF("%s: status %x\n", __func__, ret); | |
173 | break; | |
0b2ec6fc MW |
174 | case 0x90: |
175 | switch (boff) { | |
176 | case 0: | |
368a354f | 177 | ret = pfl->ident0 << 8 | pfl->ident1; |
0b2ec6fc MW |
178 | DPRINTF("%s: Manufacturer Code %04x\n", __func__, ret); |
179 | break; | |
180 | case 1: | |
368a354f | 181 | ret = pfl->ident2 << 8 | pfl->ident3; |
0b2ec6fc MW |
182 | DPRINTF("%s: Device ID Code %04x\n", __func__, ret); |
183 | break; | |
184 | default: | |
fc5b64d0 PC |
185 | DPRINTF("%s: Read Device Information boff=%x\n", __func__, |
186 | (unsigned)boff); | |
0b2ec6fc MW |
187 | ret = 0; |
188 | break; | |
189 | } | |
190 | break; | |
05ee37eb AZ |
191 | case 0x98: /* Query mode */ |
192 | if (boff > pfl->cfi_len) | |
193 | ret = 0; | |
194 | else | |
195 | ret = pfl->cfi_table[boff]; | |
196 | break; | |
197 | default: | |
198 | /* This should never happen : reset state & treat it as a read */ | |
199 | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); | |
200 | pfl->wcycle = 0; | |
201 | pfl->cmd = 0; | |
202 | } | |
203 | return ret; | |
204 | } | |
205 | ||
206 | /* update flash content on disk */ | |
c227f099 | 207 | static void pflash_update(pflash_t *pfl, int offset, |
05ee37eb AZ |
208 | int size) |
209 | { | |
210 | int offset_end; | |
211 | if (pfl->bs) { | |
212 | offset_end = offset + size; | |
213 | /* round to sectors */ | |
214 | offset = offset >> 9; | |
215 | offset_end = (offset_end + 511) >> 9; | |
216 | bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9), | |
217 | offset_end - offset); | |
218 | } | |
219 | } | |
220 | ||
a8170e5e | 221 | static inline void pflash_data_write(pflash_t *pfl, hwaddr offset, |
3d08ff69 | 222 | uint32_t value, int width, int be) |
d361be25 AZ |
223 | { |
224 | uint8_t *p = pfl->storage; | |
225 | ||
fad8c772 EI |
226 | DPRINTF("%s: block write offset " TARGET_FMT_plx |
227 | " value %x counter " TARGET_FMT_plx "\n", | |
d361be25 AZ |
228 | __func__, offset, value, pfl->counter); |
229 | switch (width) { | |
230 | case 1: | |
231 | p[offset] = value; | |
d361be25 AZ |
232 | break; |
233 | case 2: | |
3d08ff69 BS |
234 | if (be) { |
235 | p[offset] = value >> 8; | |
236 | p[offset + 1] = value; | |
237 | } else { | |
238 | p[offset] = value; | |
239 | p[offset + 1] = value >> 8; | |
240 | } | |
d361be25 AZ |
241 | break; |
242 | case 4: | |
3d08ff69 BS |
243 | if (be) { |
244 | p[offset] = value >> 24; | |
245 | p[offset + 1] = value >> 16; | |
246 | p[offset + 2] = value >> 8; | |
247 | p[offset + 3] = value; | |
248 | } else { | |
249 | p[offset] = value; | |
250 | p[offset + 1] = value >> 8; | |
251 | p[offset + 2] = value >> 16; | |
252 | p[offset + 3] = value >> 24; | |
253 | } | |
d361be25 AZ |
254 | break; |
255 | } | |
256 | ||
257 | } | |
258 | ||
a8170e5e | 259 | static void pflash_write(pflash_t *pfl, hwaddr offset, |
3d08ff69 | 260 | uint32_t value, int width, int be) |
05ee37eb | 261 | { |
05ee37eb AZ |
262 | uint8_t *p; |
263 | uint8_t cmd; | |
264 | ||
05ee37eb | 265 | cmd = value; |
05ee37eb | 266 | |
fad8c772 | 267 | DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n", |
c8b153d7 | 268 | __func__, offset, value, width, pfl->wcycle); |
05ee37eb | 269 | |
e9cbbcac EI |
270 | if (!pfl->wcycle) { |
271 | /* Set the device in I/O access mode */ | |
cfe5f011 | 272 | memory_region_rom_device_set_readable(&pfl->mem, false); |
e9cbbcac | 273 | } |
05ee37eb AZ |
274 | |
275 | switch (pfl->wcycle) { | |
276 | case 0: | |
277 | /* read mode */ | |
278 | switch (cmd) { | |
279 | case 0x00: /* ??? */ | |
280 | goto reset_flash; | |
d361be25 AZ |
281 | case 0x10: /* Single Byte Program */ |
282 | case 0x40: /* Single Byte Program */ | |
fad8c772 | 283 | DPRINTF("%s: Single Byte Program\n", __func__); |
d361be25 | 284 | break; |
05ee37eb AZ |
285 | case 0x20: /* Block erase */ |
286 | p = pfl->storage; | |
287 | offset &= ~(pfl->sector_len - 1); | |
288 | ||
368a354f PC |
289 | DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes %x\n", |
290 | __func__, offset, (unsigned)pfl->sector_len); | |
05ee37eb | 291 | |
de8efe8f JJ |
292 | if (!pfl->ro) { |
293 | memset(p + offset, 0xff, pfl->sector_len); | |
294 | pflash_update(pfl, offset, pfl->sector_len); | |
295 | } else { | |
296 | pfl->status |= 0x20; /* Block erase error */ | |
297 | } | |
05ee37eb AZ |
298 | pfl->status |= 0x80; /* Ready! */ |
299 | break; | |
300 | case 0x50: /* Clear status bits */ | |
301 | DPRINTF("%s: Clear status bits\n", __func__); | |
302 | pfl->status = 0x0; | |
303 | goto reset_flash; | |
304 | case 0x60: /* Block (un)lock */ | |
305 | DPRINTF("%s: Block unlock\n", __func__); | |
306 | break; | |
307 | case 0x70: /* Status Register */ | |
308 | DPRINTF("%s: Read status register\n", __func__); | |
309 | pfl->cmd = cmd; | |
310 | return; | |
0b2ec6fc MW |
311 | case 0x90: /* Read Device ID */ |
312 | DPRINTF("%s: Read Device information\n", __func__); | |
313 | pfl->cmd = cmd; | |
314 | return; | |
05ee37eb AZ |
315 | case 0x98: /* CFI query */ |
316 | DPRINTF("%s: CFI query\n", __func__); | |
317 | break; | |
318 | case 0xe8: /* Write to buffer */ | |
319 | DPRINTF("%s: Write to buffer\n", __func__); | |
320 | pfl->status |= 0x80; /* Ready! */ | |
321 | break; | |
5928023c SW |
322 | case 0xf0: /* Probe for AMD flash */ |
323 | DPRINTF("%s: Probe for AMD flash\n", __func__); | |
324 | goto reset_flash; | |
05ee37eb AZ |
325 | case 0xff: /* Read array mode */ |
326 | DPRINTF("%s: Read array mode\n", __func__); | |
327 | goto reset_flash; | |
328 | default: | |
329 | goto error_flash; | |
330 | } | |
331 | pfl->wcycle++; | |
332 | pfl->cmd = cmd; | |
12dabc79 | 333 | break; |
05ee37eb AZ |
334 | case 1: |
335 | switch (pfl->cmd) { | |
d361be25 AZ |
336 | case 0x10: /* Single Byte Program */ |
337 | case 0x40: /* Single Byte Program */ | |
338 | DPRINTF("%s: Single Byte Program\n", __func__); | |
de8efe8f JJ |
339 | if (!pfl->ro) { |
340 | pflash_data_write(pfl, offset, value, width, be); | |
341 | pflash_update(pfl, offset, width); | |
342 | } else { | |
343 | pfl->status |= 0x10; /* Programming error */ | |
344 | } | |
d361be25 AZ |
345 | pfl->status |= 0x80; /* Ready! */ |
346 | pfl->wcycle = 0; | |
347 | break; | |
05ee37eb AZ |
348 | case 0x20: /* Block erase */ |
349 | case 0x28: | |
350 | if (cmd == 0xd0) { /* confirm */ | |
3656744c | 351 | pfl->wcycle = 0; |
05ee37eb | 352 | pfl->status |= 0x80; |
9248f413 | 353 | } else if (cmd == 0xff) { /* read array mode */ |
05ee37eb AZ |
354 | goto reset_flash; |
355 | } else | |
356 | goto error_flash; | |
357 | ||
358 | break; | |
359 | case 0xe8: | |
71fb2348 AZ |
360 | DPRINTF("%s: block write of %x bytes\n", __func__, value); |
361 | pfl->counter = value; | |
05ee37eb AZ |
362 | pfl->wcycle++; |
363 | break; | |
364 | case 0x60: | |
365 | if (cmd == 0xd0) { | |
366 | pfl->wcycle = 0; | |
367 | pfl->status |= 0x80; | |
368 | } else if (cmd == 0x01) { | |
369 | pfl->wcycle = 0; | |
370 | pfl->status |= 0x80; | |
371 | } else if (cmd == 0xff) { | |
372 | goto reset_flash; | |
373 | } else { | |
374 | DPRINTF("%s: Unknown (un)locking command\n", __func__); | |
375 | goto reset_flash; | |
376 | } | |
377 | break; | |
378 | case 0x98: | |
379 | if (cmd == 0xff) { | |
380 | goto reset_flash; | |
381 | } else { | |
382 | DPRINTF("%s: leaving query mode\n", __func__); | |
383 | } | |
384 | break; | |
385 | default: | |
386 | goto error_flash; | |
387 | } | |
12dabc79 | 388 | break; |
05ee37eb AZ |
389 | case 2: |
390 | switch (pfl->cmd) { | |
391 | case 0xe8: /* Block write */ | |
de8efe8f JJ |
392 | if (!pfl->ro) { |
393 | pflash_data_write(pfl, offset, value, width, be); | |
394 | } else { | |
395 | pfl->status |= 0x10; /* Programming error */ | |
396 | } | |
05ee37eb AZ |
397 | |
398 | pfl->status |= 0x80; | |
399 | ||
400 | if (!pfl->counter) { | |
a8170e5e | 401 | hwaddr mask = pfl->writeblock_size - 1; |
b4bf0a9a EI |
402 | mask = ~mask; |
403 | ||
05ee37eb AZ |
404 | DPRINTF("%s: block write finished\n", __func__); |
405 | pfl->wcycle++; | |
de8efe8f JJ |
406 | if (!pfl->ro) { |
407 | /* Flush the entire write buffer onto backing storage. */ | |
408 | pflash_update(pfl, offset & mask, pfl->writeblock_size); | |
409 | } else { | |
410 | pfl->status |= 0x10; /* Programming error */ | |
411 | } | |
05ee37eb AZ |
412 | } |
413 | ||
414 | pfl->counter--; | |
415 | break; | |
7317b8ca AZ |
416 | default: |
417 | goto error_flash; | |
05ee37eb | 418 | } |
12dabc79 | 419 | break; |
05ee37eb AZ |
420 | case 3: /* Confirm mode */ |
421 | switch (pfl->cmd) { | |
422 | case 0xe8: /* Block write */ | |
423 | if (cmd == 0xd0) { | |
424 | pfl->wcycle = 0; | |
425 | pfl->status |= 0x80; | |
05ee37eb AZ |
426 | } else { |
427 | DPRINTF("%s: unknown command for \"write block\"\n", __func__); | |
428 | PFLASH_BUG("Write block confirm"); | |
7317b8ca | 429 | goto reset_flash; |
05ee37eb | 430 | } |
7317b8ca AZ |
431 | break; |
432 | default: | |
433 | goto error_flash; | |
05ee37eb | 434 | } |
12dabc79 | 435 | break; |
05ee37eb AZ |
436 | default: |
437 | /* Should never happen */ | |
438 | DPRINTF("%s: invalid write state\n", __func__); | |
439 | goto reset_flash; | |
440 | } | |
441 | return; | |
442 | ||
443 | error_flash: | |
d96fc51c PC |
444 | qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence " |
445 | "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)" | |
446 | "\n", __func__, offset, pfl->wcycle, pfl->cmd, value); | |
05ee37eb AZ |
447 | |
448 | reset_flash: | |
cfe5f011 | 449 | memory_region_rom_device_set_readable(&pfl->mem, true); |
05ee37eb AZ |
450 | |
451 | pfl->bypass = 0; | |
452 | pfl->wcycle = 0; | |
453 | pfl->cmd = 0; | |
05ee37eb AZ |
454 | } |
455 | ||
456 | ||
a8170e5e | 457 | static uint32_t pflash_readb_be(void *opaque, hwaddr addr) |
3d08ff69 BS |
458 | { |
459 | return pflash_read(opaque, addr, 1, 1); | |
460 | } | |
461 | ||
a8170e5e | 462 | static uint32_t pflash_readb_le(void *opaque, hwaddr addr) |
3d08ff69 BS |
463 | { |
464 | return pflash_read(opaque, addr, 1, 0); | |
465 | } | |
466 | ||
a8170e5e | 467 | static uint32_t pflash_readw_be(void *opaque, hwaddr addr) |
3d08ff69 BS |
468 | { |
469 | pflash_t *pfl = opaque; | |
470 | ||
471 | return pflash_read(pfl, addr, 2, 1); | |
472 | } | |
473 | ||
a8170e5e | 474 | static uint32_t pflash_readw_le(void *opaque, hwaddr addr) |
05ee37eb | 475 | { |
3d08ff69 BS |
476 | pflash_t *pfl = opaque; |
477 | ||
478 | return pflash_read(pfl, addr, 2, 0); | |
05ee37eb AZ |
479 | } |
480 | ||
a8170e5e | 481 | static uint32_t pflash_readl_be(void *opaque, hwaddr addr) |
05ee37eb | 482 | { |
c227f099 | 483 | pflash_t *pfl = opaque; |
05ee37eb | 484 | |
3d08ff69 | 485 | return pflash_read(pfl, addr, 4, 1); |
05ee37eb AZ |
486 | } |
487 | ||
a8170e5e | 488 | static uint32_t pflash_readl_le(void *opaque, hwaddr addr) |
05ee37eb | 489 | { |
c227f099 | 490 | pflash_t *pfl = opaque; |
05ee37eb | 491 | |
3d08ff69 | 492 | return pflash_read(pfl, addr, 4, 0); |
05ee37eb AZ |
493 | } |
494 | ||
a8170e5e | 495 | static void pflash_writeb_be(void *opaque, hwaddr addr, |
3d08ff69 | 496 | uint32_t value) |
05ee37eb | 497 | { |
3d08ff69 | 498 | pflash_write(opaque, addr, value, 1, 1); |
05ee37eb AZ |
499 | } |
500 | ||
a8170e5e | 501 | static void pflash_writeb_le(void *opaque, hwaddr addr, |
3d08ff69 BS |
502 | uint32_t value) |
503 | { | |
504 | pflash_write(opaque, addr, value, 1, 0); | |
505 | } | |
506 | ||
a8170e5e | 507 | static void pflash_writew_be(void *opaque, hwaddr addr, |
3d08ff69 | 508 | uint32_t value) |
05ee37eb | 509 | { |
c227f099 | 510 | pflash_t *pfl = opaque; |
05ee37eb | 511 | |
3d08ff69 | 512 | pflash_write(pfl, addr, value, 2, 1); |
05ee37eb AZ |
513 | } |
514 | ||
a8170e5e | 515 | static void pflash_writew_le(void *opaque, hwaddr addr, |
3d08ff69 | 516 | uint32_t value) |
05ee37eb | 517 | { |
c227f099 | 518 | pflash_t *pfl = opaque; |
05ee37eb | 519 | |
3d08ff69 | 520 | pflash_write(pfl, addr, value, 2, 0); |
05ee37eb AZ |
521 | } |
522 | ||
a8170e5e | 523 | static void pflash_writel_be(void *opaque, hwaddr addr, |
3d08ff69 BS |
524 | uint32_t value) |
525 | { | |
526 | pflash_t *pfl = opaque; | |
527 | ||
528 | pflash_write(pfl, addr, value, 4, 1); | |
529 | } | |
530 | ||
a8170e5e | 531 | static void pflash_writel_le(void *opaque, hwaddr addr, |
3d08ff69 BS |
532 | uint32_t value) |
533 | { | |
534 | pflash_t *pfl = opaque; | |
535 | ||
536 | pflash_write(pfl, addr, value, 4, 0); | |
537 | } | |
538 | ||
cfe5f011 AK |
539 | static const MemoryRegionOps pflash_cfi01_ops_be = { |
540 | .old_mmio = { | |
541 | .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, }, | |
542 | .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, }, | |
543 | }, | |
544 | .endianness = DEVICE_NATIVE_ENDIAN, | |
05ee37eb AZ |
545 | }; |
546 | ||
cfe5f011 AK |
547 | static const MemoryRegionOps pflash_cfi01_ops_le = { |
548 | .old_mmio = { | |
549 | .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, }, | |
550 | .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, }, | |
551 | }, | |
552 | .endianness = DEVICE_NATIVE_ENDIAN, | |
05ee37eb AZ |
553 | }; |
554 | ||
368a354f | 555 | static int pflash_cfi01_init(SysBusDevice *dev) |
05ee37eb | 556 | { |
368a354f PC |
557 | pflash_t *pfl = FROM_SYSBUS(typeof(*pfl), dev); |
558 | uint64_t total_len; | |
d0e7605e | 559 | int ret; |
05ee37eb | 560 | |
368a354f | 561 | total_len = pfl->sector_len * pfl->nb_blocs; |
05ee37eb AZ |
562 | |
563 | /* XXX: to be fixed */ | |
c8b153d7 | 564 | #if 0 |
05ee37eb AZ |
565 | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) && |
566 | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024)) | |
567 | return NULL; | |
c8b153d7 | 568 | #endif |
05ee37eb | 569 | |
cfe5f011 | 570 | memory_region_init_rom_device( |
368a354f PC |
571 | &pfl->mem, pfl->be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl, |
572 | pfl->name, total_len); | |
573 | vmstate_register_ram(&pfl->mem, DEVICE(pfl)); | |
cfe5f011 | 574 | pfl->storage = memory_region_get_ram_ptr(&pfl->mem); |
368a354f | 575 | sysbus_init_mmio(dev, &pfl->mem); |
05ee37eb | 576 | |
05ee37eb AZ |
577 | if (pfl->bs) { |
578 | /* read the initial flash content */ | |
d0e7605e | 579 | ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); |
368a354f | 580 | |
d0e7605e | 581 | if (ret < 0) { |
368a354f | 582 | vmstate_unregister_ram(&pfl->mem, DEVICE(pfl)); |
cfe5f011 | 583 | memory_region_destroy(&pfl->mem); |
368a354f | 584 | return 1; |
d0e7605e | 585 | } |
05ee37eb | 586 | } |
de8efe8f JJ |
587 | |
588 | if (pfl->bs) { | |
589 | pfl->ro = bdrv_is_read_only(pfl->bs); | |
590 | } else { | |
591 | pfl->ro = 0; | |
592 | } | |
593 | ||
74475455 | 594 | pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl); |
05ee37eb AZ |
595 | pfl->wcycle = 0; |
596 | pfl->cmd = 0; | |
597 | pfl->status = 0; | |
05ee37eb AZ |
598 | /* Hardcoded CFI table */ |
599 | pfl->cfi_len = 0x52; | |
600 | /* Standard "QRY" string */ | |
601 | pfl->cfi_table[0x10] = 'Q'; | |
602 | pfl->cfi_table[0x11] = 'R'; | |
603 | pfl->cfi_table[0x12] = 'Y'; | |
604 | /* Command set (Intel) */ | |
605 | pfl->cfi_table[0x13] = 0x01; | |
606 | pfl->cfi_table[0x14] = 0x00; | |
607 | /* Primary extended table address (none) */ | |
608 | pfl->cfi_table[0x15] = 0x31; | |
609 | pfl->cfi_table[0x16] = 0x00; | |
610 | /* Alternate command set (none) */ | |
611 | pfl->cfi_table[0x17] = 0x00; | |
612 | pfl->cfi_table[0x18] = 0x00; | |
613 | /* Alternate extended table (none) */ | |
614 | pfl->cfi_table[0x19] = 0x00; | |
615 | pfl->cfi_table[0x1A] = 0x00; | |
616 | /* Vcc min */ | |
617 | pfl->cfi_table[0x1B] = 0x45; | |
618 | /* Vcc max */ | |
619 | pfl->cfi_table[0x1C] = 0x55; | |
620 | /* Vpp min (no Vpp pin) */ | |
621 | pfl->cfi_table[0x1D] = 0x00; | |
622 | /* Vpp max (no Vpp pin) */ | |
623 | pfl->cfi_table[0x1E] = 0x00; | |
624 | /* Reserved */ | |
625 | pfl->cfi_table[0x1F] = 0x07; | |
626 | /* Timeout for min size buffer write */ | |
627 | pfl->cfi_table[0x20] = 0x07; | |
628 | /* Typical timeout for block erase */ | |
629 | pfl->cfi_table[0x21] = 0x0a; | |
630 | /* Typical timeout for full chip erase (4096 ms) */ | |
631 | pfl->cfi_table[0x22] = 0x00; | |
632 | /* Reserved */ | |
633 | pfl->cfi_table[0x23] = 0x04; | |
634 | /* Max timeout for buffer write */ | |
635 | pfl->cfi_table[0x24] = 0x04; | |
636 | /* Max timeout for block erase */ | |
637 | pfl->cfi_table[0x25] = 0x04; | |
638 | /* Max timeout for chip erase */ | |
639 | pfl->cfi_table[0x26] = 0x00; | |
640 | /* Device size */ | |
641 | pfl->cfi_table[0x27] = ctz32(total_len); // + 1; | |
642 | /* Flash device interface (8 & 16 bits) */ | |
643 | pfl->cfi_table[0x28] = 0x02; | |
644 | pfl->cfi_table[0x29] = 0x00; | |
645 | /* Max number of bytes in multi-bytes write */ | |
368a354f | 646 | if (pfl->width == 1) { |
4737fa26 EI |
647 | pfl->cfi_table[0x2A] = 0x08; |
648 | } else { | |
649 | pfl->cfi_table[0x2A] = 0x0B; | |
650 | } | |
b4bf0a9a EI |
651 | pfl->writeblock_size = 1 << pfl->cfi_table[0x2A]; |
652 | ||
05ee37eb AZ |
653 | pfl->cfi_table[0x2B] = 0x00; |
654 | /* Number of erase block regions (uniform) */ | |
655 | pfl->cfi_table[0x2C] = 0x01; | |
656 | /* Erase block region 1 */ | |
368a354f PC |
657 | pfl->cfi_table[0x2D] = pfl->nb_blocs - 1; |
658 | pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8; | |
659 | pfl->cfi_table[0x2F] = pfl->sector_len >> 8; | |
660 | pfl->cfi_table[0x30] = pfl->sector_len >> 16; | |
05ee37eb AZ |
661 | |
662 | /* Extended */ | |
663 | pfl->cfi_table[0x31] = 'P'; | |
664 | pfl->cfi_table[0x32] = 'R'; | |
665 | pfl->cfi_table[0x33] = 'I'; | |
666 | ||
667 | pfl->cfi_table[0x34] = '1'; | |
262e1eaa | 668 | pfl->cfi_table[0x35] = '0'; |
05ee37eb AZ |
669 | |
670 | pfl->cfi_table[0x36] = 0x00; | |
671 | pfl->cfi_table[0x37] = 0x00; | |
672 | pfl->cfi_table[0x38] = 0x00; | |
673 | pfl->cfi_table[0x39] = 0x00; | |
674 | ||
675 | pfl->cfi_table[0x3a] = 0x00; | |
676 | ||
677 | pfl->cfi_table[0x3b] = 0x00; | |
678 | pfl->cfi_table[0x3c] = 0x00; | |
679 | ||
262e1eaa AJ |
680 | pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */ |
681 | ||
368a354f PC |
682 | return 0; |
683 | } | |
684 | ||
685 | static Property pflash_cfi01_properties[] = { | |
686 | DEFINE_PROP_DRIVE("drive", struct pflash_t, bs), | |
687 | DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0), | |
688 | DEFINE_PROP_UINT64("sector-length", struct pflash_t, sector_len, 0), | |
689 | DEFINE_PROP_UINT8("width", struct pflash_t, width, 0), | |
690 | DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0), | |
691 | DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0), | |
692 | DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0), | |
693 | DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0), | |
694 | DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0), | |
695 | DEFINE_PROP_STRING("name", struct pflash_t, name), | |
696 | DEFINE_PROP_END_OF_LIST(), | |
697 | }; | |
698 | ||
699 | static void pflash_cfi01_class_init(ObjectClass *klass, void *data) | |
700 | { | |
701 | DeviceClass *dc = DEVICE_CLASS(klass); | |
702 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); | |
703 | ||
704 | k->init = pflash_cfi01_init; | |
705 | dc->props = pflash_cfi01_properties; | |
706 | } | |
707 | ||
708 | ||
709 | static const TypeInfo pflash_cfi01_info = { | |
710 | .name = "cfi.pflash01", | |
711 | .parent = TYPE_SYS_BUS_DEVICE, | |
712 | .instance_size = sizeof(struct pflash_t), | |
713 | .class_init = pflash_cfi01_class_init, | |
714 | }; | |
715 | ||
716 | static void pflash_cfi01_register_types(void) | |
717 | { | |
718 | type_register_static(&pflash_cfi01_info); | |
719 | } | |
720 | ||
721 | type_init(pflash_cfi01_register_types) | |
722 | ||
723 | pflash_t *pflash_cfi01_register(hwaddr base, | |
724 | DeviceState *qdev, const char *name, | |
725 | hwaddr size, | |
726 | BlockDriverState *bs, | |
727 | uint32_t sector_len, int nb_blocs, int width, | |
728 | uint16_t id0, uint16_t id1, | |
729 | uint16_t id2, uint16_t id3, int be) | |
730 | { | |
731 | DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); | |
1356b98d | 732 | SysBusDevice *busdev = SYS_BUS_DEVICE(dev); |
368a354f PC |
733 | pflash_t *pfl = (pflash_t *)object_dynamic_cast(OBJECT(dev), |
734 | "cfi.pflash01"); | |
735 | ||
736 | if (bs && qdev_prop_set_drive(dev, "drive", bs)) { | |
737 | abort(); | |
738 | } | |
739 | qdev_prop_set_uint32(dev, "num-blocks", nb_blocs); | |
740 | qdev_prop_set_uint64(dev, "sector-length", sector_len); | |
741 | qdev_prop_set_uint8(dev, "width", width); | |
742 | qdev_prop_set_uint8(dev, "big-endian", !!be); | |
743 | qdev_prop_set_uint16(dev, "id0", id0); | |
744 | qdev_prop_set_uint16(dev, "id1", id1); | |
745 | qdev_prop_set_uint16(dev, "id2", id2); | |
746 | qdev_prop_set_uint16(dev, "id3", id3); | |
747 | qdev_prop_set_string(dev, "name", name); | |
748 | qdev_init_nofail(dev); | |
749 | ||
750 | sysbus_mmio_map(busdev, 0, base); | |
05ee37eb AZ |
751 | return pfl; |
752 | } | |
cfe5f011 AK |
753 | |
754 | MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl) | |
755 | { | |
756 | return &fl->mem; | |
757 | } |